Data Logging Subsystem for Memory Subsystem Controller

Abstract

The present application relates to a data logging subsystem for a memory subsystem controller. A processing device at the memory subsystem monitors data traffic including data packets transmitted between the memory subsystem and a host system. The data packets are classified according to packet types. Log data including frequency and latency information associated with each packet type is generated. The log data is stored in a memory component of the memory subsystem.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to a memory subsystem controller data logging subsystem. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] According to an embodiment of the present disclosure, a memory subsystem is provided. The memory subsystem includes: a memory component, which includes a log data storage device; and a processing device, which is coupled to the log data storage device. The processing device performs operations including the following: monitoring data traffic on a communication channel of a physical host interface within a time interval, the data traffic including data packets transmitted between the memory subsystem and the host system via the communication channel of the physical host interface; classifying each data packet in the data traffic according to the packet type; generating log data including the frequency of each packet type in the data traffic and the latency information associated with each packet type; and storing the log data in the log data storage device.

[0004] According to another embodiment of the present disclosure, a method is provided. The method includes: monitoring data traffic on a communication channel of a physical host interface within a time interval through a memory subsystem controller, the data traffic including data packets transmitted between a memory subsystem and a host system via the communication channel of the physical host interface; classifying each data packet in the data traffic according to the packet type through the memory subsystem controller; generating log data including the frequency of each packet type in the data traffic and latency information associated with each packet type through the memory subsystem controller; and storing the log data in a log data storage device of the memory subsystem.

[0005] According to another embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions, which, when executed by a processing device, configure the processing device to perform operations including: monitoring data traffic on a communication channel of a physical host interface within a time interval, the data traffic including data packets transmitted between a memory subsystem and a host system via the communication channel of the physical host interface; classifying each data packet in the data traffic according to the packet type; generating log data including the frequency of each packet type in the data traffic and latency information associated with each packet type; and storing the log data in a log data storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 Components of a recording subsystem that may be included in a memory subsystem according to some embodiments of the present disclosure are shown.

[0009] Figure 3 and 4 is a flow chart of an example method of recording data regarding data traffic through a memory subsystem communication channel according to some embodiments of the present disclosure.

[0010] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0011] Aspects of the present disclosure relate to a data logging subsystem of a memory subsystem controller. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0012] Various types of data packets may be exchanged between the memory subsystem and the host system for various purposes. As an example, transaction layer packets (TLPs) and data link layer packets (DLLPs) may be transferred back and forth between the memory subsystem and the host system. In addition to direct data transfers, many of these types of data packets are exchanged between the memory subsystem and the host system to manage the quality of the link between the memory subsystem and the host system. Thus, the types of data packets transferred over a communication channel and the frequency with which such packets are transferred may provide an indicator of the "health" of the communication channel.

[0013] Traditionally, external tools called protocol analyzers are used to capture and analyze data traffic on a communication channel in order to assess the communication channel link quality. Typically, a protocol analyzer must be introduced into the communication channel in order to be able to assess the channel. Introducing this new element into the channel can cause disruptions in the channel, which can cause issues with the accuracy of the analyzer readings. Furthermore, most protocol analyzers are in the form of laboratory instruments that are only designed to analyze small numbers of samples and are generally not capable of acquiring protocol link information in bulk, as would be possible in a batch manufacturing environment.

[0014] Aspects of the present disclosure address the above and other deficiencies using a memory subsystem controller that is configured to include a logging subsystem to monitor data traffic and generate log data that includes frequency and latency information associated with a specific packet type transmitted between the memory subsystem and the host system. In this way, the memory subsystem can report a statistical summary of the number of packets of a specific packet type received in a given time interval and the latency associated with the specific packet type (e.g., the minimum, maximum, and average latency between data packets in the time interval).

[0015] According to some embodiments, the logging subsystem may include counters and timers placed on receiver (RX) and transmitter (TX) channels of a physical host interface used to transfer data between a host system and a memory subsystem. The counters and timers work together to count the occurrences of each packet type within a time interval and measure latency between data packets. The logging subsystem generates and stores log data associated with data traffic across the host interface based on information generated by the counters and timers.

[0016] Having the logging subsystem generate log data in this manner allows the memory subsystem controller to report information that is normally only available using a protocol analyzer, thereby avoiding the need to use expensive laboratory instruments with low-capacity capabilities. By logging data in this manner, the logging subsystem can allow for batch collection of protocol timing information during the manufacturing process, allowing degraded or damaged parts and test sites to be identified and remedial action to be taken before more serious problems occur. For example, log data indicating excessive latency or abnormal TLP packet frequency can be used to identify weak parts or test sites. The log data generated by the logging component can enable performance adjustments to improve the memory subsystem.

[0017] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include SSDs, flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0019] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0021] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0022] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface 102. Examples of the physical host interface 102 include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface 102 may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may also utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface 102 may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0023] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion of a memory cell, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0026] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0028] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0029] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include ROM for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0030] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via the physical host interface 102. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0031] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0032] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] As shown, the memory subsystem controller 115 includes a recording subsystem 113 for monitoring and generating log data describing data packets exchanged between the host system 120 and the memory subsystem 110 via the physical host interface 102. The log data generated by the recording subsystem 113 may include frequency and latency information associated with the data exchanged between the host system 120 and the memory subsystem 110. The data packets exchanged between the host system 120 and the memory subsystem 110 may be various packet types (e.g., transaction layer packets (TLPs), data link layer packets (DLLPs) or other packet types) and log data that may be specifically organized according to the packet type. That is, the log data may include frequency and latency information associated with a specific packet type. As an example, the log data may include data describing the frequency and latency of the DLPs exchanged via the physical host interface 102, and data describing the frequency and latency of the TLPs exchanged via the physical host interface 102. More details about the recording subsystem 113 are discussed below.

[0034] Although Figure 1 The recording subsystem 113 is shown as residing on the memory subsystem controller 115, but it should be understood that in other embodiments, the recording subsystem 113 may reside on the local media controller 135. Furthermore, in some embodiments, the recording subsystem 113 may be implemented within both the memory subsystem controller 115 and the local media controller 135. Additionally, in some embodiments, the recording subsystem 113 may be incorporated into the protocol engine of the memory subsystem 110.

[0035] Figure 2 Components of the logging subsystem 113 according to some embodiments of the present disclosure are shown. As shown, the logging subsystem 113 includes a classification component 200, a counter 202, a timer 205, and a log data storage device 206.

[0036] Typically, the recording subsystem 113 monitors data traffic transmitted between the host system 120 and the memory subsystem 110 via the physical host interface 102. The data traffic includes data packets of various packet types. The classification component 200 classifies the data packets in the monitored data traffic according to the packet type. For example, each data packet may include an indicator of the packet type (e.g., in the packet header), and the classification component 200 may classify each data packet based on the corresponding packet type indicator.

[0037] The log data storage device 206 stores log data 208 describing data packets transmitted between the memory subsystem 110 and the host system 120. The log data storage device 206 can be implemented in the local memory 119 or one of the memory devices 130 or 140. The log data 208 includes frequency information 209 and latency information 211 associated with a particular packet type. The latency information 211 can contain a statistical summary of the latency (e.g., minimum, maximum, and average latency) associated with the packet type. The recording subsystem 113 generates the log data 208 based on the information generated by the classification component 200, the counter 202, and the timer 205.

[0038] The counter 202 is responsible for counting the occurrences of each packet type within a time interval. For example, a counter 202 can be specified for each packet type. For example, a first counter can be specifically specified to count the occurrences of packets of a first packet type, a second counter can be specifically specified to count the occurrences of packets of a second packet type, a third counter can be specifically specified to count the occurrences of packets of a third packet type, and so on. In some embodiments, a multiplexer (not shown) or other suitable component can be used to send data packets to the appropriate counter 202. That is, the multiplexer can send data packets of a specific packet type to a specially designated counter 202 to count instances of the packet type. For example, the classification component 200 can send data packets to the counter 202 corresponding to the packet type by providing a control signal based on the packet type to the multiplexer.

[0039] One or more timers 205 are included in the recording subsystem 113 to measure time. For example, the timer 205 measures the time interval during which each counter counts the occurrence of each packet type. In other words, the timer 205 limits the count of the occurrence of each packet type to the time interval. In this way, frequency information 209 can be derived for each packet type.

[0040] The logging subsystem 113 may further utilize one or more timers 205 to measure the latency associated with each packet type, which may be included in the latency information 209. In some embodiments, each timer 205 may include timing circuitry (e.g., clock circuitry) for measuring time. One or more counters 202 and one or more timers 205 may be placed on both the receiver (RX) and transmitter (TX) communication channels of the physical host interface 102 to monitor and log incoming and outgoing data packets.

[0041] Figure 3 and 4Flowchart of an example method 300 for recording frequency and latency information associated with data traffic on a communication channel of a memory subsystem according to some embodiments of the present disclosure. Method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed by recording subsystem 113. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0042] In operation 305, the processing device monitors data traffic on a communication channel (e.g., a receiver or transmitter channel of the physical host interface 102) of a host interface of a memory subsystem (e.g., memory subsystem 110). The time interval may be determined based on a timer included in or in communication with the processing device.

[0043] The data traffic includes a plurality of data packets transmitted between the memory subsystem and the host system (e.g., host system 120). As an example, the data traffic may include data packets received by the memory subsystem from the host system via a receiver channel of the host interface. In another example, the data traffic may include data packets transmitted from the memory subsystem to the host system via a transmitter channel of the host interface. The communication channel of the host interface may correspond to a PCIe communication channel, a UFS communication channel, or a SATA communication channel, for example.

[0044] At operation 310, the processing device classifies each data packet in the data traffic according to one of a plurality of packet types. Each data packet may indicate a packet type, for example, in a packet header, and the processing device may classify the data packets according to the packet type indicated by the packet. For example, the processing device may determine that the data packet is a DLLP based on an indicator in the data packet indicating that the data packet is a DLLP.

[0045] At operation 315, the processing device generates log data, the log data including the frequency of occurrence of each packet type and the delay information associated with each packet type. Thus, when generating the log data, the processing device may determine the frequency of each packet type and determine the delay information associated with each packet type. Figure 4 Discusses more details about the generation of log data.

[0046] At operation 320, the processing device stores log data. For example, the processing device may include a log data storage device, and the processing device may store the log data generated in operation 315 in the log data storage device. As described above, the log data storage device may be implemented within a memory component of the memory subsystem. For example, the log data storage device may be implemented within a memory device (e.g., memory device 130 or 140) or within a local memory of a memory subsystem controller (e.g., local memory 119 of memory subsystem controller 115).

[0047] like Figure 4 As shown, in some embodiments, method 300 may include operations 305, 310, and 315. According to these embodiments, operations 305, 310, and 315 may be performed as part of operation 315 (e.g., a sub-operation or subroutine) in which the processing device generates log data. Although operations 305, 310, and 315 are described with respect to a single packet type, it should be understood that when generating log data, operations 305, 310, and 315 may be performed for each packet type observed in the data traffic on the communication channel of the memory subsystem.

[0048] In operation 405, the processing device counts the number of packets of the packet type transmitted through the communication channel within the time interval. As an example, the processing device may include: a hardware counter for counting each packet of the packet type; and a timing circuit system for measuring the time interval and constraining the count thereto. In some embodiments, the processing device may include multiple hardware counters, and each counter may be specifically designated to count the occurrence of a specific packet type. According to these embodiments, the processing device may further include one or more multiplexers to send the packet to an appropriate one of the counters. For example, the multiplexer control signal may be associated with the packet type, so that the packet type can be used to select the counter to which the packet received at the multiplexer input is sent.

[0049] At operation 410, the processing device determines a frequency of a packet type in the data traffic based on the number of packets of the packet type transmitted over the communication channel during the time interval. That is, the frequency of the packet type includes the number of packets of the packet type transmitted over the communication channel during the time interval.

[0050] In operation 415, the processing device determines the delay information associated with the packet type. The delay information may include a statistical summary associated with the packet delay. For example, the delay information may include a minimum delay, a maximum delay, and an average delay. Therefore, as shown in the figure, operation 415 may include operations 416-419. In operation 416, the processing device measures the delay of each packet of the packet type. The processing device measures the delay of the data packet based on the number of clock cycles in which no data packet is transmitted through the communication before or after the data packet is transmitted through the communication channel.

[0051] In an example, the processing device can measure the latency of the first packet by measuring the amount of time between the first packet and the second packet transmitted over the communication channel. In some embodiments, the first and second packets correspond to the same packet type. That is, according to these embodiments, the processing device measures the amount of time between two packets of the same packet type transmitted over the communication channel.

[0052] Based on the delays measured at operation 416, the processing device determines the minimum delay (at operation 417), the maximum delay (at operation 418), and the average delay (at operation 419) of the packet type observed during the time interval.

[0053] Examples

[0054] Example 1 is a memory subsystem, comprising: a memory component, which includes a log data storage device; and a processing device, which is coupled to the log data storage device, the processing device performing operations including the following: monitoring data traffic on a communication channel of a physical host interface within a time interval, the data traffic including data packets transmitted between the memory subsystem and the host system via the communication channel of the physical host interface; classifying each data packet in the data traffic according to the packet type; generating log data including the frequency of each packet type in the data traffic and latency information associated with each packet type; and storing the log data in the log data storage device.

[0055] Example 2 includes the subject matter of Example 1, and the classifying each data packet optionally includes determining a data packet type of the data packet based on a packet type indicator included in the data packet.

[0056] Example 3 includes a subject matter according to any one of Examples 1 and 2, and the generating of the log data optionally includes: counting the number of packets of the packet type transmitted through the communication channel within the time interval; and determining the frequency of the packet type based on the number of packets of the packet type transmitted through the communication channel within the time interval.

[0057] In Example 4, the subject matter of any one of Examples 1 to 3 optionally further includes one or more hardware counters for counting the number of packets of the packet type transmitted over the communication channel within the time interval.

[0058] In Example 5, the subject matter according to any one of Examples 1 to 4 optionally further includes a timer for measuring the time interval.

[0059] Example 6 includes the subject matter of any one of Examples 1 to 5, and the generating the log data optionally includes: determining latency information associated with the packet type, the latency information comprising summary statistics associated with packet latency.

[0060] Example 7 includes the subject matter of any one of Examples 1 to 6, and optionally further includes: measuring the delay of each data packet of the packet type; determining the minimum delay of the packet type; determining the maximum delay of the packet type; and determining the average delay of the packet type.

[0061] Example 8 includes the subject matter of any one of Examples 1 to 7, and optionally further includes: measuring the latency of the data packet based on a number of clock cycles in which no data packet is transmitted through the communication channel before or after the data packet is transmitted through the communication channel.

[0062] Example 9 includes the subject matter of any of Examples 1 to 8, and the communication channel is one of a receiver channel or a transmitter channel of the host interface.

[0063] Example 10 includes the subject matter of any of Examples 1-9, and the host interface optionally includes one of: a Peripheral Component Interconnect Express (PCIe), a Universal Flash Storage (UFS) communication channel, or a Serial Advanced Technology Attachment (SATA) communication channel.

[0064] Example 11 is a method comprising: monitoring, by a memory subsystem controller, data traffic on a communication channel of a physical host interface within a time interval, the data traffic comprising data packets transmitted between a memory subsystem and a host system via the communication channel of the physical host interface; classifying, by the memory subsystem controller, each data packet in the data traffic according to packet type; generating, by the memory subsystem controller, log data comprising a frequency of each packet type in the data traffic and latency information associated with each packet type; and storing the log data in a log data storage device of the memory subsystem.

[0065] Example 12 includes the subject matter of Example 11, and the classifying each data packet optionally includes determining a data packet type of the data packet based on a packet type indicator included in the data packet.

[0066] Example 13 includes the subject matter of any one of Examples 11 and 12, and the generating of the log data optionally includes: counting the number of packets of the packet type transmitted through the communication channel within the time interval; and determining the frequency of the packet type based on the number of packets of the packet type transmitted through the communication channel within the time interval.

[0067] Example 14 includes the subject matter of any one of Examples 11 to 13, and the generating the log data optionally includes: determining latency information associated with the packet type, the latency information including summary statistics associated with packet latency.

[0068] Example 15 includes the subject matter of any one of Examples 11 to 14, and optionally further includes: measuring the delay of each data packet of the packet type; determining the minimum delay of the packet type; determining the maximum delay of the packet type; and determining the average delay of the packet type.

[0069] Example 16 includes the subject matter of any of Examples 11 to 15, and optionally further includes: measuring the latency of the data packet based on a number of clock cycles in which no data packet is transmitted through the communication channel before or after the data packet is transmitted through the communication channel.

[0070] Example 17 includes the subject matter of any of Examples 11 to 16, and the communication channel is one of a receiver channel or a transmitter channel of the host interface.

[0071] Example 18 includes the subject matter of any of Examples 11 to 17, and the host interface optionally includes one of: a Peripheral Component Interconnect Express (PCIe), a Universal Flash Storage (UFS) communication channel, or a Serial Advanced Technology Attachment (SATA) communication channel.

[0072] Example 19 is a non-transitory computer-readable storage medium, which includes instructions that, when executed by a processing device, configure the processing device to perform operations including the following: monitoring data traffic on a communication channel of a physical host interface within a time interval, the data traffic including data packets transmitted between a memory subsystem and a host system via the communication channel of the physical host interface; classifying each data packet in the data traffic according to a packet type; generating log data including a frequency of each packet type in the data traffic and latency information associated with each packet type; and storing the log data in a log data storage device.

[0073] Example 20 includes the subject matter of Example 19, and generating the log data optionally includes: counting the number of packets of the packet type transmitted through the communication channel within the time interval; and determining the frequency of the packet type based on the number of packets of the packet type transmitted through the communication channel within the time interval.

[0074] Figure 5 An example machine in the form of a computer system 500 is shown within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a client-server network environment.

[0075] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0076] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0077] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, processing device 502 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an ASIC, an FPGA, a digital signal processor (DSP), a network processor, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 to communicate over a network 520.

[0078] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0079] In one embodiment, instructions 526 include instructions to implement a method corresponding to a security component (e.g., Figure 1 The functionality of the recording subsystem 113 of the present disclosure). Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "computer-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0080] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been demonstrated that it is sometimes convenient, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0081] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0082] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks); ROM; RAM; Erasable Programmable Read-Only Memory (EPROM); EEPROM; magnetic or optical cards or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used together with the programs according to the teachings herein, or the general purpose systems may prove to be convenient for constructing a more specialized device for performing the method. The structures for various of these systems will be presented as shown in the above description. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0084] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as ROM, RAM, disk storage media, optical storage media, flash memory components, etc.

[0085] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A memory subsystem comprising: A memory component including a log data storage device; as well as a processing device coupled to the memory component, the processing device comprising: a first hardware counter designated to count transaction layer packets; a second hardware counter designated to count data link layer packets; a multiplexer that sends packets to the first hardware counter and the second hardware counter; The processing device performs operations including: monitoring data traffic on a communication channel of a physical host interface within a time interval, the data traffic comprising data packets transmitted between the memory subsystem and a host system via the communication channel of the physical host interface; classifying each data packet in the data traffic according to a packet type; sending, through the multiplexer, at least one packet classified as a transaction layer packet to the first hardware counter; sending at least one packet classified as a data link layer packet to the second hardware counter through the multiplexer; Generating log data including the frequency of each packet type in the data traffic and delay information associated with each packet type, wherein generating the log data includes: counting, by the first hardware counter, the number of transaction layer packets transmitted through the communication channel within the time interval; and determining a frequency of transaction layer packets in the data traffic based on the number of transaction layer packets transmitted over the communication channel within the time interval; and The log data is stored in the log data storage device.

2. The memory subsystem of claim 1, wherein: The classifying each data packet includes determining a data packet type of the data packet based on a packet type indicator included in the data packet.

3. The memory subsystem of claim 1 , wherein said generating the log data further comprises: counting, by the second hardware counter, the number of data link layer packets transmitted through the communication channel during the time interval; as well as A frequency of data link layer packets in the data traffic is determined based on the number of data link layer packets transmitted over the communication channel within the time interval.

4. The memory subsystem of claim 3, wherein: Monitoring the data traffic includes monitoring incoming and outgoing data packets; and Classifying each data packet in the data traffic includes classifying one or more incoming data packets and one or more outgoing data packets according to packet type.

5. The memory subsystem of claim 1, wherein the processing device further comprises a timer for measuring the time interval.

6. The memory subsystem of claim 1 , wherein said generating said log data comprises: The latency information associated with a transaction layer packet is determined, the latency information comprising summary statistics associated with packet latency.

7. The memory subsystem of claim 6, wherein said determining the latency information associated with a transaction layer packet comprises: Measure the latency of each transaction layer packet; Determine the minimum latency for transaction layer grouping; Determine the maximum latency of transaction layer packets; as well as Determine the average latency of transaction layer packets.

8. The memory subsystem of claim 7, wherein said measuring the latency of each transaction layer packet comprises: A latency of the first transaction layer packet is measured based on a number of clock cycles between the first transaction layer packet and a second transaction layer packet transmitted over the communication channel.

9. The memory subsystem of claim 1, wherein the communication channel is one of a receiver channel or a transmitter channel of the host interface.

10. The memory subsystem of claim 1, wherein the host interface comprises one of: a peripheral component interconnect express (PCIe), a universal flash storage (UFS) communication channel, or a serial advanced technology attachment (SATA) communication channel.

11. A method for use in a memory subsystem, comprising: Monitoring, by a memory subsystem controller, data traffic on a communication channel of a physical host interface within a time interval, the data traffic comprising data packets transmitted between the memory subsystem and a host system via the communication channel of the physical host interface, the memory subsystem controller: a first hardware counter designated to count transaction layer packets; a second hardware counter designated to count data link layer packets; a multiplexer that sends packets to the first hardware counter and the second hardware counter; classifying, by the memory subsystem controller, each data packet in the data traffic according to a packet type; sending, through the multiplexer of the memory subsystem controller, at least one packet classified as a transaction layer packet to the first hardware counter; sending at least one packet classified as a data link layer packet to the second hardware counter through the multiplexer of the memory subsystem controller; Generating, by the memory subsystem controller, log data including the frequency of each packet type in the data traffic and latency information associated with each packet type, wherein generating the log data comprises: counting, by the first hardware counter, the number of transaction layer packets transmitted through the communication channel within the time interval; and determining a frequency of transaction layer packets in the data traffic based on the number of transaction layer packets transmitted over the communication channel within the time interval; and The log data is stored in a log data storage device of the memory subsystem.

12. The method of claim 11, wherein said classifying each data packet comprises determining a data packet type of the data packet based on a packet type indicator contained in the data packet.

13. The method according to claim 11, wherein said generating said log data comprises: counting, by the second hardware counter, the number of data link layer packets transmitted through the communication channel during the time interval; as well as A frequency of data link layer packets in the data traffic is determined based on the number of data link layer packets transmitted over the communication channel within the time interval.

14. The method according to claim 12, wherein said generating said log data comprises: Latency information associated with a transaction layer packet is determined, the latency information comprising summary statistics associated with packet latency.

15. The method of claim 14, wherein said determining the latency information associated with a transaction layer packet comprises: Measuring the latency of each data packet of the transaction layer packet; Determine the minimum latency for transaction layer grouping; Determine the maximum latency of transaction layer packets; as well as Determine the average latency of transaction layer packets.

16. The method of claim 14, wherein measuring the latency of each data packet of the first packet type comprises: The latency of the data packet is measured based on a number of clock cycles in which no data packet is transmitted over the communication channel before or after a data packet is transmitted over the communication channel.

17. The method of claim 11, wherein the communication channel is one of a receiver channel or a transmitter channel of the host interface. 18 . The method of claim 11 , wherein the host interface comprises one of: a Peripheral Component Interconnect Express (PCIe), a Universal Flash Storage (UFS) communication channel, or a Serial Advanced Technology Attachment (SATA) communication channel.

19. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, configure the processing device to perform operations comprising: monitoring data traffic on a communication channel of a physical host interface during a time interval, the data traffic comprising data packets transmitted between a memory subsystem and a host system via the communication channel of the physical host interface; classifying each data packet in the data traffic according to a packet type; providing at least one signal to a multiplexer to cause the multiplexer to send at least one packet classified as a transaction layer packet to a first hardware counter designated to count transaction layer packets; providing at least one signal to the multiplexer to cause the multiplexer to send at least one packet classified as a data link layer packet to a second hardware counter designated to count data link layer packets; Generating log data including the frequency of each packet type in the data traffic and delay information associated with each packet type, wherein generating the log data includes: counting, by the first hardware counter, the number of transaction layer packets transmitted through the communication channel within the time interval; and determining a frequency of transaction layer packets in the data traffic based on the number of transaction layer packets transmitted over the communication channel within the time interval; and The log data is stored in a log data storage device.

20. The non-transitory computer-readable storage medium of claim 19, wherein the instructions further configure the processing device to: counting, by the second hardware counter, the number of data link layer packets transmitted through the communication channel within the time interval; and A frequency of data link layer packets in the data traffic is determined based on the number of data link layer packets transmitted over the communication channel within the time interval.

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