Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a discrete core layer on the substrate; forming a sidewall on the sidewall of the core layer; removing the core layer; after removing the core layer, patterning the substrate using the sidewall as a mask to form a fin, wherein the fin includes a device fin and a dummy fin; removing the sidewall; performing one or more doping removal treatments on the dummy fin to remove the dummy fin; the steps of the doping removal treatments comprising: performing ion doping on the entire dummy fin or a portion of the thickness of the dummy fin, suitable for improving the etching selectivity between the dummy fin and the device fin; removing the dummy fin doped with ions. The embodiments of the present invention are conducive to increasing the process window of the fin cut process.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of ultra-large-scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also shortened accordingly. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, so the control ability of the gate structure over the channel becomes worse, and the difficulty of pinching off the channel by the gate voltage becomes increasingly greater, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs). In FinFETs, the gate structure can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has a stronger control over the channel and can effectively suppress the short channel effect; and FinFETs have better compatibility with existing integrated circuit manufacturing than other devices.

[0004] In the semiconductor field, according to process requirements, it is usually necessary to form fins with different pitches. Currently, one approach is to form fins with different pitches through a fin cut process, wherein the fin cut process generally includes a fin cut first process and a fin cut last process. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to increasing the process window of a fin cut process.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a discrete core layer on the substrate; forming a sidewall on the sidewall of the core layer; removing the core layer; after removing the core layer, using the sidewall as a mask to pattern the substrate to form a fin, wherein the fin includes a device fin and a dummy fin; removing the sidewall; performing one or more doping removal treatments on the dummy fin to remove the dummy fin; the steps of the doping removal treatment include: ion doping the entire dummy fin or a partial thickness of the dummy fin, suitable for improving the etching selectivity ratio of the dummy fin and the device fin; removing the dummy fin doped with ions.

[0007] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, comprising: a substrate; fins separated from the substrate, including device fins and dummy fins, wherein the dummy fins contain doped ions, and the doped ions are suitable for improving the etching selectivity of the dummy fins and the device fins.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the dummy fin is subjected to one or more doping removal treatments to remove the dummy fin; the doping removal treatments include: ion doping of the entire dummy fin or a portion of the thickness of the dummy fin, which is suitable for improving the etching selectivity of the dummy fin and the device fin; removing the dummy fin doped with ions, so that in the process of removing the dummy fin, the etching selectivity of the dummy fin and the device fin is relatively large, which is beneficial to reducing the probability of mis-etching the device fin, thereby facilitating increasing the process window of the fin cut process, and further facilitating improving the performance of the semiconductor structure.

[0010] In an optional scheme, the side wall is used as a mask for patterning the substrate to form a fin, and the position of the side wall corresponds to the fin one by one, wherein the side wall used to form the device fin is a mask side wall, and the side wall used to form the dummy fin is a dummy mask side wall, the mask side wall includes a first dummy side wall composed of a plurality of adjacent side walls, and a second dummy side wall composed of a single side wall. After removing the core layer and before patterning the substrate, the embodiment of the present invention further includes: removing the second dummy side wall, the second dummy side wall consisting of a single side wall. By removing the second dummy side wall before patterning the substrate, it is beneficial to reduce the impact on the consistency of the spacing between the remaining side walls. Accordingly, in the process of patterning the substrate with the side wall as a mask to form the fin, the size uniformity and cross-sectional morphology consistency of the fin are also high; moreover, compared with the height of the fin, the height of the side wall is smaller. By removing the second dummy side wall before patterning the substrate, it is also beneficial to reduce the difficulty of removing the second dummy side wall, thereby increasing the process window of the fin cut process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 7 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 8 to 12 It is a schematic structural diagram corresponding to each step in another method for forming a semiconductor structure;

[0013] Figures 13 to 23 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] At present, the process window of the fin cutting process is relatively small. The reasons why the process window of the fin cutting process is relatively small are analyzed by combining the two methods for forming semiconductor structures.

[0015] Take the Fin Cut last process as an example, refer to Figures 1 to 7 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 , providing a substrate 1; forming a discrete core layer 2 on the substrate 1.

[0017] refer to Figure 2 , a side wall 3 is formed on the side wall of the core layer 2.

[0018] refer to Figure 3 , remove the core layer 2.

[0019] refer to Figure 4 After removing the core layer 2 , the substrate 1 is patterned using the sidewall 3 as a mask to form a fin 4 , wherein the fin 4 includes a device fin 4 a and a dummy fin 4 b ; and the sidewall 3 is removed.

[0020] refer to Figures 5 to 7 , removing the dummy fin 4b; the step of removing the dummy fin 4b includes: forming a graphic layer 5 on the substrate 1, the graphic layer 5 covers the device fin 4a, and the graphic layer 5 has an opening 6, the opening 6 is located above the dummy fin 4b and corresponds to the position of the dummy fin 4b; using the graphic layer 5 as a mask, removing the dummy fin 4b; removing the graphic layer 5.

[0021] In the above formation method, after the fin 4 is formed, the dummy fin 4b is removed, and the size consistency of the device fin 4a is good. However, compared with the sidewall 3, the height of the fin 4 is usually larger. In the process of removing the dummy fin 4b, the etching time of the dummy fin 4b is longer. The process of removing the dummy fin 4b is likely to cause damage to the device fin 4a adjacent to the dummy fin 4b. In particular, when there is an overlay shift in the process of forming the pattern layer 5, the process of removing the dummy fin 4b causes damage to the device fin 4a adjacent to the dummy fin 4b (such as Figure 6 In addition, it is easy to produce a pseudo fin 4b residue (such as Figure 6 This easily reduces the process window of the photolithography process for forming the pattern layer 5, resulting in a smaller process window for the fin cutting process.

[0022] Another method is the Fin Cut First process, see Figures 8 to 12 , shows a structural schematic diagram corresponding to each step in another method for forming a semiconductor structure.

[0023] refer to Figure 8 , providing a substrate 11; and forming a discrete core layer 12 on the substrate 11.

[0024] refer to Fig. 9 A sidewall 13 is formed on the sidewall of the core layer 12. The sidewall 13 is used as a mask for patterning the substrate 11 to form a fin, and the sidewall 13 corresponds to the position of the fin one by one. The sidewall 13 includes a discrete mask sidewall 13a and a dummy sidewall 13b.

[0025] refer to Fig.10 , remove the core layer 12.

[0026] refer to Fig.11 After removing the core layer 12, the dummy sidewall 13b is removed.

[0027] refer to Fig.12 After removing the dummy sidewall spacer 13 b , the substrate 11 is patterned using the mask sidewall spacer 13 a as a mask to form a device fin 14 .

[0028] In the above formation method, compared with the fin post-cutting process, since the height of the side wall 13 is smaller than that of the device fin 14, the etching time of the dummy side wall 13b is correspondingly shorter during the process of removing the dummy side wall 13b, which is beneficial to reduce the probability of damaging the adjacent mask side wall 13a during the process of removing the dummy side wall 13b.

[0029] However, in the above formation method, after removing the dummy sidewall 13b, the mask sidewall 13a is used as a mask to pattern the substrate 11 to form the device fin 14. After removing the dummy sidewall 13b, the opening sizes between the mask sidewalls 13a are different, and the spacing uniformity between the mask sidewalls 13a is poor. This can easily lead to different etching rates of the substrate 11 in different areas during the process of patterning the substrate 11 using the mask sidewall 13a as a mask, which can easily lead to poor width size uniformity and cross-sectional morphology consistency of the device fin 14.

[0030] In order to solve the technical problem, in the method for forming a semiconductor structure provided in an embodiment of the present invention, the dummy fin is subjected to one or more doping removal treatments to remove the dummy fin; the doping removal treatment includes: ion doping of the entire dummy fin or a partial thickness of the dummy fin, which is suitable for improving the etching selectivity of the dummy fin and the device fin; removing the dummy fin doped with ions, so that in the process of removing the dummy fin, the etching selectivity of the dummy fin and the device fin is relatively large, which is beneficial to reducing the probability of mis-etching the device fin, thereby facilitating increasing the process window of the fin cut process, and further facilitating improving the performance of the semiconductor structure.

[0031] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 13 to 23 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0033] refer to Fig.13 , providing a substrate 100.

[0034] The substrate 100 provides a process platform for subsequent process steps, and is also used as a material layer to be etched in a patterning process. In this embodiment, the substrate 100 is used to form a substrate and a fin protruding from the substrate.

[0035] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process basis for the subsequent formation of a substrate, and the second semiconductor layer is used to provide a process basis for the subsequent formation of a fin.

[0036] In other embodiments, the substrate may also be other functional layers to be etched, such as a gate material layer.

[0037] In this embodiment, after providing the substrate 100 , the method for forming the semiconductor structure further includes: forming a pad oxide layer 110 on the substrate 100 ; forming a grinding stop layer 120 on the pad oxide layer 110 ; and forming a hard mask material layer 130 on the grinding stop layer 120 .

[0038] The pad oxide layer 110 is used to provide a buffering effect when forming the grinding stop layer 120, which is helpful to prevent the problem of dislocation when the grinding stop layer 120 is directly formed on the substrate 100. In this embodiment, the material of the pad oxide layer 110 is silicon oxide.

[0039] After the subsequent patterning of the base 100 to form a substrate and a fin protruding from the substrate, a step of forming an isolation structure on the substrate where the fin is exposed is usually included, and the process of forming the isolation structure usually includes a grinding process, and the grinding stop layer 120 is used to define the stop position of the grinding process.

[0040] In this embodiment, the material of the grinding stop layer 120 is silicon nitride.

[0041] The hard mask material layer 130 is used to form a hard mask layer after a subsequent etching process. After the sidewall is subsequently formed, the pattern of the sidewall is first transferred to the hard mask material layer 130. Even if the sidewall is damaged during the process of patterning the substrate 100, the substrate 100 can still be etched using the hard mask layer as a mask, which is beneficial to improving the process stability and process effect of the subsequent patterning of the substrate 100.

[0042] In addition, the subsequent process of forming a core layer separated from the substrate 100 and forming a sidewall generally includes a process combining deposition and etching. The top surface of the hard mask material layer 130 is also used to define the stop position of the etching process to avoid over-etching, thereby reducing the risk of damage to the substrate 100.

[0043] In this embodiment, the material of the hard mask material layer 130 is silicon oxide. In other embodiments, according to the materials of the substrate and the subsequent spacers, the material of the hard mask material layer can also be other suitable materials such as silicon nitride, silicon oxynitride, silicon oxycarbonitride or silicon.

[0044] Continue to refer Fig.13 , a separate core layer 140 is formed on the substrate 100 .

[0045] Subsequent steps also include: forming a side wall on the side wall of the core layer 140, and the core layer 140 is used to provide support for forming the side wall. The core layer 140 will be removed later, so the core layer 140 is selected from a material that is easy to remove, and the process of removing the core layer 140 causes less damage to other film layers, thereby reducing the difficulty of removing the core layer 140 later. The material of the core layer 140 includes amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, photoresist and other materials. In this embodiment, the material of the core layer 140 is amorphous silicon.

[0046] In this embodiment, the step of forming the core layer 140 includes: forming a core material layer (not shown) on the substrate 100 ; and patterning the core material layer, with the remaining core material layer serving as the core layer 140 .

[0047] refer to Fig.14 , a sidewall 21 is formed on the sidewall of the core layer 140 .

[0048] The sidewall spacer 21 is used as a mask for forming a fin portion by patterning the substrate 100, and the sidewall spacer 21 corresponds to the position of the fin portion. The fin portion formed by patterning the substrate 100 includes a device fin portion and a dummy fin portion.

[0049] In this embodiment, the sidewall 21 used to form the device fin is a mask sidewall 41, and the sidewall 21 used to form the dummy fin is a dummy mask sidewall 40, wherein the dummy mask sidewall 40 includes a first dummy sidewall 31 composed of multiple adjacent sidewalls 21, and a second dummy sidewall 32 composed of a single sidewall 21.

[0050] In this embodiment, the first dummy sidewall spacer 31 includes two adjacent sidewall spacers 21 as an example. In other embodiments, the first dummy sidewall spacer may include more than two sidewall spacers, which is not limited in the present invention.

[0051] The material of the sidewall 21 includes silicon oxide, silicon nitride, silicon oxynitride, silicon or titanium oxide, etc. In this embodiment, the material of the sidewall 21 is silicon nitride.

[0052] In this embodiment, the step of forming the side wall 21 includes: forming a side wall film (not shown) on the top and side wall of the core layer 140 and on the substrate 100 between the core layers 140; removing the side wall film on the top of the core layer 140 and on the substrate 100 between the core layers 140, and the remaining side wall film on the side wall of the core layer 140 is used as the side wall 21.

[0053] In this embodiment, the sidewall film is formed by an atomic layer deposition process.

[0054] In this embodiment, a dry etching process, for example, an anisotropic dry etching process, is used to remove the sidewall film on the substrate 100 located between the top of the core layer 140 and the core layer 140 .

[0055] refer to Fig.15 , remove the core layer 140 (such as Fig.14 The core layer 140 is removed to expose the substrate 100 at the bottom of the core layer 140, so as to prepare for subsequent patterning of the substrate 100.

[0056] In this embodiment, a wet etching process is used to etch and remove the core layer 140. Specifically, the material of the core layer 140 is amorphous silicon, and the etching solution used in the wet etching process is a mixed solution of Cl2 and HBr or a TMAH solution. In other embodiments, a dry etching process, or a process combining dry etching and wet etching, can also be used to remove the core layer.

[0057] Subsequent steps also include: using the sidewall 21 as a mask to pattern the substrate 100 .

[0058] Combined with reference Figure 16 to Figure 17 In this embodiment, after removing the core layer 140 and before patterning the substrate 100, the method for forming the semiconductor structure further includes: removing the second dummy sidewall 32 (such as Fig.16 shown).

[0059] In the present embodiment, the second dummy sidewall 32 is composed of a single sidewall 21. Compared with the solution of removing the first dummy sidewall before patterning the substrate, removing the second dummy sidewall 32 before patterning the substrate 100 is beneficial to reducing the impact on the spacing consistency between the remaining sidewalls 21. Accordingly, in the process of patterning the substrate 100 using the sidewall 21 as a mask to form a fin, the size uniformity and cross-sectional morphology uniformity of the fin are also high. Moreover, compared with the height of the fin, the height of the sidewall 21 is smaller. Therefore, compared with the solution of removing a single fin, it is less difficult to remove a single sidewall 21. Removing the second dummy sidewall 32 before patterning the substrate 100 is also beneficial to reducing the difficulty of removing the second dummy sidewall 32, thereby increasing the process window of the fin cut process.

[0060] Specifically, the height of the sidewall spacer 21 is relatively small, and during the process of removing the second dummy sidewall spacer 32 by etching, the etching time of the second dummy sidewall spacer 32 is relatively short, which is beneficial to reducing the risk of mis-etching the sidewall spacer 21 adjacent to the second dummy sidewall spacer 32 .

[0061] Specifically, the step of removing the second dummy sidewall 32 includes:

[0062] like Fig.16As shown, a filling layer 111 covering the sidewall 21 is formed on the substrate 100; a first anti-reflection coating 112 is formed on the filling layer 111; a first graphic layer 113 is formed on the first anti-reflection coating 112, and the first graphic layer 113 exposes the first anti-reflection coating 111 located on the second dummy sidewall 32.

[0063] The first pattern layer 113 is used as a mask for etching the filling layer 111 and the second dummy sidewall 32 .

[0064] In this embodiment, the material of the first pattern layer 113 is photoresist, and the first pattern layer 113 can be formed by photolithography processes such as spin coating, exposure, and development.

[0065] The filling layer 111 is used to provide a flat surface for forming the first anti-reflection coating 112 and the first pattern layer 113, thereby facilitating improving the accuracy of pattern transfer. In this embodiment, the material of the filling layer 111 is SOC (spin on carbon) material. The SOC material has a low cost, a simple formation process, high process compatibility, and a good filling performance.

[0066] The first anti-reflection coating 112 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern. In this embodiment, the first anti-reflection coating 112 is a Si-ARC layer (Si-based anti-reflection coating), which is beneficial to improving exposure uniformity, thereby further improving the transfer accuracy of the pattern.

[0067] like Fig.17 As shown, the first pattern layer 113 is used as a mask to sequentially etch the first anti-reflection coating 112, the filling layer 111 and the second dummy sidewall 32.

[0068] In this embodiment, a dry etching process is used, for example, an anisotropic dry etching process, to sequentially etch the first anti-reflective coating 112, the filling layer 111, and the second dummy sidewall 32. The anisotropic dry etching process has the characteristic of anisotropic etching, which is conducive to reducing the probability of lateral etching, thereby reducing the risk of damaging the adjacent sidewall 21; moreover, the dry etching process is conducive to achieving a higher etching selectivity.

[0069] In this embodiment, during the process of removing the second dummy sidewall spacer 32 , the dry etching process has an etching selectivity ratio of at least 5:1 between the second dummy sidewall spacer 32 and the hard mask material layer 130 .

[0070] In this embodiment, in the process of removing the second dummy sidewall 32, the etching gas of the dry etching process includes a main etching gas and an auxiliary etching gas. The main etching gas includes one or more of CxFy, CxHyFz and CxHy, and the auxiliary etching gas includes one or more of H2, O2, SO2, He and Ar. x, y and z are all positive integers.

[0071] In this embodiment, in the process of removing the second dummy sidewall 32, the first pattern layer 113 and the first anti-reflection coating 112 are gradually consumed, and after removing the second dummy sidewall 32, the first pattern layer 113 and the first anti-reflection coating 112 have been removed. Therefore, after removing the second dummy sidewall 32, the method for forming the semiconductor structure further includes: removing the filling layer 111. Specifically, the filling layer 111 can be removed by an ashing process.

[0072] refer to Fig.18 , remove the core layer 140 (such as Fig.14 As shown in the figure, the substrate 100 is patterned with the sidewall 21 as a mask to form a fin 200 , which includes a device fin 50 and a dummy fin 51 .

[0073] In this embodiment, before patterning the substrate 100, only the second dummy sidewall 32 composed of a single sidewall 21 is removed. The removal of the second dummy sidewall 32 has little effect on the consistency of the spacing between the sidewalls 21. During the process of patterning the substrate 100, the size consistency and profile consistency of the fin 200 are also high.

[0074] In this embodiment, the substrate 100 is patterned using the sidewall spacer 21 as a mask to form a substrate 210 and a fin 200 protruding from the substrate 210 .

[0075] In this embodiment, the fin 200 and the substrate 210 are an integrated structure. In other embodiments, when the substrate includes a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, in the step of etching the substrate, only the second semiconductor layer is etched, the first semiconductor layer is used as the substrate, and the remaining second semiconductor layer protruding from the first semiconductor layer is used as the fin. Accordingly, the material of the fin may also be different from that of the substrate.

[0076] The dummy fin 51 is the fin 200 to be removed, and the dummy fin 51 corresponds to the position of the fin cut.

[0077] In this embodiment, during the process of patterning the substrate 100 , the substrate 100 is patterned using the sidewall 21 as a mask, the device fin 50 is formed at a position corresponding to the mask sidewall 40 , and the dummy fin 51 is formed at a position corresponding to the first dummy sidewall 31 .

[0078] In this embodiment, the first dummy side wall 31 is composed of multiple adjacent side walls 21 . Therefore, after the dummy fin 51 is formed at the position corresponding to the first dummy side wall 31 , the number of the dummy fins 51 is also multiple, and the multiple dummy fins 51 are adjacent and form a dummy fin group 90 .

[0079] Accordingly, in this embodiment, the dummy fin group 90 has two adjacent dummy fins 51. In other embodiments, the number of dummy fins in the dummy fin group may be greater than two according to the number of spacers in the first dummy spacer.

[0080] In this embodiment, before the substrate 100 is patterned, the second dummy sidewall 32 composed of the single sidewall 21 is also removed. Therefore, after the substrate 210 and the fin 200 protruding from the substrate 210 are formed, the substrate 210 further includes a spacer 95 isolated from the dummy fin group 90 and corresponding to the position of the single fin cut, that is, the two device fins 50 located on both sides of the spacer 95 also have a spacer 95 corresponding to the position of the single fin cut. Accordingly, the spacer 95 corresponds to the position of the second dummy sidewall 32.

[0081] In this embodiment, the step of patterning the substrate 100 includes: using the sidewall 21 as a mask, sequentially etching the hard mask material layer 130 (such as Fig.17 As shown), a grinding stop layer 120 and a pad oxide layer 110.

[0082] In the process of patterning the substrate 100, the hard mask material layer 130 is patterned using the sidewall 21 as a mask to form a hard mask layer 150. Therefore, in this embodiment, in the process of patterning the substrate 100 to form the fin 200, a hard mask layer 150 is also formed on the top of the fin 200.

[0083] In this embodiment, a dry etching process, for example, an anisotropic dry etching process, is used to pattern the substrate 100. Specifically, in this embodiment, the etching gas of the dry etching process includes a main etching gas and an auxiliary etching gas, wherein the main etching gas includes one or more of CxFy, CxHyFz and CxHy, and the auxiliary etching gas includes one or more of H2, Cl2, HBr, Ar and He.

[0084] Continue to refer Fig.18 , remove the side wall 21.

[0085] In this embodiment, the sidewall spacer 21 is gradually consumed during the process of patterning the substrate 100 . Therefore, after the substrate 100 is patterned to form the fin 200 , the sidewall spacer 21 has been removed.

[0086] In other embodiments, when part of the sidewall spacer is still retained on the fin after the substrate is patterned to form the fin, an etching process may be used to remove the remaining sidewall spacer.

[0087] refer to Figures 19 to 23 , performing one or more doping removal treatments on the dummy fin 51 to remove the dummy fin 51; the doping removal treatment step includes: performing ion doping 80 (such as Fig.21 As shown), it is suitable for improving the etching selectivity ratio of the dummy fin 51 and the device fin 50; removing the dummy fin 51 doped with ions.

[0088] The dummy fins 51 are removed so that the device fins 50 have different pitch types.

[0089] In an embodiment of the present invention, the pseudo fin 51 is subjected to one or more doping removal treatments to remove the pseudo fin 51; the doping removal treatments include: ion doping the entire pseudo fin 51 or a partial thickness of the pseudo fin 51, which is suitable for improving the etching selectivity ratio of the pseudo fin 51 and the device fin 50; removing the pseudo fin 51 doped with ions, so that in the process of removing the pseudo fin 51, the etching selectivity of the pseudo fin 51 and the device fin 50 is relatively large, which is beneficial to reduce the probability of causing mis-etching to the device fin 50, thereby increasing the process window of the fin cut process, and further beneficial to improving the performance of the semiconductor structure.

[0090] In this embodiment, the material of the dummy fin 51 is amorphous silicon. In the step of performing ion doping 80 on the entire dummy fin 51 or a portion of the dummy fin 51 , the doping ions include argon ions, boron ions or arsenic ions.

[0091] Among them, by doping the dummy fin 51 with argon ions, it is beneficial to increase the roughness and looseness of the material of the dummy fin 51 doped with ions, so that the density and hardness of the material of the dummy fin 51 are reduced, and then the dummy fin 51 doped with argon ions is easier to remove, and the etching selectivity of the dummy fin 51 and the device fin 50 is correspondingly improved;

[0092] Compared with silicon, boron or arsenic has a smaller atomic radius. By doping the pseudo fin 51 with boron ions or arsenic ions, tensile stress can be generated in the silicon lattice structure, thereby forming dislocation defects in the material of the pseudo fin 51, making it easier to remove the ion-doped pseudo fin 51, thereby correspondingly improving the etching selectivity of the pseudo fin 51 and the device fin 50.

[0093] In other embodiments, other suitable ions may be selected to perform ion doping on the entire dummy fin or a portion of the thickness of the dummy fin to improve the etching selectivity between the dummy fin and the device fin, which is not limited in the present invention.

[0094] As an example, in this embodiment, the step of removing the dummy fin 51 includes performing a doping removal process once. In other embodiments, the step of removing the dummy fin may also include performing multiple doping removal processes.

[0095] The steps of the doping removal process described in this embodiment are described in detail below with reference to the accompanying drawings.

[0096] like Figures 19 to 21 As shown, the entire dummy fin 51 or a portion of the dummy fin 51 is ion doped 80. The ion doping 80 is suitable for improving the etching selectivity ratio between the dummy fin 51 and the device fin 50, thereby increasing the subsequent process window for removing the dummy fin 51 and reducing the probability of the process of removing the dummy fin 51 causing mis-etching of the device fin 50.

[0097] In this embodiment, ion doping is performed on a pseudo fin group 90 composed of multiple adjacent pseudo fins 51. Compared with ion doping 80 on a single pseudo fin 51, the area occupied by multiple pseudo fins 51 in the pseudo fin group 90 is larger, which is beneficial to reducing the difficulty of ion doping 80 on the pseudo fins 51, and is also beneficial to reducing the probability of ion doping into adjacent device fins 50.

[0098] In this embodiment, the step of removing the dummy fin 51 includes performing a doping removal process once, and accordingly, ion doping 80 is performed on the entire dummy fin 51 .

[0099] In the step of performing ion doping 80 on the entire dummy fin 51, the ion doping concentration in the dummy fin 51 should not be too small or too large. If the ion doping concentration in the dummy fin 51 is too small, the effect of the ion doping 80 for increasing the etching selectivity ratio between the dummy fin 51 and the device fin 50 is not obvious; if the ion doping concentration in the dummy fin 51 is too large, it is easy to increase the risk of ion doping into the adjacent device fin 50. For this reason, in this embodiment, the ion doping 80 is performed on the entire dummy fin 51, and the ion doping concentration in the dummy fin 51 is 1.0E18atom / cm 3 To 1.0E22atom / cm 3 .

[0100] In the present embodiment, the process of performing ion doping 80 on the entire dummy fin 51 includes an ion implantation process, and the parameters of the ion implantation process include: an implantation energy of 10 KeV to 200 KeV, and an implantation angle of 0°.

[0101] In this embodiment, ion doping 80 is performed on the entire dummy fin 51. The height of the dummy fin 51 is relatively large. Therefore, the injection energy of the ion implantation process should not be too small, so as to ensure that the ions can be implanted into the entire dummy fin 51, so that the ion doping depth in the dummy fin 51 is the height of the entire dummy fin 51; however, the injection energy of the ion implantation process should not be too large. When ion implantation is performed on the dummy fin 51, a shielding layer covering the device fin 50 is usually formed. If the injection energy is too large, the material of the shielding layer is usually a soft organic material. In order to ensure that the shielding layer can effectively block the ion implantation and prevent the ions from being implanted into the device fin 50, it is easy to cause the required thickness of the shielding layer to be too large. For this reason, in this embodiment, the injection energy of the ion implantation process is 10KeV to 200KeV.

[0102] In this embodiment, the injection angle is 0°, and the injection angle refers to the angle between the injection direction and the surface normal of the substrate 210. By setting the injection angle to 0°, ions can be injected into the pseudo fin 51 in a direction perpendicular to the surface of the substrate 210, which helps to reduce the probability of injecting ions into the device fin 50 adjacent to the pseudo fin 51, which is correspondingly beneficial to improving process stability.

[0103] It should also be noted that, combined with reference Figures 19 to 20 In this embodiment, in the step of removing the doping, before ion doping 80 is performed on the entire dummy fin 51 or a portion of the dummy fin 51, the method for forming the semiconductor structure further includes: forming a shielding layer 160 (such as Fig. 20 As shown), the shielding layer 160 has an opening 70 (as shown Fig. 20 As shown in FIG. 5 , the opening 70 is located above the dummy fin 51 and corresponds to the position of the dummy fin 51 .

[0104] The shielding layer 160 is used as a mask for ion doping of the dummy fin 51, which is helpful to prevent ions from being doped into the device fin 50. In this embodiment, the shielding layer 160 is made of spin-on carbon. In other embodiments, the shielding layer can also be other organic materials with good filling performance.

[0105] In the step of forming the blocking layer 160 , the opening 70 exposes the dummy fin 51 , or the opening 70 exposes the hard mask layer 150 on the dummy fin 51 .

[0106] In this embodiment, the opening 70 exposes the dummy fin 51 , so ion doping is performed on the dummy fin 51 at the bottom of the opening 70 , which helps to reduce the difficulty of ion doping on the dummy fin 51 .

[0107] The shielding layer 160 is used as a mask for ion doping of the pseudo fin 51. The shielding layer 160 is also used to protect the device fin 50. Therefore, when forming the shielding layer 160, the thickness of the shielding layer 160 located on the device fin 50 should not be too small, otherwise it is easy to reduce the blocking effect of the shielding layer 160 on ion implantation during the ion doping of the pseudo fin 51, and thus it is easy to reduce the protective effect of the shielding layer 160 on the device fin 50; the shielding layer 160 will be removed later, and the thickness of the shielding layer 160 located on the device fin 50 should not be too large, otherwise it is easy to increase the difficulty and time of removing the shielding layer 160 later. In this embodiment, the thickness of the shielding layer 160 is to

[0108] In the actual process, the thickness of the shielding layer 160 can be reasonably adjusted according to the actual ion implantation process parameters, such as ion implantation energy, to ensure that the shielding layer 160 can provide sufficient protection for the device fins 50. The thickness of the shielding layer 160 in the present invention is not limited to the above range.

[0109] In this embodiment, the steps of forming the shielding layer 160 include: Fig.19 As shown, a flat layer 121 covering the device fin 50 and the dummy fin 51, a second anti-reflection coating 122 located on the flat layer 121, and a second patterned layer 123 located on the second anti-reflection coating 122 are formed on the substrate 100, and the second patterned layer 123 has a pattern opening 60 exposing the second anti-reflection coating 122 located above the dummy fin 51; Fig. 20 As shown, using the second pattern layer 123 as a mask, the second anti-reflective coating 122 and the planar layer 121 are sequentially etched along the pattern opening 60 to form an opening 70 in the planar layer 121 , and the remaining planar layer 121 is used as the shielding layer 160 .

[0110] In the present embodiment, during the process of forming the second graphic layer 123, the position of the graphic opening 60 in the second graphic layer 123 corresponds to the pseudo fin group 90. Compared with the graphic opening corresponding to a single pseudo fin, the opening size of the graphic opening 60 formed in the present embodiment is larger. The second graphic layer 123 and the graphic opening 60 are formed by a photolithography process. Therefore, the process window for forming the photolithography process is larger.

[0111] For the description of the second anti-reflection coating 122 and the second graphic layer 123, reference may be made to the description of the first anti-reflection coating 112 (eg Fig.16 ) and the first graphic layer 113 (as shown Fig.16 The detailed description of this embodiment is not repeated here.

[0112] In this embodiment, a dry etching process, for example, an anisotropic dry etching process, is used to sequentially etch the second anti-reflection coating 122 and the planarization layer 121 .

[0113] In this embodiment, the opening 70 exposes the dummy fin 51, specifically, the opening 70 exposes the top of the dummy fin 51. Therefore, in the process of forming the opening 70, the etching depth of the planar layer 121 is small, and the dummy fin 51 does not need to be etched and removed, and the required etching time is correspondingly short, which is not only conducive to reducing the probability of the opening 70 exposing the adjacent device fin 50, but also, the opening 70 is formed by etching the planar layer 121 along the pattern opening 60, which is also conducive to reducing the requirement for overlay offset in the process of forming the pattern opening 60, thereby increasing the process tolerance and process window.

[0114] Therefore, in the step of forming the opening 70, after the second anti-reflective coating 122 and the planarization layer 121 are sequentially etched using the second pattern layer 123 as a mask, the hard mask layer 150 located on the dummy fin 51 is also etched away. Specifically, the pad oxide layer 110, the grinding stop layer 120, and the hard mask layer 150 located on the dummy fin 51 are etched away to expose the dummy fin 51.

[0115] In the present embodiment, in the step of removing the hard mask layer 150 located on the dummy fin 51, the etching selectivity ratio of the hard mask layer 150 to the shielding layer 160 is at least 5:1, thereby reducing the probability of causing mis-etching of the shielding layer 160, and further helping to prevent the opening 70 from exposing the adjacent device fin 50 or the hard mask layer 150 located on the adjacent device fin 50, which correspondingly helps to reduce the probability of doping ions into the device fin 50 during the subsequent ion doping process of the dummy fin 51.

[0116] As an example, in the step of removing the hard mask layer 150 located on the dummy fin 51, the etching selectivity ratio of the hard mask layer 150 to the device fin 50 is at least 5:1. The etching selectivity between the hard mask layer 150 and the device fin 50 is relatively large, which is beneficial to significantly reduce the probability of mis-etching the device fin 50.

[0117] In this embodiment, during the process of forming the opening 70 , the second pattern layer 123 and the second anti-reflection coating 122 are gradually consumed, so that after the opening 70 is formed, the second pattern layer 123 and the second anti-reflection coating 122 have been removed.

[0118] In this embodiment, the opening 70 exposing the dummy fin 51 is used as an example. In other embodiments, the opening may also only expose the hard mask layer on the dummy fin. In this embodiment, the depth of the opening is small. In the process of etching the flat layer to form the opening, the etching depth of the flat layer is smaller, and the aspect ratio of the opening is also smaller, which is beneficial to reduce the process difficulty of forming the opening. Accordingly, in the process of ion doping the entire dummy fin or a partial thickness of the dummy fin, the injection energy of the ion injection process can be appropriately adjusted so that the ion injection process can inject ions into the dummy fin through the hard mask layer.

[0119] Combined with reference Fig. 22 In this embodiment, the step of removing the doping process further includes: after ion doping 80 is performed on the entire dummy fin 51 or a portion of the thickness of the dummy fin 51 , removing the shielding layer 160 .

[0120] In the present embodiment, the subsequent process of removing the pseudo fin 51 doped with ions is taken as an example of a wet etching process. The material of the shielding layer 160 is generally an organic material. By removing the shielding layer 160 before removing the pseudo fin 51 doped with ions, it is beneficial to prevent the shielding layer 160 from contaminating the machine of the subsequent wet etching process, thereby helping to improve the process compatibility; moreover, removing the shielding layer 160 can also expose the side wall of the pseudo fin 51, which is beneficial to increase the contact area between the etching solution of the wet etching process and the pseudo fin 51, thereby facilitating the removal of the pseudo fin 51 to reduce the probability of residual pseudo fin 51.

[0121] In this embodiment, an ashing process is used to remove the shielding layer 160 .

[0122] In other embodiments, according to actual process requirements, the shielding layer can also be removed after removing the dummy fins doped with ions. For example, when a subsequent plasma etching process is used to remove the dummy fins doped with ions, the shielding layer can also be used as an etching mask for the plasma etching process, which is beneficial to reduce the probability of mis-etching the device fins and is also beneficial to improving process integration.

[0123] like Fig.23 As shown, the dummy fin 51 doped with ions is removed (as shown in FIG. Fig. 22 shown).

[0124] In this embodiment, ion doping is performed on the entire dummy fin 51 as an example, and therefore, the entire dummy fin 51 doped with ions is removed.

[0125] In the step of removing the dummy fin 51 doped with ions, the etching selectivity ratio of the dummy fin 51 and the device fin 50 is at least 10:1, the etching selectivity of the dummy fin 51 and the device fin 50 is relatively high, and the probability of damage to the device fin 50 is low, which is conducive to increasing the process window for removing the dummy fin 51 doped with ions.

[0126] In this embodiment, a wet etching process is used to remove the dummy fin 51 doped with ions. The wet etching process is easy to achieve a large etching selectivity ratio, and the operation of the wet etching process is simple and the process cost is low; moreover, the wet etching process has the characteristic of isotropic etching, and the dummy fin 51 is easy to be removed cleanly.

[0127] Specifically, after removing the blocking layer 160 , the embodiment of the present invention uses a wet etching process to remove the ion-doped pseudo fin 51 , so that the etching solution contacts the top surface and side wall of the pseudo fin 51 , which is beneficial to cleanly remove the pseudo fin 51 and further helps to reduce the probability of residual pseudo fin 51 .

[0128] In other embodiments, the process for removing the dummy fin doped with ions may also be a plasma etching process. By adopting the plasma etching process, it is advantageous to perform ion implantation and plasma etching processes in the same plasma equipment, thereby simplifying the process steps and improving the process integration.

[0129] In this embodiment, the etching solution of the wet etching process includes an HNA solution. The HNA solution refers to a mixed solution of hydrofluoric acid, nitric acid, and acetic acid. Compared with the etching rate of the HNA solution on silicon not doped with ions, the etching rate of the HNA solution on silicon doped with the above ions is greater. By selecting the HNA solution, it is beneficial to improve the etching selectivity of the wet etching process for the pseudo fin 51 doped with ions and the device fin 50, thereby significantly reducing the probability of damage to the device fin 50.

[0130] As an example, the parameters of the wet etching process include: in the mixed solution of hydrofluoric acid, nitric acid and acetic acid, the volume ratio of hydrofluoric acid, nitric acid and acetic acid water is 1:1:1 to 1:4:8. By setting the volume ratio of hydrofluoric acid, nitric acid and acetic acid within the above range, it is ensured that the HNA solution can have a larger etching selectivity ratio for the dummy fin 51 doped with ions and the device fin 50.

[0131] It should be noted that, in the actual process, while setting the volume ratio of hydrofluoric acid, nitric acid and acetic acid within the above range, the volume ratio of these three acids (hydrofluoric acid, nitric acid and acetic acid) to water can also be adjusted to adjust the etching rate of the HNA solution on the ion-doped pseudo fin 51. The present invention does not limit the volume ratio of these three acids to water.

[0132] During the actual wet etching process, the etching solution may be subjected to an oscillation treatment. For example, an ultrasonic etching solution may be used to etch the dummy fin 51 , which is beneficial to improving the etching rate of the dummy fin 51 .

[0133] Subsequent steps generally include: removing the pad oxide layer 110, the grinding stop layer 120, and the hard mask layer 150, etc. The subsequent process steps will not be described in detail in this embodiment.

[0134] Accordingly, the method for forming a semiconductor structure of the present invention also provides another embodiment. The similarities between this embodiment and the previous embodiment are not repeated here. The difference between this embodiment and the previous embodiment is that: the step of removing the dummy fin includes performing multiple doping removal treatments. Accordingly, the doping treatment includes: ion doping of a partial thickness of the dummy fin; and removing the dummy fin doped with ions.

[0135] In this embodiment, the doping process is repeated multiple times until the dummy fins are completely removed.

[0136] In this embodiment, during each doping process, ion doping is only performed on a partial thickness of the dummy fin, that is, the doping depth of each ion doping is only a partial height of the dummy fin, which helps to reduce the difficulty of ion doping the dummy fin.

[0137] For the detailed description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the aforementioned embodiments, and this embodiment will not be described in detail here.

[0138] Accordingly, the present invention also provides a semiconductor structure. Fig. 22 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0139] The semiconductor structure includes: a substrate 210; a fin 200 separated from the substrate 210, including a device fin 50 and a dummy fin 51, wherein the dummy fin 51 has doped ions, and the doped ions are suitable for improving the etching selectivity between the dummy fin 51 and the device fin 50.

[0140] The device fin 50 is used to form a semiconductor device. Specifically, the device fin 50 is used to provide a conductive channel when the device is working. The dummy fin 51 is the fin 200 to be removed. After the dummy fin 51 is removed, it is beneficial to have different types of spacing between the device fins 50.

[0141] In the semiconductor structure provided by the embodiment of the present invention, the pseudo fin 51 also has doped ions, and the doped ions are suitable for improving the etching selectivity of the pseudo fin 51 and the device fin 50; the pseudo fin 51 will be removed subsequently. Therefore, by making the pseudo fin 51 also have doped ions having the doped ions, it is beneficial for the subsequent process of removing the pseudo fin 51 to have a larger etching selectivity between the pseudo fin 51 and the device fin 50, thereby helping to reduce the probability of causing mis-etching to the device fin 50, and further helping to increase the process window of the fin cutting process and improve the performance of the semiconductor structure.

[0142] The substrate 210 is used to provide a process platform for forming a semiconductor structure.

[0143] In this embodiment, the material of the substrate 210 is silicon.

[0144] In this embodiment, the fin 200 and the substrate 210 are an integrated structure.

[0145] In this embodiment, the fin 200 is made of the same material as the substrate 100 , that is, silicon.

[0146] In this embodiment, the doping ions in the dummy fin 51 include argon ions, boron ions or arsenic ions.

[0147] Among them, by doping the material of the pseudo fin 51 with argon ions, it is beneficial to increase the roughness and looseness of the material of the pseudo fin 51 doped with ions, so that the density and hardness of the material of the pseudo fin 51 are smaller, thereby making the pseudo fin 51 doped with argon ions easier to remove, and correspondingly improving the etching selectivity of the pseudo fin 51 and the device fin 50; compared with silicon, boron or arsenic has a smaller atomic radius. By doping the pseudo fin 51 with boron ions or arsenic ions, tensile stress can be generated in the lattice structure of silicon, thereby forming dislocation defects in the material of the pseudo fin 51, thereby making the pseudo fin 51 doped with ions easier to remove, and thereby improving the etching selectivity of the pseudo fin 51 and the device fin 50.

[0148] In some other embodiments, the dummy fins may be doped with other suitable ions to improve the etching selectivity ratio between the dummy fins and the device fins, which is not limited in the present invention.

[0149] In this embodiment, the doping depth of ions in the dummy fin 51 is the entire height of the dummy fin 51 .

[0150] The doping concentration of the ions in the dummy fin 51 should not be too small, otherwise the effect of the doped ions in increasing the etching selectivity between the dummy fin 51 and the device fin 50 is not obvious; the doping concentration of the ions in the dummy fin 51 should not be too high, otherwise it is easy to increase the risk of doping the ions into the adjacent device fin 50. For this reason, in this embodiment, the doping depth of the ions in the dummy fin 51 is the entire height of the dummy fin 51, and the ion doping concentration in the dummy fin 51 is 1.0E18atom / cm 3 To 1.0E22atom / cm 3 .

[0151] In this embodiment, the dummy fin 51 corresponds to the position of a fin cut. There are multiple dummy fins 51 , and the multiple dummy fins 51 are adjacent to each other and form a dummy fin group 90 .

[0152] In this embodiment, the dummy fin group 90 having two adjacent dummy fins 51 is taken as an example. In other embodiments, the number of dummy fins in the dummy fin group may be greater than two.

[0153] In this embodiment, the multiple dummy fins 51 in the dummy fin group 90 are doped with ions, that is, the multiple dummy fins 51 in the dummy fin group 90 are removed in the subsequent process steps. Compared with the solution of removing the first dummy side wall used to form the dummy fin group 90 in the previous process, the present invention can subsequently remove the dummy fin group 90 having multiple adjacent dummy fins 51 through a fin post-cutting process, which is beneficial to improving the size uniformity and cross-sectional morphology uniformity of the fins 200.

[0154] Moreover, in the present embodiment, the plurality of dummy fins 51 in the dummy fin group 90 are doped with ions, which is helpful to reduce the difficulty of ion doping for the dummy fins 51 compared with doping ions in a single dummy fin.

[0155] In this embodiment, the substrate 210 also includes a gap 95 isolated from the pseudo fin group 90 and corresponding to the position of a single fin cut, that is, there is also a gap 95 corresponding to the position of a single fin cut between the two device fins 50 located on both sides of the gap 95. The substrate 210 has the gap 95 because the second pseudo side wall corresponding to the position of the single fin cut is removed before forming the fin 200. The second pseudo side wall is correspondingly composed of a single side wall. Before forming the fin 200, the second pseudo side wall composed of a single side wall is removed, which is beneficial to reduce the impact on the uniformity of the spacing between the remaining side walls, and is correspondingly beneficial to improving the size uniformity and cross-sectional morphology consistency of the fin 200. Moreover, the height of the side wall is less than the height of the fin 200. Compared with removing a single fin 200, the process difficulty of removing a single side wall is less, which is beneficial to reducing the difficulty of the fin cutting process.

[0156] In this embodiment, the semiconductor structure further includes: a pad oxide layer 110 located on the top of the device fin 50 ; a grinding stop layer 120 located on the pad oxide layer 110 ; and a hard mask layer 150 located on the grinding stop layer 120 .

[0157] The pad oxide layer 110 is used to provide a buffer for the grinding stop layer 120, which is helpful to prevent the grinding stop layer 120 from being dislocated on the device fin 50. In this embodiment, the material of the pad oxide layer 110 is silicon oxide.

[0158] After removing the dummy fin 51 , subsequent process steps generally include: forming an isolation structure on the substrate 210 where the device fin 50 is exposed, and the process of forming the isolation structure generally includes a grinding process, and the grinding stop layer 120 is used to define the stop position of the grinding process.

[0159] In this embodiment, the material of the grinding stop layer 120 is silicon nitride.

[0160] The fin 200 is formed by patterning the substrate using the side wall as a mask. By setting the hard mask layer 150, during the process of patterning the substrate, the pattern of the side wall can be first transferred to the hard mask layer 150. Even if the side wall is damaged during the process of patterning the substrate, the substrate can still be etched using the hard mask layer 150 as a mask, which is beneficial to improving the process stability and process effect of the patterned substrate.

[0161] In this embodiment, the material of the hard mask layer 150 is silicon oxide.

[0162] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0163] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a discrete core layer on the substrate; Forming sidewalls on the sidewalls of the core layer, the sidewalls are used as masks for forming fins on the patterned substrate, and the sidewalls correspond to the positions of the fins one by one, wherein the sidewalls used to form the device fins are mask sidewalls, and the sidewalls used to form the dummy fins are dummy mask sidewalls, and the dummy mask sidewalls include a first dummy sidewall composed of a plurality of adjacent sidewalls, and a second dummy sidewall composed of a single sidewall; removing the core layer; After removing the core layer, removing the second dummy sidewall; After removing the second dummy sidewall spacer, the substrate is patterned using the sidewall spacer as a mask to form a fin portion, wherein the fin portion includes a device fin portion and a dummy fin portion, wherein the device fin portion is formed at a position corresponding to the mask sidewall spacer, and the dummy fin portion is formed at a position corresponding to a plurality of the dummy mask sidewall spacers in the first dummy sidewall spacer; removing the side wall; The pseudo fin is subjected to one or more doping removal treatments to remove the pseudo fin; the steps of the doping removal treatments include: ion doping the entire pseudo fin or a portion of the thickness of the pseudo fin, suitable for improving the etching selectivity between the pseudo fin and the device fin; and removing the pseudo fin doped with ions.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of performing ion doping on the entire dummy fin or a portion of the thickness of the dummy fin, the doping ions include argon ions, boron ions or arsenic ions.

3. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing the dummy fins includes: performing a doping removal process once; The doping removal process includes: performing ion doping on the entire dummy fin; and removing the dummy fin doped with ions.

4. The method for forming a semiconductor structure according to claim 3, wherein: In the step of ion doping the entire dummy fin, the ion doping concentration in the dummy fin is 1.0E18atom / cm 3 To 1.0E22atom / cm 3 .

5. The method for forming a semiconductor structure according to claim 3, wherein: The process of performing ion doping on the entire dummy fin includes an ion implantation process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The parameters of the ion implantation process include: an implantation energy of 10 KeV to 200 KeV, and an implantation angle of 0°.

7. The method for forming a semiconductor structure according to claim 1, wherein: In the step of doping removal, before ion doping the entire dummy fin or a partial thickness of the dummy fin, the method for forming the semiconductor structure also includes: forming a shielding layer covering the device fin, the shielding layer having an opening, the opening being located above the dummy fin and corresponding to the position of the dummy fin.

8. The method for forming a semiconductor structure according to claim 7, wherein: In the process of patterning the substrate, a hard mask layer is also formed on the top of the fin; In the step of forming the blocking layer, the opening exposes the dummy fin, or the opening exposes the hard mask layer on the dummy fin.

9. The method for forming a semiconductor structure according to claim 7, wherein: The step of doping removal further includes: after ion doping the entire dummy fin or a portion of the dummy fin thickness, and before removing the dummy fin doped with ions, removing the blocking layer.

10. The method for forming a semiconductor structure according to claim 7, wherein: In the step of forming the shielding layer, the thickness of the shielding layer located on the device fin is to 11. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the dummy fin doped with ions, an etching selectivity ratio between the dummy fin and the device fin is at least 10:

1.

12. The method for forming a semiconductor structure according to claim 1, wherein: The process of removing the dummy fin doped with ions includes a wet etching process or a plasma etching process.

13. The method for forming a semiconductor structure according to claim 12, wherein: The dummy fin doped with ions is removed by a wet etching process, wherein an etching solution of the wet etching process includes a mixed solution of hydrofluoric acid, nitric acid and acetic acid.

14. The method for forming a semiconductor structure according to claim 13, wherein: The parameters of the wet etching process include: in the mixed solution of hydrofluoric acid, nitric acid and acetic acid, the volume ratio of hydrofluoric acid, nitric acid and acetic acid is 1:1:1 to 1:4:

8.

15. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that: include: substrate; The fins separated from the substrate include device fins and dummy fins, wherein the dummy fins have doped ions, and the doped ions are suitable for improving the etching selectivity between the dummy fins and the device fins; The dummy fin portion corresponds to a position of the fin cut, the number of the dummy fin portions is multiple, and the multiple dummy fin portions are adjacent to each other and form a dummy fin portion group; The substrate also includes a spacer isolated from the dummy fin group and corresponding to a location of a single fin cut.

16. The semiconductor structure according to claim 15, wherein: The doping ions include argon ions, boron ions or arsenic ions.

17. The semiconductor structure according to claim 15, wherein: The doping depth of the ions in the dummy fin is the entire height of the dummy fin, and the doping concentration of the ions in the dummy fin is 1.0E18atom / cm 3 To 1.0E22atom / cm 3 .

Images