Semiconductor device structure and method for forming the same

Abstract

A semiconductor device structure and a method for forming the same, wherein the structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed on the substrate, and a first passivation layer disposed on the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed on the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed on the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each include a nitride.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device structure and a method for forming the same, and more particularly to a semiconductor device structure including a redistribution layer and a method for forming the same. Background Art

[0002] In the formation of an integrated circuit, devices such as transistors are formed on a semiconductor substrate. An interconnect structure is then formed on the integrated circuit device. A redistribution layer (RDL) is formed on the interconnect structure. The redistribution layer includes at least a conductive feature and a passivation layer, and the conductive feature is electrically connected to the interconnect structure. The passivation layer is formed on the conductive feature.

[0003] However, different materials of the redistribution layer may have different thermal expansion coefficients. The mismatch of thermal expansion coefficients of the redistribution layer leads to the formation of cracks extending from the redistribution layer to the interconnect structure, which may cause device failure. Therefore, there is a need to solve the above problem. Summary of the invention

[0004] According to an embodiment of the present disclosure, a semiconductor device structure is provided, including a substrate having one or more devices thereon, one or more bonding pads disposed on the substrate, and a first passivation layer disposed on the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed on the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer includes a third passivation sublayer disposed on the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first passivation sublayer, the second passivation sublayer, and the third passivation sublayer each include a nitride.

[0005] According to an embodiment of the present disclosure, a semiconductor device structure is provided, including a substrate having one or more devices thereon, an interconnect structure disposed on the substrate, one or more bonding pads disposed on the interconnect structure, and a first passivation layer disposed on the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed on the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer includes a third passivation sublayer disposed on the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least one of the first passivation sublayer, the second passivation sublayer, and the third passivation sublayer is a nitride layer, and its thickness is at least 40% of the total thickness of the first passivation layer.

[0006] According to an embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, including forming one or more devices on a substrate, forming a first dielectric layer on the one or more devices, forming an opening in the first dielectric layer, forming a first conductive feature in the opening, forming a bonding pad on the first conductive feature, and forming a second dielectric layer on the bonding pad and the first dielectric layer. Forming the second dielectric layer includes forming a first sublayer including a first material on the bonding pad and the first dielectric layer. Forming the second dielectric layer also includes forming a second sublayer on the first sublayer, and the second sublayer includes a second material different from the first material. Forming the second dielectric layer also includes forming a third sublayer on the second sublayer, and the third sublayer includes a third material different from the second material. At least two of the first sublayer, the second sublayer, and the third sublayer each include a nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard methods in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a cross-sectional view of a semiconductor device structure according to some embodiments;

[0009] Figure 2 is a flow chart of a method for manufacturing a semiconductor device structure according to some embodiments;

[0010] Figure 3A and Figure 3B According to some embodiments, Figure 1 A cross-sectional view of a redistribution layer at a stage during the fabrication of a semiconductor device structure;

[0011] Figure 4 According to some embodiments of the invention Figure 1 A flow chart of a method for redistributing a semiconductor device structure;

[0012] FIG. 5A to FIG. 5I According to some embodiments, Figure 4 a cross-sectional view of a redistribution layer during various manufacturing stages of a method of;

[0013] Fig. 6A is a cross-sectional view of a passivation layer disposed on a plurality of conductive features according to some embodiments;

[0014] Figure 6B According to some embodiments Fig. 6A A top view of multiple conductive features.

[0015]

Explanation of symbols

[0016] 100:Semiconductor device structure

[0017] 102:Substrate

[0018] 104: Isolation Features

[0019] 106: Active Zone

[0020] 110: Installation

[0021] 120: Interconnection structure

[0022] 122: Interlayer dielectric

[0023] 124,126: Conductive characteristics

[0024] 140: Redistribution layer

[0025] 144: first passivation layer

[0026] 144A: first passivation sublayer

[0027] 144B: second passivation sublayer

[0028] 146: Second passivation layer

[0029] 146A: first passivation sublayer

[0030] 146B: second passivation sublayer

[0031] 146C: third passivation sublayer

[0032] 146D: fourth passivation sublayer

[0033] 146E: Fifth passivation sublayer

[0034] 150: Conductive characteristics

[0035] 152: Conductive characteristics

[0036] 154: Under Bump Metal Layer

[0037] 156: Conductive structure

[0038] 200: Method

[0039] 202,204,206: Steps

[0040] 400: Method

[0041] 402,404,406,408,410,412,414,416,418,420: Steps

[0042] 500:Substrate

[0043] 501: Conductive characteristics

[0044] 502: Dielectric material

[0045] 503: Conductive surface

[0046] 504: first dielectric layer

[0047] 505: Dielectric surface

[0048] 506: second dielectric layer

[0049] 507: Opening

[0050] 508: Conductive characteristics

[0051] 510: Conductive characteristics

[0052] 512: third dielectric layer

[0053] 514: fourth dielectric layer

[0054] 516: fifth dielectric layer

[0055] 518: Sixth dielectric layer

[0056] 520: seventh dielectric layer

[0057] 602A, 602B, 602C, 602D: Conductive characteristics

[0058] 604A, 604B, 604C, 604D: Conductive characteristics

[0059] 606A, 606B, 606C, 606D: Conductive characteristics

[0060] T1,T2,T3,T4,T5,T6,T7,T8,T9,T10:Thickness

[0061] W1: First width

[0062] W2: Second width

[0063] D1,D2,D3: distance DETAILED DESCRIPTION

[0064] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0065] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to facilitate describing one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0066] Figure 1 is a cross-sectional view of a semiconductor device structure 100 according to some embodiments. Figure 2 is a flow chart of a method 200 of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 and Figure 2 , together with a semiconductor device structure 100 and a method 200 for manufacturing the semiconductor device structure 100 are described. The semiconductor device structure 100 may be an integrated circuit (IC) structure having a plurality of integrated circuit (IC) devices, such as transistors, diodes, sensors, memory cells, or a combination thereof.

[0067] The semiconductor device structure 100 includes a substrate 102. The substrate 102 may be a semiconductor substrate, such as a bulk silicon substrate. In some embodiments, the substrate 102 may be an elemental semiconductor, such as crystalline silicon or germanium, a compound semiconductor (e.g., silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), other suitable materials, or combinations thereof. Possible substrates 102 may also include silicon-on-insulator (SOI) substrates. SOI substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0068] The substrate 102 also includes various isolation features, such as isolation features 104 formed on the substrate 102 and defining various active regions 106 on the substrate 102. The isolation features 104 use isolation techniques such as shallow trench isolation (STI) to define and electrically insulate the various active regions 106. The isolation features 104 can be made of silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The isolation features 104 are formed by any suitable process. As an example, forming shallow trench isolation features includes a lithography process to expose a portion of the substrate 102, etching a trench in the exposed portion of the substrate 102 (e.g., by using dry etching and / or wet etching), filling the trench with one or more dielectric materials (e.g., by using a chemical vapor deposition process), and planarizing the substrate 102 and removing excess portions of the dielectric material by a polishing process (e.g., a chemical mechanical polishing (CMP) process). In some embodiments, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer and a silicon oxide filling layer.

[0069] The active region 106 is a region having various features that may be part of one or more devices 110, such as transistors, diodes, image sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices. The active region 106 may include a semiconductor material similar to the bulk semiconductor material of the substrate 102 (such as silicon) or a different semiconductor material, such as silicon germanium, silicon carbide, or multiple semiconductor material layers (such as alternative silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth to enhance performance (such as strain effects to increase carrier mobility). In some embodiments, the active region 106 is three-dimensional, and the devices 110 in the active region 106 may be three-dimensional devices, such as field-effect transistors (FinFETs), nanosheet transistors, or other suitable three-dimensional devices.

[0070] The substrate 102 may include various doped features, such as n-type doped wells, p-type doped wells, sources and drains, other doped features, or combinations thereof, configured to form various devices 110 or elements of the devices 110 .

[0071] The semiconductor device structure 100 further includes an interconnect structure 120 formed on the substrate 102, such as on the active region 106 and the isolation features 104. The interconnect structure 120 includes various conductive features, such as a first plurality of conductive features 124 and a second plurality of conductive features 126, and an interlayer dielectric (ILD) 122 for separating and isolating the various conductive features 124, 126. In some embodiments, the first plurality of conductive features 124 are conductive vias, and the second plurality of conductive features 126 are conductive lines. The interconnect structure 120 includes multiple levels of conductive features 126, and the conductive features 126 are arranged in each level to provide electrical paths to various devices 110 disposed below. The conductive features 124 provide vertical circuits from the substrate 102 to the conductive features 126 and between the conductive features 126. The conductive features 124 and the conductive features 126 can be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive features 124 and conductive features 126 are made of copper, aluminum, aluminum-copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, titanium silicide, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, tungsten silicide, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof. A conductive contact (not shown) may be formed between device 110 and conductive features 124, and the conductive contact may be made of tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof.

[0072] The interlayer dielectric 122 includes one or more dielectric materials to provide insulation functions to various device components (e.g., gates) and various conductive features (e.g., wires, vias, and contacts). The interlayer dielectric 122 may include multiple dielectric layers embedded with multiple levels of conductive features 124 and conductive features 126. The interlayer dielectric 122 is made of a dielectric material, such as silicon oxide, a low-k dielectric material, other suitable dielectric materials, or a combination thereof. In some embodiments, the low-k dielectric material includes fluorinated quartz glass, carbon-doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, bisbenzocyclobutene, polyimide, and / or other suitable dielectric materials having a dielectric constant substantially less than that of thermal silicon oxide. In some embodiments, the interlayer dielectric 122 includes silicon oxide, silicon oxycarbide, one or more porous low-k dielectric materials, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, high-density plasma oxide formed by a high-density plasma chemical vapor deposition (HDP-CVD) process or other suitable process, spin-on glass, polyimide, other suitable materials or combinations thereof. For example, the formation of the interlayer dielectric 122 includes deposition and chemical mechanical polishing processes. Deposition may include spin coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition, other suitable deposition techniques or combinations thereof. The interlayer dielectric 122 may include multiple layers and may be formed together with various conductive features using a suitable process (e.g., a damascene process).

[0073] In some embodiments, the interconnect structure 120 or a portion thereof is formed by deposition and patterning. For example, a conductive material such as aluminum copper is deposited by physical vapor deposition (PVD) and then patterned by lithography and etching processes. An interlayer dielectric 122 is then formed on the aluminum copper by a deposition process such as chemical vapor deposition or plasma enhanced chemical vapor deposition. In some embodiments, the conductive features 124 and 126 are formed by a damascene process. A dual damascene process may be performed to form a conductive feature 126 at one level and a conductive feature 124 below the conductive feature 126.

[0074] The semiconductor device structure 100 further includes a redistribution layer (RDL) 140 disposed on the interconnect structure 120 to redistribute the bonding pads. The RDL 140 helps to arrange the bonding pads, such as from the edge to the center of the integrated circuit die for flip chip bonding or other suitable packaging technology to integrate the integrated circuit die into a board (e.g., a printed circuit board).

[0075] The redistribution layer 140 includes one or more passivation layers and conductive features formed in the one or more passivation layers. In some embodiments, the redistribution layer 140 includes a first passivation layer 144 and a second passivation layer 146 disposed on the first passivation layer 144. The first passivation layer 144 may be a single layer of dielectric material, such as silicon oxide, silicon oxycarbide, one or more porous low dielectric constant dielectric materials, undoped silicon oxide glass, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, high-density plasma oxide formed by a high-density plasma chemical vapor deposition process or other suitable process, spin-on glass, polyimide, other suitable materials or combinations thereof. In some embodiments, the first passivation layer 144 includes a multilayer stack of dielectric materials. For example, the first passivation layer 144 may include a silicon nitride layer and an undoped silicon oxide glass layer disposed on the silicon nitride layer. Other configurations of the first passivation layer 144 are within the scope of the present disclosure. The second passivation layer 146 includes a multi-layer stack of dielectric materials and is described in further detail below.

[0076] Redistribution layer 140 includes conductive feature 150 and conductive feature 152. Conductive feature 150 may be a conductive via, and conductive feature 152 may be a bonding pad. Figure 1 As shown, one or more conductive features 150 may be disposed in the first passivation layer 144, and the conductive features 150 may be aligned with and in contact with corresponding conductive features 126 located on top of the interconnect structure 120. One or more conductive features 152 may be disposed on corresponding conductive features 150 located in the first passivation layer 144. The second passivation layer 146 may be disposed on the conductive features 152 and on the first passivation layer 144.

[0077] One or more under bump metallurgy (UBM) layers 154 are disposed in the second passivation layer 146 and contact the corresponding conductive features 152. Conductive structures 156 are formed on each under bump metal layer 154. The under bump metal layer 154 is made of a conductive material, such as copper, aluminum, tungsten, titanium, tantalum, other suitable conductive materials, alloys thereof, or combinations thereof. The under bump metal layer 154 may include an adhesion layer and / or a wetting layer. In some embodiments, the under bump metal layer 154 further includes a seed layer. The conductive structure 156 may be a spherical bump or a columnar object. The conductive structure 156 is made of a conductive material, such as tin, copper, gold, silver, alloys thereof, other suitable materials, or combinations thereof.

[0078] Figure 2 2 is a flow chart of a method 200 for manufacturing a semiconductor device structure 100 according to some embodiments. Some manufacturing details are provided above and will not be repeated here. The method 200 begins at step 202, where a plurality of devices 110 are formed on a substrate 102. Isolation features 104 may have been formed on the substrate 102. In step 204, an interconnect structure 120 is formed on the plurality of devices 110. In step 206, a redistribution layer 140 is formed on the interconnect structure 120. The redistribution layer 140 includes a second passivation layer 146, which can reduce the formation of cracks in the second passivation layer 146 and / or confine the cracks within the second passivation layer 146. The method 200 may include other steps before, during, or after the above steps. The method of forming the redistribution layer 140 is described in detail below.

[0079] Figure 3A According to some embodiments, Figure 1 FIG. 1 is a cross-sectional view of a redistribution layer 140 at a stage during the fabrication of the semiconductor device structure 100 . Figure 3AAs shown, in some embodiments, the redistribution layer 140 includes a first passivation layer 144, and the first passivation layer 144 has a first passivation sublayer 144A and a second passivation sublayer 144B disposed on the first passivation sublayer 144A. The first passivation sublayer 144A is made of a dielectric material, such as silicon oxide, silicon oxycarbide, one or more porous low-k dielectric materials, undoped silicon oxide glass, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, silicon nitride, silicon oxynitride, silicon oxycarbonitride, high-density plasma oxide formed by a high-density plasma chemical vapor deposition process or other suitable process, spin-on glass, polyimide, other suitable materials or combinations thereof. The second passivation sublayer 144B is made of a dielectric material, such as silicon oxide, silicon oxycarbide, one or more porous low dielectric constant dielectric materials, undoped silica glass, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, high-density plasma oxide formed by a high-density plasma chemical vapor deposition process or other suitable process, spin-on glass or polyimide. The dielectric material of the second passivation sublayer 144B is different from the dielectric material of the first passivation sublayer 144A. In one embodiment, the first passivation sublayer 144A is silicon nitride and the second passivation sublayer 144B is undoped silica glass. Other configurations of the first passivation layer 144 are within the scope of the present disclosure. The first passivation sublayer 144A has a thickness T1 in the range of about 50 nanometers to about 100 nanometers. The second passivation sublayer 144B has a thickness T2 in the range of about 500 nanometers to about 1000 nanometers.

[0080] Conductive features 150 are disposed in the first passivation sublayer 144A and the second passivation sublayer 144B. The conductive features 150 extend through the first passivation sublayer 144A and the second passivation sublayer 144B. Conductive features 152 are disposed on the respective conductive features 150. The second passivation layer 146 is disposed on the first passivation layer 144 and the conductive features 152. Due to the mismatch in thermal expansion coefficients between the conductive features 152 and the dielectric material in the redistribution layer 140, tensile stress is induced in the conductive features 152. The tensile stress induced in the conductive features 152 causes the conductive features 152 to warp to form a concave shape, which in turn causes one or more cracks to form in the redistribution layer 140. The cracks may propagate into the interconnect structure 120, causing device failure. To address this problem, a second passivation layer 146 having a multi-layer stack is used. In some embodiments, the second passivation layer 146 includes a nitride layer having a thickness of at least 40% (eg, about 40% to about 80%) of the total thickness of the second passivation layer 146. In some embodiments, the second passivation layer 146 includes two nitride layers. The second passivation layer 146 is described in detail below.

[0081] The second passivation layer 146 is a multi-layer stack to reduce the formation of cracks in the redistribution layer 140, to confine the cracks within the second passivation layer 146, or to have both functions. Figure 3A As shown, in some embodiments, the second passivation layer 146 includes a first passivation sublayer 146A disposed on the first passivation layer 144 and the conductive features 152, a second passivation sublayer 146B disposed on the first passivation sublayer 146A, and a third passivation sublayer 146C disposed on the second passivation sublayer 146B. One or more of the first passivation sublayer 146A, the second passivation sublayer 146B, and the third passivation sublayer 146C may be conformally formed by a conformal deposition process, such as atomic layer deposition (ALD). Each of the first passivation sublayer 146A, the second passivation sublayer 146B, and the third passivation sublayer 146C is made of a dielectric material, such as silicon oxide, silicon oxycarbide, one or more porous low-k dielectric materials, undoped silicon oxide glass, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, silicon nitride, silicon oxynitride, silicon oxycarbonitride, high-density plasma oxide formed by a high-density plasma chemical vapor deposition process or other suitable process, spin-on glass, polyimide, other suitable materials or combinations thereof. Adjacent passivation sublayers are made of different dielectric materials. At least one of the first passivation sublayer 146A, the second passivation sublayer 146B, and the third passivation sublayer 146C is made of a nitride, such as silicon nitride, aluminum nitride, titanium nitride, or tantalum nitride. The nitride-based passivation sublayer has one or more of the following properties, including a Young's modulus greater than 150 GPa (such as from about 150 GPa to about 350 GPa), a strength greater than 3 MPa·m 1 / 2 Fracture toughness (such as from about 3MPa·m 1 / 2 To about 7MPa·m 1 / 2 ) or a compressive stress greater than -1E9 dynes / cm2 (e.g., from about -1E9 dynes / cm2 to about -3.5E10 dynes / cm2). Such properties are referred to as crack reduction properties in the present disclosure. In one embodiment, one of the first passivation sublayer 146A, the second passivation sublayer 146B, and the third passivation sublayer 146C is made of silicon nitride, which has all of the above-mentioned crack reduction properties.

[0082] In some embodiments, one of the first passivation sublayer 146A, the second passivation sublayer 146B, and the third passivation sublayer 146C is made of nitride, and the nitride-based passivation sublayer has a thickness of at least 40% (e.g., about 40% to about 80%) of the total thickness of the second passivation layer 146. The nitride-based passivation sublayer has at least one crack reduction property, and has a thickness ranging from about 40% to about 80% of the total thickness of the second passivation layer 146, which can reduce the formation of cracks in the second passivation layer 146 and / or confine the cracks within the second passivation layer 146 by reducing the tensile stress of the conductive features 152. In one aspect, the nitride-based passivation sublayer has a thickness greater than or equal to 1000 nanometers, for example, from about 1000 nanometers to about 2000 nanometers. In some embodiments, the first passivation sublayer 146A is made of undoped silica glass and has a thickness T3 ranging from about 100 nanometers to about 500 nanometers, the second passivation sublayer 146B is made of high-density plasma oxide and has a thickness T4 ranging from about 1000 nanometers to about 2000 nanometers, and the third passivation sublayer 146C is made of silicon nitride and has a thickness T5 greater than or equal to 1000 nanometers (e.g., from about 1000 nanometers to about 2000 nanometers). In one embodiment, the total thickness of the second passivation layer 146 is about 2300 nanometers, and the thickness of the third passivation sublayer 146C is about 1000 nanometers, which is about 43% of the total thickness of the second passivation layer 146. In some embodiments, the third passivation sublayer 146C is made of silicon nitride and has a thickness of at least 40% of the total thickness of the second passivation layer 146, and it has been observed that the tensile stress in the conductive feature 152 disposed below the second passivation layer 146 is reduced by 15% to 25% compared to conventional passivation layers, and the device failure rate is reduced from 13% to 5%.

[0083] In some embodiments, both of the first passivation sublayer 146A, the second passivation sublayer 146B, and the third passivation sublayer 146C are made of a nitride having at least one crack reduction property. The two nitride-based passivation sublayers may be made of the same nitride material or different nitride materials. In some embodiments, one or more passivation sublayers separate the two nitride-based passivation sublayers. For example, the first passivation sublayer 146A is made of silicon nitride and has a thickness T3 of about 300 nanometers to about 1000 nanometers, the second passivation sublayer 146B is made of undoped silicon oxide glass and has a thickness T4 of about 100 nanometers to about 500 nanometers, and the third passivation sublayer 146C is made of silicon nitride and has a thickness T5 of about 300 nanometers to about 1000 nanometers. In one embodiment, the thickness T5 of the third passivation sublayer 146C is greater than the thickness T3 of the first passivation sublayer 146A.

[0084] Figure 3B According to some embodiments, in manufacturing Figure 1 FIG. 1 is a cross-sectional view of a redistribution layer 140 at a stage during the semiconductor device structure 100. Figure 3B As shown, in some embodiments, the redistribution layer 140 includes a first passivation layer 144 having a first passivation sublayer 144A and a second passivation sublayer 144B, a conductive feature 150, a conductive feature 152, and a second passivation layer 146. In some embodiments, the second passivation layer 146 includes a first passivation sublayer 146A, a second passivation sublayer 146B, a third passivation sublayer 146C, a fourth passivation sublayer 146D disposed on the third passivation sublayer 146C, and a fifth passivation sublayer 146E disposed on the fourth passivation sublayer 146D. One or both of the fourth passivation sublayer 146D and the fifth passivation sublayer 146E may be conformally formed by a conformal deposition process (e.g., atomic layer deposition). Each of the fourth to fifth passivation sublayers 146D to 146E is made of a dielectric material, such as silicon oxide, silicon oxycarbide, one or more porous low-k dielectric materials, undoped silicon oxide glass, borophosphosilicate glass, phosphosilicate glass, borosilicate glass, silicon nitride, silicon oxynitride, silicon oxycarbonitride, high-density plasma oxide formed by a high-density plasma chemical vapor deposition process or other suitable process, spin-on glass or polyimide, other suitable materials or combinations thereof. At least one passivation sublayer of the second passivation layer 146 is made of a nitride having at least one crack reduction property, and the thickness of the nitride-based passivation sublayer is at least 40% of the total thickness of the second passivation layer 146. Adjacent passivation sublayers are made of different dielectric materials. For example, the first passivation sublayer 146A is made of a material different from the second passivation sublayer 146B, the third passivation sublayer 146C is made of a material different from the second passivation sublayer 146B, the fourth passivation sublayer 146D is made of a material different from the third passivation sublayer 146C, and the fifth passivation sublayer 146E is made of a material different from the fourth passivation sublayer 146D. In some aspects, non-adjacent passivation sublayers can be made of the same material.

[0085] In some embodiments, one of the first passivation sublayer 146A, the second passivation sublayer 146B, the third passivation sublayer 146C, the fourth passivation sublayer 146D, and the fifth passivation sublayer 146E is made of a nitride having at least one crack reduction property, and the thickness of the nitride-based passivation sublayer is at least 40%, for example, about 40% to about 80%, of the total thickness of the second passivation layer 146. In another embodiment, at least two of the first passivation sublayer 146A, the second passivation sublayer 146B, the third passivation sublayer 146C, the fourth passivation sublayer 146D, and the fifth passivation sublayer 146E are made of a nitride having at least one crack reduction property. The at least two nitride-based passivation sublayers may be made of the same nitride material or different nitride materials. In some embodiments, the at least two nitride-based passivation sublayers each have a thickness of about 300 nanometers to about 1000 nanometers. By using two nitride-based passivation sublayers each having at least one crack reduction property and having a thickness ranging from about 300 nanometers to about 1000 nanometers, the second passivation layer 146 can reduce the formation of cracks in the second passivation layer 146 and / or confine cracks within the second passivation layer 146 by reducing the tensile stress of the conductive features 152. In one aspect, one or more passivation sublayers separate the two nitride-based passivation sublayers. For example, the first passivation sublayer 146A is made of undoped silica glass and has a thickness T3 of about 100 nanometers to about 500 nanometers, the second passivation sublayer 146B is made of high-density plasma oxide and has a thickness T4 of about 1000 nanometers to about 2000 nanometers, the third passivation sublayer 146C is made of silicon nitride and has a thickness T5 of about 300 nanometers to about 1000 nanometers, the fourth passivation sublayer 146D is made of undoped silica glass and has a thickness T6 of less than about 100 nanometers (such as about 50 nanometers to about 100 nanometers), and the fifth passivation sublayer 146E is made of silicon nitride and has a thickness T7 of about 300 nanometers to about 1000 nanometers. In one aspect, the thickness T7 of the fifth passivation sublayer 146E is greater than the thickness T5 of the third passivation sublayer 146C. In some embodiments, the third passivation sublayer 146C and the fifth passivation sublayer 146E are made of silicon nitride and each has a thickness of about 300 nanometers to about 1000 nanometers, so that the tensile stress in the conductive feature 152 disposed below the second passivation layer 146 is reduced by 15% to 60% compared to conventional passivation layers, and the device failure rate is reduced from 13% to 0%.

[0086] The second passivation layer 146 (eg, Figure 3A , or the first to fifth passivation sublayers 146A to 146E (eg, Figure 3BThe embodiment shown in the figure reduces cracks formed in the second passivation layer 146 and / or confines the cracks within the second passivation layer 146. As described herein, the second passivation layer 146 can be used in the redistribution layer 140. The second passivation layer 146 can be used in other structures where cracks form and propagate due to mismatch in thermal expansion coefficients.

[0087] Figure 4 According to some embodiments, a method for manufacturing Figure 1 4 is a flow chart of a method 400 for forming a redistribution layer 140 of a semiconductor device structure 100 . FIG. 5A to FIG. 5I According to some embodiments, Figure 4 4 is a cross-sectional view of the redistribution layer 140 during various manufacturing stages of the method 400. Figure 4 and FIG. 5A to FIG. 5I The redistribution layer 140 and the method 400 of manufacturing the redistribution layer 140 are collectively described. Figure 4 and Figure 5A As shown in FIG. 4 , the method 400 begins at step 402 to form a first dielectric layer 504 on a substrate 500. The substrate 500 may be Figure 1 The substrate 102 is shown with an interconnect structure 120 disposed thereon. The substrate 500 includes a dielectric material 502 and one or more conductive features 501. The dielectric material 502 may be Figure 1 The interlayer dielectric 122 shown, the conductive feature 501 can be as Figure 1 1 and 126 are shown. Each conductive feature 501 has a conductive surface 503, and each dielectric material 502 has a dielectric surface 505. A first dielectric layer 504 may be formed on the conductive surface 503 and the dielectric surface 505. The first dielectric layer 504 may be deposited by any suitable deposition method, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, or spin coating. The first dielectric layer 504 may be, for example, Figure 3B The first passivation layer 144 is shown as a first passivation sub-layer 144A.

[0088] At step 404, if Figure 5B As shown, a second dielectric layer 506 is formed on the first dielectric layer 504. The second dielectric layer 506 can be deposited by any suitable deposition method, such as atomic layer deposition, chemical vapor deposition, plasma chemical vapor deposition, high-density plasma chemical vapor deposition, or spin coating. The second dielectric layer 506 can be as follows Figure 3B Next, in step 406, the first dielectric layer 504 and the second dielectric layer 506 are patterned, and openings 507 are formed in the first dielectric layer 504 and the second dielectric layer 506, as shown in FIG. Figure 5CAs shown. The patterning of the first dielectric layer 504 and the second dielectric layer 506 may include forming a mask on the second dielectric layer 506 and removing a portion of the mask located above the conductive feature 501. The opening 507 may be formed by any suitable removal process, such as dry etching. The conductive surface 503 is exposed through the opening 507, and the first dielectric layer 504 and the second dielectric layer 506 still cover the dielectric surface 505.

[0089] In step 408, if Figure 5D As shown, a first plurality of conductive features 508 are formed in the opening 507. The conductive features 508 may be Figure 3B Conductive features 508 are shown as conductive features 150. Conductive features 508 may be formed by any suitable deposition method, such as physical vapor deposition or electrochemical plating (ECP). After forming conductive features 508, a chemical mechanical polishing process may be performed to remove any conductive material formed on second dielectric layer 506. Next, in step 410, a second plurality of conductive features 510 are formed on conductive features 508, such as Figure 5D Each conductive feature 510 may be formed on a corresponding conductive feature 508. The conductive feature 510 may be Figure 3B Conductive feature 152 is shown. Conductive feature 510 can be formed by any suitable deposition method, such as physical vapor deposition or electrochemical plating. In some embodiments, conductive feature 508 and conductive feature 510 are formed by a single deposition process. For example, a deposition process can be performed to fill opening 507 with a conductive material and form a conductive material layer on second dielectric layer 506, and then pattern the conductive material layer and remove a portion of the conductive material to form conductive feature 510.

[0090] In step 412, if Figure 5E As shown, a third dielectric layer 512 is formed on the conductive feature 510 and the second dielectric layer 506. The third dielectric layer 512 may be formed conformally. The third dielectric layer 512 may be deposited by any suitable deposition method, such as atomic layer deposition, chemical vapor deposition, plasma chemical vapor deposition, high-density plasma chemical vapor deposition, or spin coating. The third dielectric layer 512 may be, for example, Figure 3B Next, in step 414, a fourth dielectric layer 514 is formed on the third dielectric layer 512. Fig. 5F As shown. The fourth dielectric layer 514 may be formed conformally. The fourth dielectric layer 514 may be deposited by any suitable deposition method, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, or spin coating. The fourth dielectric layer 514 may be as follows Figure 3B The second passivation sub-layer 146B of the second passivation layer 146 is shown.

[0091] In step 416, if Figure 5G As shown, a fifth dielectric layer 516 is formed on the fourth dielectric layer 514. The fifth dielectric layer 516 may be formed conformally. The fifth dielectric layer 516 may be deposited by any suitable deposition method, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, or spin coating. The fifth dielectric layer 516 may be, for example, Figure 3B The third passivation sublayer 146C of the second passivation layer 146 shown. In some embodiments, the fifth dielectric layer 516 may be made of a nitride. For example, the fifth dielectric layer 516 is made of silicon nitride and is deposited by a plasma enhanced chemical vapor deposition process. An exemplary plasma enhanced chemical vapor deposition process may include flowing a precursor gas and an additional gas into a process chamber. The precursor gas may be a silicon-containing gas and a nitrogen-containing gas. The silicon-containing gas may include silane, disilane, trimethylsilyl (TMS), tris (dimethylamino) silane (tris (dimethylamino) silane, TDMAS), bis (tertiary-butylamino) silane (bis (tertiary-butylamino) silane, BTBAS), dichlorosilane (dichlorosilane, DCS) or a combination thereof. The nitrogen-containing gas may include nitrogen, ammonia or a combination thereof. The additional gas may include a carrier gas and a gas that can adjust the properties of the silicon nitride layer. The carrier gas may be an inert gas, such as argon. The gas that can adjust the properties of the silicon nitride layer can include hydrogen, which can increase the compressive stress of the silicon nitride layer. The flow rate of the silicon-containing gas ranges from about 10 standard cubic centimeter per minute (sccm) to about 200 sccm, the flow rate of the nitrogen-containing gas ranges from about 50 sccm to about 500 sccm, and the flow rate of the carrier gas ranges from about 100 sccm to about 5000 sccm. The radio frequency power source can be in a frequency range of about 0.3 MHz to about 14 MHz, such as about 13.56 MHz, and the radio frequency power can be in a range of about 10 watts to about 5000 watts. The chamber pressure can be in a range of about 10 mTorr to about 15 Torr, and the substrate temperature can be in a range of about 200 degrees Celsius to about 700 degrees Celsius.

[0092] In some embodiments, the third dielectric layer 512 is Figure 3AThe first passivation sublayer 146A is shown, the fourth dielectric layer 514 is the second passivation sublayer 146B, the fifth dielectric layer 516 is the third passivation sublayer 146C, and the thickness of the fifth dielectric layer 516 is at least 40% of the total thickness of the third dielectric layer 512, the fourth dielectric layer 514, and the fifth dielectric layer 516. Subsequent processes include patterning and removing portions of the third dielectric layer 512, the fourth dielectric layer 514, and the fifth dielectric layer 516 to expose the conductive features 510, and forming an under bump metallization layer 154 (such as Figure 1 In some embodiments, the fifth dielectric layer 516 has a thickness ranging from about 300 nanometers to about 1000 nanometers, and an additional dielectric layer is formed on the fifth dielectric layer 516.

[0093] Next, in step 418, a sixth dielectric layer 518 is formed on the fifth dielectric layer 516. Figure 5H As shown in . The sixth dielectric layer 518 may be formed conformally. The sixth dielectric layer 518 may be deposited by any suitable deposition method, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, or spin coating. The sixth dielectric layer 518 may be Figure 3B The fourth passivation sub-layer 146D of the second passivation layer 146 is shown.

[0094] In step 420, if Fig.5I As shown, a seventh dielectric layer 520 is formed on the sixth dielectric layer 518. The seventh dielectric layer 520 may be formed conformally. The seventh dielectric layer 520 may be deposited by any suitable deposition method, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, or spin coating. The seventh dielectric layer 520 may be, for example, Figure 3B 14. The fifth passivation sublayer 146E of the second passivation layer 146 is shown. In some embodiments, the seventh dielectric layer 520 may be made of a nitride. In one embodiment, the seventh dielectric layer 520 is made of silicon nitride and is deposited by the above-mentioned plasma enhanced chemical vapor deposition process. The thickness of the seventh dielectric layer 520 ranges from about 300 nanometers to about 1000 nanometers. In some embodiments, the fifth dielectric layer 516 and the seventh dielectric layer 520 are made of a nitride such as silicon nitride, and the seventh dielectric layer 520 is thicker than the fifth dielectric layer 516.

[0095] Because the second passivation layer 146 can reduce the formation of cracks and / or confine cracks within the second passivation layer 146, the limits on the size and placement of conventional conductive features are expanded. Fig. 6A FIG. 1 is a cross-sectional view of a second passivation layer 146 on a plurality of conductive features according to some embodiments. Fig. 6AAs shown in FIG. 1 , the conductive features include conductive features 602A, 602B, 602C, and 602D at the first level. The conductive features 602A, 602B, 602C, and 602D may be as follows: Figure 1 1 and 1 . The conductive features 126 shown in FIG. 1 are disposed in the interconnect structure 120. The conductive feature 602A has a first width W1, and the conductive features 602B, 602C, and 602D each have a second width W2. In some embodiments, the first width W1 is greater than the second width W2. In some embodiments, the conductive features 602B, 602C, and 602D have different widths from each other. The conductive features 602A, 602B, 602C, and 602D can be formed by forming a conductive layer, patterning the conductive layer, and removing portions of the conductive layer. In some embodiments, the conductive features 602A, 602B, 602C, and 602D have the same thickness T8.

[0096] The second level conductive features 604A, 604B, 604C, and 604D are disposed above the conductive features 602A, 602B, 602C, and 602D. The conductive features 604A, 604B, 604C, and 604D may be as follows: Figure 1 Conductive features 126 are shown disposed on top of interconnect structure 120. Both levels of conductive features 602A to 602D and 604A to 604D can be embedded in interlayer dielectric 122. In one embodiment, conductive features 604A, 604B, 604C, 604D are aligned with corresponding conductive features 602A, 602B, 602C, 602D. For clarity, conductive vias connecting two levels of conductive features 602A to 602D and 604A to 604D are omitted. Conductive feature 604A can have a width that is the same or different from the first width W1 of conductive feature 602A. Conductive features 604B, 604C, 604D can have widths that are the same or different from each other. In some embodiments, conductive features 604B, 604C, 604D each have a second width W2. Conductive features 604A, 604B, 604C, and 604D may be formed by forming a conductive layer, patterning the conductive layer, and removing portions of the conductive layer. In one embodiment, conductive features 604A, 604B, 604C, and 604D have the same thickness T9, and thickness T9 is greater than thickness T8.

[0097] like Fig. 6A As shown, the first passivation layer 144 is disposed on the second-level conductive features 604A to 604D and the interlayer dielectric 122. The third-level conductive features 606A, 606B, 606C, and 606D are disposed on the first passivation layer 144 and above the conductive features 604A, 604B, 604C, and 604D. The conductive features 606A, 606B, 606C, and 606D may be as follows: Figure 1 Conductive features 152 are shown disposed in redistribution layer 140. In some embodiments, conductive features 606A, 606B, 606C, 606D are aligned with corresponding conductive features 604A, 604B, 604C, 604D. Conductive feature 606A may have a width that is the same as or different from the first width W1 of conductive feature 602A. Conductive features 606B, 606C, 606D may have widths that are the same as or different from each other. In some embodiments, conductive features 606B, 606C, 606D each have a second width W2. Conductive features 606A, 606B, 606C, 606D may be formed by forming a conductive layer, patterning the conductive layer, and removing portions of the conductive layer. In one embodiment, conductive features 606A, 606B, 606C, and 606D have the same thickness T10, and thickness T10 is greater than thickness T9.

[0098] Figure 6B According to some embodiments Fig. 6A 606A to 606D. In some embodiments, conductive feature 606A is a bonding pad, and conductive feature 606B, conductive feature 606C, and conductive feature 606D are wires. Figure 6B As shown, conductive feature 606A has a polygonal shape. In one embodiment, conductive feature 606A is rectangular and has a fixed width. In another embodiment, conductive feature 606A is octagonal and has a variable width, such as Figure 6BAs shown. Conductive feature 606B is adjacent to conductive feature 606A and has a polygonal shape, such as a rectangle. In one embodiment, the distance between conductive feature 606A and conductive feature 606B is fixed. In another embodiment, the distance between conductive feature 606A and conductive feature 606B is variable. For example, the center portion of conductive feature 606A is at a distance D1 from conductive feature 606B, and the edge portion of conductive feature 606A is at a distance D2 from conductive feature 606B. Depending on the shape of conductive feature 606A and / or the shape of conductive feature 606B, distance D1 may be greater than or less than distance D2.

[0099] In some embodiments, conductive feature 606C is adjacent to conductive feature 606B and has a polygonal shape, such as a rectangle. There is a distance D3 between conductive feature 606C and conductive feature 606B. In some embodiments, distance D3 is less than distance D1, such as about half of distance D1. Conductive feature 606D is adjacent to conductive feature 606C and has a polygonal shape, such as a rectangle. Conductive feature 606C and conductive feature 606D may be separated by distance D3.

[0100] Various embodiments of the present disclosure provide a second passivation layer 146 of the semiconductor device structure 100 and a method of manufacturing the second passivation layer 146. The second passivation layer 146 is disposed on the conductive features and the dielectric material. In one embodiment, the second passivation layer 146 includes a plurality of dielectric layers, and at least one of the plurality of dielectric layers is made of nitride and has at least one of the following properties, including a Young's modulus greater than 150 GPa (such as from about 150 GPa to about 350 GPa), a Young's modulus greater than 3 MPa·m 1 / 2 Fracture toughness (such as from about 3MPa·m 1 / 2 To about 7MPa·m 1 / 2 ) or a compressive stress greater than -1E9 dynes / cm2 (such as from about -1E9 dynes / cm2 to about -3.5 dynes / cm2). The thickness of the nitride-based dielectric layer in the second passivation layer 146 is at least 40%, such as about 40% to about 80%, of the total thickness of the second passivation layer 146. In another embodiment, at least two dielectric layers of the second passivation layer 146 are made of a nitride having at least one of the above-mentioned properties. Some embodiments can achieve advantages. For example, the second passivation layer 146 reduces the formation of cracks in the second passivation layer 146 and / or confines the cracks within the second passivation layer 146 by reducing the tensile stress of the conductive feature 152 (such as a bonding pad) disposed thereunder.

[0101] One embodiment provided by the present disclosure is a semiconductor device structure. This structure includes a substrate having one or more devices thereon, one or more bonding pads disposed on the substrate, and a first passivation layer disposed on the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed on the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed on the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first passivation sublayer, the second passivation sublayer, and the third passivation sublayer each include a nitride.

[0102] In some embodiments, the nitride comprises silicon nitride, aluminum nitride, titanium nitride, or tantalum nitride. In some embodiments, the nitride is silicon nitride. In some embodiments, the first passivation layer further comprises a fourth passivation sublayer having a fourth dielectric material and a fifth passivation sublayer disposed on the fourth passivation sublayer, the fifth passivation sublayer comprising a fifth dielectric material different from the fourth dielectric material, wherein the first passivation sublayer is disposed on the fifth passivation sublayer. In some embodiments, the semiconductor device structure further comprises a second passivation layer disposed on the substrate, wherein the second passivation layer comprises a sixth passivation sublayer and a seventh passivation sublayer disposed on the sixth passivation sublayer, wherein the first passivation layer is disposed on the seventh passivation sublayer. In some embodiments, the second passivation sublayer, the fourth passivation sublayer, and the fifth passivation sublayer each comprise an oxide, and the first passivation sublayer and the third passivation sublayer each comprise a nitride. In some embodiments, the second passivation sublayer and the fourth passivation sublayer each comprise undoped silicon oxide glass, the fifth passivation sublayer comprises a high-density plasma oxide, and the first passivation sublayer and the third passivation sublayer each comprise silicon nitride. In some embodiments, the semiconductor device structure further includes an interconnect structure disposed on the substrate, and one or more bonding pads are disposed on the interconnect structure, wherein the interconnect structure includes a first-level conductive feature and a second-level conductive line disposed on the first-level conductive line, wherein the first-level conductive feature includes a first conductive line, a second conductive line adjacent to the first conductive line, and a third conductive line adjacent to the second conductive line, and the second-level conductive line includes a fourth conductive line, a fifth conductive line adjacent to the fourth conductive line, and a sixth conductive line adjacent to the fifth conductive line, wherein the bonding pad of the one or more bonding pads is disposed on the fourth conductive line of the second-level conductive line and aligned with the fourth conductive line. In some embodiments, the first conductive line, the second conductive line, and the third conductive line of the first-level conductive line have a first thickness, the fourth conductive line, the fifth conductive line, and the sixth conductive line of the second-level conductive line have a second thickness, and the bonding pad has a third thickness, wherein the second thickness is greater than the first thickness, and the third thickness is greater than the second thickness. In some embodiments, each of the first conductive line and the fourth conductive line has a first width, each of the second conductive line and the fifth conductive line has a second width, each of the third conductive line and the sixth conductive line has a third width, and the bonding pad has a first width, wherein the first width is greater than the second width and the third width. In some embodiments, the first wire and the fourth wire are respectively separated from the second wire and the fifth wire by a first distance, the second wire and the fifth wire are respectively separated from the third wire and the sixth wire by a second distance, and the second distance is less than the first distance. In some embodiments, the semiconductor device structure further includes a conductive feature adjacent to the bonding pad, wherein the bonding pad and the adjacent conductive feature are separated by a first distance. In some embodiments, the semiconductor device structure further includes a conductive feature adjacent to the bonding pad, wherein the bonding pad has a central portion and the adjacent conductive feature separated by a third distance, and the bonding pad has an edge portion and the adjacent conductive feature separated by a fourth distance, wherein the fourth distance is greater than the third distance.

[0103] Another embodiment provided by the present disclosure is a semiconductor device structure. This structure includes a substrate having one or more devices thereon, an interconnect structure disposed on the substrate, one or more bonding pads disposed on the interconnect structure, and a first passivation layer disposed on the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed on the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed on the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least one of the first passivation sublayer, the second passivation sublayer, and the third passivation sublayer is a nitride layer, the thickness of which is at least 40% of the total thickness of the first passivation layer.

[0104] In some embodiments, the third passivation sublayer is silicon nitride having a thickness greater than or equal to 1000 nanometers. In some embodiments, the semiconductor device structure further includes a second passivation layer, wherein the first passivation layer is disposed on the second passivation layer. In some embodiments, the second passivation layer includes a fourth passivation sublayer disposed on the interconnect structure and a fifth passivation sublayer disposed on the fourth passivation sublayer.

[0105] Another embodiment provided by the present disclosure is a method for forming a semiconductor device structure. The method includes forming one or more devices on a substrate, forming a first dielectric layer on the one or more devices, forming an opening in the first dielectric layer, forming a first conductive feature in the opening, forming a bonding pad on the first conductive feature, and forming a second dielectric layer on the bonding pad and the first dielectric layer. Forming the second dielectric layer includes forming a first sublayer on the bonding pad and the first dielectric layer. The first sublayer includes a first material. Forming the second dielectric layer also includes forming a second sublayer on the first sublayer, and the second sublayer includes a second material different from the first material. Forming the second dielectric layer also includes forming a third sublayer on the second sublayer, and the third sublayer includes a third material different from the second material. At least two of the first sublayer, the second sublayer, and the third sublayer each include a nitride.

[0106] In some embodiments, the third sublayer includes silicon nitride, and the third sublayer is formed by a plasma enhanced chemical vapor deposition process. In some embodiments, forming the second dielectric layer further includes forming a fourth sublayer on the first sublayer on the bonding pad and the first dielectric layer, and forming a fifth sublayer on the fourth sublayer, wherein the first sublayer is formed on the fifth sublayer, and the first sublayer includes silicon nitride.

[0107] The features of some embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, characterized in that: include: a substrate, comprising one or more devices formed on the substrate; one or more bonding pads disposed on the substrate; and a first passivation layer disposed on the one or more bonding pads, wherein the first passivation layer comprises: a first passivation sublayer comprising a first dielectric material, the first passivation sublayer contacting the one or more bonding pads; a second passivation sublayer disposed on the first passivation sublayer, the second passivation sublayer comprising a second dielectric material different from the first dielectric material; and A third passivation sublayer is disposed on the second passivation sublayer, the third passivation sublayer comprising a third dielectric material different from the second dielectric material, wherein at least one of the second passivation sublayer and the third passivation sublayer and the first passivation sublayer each comprise a nitride having a compressive stress greater than -1E9 dyne / cm2.

2. The semiconductor device structure according to claim 1, wherein: The nitride includes silicon nitride, aluminum nitride, titanium nitride or tantalum nitride.

3. The semiconductor device structure according to claim 2, wherein: The nitride is silicon nitride.

4. The semiconductor device structure according to claim 1, wherein: The first passivation layer further comprises: a fourth passivation sublayer comprising a fourth dielectric material; and A fifth passivation sublayer is disposed on the fourth passivation sublayer, wherein the fifth passivation sublayer comprises a fifth dielectric material different from the fourth dielectric material, wherein the fourth passivation sublayer is disposed on the third passivation sublayer.

5. The semiconductor device structure according to claim 4, wherein: Further comprising a second passivation layer disposed on the substrate, wherein the second passivation layer comprises: a sixth passivation sublayer; and A seventh passivation sublayer is disposed on the sixth passivation sublayer, wherein the first passivation layer is disposed on the seventh passivation sublayer.

6. The semiconductor device structure according to claim 4, wherein: The second passivation sublayer, the fourth passivation sublayer, and the fifth passivation sublayer each include an oxide, and the first passivation sublayer and the third passivation sublayer each include the nitride.

7. The semiconductor device structure according to claim 6, wherein: The second passivation sublayer and the fourth passivation sublayer each include undoped silicon oxide glass, the fifth passivation sublayer includes high density plasma oxide, and the first passivation sublayer and the third passivation sublayer each include silicon nitride.

8. The semiconductor device structure according to claim 1, wherein: Further comprising an interconnect structure disposed on the substrate, and the one or more bonding pads are disposed on the interconnect structure, wherein the interconnect structure comprises: a first level conductive feature, comprising a first conductive line, a second conductive line adjacent to the first conductive line, and a third conductive line adjacent to the second conductive line; and A second-level conductive feature is disposed on the first-level conductive feature, wherein the second-level conductive feature includes a fourth wire, a fifth wire adjacent to the fourth wire, and a sixth wire adjacent to the fifth wire, wherein a bonding pad among the one or more bonding pads is disposed on the fourth wire of the second-level conductive feature and aligned with the fourth wire.

9. The semiconductor device structure according to claim 8, wherein: The first wire, the second wire, and the third wire of the first-level conductive feature have a first thickness, the fourth wire, the fifth wire, and the sixth wire of the second-level conductive feature have a second thickness, and the bonding pad has a third thickness, wherein the second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

10. The semiconductor device structure according to claim 9, wherein: Each of the first and fourth wires has a first width, each of the second and fifth wires has a second width, each of the third and sixth wires has a third width, and the bonding pad has the first width, wherein the first width is greater than the second and third widths.

11. The semiconductor device structure according to claim 10, wherein: The first wire and the fourth wire are respectively separated from the second wire and the fifth wire by a first distance, the second wire and the fifth wire are respectively separated from the third wire and the sixth wire by a second distance, and the second distance is smaller than the first distance.

12. The semiconductor device structure according to claim 11, wherein: The method further includes a conductive feature adjacent to the bonding pad, wherein the bonding pad and the adjacent conductive feature are separated by the first distance.

13. The semiconductor device structure according to claim 11, wherein: Further comprising a conductive feature adjacent to the bonding pad, wherein the bonding pad has a center portion and is separated from the adjacent conductive feature by a third distance, and the bonding pad has an edge portion and is separated from the adjacent conductive feature by a fourth distance, wherein the fourth distance is greater than the third distance.

14. A semiconductor device structure, characterized in that: include: a substrate, comprising one or more devices formed on the substrate; an interconnect structure disposed on the substrate; one or more bonding pads disposed on the interconnect structure; and a first passivation layer disposed on the one or more bonding pads, wherein the first passivation layer comprises: a first passivation sublayer comprising a first dielectric material, the first passivation sublayer contacting the one or more bonding pads; a second passivation sublayer disposed on the first passivation sublayer, the second passivation sublayer comprising a second dielectric material different from the first dielectric material; and A third passivation sublayer is disposed on the second passivation sublayer, the third passivation sublayer includes a third dielectric material different from the second dielectric material, wherein the first passivation sublayer is a first nitride layer having a compressive stress greater than -1E9 dynes / square centimeter, at least one of the second passivation sublayer and the third passivation sublayer is a second nitride layer having a compressive stress greater than -1E9 dynes / square centimeter, and the total thickness of the first nitride layer and the second nitride layer is at least 40% of the total thickness of the first passivation layer.

15. The semiconductor device structure according to claim 14, wherein: The third passivation sublayer is silicon nitride with a thickness greater than or equal to 1000 nanometers.

16. The semiconductor device structure according to claim 14, wherein: A second passivation layer is further included, wherein the first passivation layer is disposed on the second passivation layer.

17. The semiconductor device structure according to claim 16, wherein: The second passivation layer comprises: a fourth passivation sublayer disposed on the interconnect structure; and A fifth passivation sublayer is disposed on the fourth passivation sublayer.

18. A method for forming a semiconductor device structure, characterized in that: include: forming one or more devices on a substrate; forming a first dielectric layer on the one or more devices; forming an opening in the first dielectric layer; forming a first conductive feature in the opening; forming a bonding pad over the first conductive feature; and Forming a second dielectric layer on the bonding pad and the first dielectric layer, wherein forming the second dielectric layer comprises: forming a first passivation sublayer contacting the bonding pad over the bonding pad and the first dielectric layer, wherein the first passivation sublayer comprises a first dielectric material; forming a second passivation sublayer on the first passivation sublayer, wherein the second passivation sublayer comprises a second dielectric material different from the first dielectric material; and A third passivation sublayer is formed on the second passivation sublayer, wherein the third passivation sublayer includes a third dielectric material different from the second dielectric material, and at least one of the second passivation sublayer and the third passivation sublayer and the first passivation sublayer each include a nitride having a compressive stress greater than -1E9 dynes / cm2.

19. The method according to claim 18, characterized in that The third passivation sublayer includes silicon nitride and is formed by a plasma enhanced chemical vapor deposition process.

20. The method of claim 19, wherein: Forming the second dielectric layer further comprises: forming a fourth passivation sublayer on the third passivation sublayer; and A fifth passivation sublayer is formed on the fourth passivation sublayer, wherein the fifth passivation sublayer is made of silicon nitride.

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