Switching device with bidirectional driving characteristics and operation method thereof

Abstract

A bidirectional two-terminal phase-change memory device using a tunneling film and an operation method thereof are disclosed. According to one embodiment, the phase-change memory device includes: a first electrode; a second electrode; and a phase-change memory unit between the first electrode and the second electrode, wherein the phase-change memory unit includes: a P-type intermediate layer used for data storage when a crystal state changes due to a voltage applied through the first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling film arranged in at least one of a region between the upper layer and the intermediate layer and a region between the lower layer and the intermediate layer to reduce leakage current in the intermediate layer or prevent mixing between a P-type dopant and an N-type dopant.

Description

Technical Field

[0001] The following embodiments relate to selection devices, and more particularly, to techniques for implementing selection devices configured to support bidirectional switching operations. Background Art

[0002] With the rapid development of information technology (IT) technology, advanced memory devices having characteristics such as ultra-high speed, large capacity, and high integration density are required, which are suitable for the development of portable information communication systems and devices that process a large amount of information in a wireless manner. Therefore, although three-dimensional (3D) vertical (V)-NAND memory currently has the highest integration density, the string height increases as the number of levels increases, and therefore, it is expected that the realization of ultra-high integration density will be limited by the difficulty in forming a relatively high height of about 100 or more levels.

[0003] To replace 3D V-NAND memory, advanced memory devices such as spin torque transfer magnetic random access memory (STT-MRAM), ferroelectric RAM (FeRAM), resistive RAM (ReRAM), and phase change RAM (PCRAM) have been studied, which are superior to typical memory devices in terms of power and data retention characteristics and write / read characteristics.

[0004] Among them, in response to heat transfer to the phase change layer caused by the flow of current or the applied voltage difference between the first electrode and the second electrode, the PCRAM (hereinafter referred to as phase change memory) represents the change in the resistance state according to the phase change characteristics of the phase change layer as a binary value. In one example, when heat is transferred to the phase change layer, the PCRAM causes the crystal state of the phase change layer to change between a crystalline state and an amorphous state. Therefore, based on the phase change characteristics of having low resistance in the crystalline state and high resistance in the amorphous state, the PCRAM can represent a binary value corresponding to each resistance state (for example, when having low resistance in the crystalline state of the phase change layer, the PCRAM has a set state with a binary value [0], and when having high resistance in the amorphous state of the phase change layer, the PCRAM has a static state with a binary value [1]).

[0005] Phase change memory is intensively studied for use as an advanced semiconductor memory device because of its low manufacturing cost and high speed operation. In addition, it has been proposed to implement the phase change memory as a structure having various 3D architectures to improve the two-dimensional (2D) scaling limit.

[0006] However, since a conventional bidirectional threshold switch (OTS) used as a selection device in a phase change memory requires an intermediate electrode located between the OTS and the phase change layer in contact with each other, the OTS has the disadvantages of being difficult to achieve high integration density in scaling and problems with material reliability due to scaling, and is difficult to block leakage current.

[0007] Accordingly, there is a need to develop a selection device to replace the conventional OTS.

[0008] In addition, in dynamic random access memory (DRAM), it is a very important issue to improve the selection device due to the scaling of memory cells, and the performance of the selection device is closely related to the leakage current. That is, DRAM has been researched and developed in the direction of ensuring the performance of the selection device by suppressing the leakage current.

[0009] Therefore, structures such as a recessed channel array transistor (RCAT) and a buried word line (BWL) have been proposed, but a sub-10-nm DRAM selection device requires device characteristics that significantly suppress leakage current, which is different from the proposed structures.

[0010] Therefore, it is necessary to propose a selection device that allows the substrate itself to have extremely low leakage current. Summary of the invention

[0011] Technical issues

[0012] The embodiment provides a phase change memory that implements a selection device to replace a conventional cycloidal threshold switch (OTS).

[0013] More specifically, an embodiment proposes a phase change memory cell and a phase change memory device, wherein an NPN structure is configured with a P-type middle layer and an N-type upper layer and an N-type lower layer arranged at both ends of the middle layer, so that bidirectional current drive can be achieved by forming a bidirectional PN diode using the NPN structure, and at the same time, a selection device is implemented, which is configured to selectively switch the voltage applied to the middle layer from the first electrode and the second electrode using the bidirectional PN diode.

[0014] In this case, the embodiment provides a phase change memory cell and a phase change memory device in which a function of data storage is integrated with a function of a selection device by configuring the selection device with a structure including an intermediate layer serving as data storage.

[0015] In particular, the embodiments provide a phase change memory cell and a phase change memory device, wherein at least one tunneling film is located in at least one of a region between an upper layer and an intermediate layer and a region between a lower layer and an intermediate layer to reduce leakage current in the intermediate layer.

[0016] Furthermore, the embodiment provides a phase change memory cell and a phase change memory device which further reduce leakage current by using a material having a low leakage current characteristic as an N-type semiconductor material forming an upper layer and a lower layer.

[0017] In addition, an embodiment proposes a phase change memory device, wherein a P-type phase change layer and an N-type semiconductor layer form a PN diode by interposing the P-type phase change layer and the N-type semiconductor layer between a first electrode and a second electrode, and a Schottky diode is formed at the contact interface between the P-type phase change layer and the second electrode, so that the phase change layer used for data storage can be integrated with a selection device and bidirectional current drive can be achieved.

[0018] In addition, an embodiment proposes a dynamic random access memory (DRAM) selection device and a manufacturing method thereof, wherein an indium gallium zinc oxide (IGZO) channel structure is formed in a silicon substrate and used as at least a portion of a channel region of the DRAM selection device, so that the substrate of the DRAM selection device itself can have extremely low leakage current.

[0019] Technical Solution

[0020] According to one embodiment, a phase change memory device includes: a first electrode; a second electrode; and a phase change memory unit between the first electrode and the second electrode. The phase change memory unit includes: a P-type intermediate layer, which is used as data storage when the crystal state changes due to the voltage applied through the first electrode and the second electrode; an upper layer and a lower layer, which are formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling film, which is arranged in at least one of a region between the upper layer and the intermediate layer and a region between the lower layer and the intermediate layer to reduce leakage current in the intermediate layer or prevent mixing between P-type dopants and N-type dopants.

[0021] According to an aspect, at least one tunneling thin film may be formed using a material to have a thickness to reduce leakage current or prevent mixing between a P-type dopant and an N-type dopant while allowing a flow of tunneling current.

[0022] According to another aspect, the phase change memory cell may be formed to have an NPN structure and selectively switch voltages applied to the first electrode and the second electrode to the intermediate layer.

[0023] According to yet another aspect, the phase change memory cell can implement bidirectional current driving by forming a bidirectional PN diode using an NPN structure.

[0024] According to still another aspect, the phase change memory cell may perform a write operation that changes a crystal state of the intermediate layer when the intermediate layer is depleted due to a NP reverse bias in an NPN structure and a tunneling current flows.

[0025] According to yet another aspect, the phase change memory cell performs a read operation of reading a voltage difference caused by a change in a depletion start voltage due to a change in a crystal state of an intermediate layer, or the phase change memory cell performs a read operation of reading a read current according to a resistance change of the intermediate layer.

[0026] According to still another aspect, the intermediate layer may be formed using a phase change material containing a transition metal to have a reverse phase change characteristic.

[0027] According to one embodiment, a phase change memory having a three-dimensional (3D) architecture includes: at least one first electrode formed to extend in a horizontal direction; a second electrode formed to extend in a direction perpendicular to the at least one first electrode; and at least one phase change memory cell between the at least one first electrode and the second electrode. Each of the at least one phase change memory cells includes: a P-type intermediate layer used as data storage when a crystal state changes due to a voltage applied through the at least one first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling film arranged in at least one of a region between the upper layer and the intermediate layer and a region between the lower layer and the intermediate layer to reduce leakage current in the intermediate layer or prevent mixing between a P-type dopant and an N-type dopant.

[0028] According to one embodiment, a phase change memory device includes: a first electrode; a second electrode; a P-type phase change layer between the first electrode and the second electrode, the P-type phase change layer being used as data storage when a crystal state changes due to a voltage applied through the first electrode and the second electrode; and an N-type semiconductor layer disposed on the P-type phase change layer. The P-type phase change layer and the N-type semiconductor layer form a PN diode, and the P-type phase change layer forms a Schottky diode at a contact interface with the second electrode.

[0029] According to one aspect, a phase change memory device can implement bidirectional current driving by using a PN diode and a Schottky diode.

[0030] According to another aspect, the P-type phase change layer may be formed by using a phase change material containing a transition metal to form a Schottky diode having a stable Schottky characteristic at a contact interface with the second electrode.

[0031] According to one embodiment, a dynamic random access memory (DRAM) selection device configured to reduce leakage current includes: a silicon substrate; a word line buried in the silicon substrate; and an indium gallium zinc oxide (IGZO) channel structure formed in the silicon substrate to surround at least a portion of the word line. The IGZO channel structure is used as at least a portion of a channel region in the DRAM selection device.

[0032] According to one aspect, the depth of at least a portion of the IGZO channel structure surrounding the word line can be determined to be: a value for allowing the IGZO channel structure to be used as at least a portion of the channel region in a DRAM selection device, and / or a value for reducing leakage current in the DRAM selection device above a predetermined value.

[0033] According to another aspect, an IGZO channel structure may be formed in a silicon substrate by using an atomic layer deposition (ALD) process or an epitaxial growth process.

[0034] According to yet another aspect, a plurality of DRAM selection devices may be disposed and stacked in a vertical direction or a horizontal direction to form a 3D structure.

[0035] Beneficial effects of the present invention

[0036] Embodiments may provide a phase change memory that implements a selection device to replace a conventional directional threshold switch (OTS).

[0037] More specifically, an embodiment may provide a phase change memory cell and a phase change memory device, wherein an NPN structure is configured with a P-type middle layer and an N-type upper layer and an N-type lower layer arranged at both ends of the middle layer, so that bidirectional current drive can be achieved by forming a bidirectional PN diode using the NPN structure, and at the same time a selection device is implemented, which is configured to selectively switch the voltage applied to the middle layer from the first electrode and the second electrode using a bidirectional PN diode.

[0038] In this case, the embodiment may provide a phase change memory cell and a phase change memory device in which a function of data storage is integrated with a function of a selection device by configuring the selection device using a structure including an intermediate layer serving as data storage.

[0039] In particular, embodiments may provide a phase change memory cell and a phase change memory device, wherein at least one tunneling film is located in at least one of a region between an upper layer and an intermediate layer and a region between a lower layer and an intermediate layer to reduce leakage current in the intermediate layer.

[0040] Furthermore, the embodiments may provide a phase change memory cell and a phase change memory device which use a material having a low leakage current characteristic as an N-type semiconductor material forming an upper layer and a lower layer and further reduce leakage current.

[0041] In addition, an embodiment may provide a phase change memory device, wherein a P-type phase change layer and an N-type phase change layer are formed into a PN diode by interposing the P-type phase change layer and the N-type phase change layer between a first electrode and a second electrode, and a Schottky diode is formed at the contact interface between the P-type phase change layer and the second electrode, so that the phase change layer used for data storage can be integrated with a selection device, and bidirectional current drive can be realized at the same time.

[0042] In addition, an embodiment may provide a DRAM selection device and a method for manufacturing the same, wherein an indium gallium zinc oxide (IGZO) channel structure is formed in a silicon substrate and used as at least a portion of a channel region of the DRAM selection device, so that the substrate of the DRAM selection device itself may have extremely low leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1a to Figure 1c is a schematic diagram of a phase change memory device according to an embodiment.

[0044] Figure 2 is a schematic diagram showing a phase change memory device implementing bidirectional current driving according to an embodiment.

[0045] Figure 3 is a schematic diagram showing a selection device integrally implemented with a phase change layer in a phase change memory device according to an embodiment.

[0046] Figure 4 is a schematic diagram for explaining characteristics of a tunneling thin film included in a phase change memory device according to an embodiment.

[0047] Figure 5 is a schematic diagram for explaining a write operation of a phase change memory device according to an embodiment.

[0048] Figure 6 is a schematic diagram for explaining a read operation of a phase change memory device according to an embodiment.

[0049] Figure 7 is a schematic diagram of a phase change memory implemented with a three-dimensional (3D) architecture according to an embodiment.

[0050] Figure 8 is a schematic diagram of a phase change memory device according to an embodiment.

[0051] Fig. 9 is a schematic diagram showing a phase change memory device implementing bidirectional current driving according to an embodiment.

[0052] Fig.10 is a schematic diagram showing a selection device integrally implemented with a phase change layer in a phase change memory device according to an embodiment.

[0053] Fig.11 is a schematic diagram for explaining characteristics of a Schottky diode formed in a phase change memory device according to an embodiment.

[0054] Fig.12 is a schematic diagram of a phase change memory implemented with a 3D architecture according to an embodiment.

[0055] Fig.13is a schematic diagram of a dynamic random access memory (DRAM) selection device according to an embodiment.

[0056] Fig.14 According to another embodiment Fig.13 Schematic diagram of a DRAM selection device shown in FIG.

[0057] Fig.15 is a schematic diagram for explaining characteristics of an indium gallium zinc oxide (IGZO) channel structure included in a DRAM selection device according to an embodiment.

[0058] Fig.16 is a schematic diagram of a DRAM selection device according to another embodiment.

[0059] Fig.17 is a flow chart of a method of manufacturing a DRAM selection device according to an embodiment.

[0060] Figures 18 to 25 is a schematic diagram for explaining a method of manufacturing a DRAM selection device according to an embodiment. DETAILED DESCRIPTION

[0061] The embodiments will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments. In addition, the same reference numerals in the drawings represent the same elements.

[0062] In addition, the terms used here are to appropriately describe the exemplary embodiments of the present disclosure, and may vary according to the intention of users or operators or customs in the field to which the present disclosure belongs. Therefore, the terms used here should be defined based on the entire content of this specification.

[0063] Figure 1a to Figure 1c is a schematic diagram of a phase change memory device according to an embodiment. Figure 2 is a schematic diagram showing a phase change memory device implementing bidirectional current driving according to an embodiment. Figure 3 is a schematic diagram showing a selection device implemented integrally with a phase change layer in a phase change memory device according to an embodiment. Figure 4 is a schematic diagram for explaining characteristics of a tunneling thin film included in a phase change memory device according to an embodiment.

[0064] Reference Figures 1a to 4 According to the embodiment, the phase change memory device 100 includes a first electrode 110 and a second electrode 120 and a phase change memory unit 130 interposed therebetween. The first electrode 110 and the second electrode 120 are formed using a conductive metal material such as tungsten (W), tantalum nitride (TaN), and titanium nitride (TiN).

[0065] The structure of the phase change memory cell 130 includes a P-type middle layer 131, an N-type upper layer 132, a lower layer 133, and at least one tunneling film 134. Therefore, the phase change memory cell 130 can realize bidirectional current driving by forming bidirectional PN diodes 210 and 220 using an NPN structure. In one example, Figure 2 As shown, the first PN diode 210 can be formed in the first direction by using the middle layer 131 and the upper layer 132, and the second PN diode 220 can be formed in the second direction opposite to the first direction by using the middle layer 131 and the lower layer 133. Therefore, the phase change memory unit 130 can realize bidirectional current driving in the first direction and the second direction.

[0066] Here, the bidirectional PN diodes 210 and 220 may be used as a selection device configured to selectively switch a voltage applied to the P-type intermediate layer 131 through the first electrode 110 and the second electrode 120 .

[0067] Therefore, based on the P-type intermediate layer 131 used as data storage, the phase change memory cell 130 implements the bidirectional PN diodes 210 and 220 operating as selection devices. Therefore, the data storage function (or the function of representing data in the crystal state of the intermediate layer 131, which changes due to the voltage applied through the first electrode 110 and the second electrode 120) can be integrated with the function of the selection device (or the function of selectively switching the voltage applied to the intermediate layer 131 through the first electrode 110 and the second electrode 120). That is, the P-type intermediate layer 131 can be used as data storage in the phase change memory cell 130, such as Figure 3 As shown, bidirectional diodes 210 and 220 can also be used as selection devices by forming the bidirectional diodes 210 and 220 at the same time.

[0068] By using the intermediate layer 131 for data storage and the selection device as a whole, the phase change memory unit 130 can prevent and solve the disadvantages of the difficulty in achieving high integration density in the scaling of conventional OTS and the material reliability problem caused by scaling.

[0069] The P-type intermediate layer 131 is used for data storage when the crystal state changes due to the voltage applied through the first electrode 110 and the second electrode 120. That is, the intermediate layer 131 refers to a phase change layer whose crystal state changes between a crystalline state and an amorphous state due to the voltage applied through the first electrode 110 and the second electrode 120. As a constituent material, a material having a typical phase change characteristic (or a characteristic of having low resistance in a crystalline state and having high resistance in an amorphous state) or a material having a reverse phase change characteristic (or a characteristic of having high resistance in a crystalline state and having low resistance in an amorphous state) can be used. Hereinafter, having high resistance in a crystalline state will refer to having relatively high resistance based on resistance obtained in an amorphous state, and having low resistance in an amorphous state will refer to having relatively low resistance based on resistance obtained in a crystalline state.

[0070] For example, the intermediate layer 131 may be formed using a phase change material containing a transition metal to have a reverse phase change characteristic. In this case, at least one of germanium (Ge), antimony (Sb) and tellurium (Te) may be used as a phase change material, and at least one of chromium (Cr), titanium (Ti), nickel (Ni), zinc (Zn), copper (Cu) and molybdenum (Mo) may be used as a transition metal. The content ratio of the transition metal contained in the phase change material may be adjusted to maximize the resistance ratio between the case where the intermediate layer 131 is in a crystalline state and the case where the intermediate layer 131 is in an amorphous state. For example, the content ratio of the transition metal (such as chromium (Cr) (or titanium (Ti), nickel (Ni), zinc (Zn), copper (Cu), molybdenum (Mo), etc.)) contained in the phase change material (such as germanium (Ge) and tellurium (Te)) may be adjusted to have a weight percentage of less than 10% based on Ge and Te, so as to maximize the resistance ratio between the case where the intermediate layer 131 is in a crystalline state and the case where the intermediate layer 131 is in an amorphous state.

[0071] The upper layer 132 and the lower layer 133 are formed at both ends of the intermediate layer 131 using an N-type semiconductor material. For example, each of the upper layer 132 and the lower layer 133 may be formed using an N-type semiconductor material including at least one of Zn, In, and Ga having low leakage current characteristics, a group IV semiconductor material, or a group III-V compound. Here, a zinc oxide (ZnOx)-based material may be used as the N-type semiconductor material, and may include at least one of aluminum-doped zinc oxide (AZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium zinc oxide (IGZO), and silver (Ag)-ZnO.

[0072] At least one tunneling film 134 is arranged in at least one of the region between the upper layer 132 and the middle layer 131 or the region between the lower layer 133 and the middle layer 131, and reduces leakage current in the middle layer 131 or prevents mixing between P-type dopants and N-type dopants. In one example, at least one tunneling film 134 may be arranged in both the region between the upper layer 132 and the middle layer 131 and the region between the lower layer 133 and the middle layer 131 (e.g., Figure 1a ), may be arranged only in the region between the lower layer 133 and the middle layer 131 (as shown in Figure 1b ), or may be arranged in the region between the upper layer 132 and the middle layer 131 (as shown Figure 1c shown).

[0073] In particular, at least one tunneling film 134 may be formed with a material to have a thickness to reduce leakage current or prevent mixing between P-type dopants and N-type dopants while allowing the flow of tunneling current. For example, a material (e.g., including SiO 2 、Si 3 N 4 , SiON and AlO x At least one tunneling film 134 is formed by using a high resistance material of at least one of the P-type dopants and the N-type dopants. In another example, the thickness of the at least one tunneling film 134 may be adjusted based on a target value for reducing leakage current or a target value for preventing mixing between a P-type dopant and an N-type dopant. In this regard, refer to Figure 4 , it can be seen that as the thickness of the at least one tunneling film 134 increases, the leakage current of the at least one tunneling film 134 is greatly reduced. Accordingly, the at least one tunneling film 134 can be formed to such a thickness that the leakage current of the at least one tunneling film 134 is reduced to a target value under the assumption that the tunneling current can flow.

[0074] As described above, the phase change memory cell 130 according to the embodiment has a structure including at least one tunneling film 134, and thus can significantly reduce the leakage current in the intermediate layer 131 and prevent the mixing between the P-type dopant and the N-type dopant. In addition, as described above, by using a material having a low leakage current characteristic as a material forming the upper layer 132 and the lower layer 133, the leakage current can be further reduced, and the mixing between the P-type dopant and the N-type dopant can be prevented.

[0075] The above-mentioned characteristics of the phase change memory unit 130 can also be fully applied to the phase change memory device 100 including the phase change memory unit 130. Accordingly, the phase change memory device 100 according to the present embodiment can also make the intermediate layer 131 used for data storage and the selection device integrated, and realize bidirectional current drive at the same time. Therefore, the disadvantages of conventional OTS in that it is difficult to achieve high integration density when scaling and the material reliability problems caused by scaling can be prevented and solved. In addition, the phase change memory device 100 includes at least one tunneling film 134, so that leakage current can be blocked and prevented, and at the same time, mixing between P-type dopants and N-type dopants can be prevented.

[0076] In addition, although the phase change memory cell 130 and the phase change memory device 100 including the phase change memory cell 130 explained above have been described as a simplified structure, they may be implemented to have a highly integrated 3D architecture. Figure 7 A detailed description thereof is given.

[0077] In addition, the following will refer to Figure 5 and Figure 6 The above-described phase-change memory cell 130 and a write operation and a read operation performed by the phase-change memory device 100 including the same are described.

[0078] Figure 5 is a schematic diagram for explaining a write operation of a phase change memory device according to an embodiment, and Figure 6 is a schematic diagram for explaining a read operation of a phase change memory device according to an embodiment. More specifically, Figure 5 and Figure 6 It is used to describe the above reference Figures 1a to 4 A schematic diagram of a write operation and a read operation of a phase change memory device of a phase change memory cell is described.

[0079] Reference Figure 5 , when the intermediate layer 510 is depleted due to the NP reverse bias in the NPN structure and the tunneling current flows, the phase-change memory cell according to the embodiment performs a write operation of changing the crystal state of the intermediate layer 510 .

[0080] For example, when Figure 5 When a reverse bias is applied to the NIP structure formed by the upper layer 520, the upper tunneling film 530, and the middle layer 510 shown, the middle layer 510 is depleted. Therefore, when the middle layer 510 is sufficiently depleted, a tunneling current flows as electrons of the upper layer 520 enter the middle layer 510 through the upper tunneling film 530, pass through the middle layer 510, and enter the lower tunneling film 540. Therefore, a write operation that changes the crystal state of the middle layer 510 according to a driving voltage (depending on a set voltage or a reset voltage) can be performed.

[0081] Reference Figure 6 In the phase-change memory cell according to the embodiment, when the crystal state of the intermediate layer 610 changes between the low resistance state and the high resistance state as shown in the figure, a voltage difference that means the change of the depletion start voltage occurs. Therefore, the phase-change memory cell according to the present embodiment can perform a read operation using these characteristics. For example, the phase-change memory cell can perform a read operation by reading a voltage difference caused by changing the depletion start voltage according to the change of the crystal state of the intermediate layer 610.

[0082] In contrast, the phase change memory cell can perform a read operation in a common manner. For example, the phase change memory cell can perform a read operation by directly reading the read current itself according to the change in the resistance of the intermediate layer 610 .

[0083] Figure 7 is a schematic diagram of a phase change memory having a 3D architecture according to an embodiment. In the following, a phase change memory refers to a memory having a 3D architecture by combining the above references. Figures 1a to 4 A 3D memory architecture is formed by multiple phase change memory devices.

[0084] Reference Figure 7 The phase change memory 700 includes at least one first electrode 710 formed to extend in a horizontal direction; a second electrode 720 formed to extend in a direction perpendicular to the at least one first electrode 710; and at least one phase change memory unit 730 between the at least one first electrode 710 and the second electrode 720.

[0085] In the phase change memory 700 having the above structure, at least one phase change memory unit 730 corresponds to the above reference Figures 1a to 4 That is, each of the at least one phase-change memory unit 730 may include: a P-type intermediate layer 731, which is used as data storage when the crystal state changes due to the voltage applied through the at least one first electrode 710 and the second electrode 720; an upper layer 732 and a lower layer 733 formed using an N-type semiconductor material at both ends of the intermediate layer 731; and at least one tunneling film 734, which is arranged in at least one of the region between the upper layer 732 and the intermediate layer 731 and the region between the lower layer 733 and the intermediate layer 731 to reduce leakage current in the intermediate layer 731 or prevent mixing between P-type dopants and N-type dopants.

[0086] Since each of the at least one phase change memory unit 730 corresponds to the above reference Figures 1a to 4 The phase change memory cell described herein is thus referred to as Figures 1a to 4The bidirectional current driving characteristics, the characteristics of integrating the data storage function with the selection device function, and the characteristics of reducing leakage current exhibited by the described phase change memory cell can be equally applied to each of the at least one phase change memory cell 730. Figures 1a to 4 A detailed description thereof is provided, so the detailed description thereof will be omitted.

[0087] Figure 8 is a schematic diagram of a phase change memory device according to an embodiment. Fig. 9 is a schematic diagram showing a phase change memory device implementing bidirectional current driving according to an embodiment. Fig.10 is a schematic diagram showing a selection device integrally implemented with a phase change layer in a phase change memory device according to an embodiment. Fig.11 is a schematic diagram for explaining characteristics of a Schottky diode formed in a phase change memory device according to an embodiment.

[0088] Reference Figures 8 to 11 The phase change memory device 800 according to the embodiment includes a first electrode 810 and a second electrode 820 and a phase change memory unit 830 interposed therebetween. The first electrode 810 and the second electrode 820 are formed using a conductive metal material such as W, TaN, and TiN.

[0089] The phase change memory unit 830 has a structure including a P-type phase change layer 831 and an N-type semiconductor layer 832 arranged on the P-type phase change layer 831, and the P-type phase change layer 831 is used for data storage when the crystal state changes due to the voltage applied through the first electrode 810 and the second electrode 820.

[0090] Therefore, the P-type phase change layer 831 and the N-type semiconductor layer 832 can form a PN diode, the P-type phase change layer 831 can form a Schottky diode at the contact interface with the second electrode 820, and the phase change memory unit 830 can be implemented using the formed PN diode and Schottky diode. Fig. 9 Bidirectional current drive shown.

[0091] Here, a PN diode and a Schottky diode may be used as a selection device configured to selectively switch a voltage applied to the P-type phase change layer 831 through the first electrode 810 and the second electrode 820 .

[0092] Accordingly, based on the P-type phase change layer 831 used for data storage, the phase change memory unit 830 can realize a PN diode and a Schottky diode working as a selection device. Therefore, the data storage function (or the function of representing data in the crystal state of the P-type phase change layer 831, which changes due to the voltage applied through the first electrode 810 and the second electrode 820) can be formed integrally with the function of the selection device (or selectively switching the voltage applied to the P-type phase change layer 831 through the first electrode 810 and the second electrode 820). That is, as Fig.10 As shown, the P-type phase change layer 831 can be used for data storage in the phase change memory cell 830 and also used as a selection device by forming a PN diode and a Schottky diode.

[0093] By integrating the phase change layer 831 with the selection device, the phase change memory cell 830 can prevent and solve the disadvantages of the conventional OTS in achieving high integration density during scaling and the material reliability problem caused by scaling.

[0094] Although the P-type phase change layer 831 includes a phase change material whose crystal state changes between a crystalline state and an amorphous state due to a voltage applied through the first electrode 810 and the second electrode 820, the phase change material does not have a typical phase change characteristic (or a characteristic of having low resistance in a crystalline state and high resistance in an amorphous state), but has a reverse phase change characteristic (or a characteristic of having high resistance in a crystalline state and low resistance in an amorphous state). Hereinafter, having high resistance in a crystalline state means having relatively high resistance based on resistance obtained in an amorphous state, and having low resistance in an amorphous state means having relatively low resistance based on resistance obtained in a crystalline state.

[0095] Specifically, the P-type phase change layer 831 may be formed by doping nitrogen into a phase change material containing a transition metal to form a Schottky diode having a stable Schottky characteristic at the contact interface with the second electrode 820. In this case, at least one of Ge, Sb, and Te may be used as the phase change material, and at least one of Cr, Ti, Ni, Zn, Cu, and Mo may be used as the transition metal.

[0096] The content ratio of the transition metal contained in the phase change material can be adjusted to maximize the resistance ratio between the case where the phase change layer 831 is in a crystalline state and the case where the phase change layer 831 is in an amorphous state. For example, the content ratio of the transition metal (e.g., Cr (or Ti, Ni, Zn, Cu, Mo, etc.)) contained in the phase change material (e.g., Ge and Te) can be adjusted to have a weight percentage of less than 10% based on Ge and Te, thereby maximizing the resistance ratio between the case where the phase change layer 831 is in a crystalline state and the case where the phase change layer 831 is in an amorphous state.

[0097] In addition, the concentration of nitrogen doped into the phase change material containing the transition metal may be adjusted so that the P-type phase change layer 831 forms a Schottky diode having stable Schottky characteristics at the contact interface with the second electrode 820 .

[0098] As described above, in the phase change memory cell 830, the P-type phase change layer 831 can be formed by doping nitrogen into the phase change material containing the transition metal. Fig.11 As shown, the Schottky diode formed at the contact interface between the P-type phase change layer 831 and the second electrode 820 may have a stable Schottky characteristic and exhibit the same performance as a PN diode.

[0099] The N-type semiconductor layer 832 may be formed using an N-type oxide semiconductor material including at least one cation of Zn, In, and Ga, a Group IV semiconductor material, or a Group III-V compound having low leakage current characteristics, and thus may achieve excellent leakage current characteristics with a wide band gap. Here, the ZnO-based semiconductor material having low leakage current characteristics may be used. x A material may be used as the N-type oxide semiconductor material, and at least one of AZO, ZTO, IZO, ITO, IGZO, and Ag-ZnO may be used as the ZnO-based x materials.

[0100] As described above, the phase change memory cell 830 according to the embodiment forms a PN diode and a Schottky diode based on the P-type phase change layer 831 and the N-type semiconductor layer 832. Therefore, the phase change layer 831 used for data storage can be integrated with the selection device and can realize bidirectional current driving at the same time. Therefore, the phase change memory cell 830 can prevent and solve the disadvantages of the difficulty in achieving high integration density in the scaling of conventional OTS and the material reliability problems caused by scaling.

[0101] In addition, the phase change memory cell 830 may block and prevent leakage current by forming the N-type semiconductor layer 832 using low leakage current characteristics.

[0102] The above-mentioned characteristics of the phase change memory unit 830 can also be fully applied to the phase change memory unit 830 including the phase change memory unit 830. Accordingly, the phase change memory device 800 according to the present embodiment can also realize the phase change layer 831 used for data storage in an integrated manner with the selection device, while realizing bidirectional current drive. Therefore, the disadvantages of the difficulty in achieving high integration density in the scaling of the conventional OTS and the material reliability problems caused by the scaling can be prevented and solved. In addition, the N-type semiconductor layer 832 can be formed using a material having a low leakage current characteristic, and therefore, the leakage current can be blocked and prevented.

[0103] In addition, although the phase change memory cell 830 and the phase change memory device 800 including the same explained above have been described as a simplified structure, they may be implemented to have a highly integrated 3D architecture. A detailed description thereof will be provided below.

[0104] Fig.12 is a schematic diagram of a phase change memory implemented with a 3D architecture according to an embodiment.

[0105] Reference Fig.12 The phase change memory 1200 includes at least one first electrode 1210 formed to extend in a lateral direction; a second electrode 1220 formed to extend in a direction perpendicular to the at least one first electrode 1210; and at least one phase change memory unit 1230 interposed between the at least one first electrode 1210 and the second electrode 1220.

[0106] In the phase change memory 1200 having the above structure, at least one phase change memory unit 1230 corresponds to the above reference Figures 8 to 11 That is, each of the at least one phase change memory unit 1230 may include: at least one P-type phase change layer 1231, which is interposed between at least one first electrode 1210 and the second electrode 1220 and is used as data storage when the crystal state changes due to the voltage applied through the at least one first electrode 1210 and the second electrode 1220; and at least one N-type semiconductor layer 1232, which is in contact with the at least one P-type phase change layer 1231 and is interposed between the at least one first electrode 1210 and the second electrode 1220. Therefore, the at least one P-type phase change layer 1231 and the at least one N-type semiconductor layer 1232 form a PN diode, and the at least one P-type phase change layer 1231 forms a Schottky diode at the contact interface with the second electrode 1220.

[0107] A detailed description of each of the at least one phase change memory unit 1230 including at least one P-type phase change layer 1231 and at least one N-type semiconductor layer 1232 will be omitted because reference has been made to the Figures 8 to 12 A detailed description is provided.

[0108] Fig.13 is a schematic diagram of a dynamic random access memory (DRAM) selection device according to an embodiment. Fig.14 According to another embodiment, Fig.13 Schematic diagram of a DRAM selection device shown in FIG. Fig.15 is a schematic diagram for explaining characteristics of an indium gallium zinc oxide (IGZO) channel structure included in a DRAM selection device according to an embodiment.

[0109] Reference Fig.13 and Fig.14 , a DRAM selection device 1300 according to an embodiment includes a silicon substrate 1310 , a word line 1320 buried in the silicon substrate 1310 , and an IGZO channel structure 1330 formed in the silicon substrate 1310 to surround at least a portion of the word line 1320 .

[0110] Here, the word line 1320 is buried in the silicon substrate 1310, and thus a recessed channel array transistor (RCAT) and / or buried word line (BWL) structure with increased channel length may be applied. Since the word line 1320 has the same structure as a conventional RCAT and / or BWL, a detailed description thereof is omitted.

[0111] The IGZO channel structure 1330 is formed using an IGZO material (e.g., a ZnOx-based material, which is an oxide including at least one cation of Zn, In, and Ga) in the silicon substrate 1310, and is used as at least a portion of a channel region in the DRAM selection device 1300. In one example, as the channel region of the DRAM selection device 1300, only the IGZO channel structure 1330 may be used, or a partial region of the silicon substrate 1310 and the IGZO channel structure 1330 may be used. Hereinafter, although a case where the IGZO channel structure 1330 is formed using an IGZO material has been described, the present disclosure is not limited thereto, and the IGZO channel structure 1330 may be formed using at least one of AZO, ZTO, IZO, ITO, IGZO, and Ag-ZnO.

[0112] In this case, whether the IGZO channel structure 1330 is used as the entirety or a portion of the channel region in the DRAM selection device 1300 depends on the depth of the IGZO channel structure 1330 surrounding at least a portion of the word line 1320. Fig.13 As shown, the IGZO channel structure 1330 has a depth of about 2 / 3 of the depth of the word line 1320 and is formed to surround the word line 1320. Therefore, Fig.13 The DRAM selection device 1300 may use a partial region 1311 of a silicon substrate 1310 and an IGZO channel structure 1330 as a channel region.

[0113] As another example, Fig.14 As shown, the depth of the IGZO channel structure 1330 is greater than the depth of the word line 1320 and is formed to surround the word line 1320. Fig.14 The DRAM selection device 1300 may use the IGZO channel structure 1330 as the entire channel region.

[0114] As described above, the depth of at least a portion of the IGZO channel structure 1330 surrounding the word line 1320 may be determined as a value for allowing the IGZO channel structure 1330 to be used as at least a portion of the channel region in the DRAM selection device 1300. For example, the depth of at least a portion of the IGZO channel structure 1330 surrounding the word line 1320 may be determined as a value greater than or equal to a threshold depth for allowing the IGZO channel structure 1330 to be used as at least a portion of the channel region in the DRAM selection device 1300.

[0115] In addition, the depth of at least a portion of the IGZO channel structure 1330 surrounding the word line 1320 may be determined as a value for reducing the leakage current by more than a predetermined value in the DRAM selection device 1300. That is, because the IGZO channel structure 1330 has a low leakage current characteristic compared to the silicon substrate 1310, the depth of the IGZO channel structure 1330 may be determined so that the specific gravity of the IGZO channel structure 1330 on the channel region is increased to be more than the specific gravity of the silicon substrate 1310 to suppress the leakage current on the channel region to a target value.

[0116] like Fig.15 As shown in (a) of FIG. 1 , since IGZO, which is a material forming the IGZO channel structure 1330, has a wider band gap than silicon, IGZO has a very low leakage current characteristic. Therefore, the IGZO channel structure 1330 having a low leakage current characteristic has a normal state. Fig.15 The current characteristics shown in (b) in FIG.

[0117] Accordingly, the DRAM selection device 1300 according to this embodiment can use the IGZO channel structure 1330 having the low leakage current characteristic as at least a part of the channel region, thereby achieving the technical effect of making the substrate itself have extremely low leakage current characteristics.

[0118] The IGZO channel structure 1330 may be formed in the silicon substrate 1310 by using an atomic layer deposition (ALD) process. The DRAM selection device 1300 including the IGZO channel structure formed using the ALD process may have Fig.13 and Fig.14 The structure shown.

[0119] However, the present disclosure is not limited thereto, and the IGZO channel structure 1330 may be formed in the silicon substrate 1310 using an epitaxial growth process. In this case, the DRAM selection device 1300 may further include a component for implementing the epitaxial growth process. Fig.16 .

[0120] In addition, the DRAM selection device 1300 according to the embodiment may be disposed in a vertical direction or a horizontal direction and stacked in plurality to form a 3D structure.

[0121] Fig.16 is a schematic diagram of a DRAM selection device according to another embodiment.

[0122] Reference Fig.16 According to another embodiment, a DRAM selection device 1600 may include a silicon substrate 1610, a word line 1620 buried in the silicon substrate 1610, and an IGZO channel structure 1630 formed in the silicon substrate 410 to surround at least a portion of the word line 1620. Therefore, the DRAM selection device 1600 may have the same Fig.13 The DRAM selection device 1300 shown has a similar structure. However, Fig.16 The DRAM selection device 1600 is Fig.13 The DRAM selection device 1300 is different in that the DRAM selection device 1600 further includes an IGZO seed 440 for the epitaxial growth process. That is, Figure 4 The DRAM selection device 1600 may form the IGZO channel structure 1630 using an epitaxial growth process based on an IGZO seed 1640 .

[0123] exist Fig.16 In the DRAM selection device 1600, other components except the IGZO seed 1640 are formed in the same structure to perform the same Fig.13 The other components of the DRAM selection device 1300 have the same functions, and therefore, their detailed descriptions are omitted.

[0124] Fig.17 is a flowchart of a method of manufacturing a dynamic random access memory (DRAM) selection device according to an embodiment, and Figures 18 to 25 is a schematic diagram of a method of manufacturing a DRAM selection device according to an embodiment.

[0125] Hereinafter, it is assumed that the method of manufacturing a DRAM selection device according to the embodiment is performed by a mechanized and automated manufacturing system.

[0126] Reference Fig.17 In operation S1710, the manufacturing system prepares Fig.18 Silicon substrate 1810 is shown.

[0127] Hereinafter, in operation S1720, the manufacturing system etches at least a portion 1910 of the silicon substrate 1810 and generates a sacrificial film 2010. For example, the manufacturing system etches the at least a portion 1910 of the silicon substrate 1810 (eg, Fig.19), and a sacrificial film 2010 is generated in the etched space 1910 (as shown in Fig. 20 shown).

[0128] Next, in operation S1730, the manufacturing system etches at least a portion 2110 of the silicon substrate 1018 to expose at least a portion 2011 of the sacrificial film 2010, and forms an IGZO channel structure 2220 in the space 2210 in which at least a portion 2110 is etched. Fig.21 As shown, the manufacturing system can perform a groove etching on at least a portion 2110 of the silicon substrate 1810 to expose at least a portion 2011 of the sacrificial film 2010, and Fig. 22 As shown, an IGZO channel structure 2220 is formed in a space 2210 where at least a portion 2110 is etched by using an ALD process or an epitaxial growth process. When the IGZO channel structure 2220 is formed using an epitaxial growth process, the manufacturing system may generate an IGZO seed (not shown) for an epitaxial growth process in the space 2210 of at least the etched portion 2110, and form the IGZO channel structure 2220 using an epitaxial growth process based on the IGZO seed. As described above, the IGZO channel structure 2220 used in operation S1730 may be used as at least a portion of a channel region in a DRAM selection device.

[0129] In this case, the manufacturing system may form the IGZO channel structure 2220 to surround at least a portion of the word line 2420, which will be generated in operation S1740 described below. In particular, the depth of the IGZO channel structure 2220 surrounding at least a portion of the word line 2420 may be determined as a value for allowing the IGZO channel structure 2220 to be used as at least a portion of the channel region in the DRAM selection device, and / or a value for reducing the leakage current in the DRAM selection device by more than a predetermined value.

[0130] Next, in operation S1740, the manufacturing system removes the sacrificial film 2010 of the silicon substrate 1810 and generates a word line 2420 in the space 2310 from which the sacrificial film 2010 is removed. Fig.23 As shown, the manufacturing system can remove the sacrificial film 2010 of the silicon substrate 1810, and as shown in Fig.24 As shown, a gate oxide 2410 and a word line 2420 are generated by forming a film in the space 2310 from which the sacrificial film 2010 is removed.

[0131] In the following, Fig.25 As shown, in operation S1750 , the manufacturing system forms an electrode 2510 to be connected to a bit line and a capacitor on the IGZO channel structure 2220 .

[0132] In the above operations S1710 to S1750, the operation of generating the sacrificial film 2010, the operation of generating the IGZO channel structure 2220, and the operation of generating the word line 2420 may be repeatedly performed a predetermined number of times on the silicon substrate 610, or may be repeatedly performed a predetermined number of times on other silicon substrates stacked above and below the silicon substrate 1810. Thus, a plurality of DRAM selection devices may be manufactured in a vertical direction or a horizontal direction to form a 3D structure.

[0133] Although the embodiments have been described above with reference to limited embodiments and drawings, it will be understood by those skilled in the art that various changes and modifications may be made therein based on the above description. For example, even when the described techniques are performed in a different order than the described methods and / or even when the described components (e.g., systems, structures, devices, circuits, etc.) are combined in a different form than the described methods or replaced by other components or equivalents, appropriate results may be achieved.

[0134] Accordingly, other implementations, other examples, and equivalents of the claims are within the scope and spirit of the claims described below.

Claims

1. A phase change memory device, comprising: a first electrode; a second electrode; as well as a phase change memory unit between the first electrode and the second electrode, Wherein, the phase change memory unit comprises: A P-type intermediate layer is used for data storage because a crystal state thereof changes due to a voltage applied through the first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling film disposed in at least one of a region between the upper layer and the middle layer and a region between the lower layer and the middle layer, the at least one tunneling film being configured to reduce leakage current in the middle layer or prevent mixing between a P-type dopant and an N-type dopant, Wherein, the phase change memory unit is configured as follows: A read operation is performed to read a voltage difference caused by a change in a depletion start voltage due to a change in a crystal state of the intermediate layer.

2. The phase change memory device according to claim 1, wherein: The at least one tunneling thin film is formed using a material to have a thickness to reduce the leakage current or prevent mixing between the P-type dopant and the N-type dopant while allowing a tunneling current to flow.

3. The phase change memory device according to claim 1, wherein: The phase change memory cell is formed to have an NPN structure to selectively switch a voltage applied to the intermediate layer from the first electrode and the second electrode.

4. The phase change memory device according to claim 1, wherein: The phase change memory cell is configured to realize bidirectional current driving by forming a bidirectional PN diode using an NPN structure.

5. The phase change memory device according to claim 1, wherein: The phase change memory cell is configured to perform a write operation of changing a crystal state of the middle layer when the middle layer is depleted due to a NP reverse bias in an NPN structure and a tunneling current flows.

6. The phase change memory device according to claim 1, wherein: The intermediate layer is formed using a phase change material containing a transition metal to have a reverse phase change characteristic.

7. A phase change memory having a three-dimensional 3D architecture, the phase change memory comprising: at least one first electrode formed to extend in a horizontal direction; a second electrode formed to extend in a direction perpendicular to the at least one first electrode; as well as at least one phase change memory unit, between the at least one first electrode and the second electrode, Wherein, each of the at least one phase change memory unit comprises: The P-type intermediate layer is used for data storage because the crystal state changes due to the voltage applied through the at least one first electrode and the second electrode; an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and at least one tunneling film disposed in at least one of a region between the upper layer and the middle layer or a region between the lower layer and the middle layer, the at least one tunneling film being configured to reduce leakage current in the middle layer or prevent mixing between a P-type dopant and an N-type dopant, Wherein, each of the at least one phase change memory unit is configured as: A read operation is performed to read a voltage difference caused by a change in a depletion start voltage due to a change in a crystal state of the intermediate layer.

8. A phase change memory device, comprising: a first electrode; a second electrode; A P-type phase change layer, disposed between the first electrode and the second electrode, the P-type phase change layer being used for data storage because a crystal state of the P-type phase change layer changes due to a voltage applied through the first electrode and the second electrode; as well as An N-type semiconductor layer is arranged on the P-type phase change layer, Wherein, the P-type phase change layer and the N-type semiconductor layer form a PN diode, and The P-type phase change layer forms a Schottky diode at a contact interface with the second electrode.

9. The phase change memory device according to claim 8, wherein: The phase change memory device is configured to implement bidirectional current driving using the PN diode and the Schottky diode.

10. The phase change memory device according to claim 8, wherein: The P-type phase change layer is formed by doping nitrogen into a phase change material containing a transition metal to form a Schottky diode having a stable Schottky characteristic at a contact interface with the second electrode.

11. A dynamic random access memory (DRAM) selection device, configured to reduce leakage current, the DRAM selection device comprising: Silicon substrate; A word line, buried in the silicon substrate; as well as an indium gallium zinc oxide (IGZO) channel structure formed in the silicon substrate to surround at least a portion of the word line, Wherein, the IGZO channel structure is used as at least a part of the channel region in the DRAM selection device.

12. The DRAM selection device according to claim 11, wherein: The depth of the IGZO channel structure surrounding at least a portion of the word line is determined to be a value for allowing the IGZO channel structure to be used as at least a portion of the channel region in the DRAM selection device and / or a value for reducing the leakage current in the DRAM selection device above a predetermined value.

13. The DRAM selection device according to claim 11, wherein: The IGZO channel structure is formed in the silicon substrate by using an atomic layer deposition (ALD) process or an epitaxial growth process.

14. The DRAM selection device according to claim 11, wherein: The DRAM selection device is disposed and stacked in a plurality in a vertical direction or a horizontal direction to form a 3D structure.

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