Bad block detection method and test system for non-volatile memory device

Abstract

A bad block detection method and a test system for a nonvolatile memory device are disclosed. The test system includes: a nonvolatile memory device including a plurality of memory blocks operating in a multi-plane mode; and a tester detecting bad blocks of the nonvolatile memory device. The nonvolatile memory device generates a ready / busy signal based on whether an erase cycle for detecting bad blocks is performed. When at least one normal block is detected from the plurality of memory blocks included in a plane operating in the multi-plane mode, the nonvolatile memory device generates a ready / busy signal having a first busy interval. When all of the plurality of memory blocks included in the plane operating in the multi-plane mode are detected as bad blocks, the nonvolatile memory device generates a ready / busy signal having a second busy interval shorter than the first busy interval.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2020-0026038 filed on March 2, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more inventive concepts described herein relate to a semiconductor memory, and more particularly, to a test system and a test method thereof for reducing a time taken to detect a bad block. Background Art

[0003] A semiconductor memory device is a storage device that can store data and read the stored data when necessary. Semiconductor memory devices can be mainly classified as volatile memory devices or non-volatile memory devices. Data stored in a volatile memory device disappears when the power is turned off. Data stored in a non-volatile memory device is retained even when the power is turned off. Non-volatile memory devices include mask read-only memory (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), etc.

[0004] Typically, data cannot be freely written to MROM, PROM, and EPROM, and cannot be freely erased from MROM, PROM, and EPROM, so it is difficult for users to update the information stored therein. In contrast, data can be electrically written to and electrically erased from EEPROM. Therefore, the demand for EEPROM is increasing, especially for system programming and auxiliary storage devices that need to update stored information. In more detail, compared with conventional EEPROM, flash EEPROM is more highly integrated. Therefore, it is advantageous to apply flash EEPROM instead of conventional EEPROM to high-capacity auxiliary storage devices. Among flash EEPROMs, NAND (NAND) type flash EEPROM (hereinafter, referred to as "NAND flash") can be more highly integrated than any other flash EEPROM. In addition, NAND flash can have high capacity and excellent write performance and erase performance.

[0005] Access to the NAND flash memory is performed in units of blocks. Because access to the NAND flash memory is performed in units of blocks, when a block includes a bad bit, the block may be a "bad block", so that a bad block of the NAND flash memory is caused by even one bad bit. When data is written to a bad block, various errors (such as read errors, write errors, and erase errors) may occur. In addition, even if a read operation, a write operation, or an erase operation is performed normally, the data stored in the bad block may be changed. Therefore, for the purpose of ensuring that the bad block does not cause an error, the NAND flash memory may perform a test for detecting a bad block. Summary of the invention

[0006] Embodiments of the present disclosure provide a testing system and a testing method thereof for reducing the time spent on detecting bad blocks.

[0007] According to an exemplary embodiment, a test system includes: a nonvolatile memory device including a plurality of memory blocks operating in a multi-plane mode; and a tester detecting bad blocks of the nonvolatile memory device. The nonvolatile memory device generates a ready / busy signal based on whether an erase cycle for detection of bad blocks is performed. When at least one normal block is detected from a plurality of blocks included in a plane operating in the multi-plane mode, the nonvolatile memory device generates a ready / busy signal having a first busy interval. When all blocks included in a plane operating in the multi-plane mode are detected as bad blocks, the nonvolatile memory device generates a ready / busy signal having a second busy interval shorter than the first busy interval.

[0008] According to an exemplary embodiment, a nonvolatile memory device includes a plurality of memory blocks operating in a multi-plane mode. A bad block detection method of the nonvolatile memory device includes: receiving a command signal from the outside at the nonvolatile memory device; receiving an address signal from the outside at the nonvolatile memory device. The bad block detection method also includes: receiving a confirmation command signal from the outside at the nonvolatile memory device; detecting a bad block at the nonvolatile memory device based on address information included in the address signal. The bad block detection method also includes: generating a ready / busy signal based on whether an erase cycle for detection of a bad block is performed at the nonvolatile memory device. When at least one normal block is detected from a plurality of blocks included in a plane operating in a multi-plane mode, the nonvolatile memory device generates a ready / busy signal having a first busy interval. When all blocks included in a plane operating in a multi-plane mode are detected as bad blocks, the nonvolatile memory device generates a ready / busy signal having a second busy interval shorter than the first busy interval.

[0009] According to an exemplary embodiment, a nonvolatile memory device includes a plurality of memory blocks operating in a multi-plane mode. A bad block detection method for a nonvolatile memory device includes: a tester inputs a command signal to the nonvolatile memory device; and the tester inputs an address signal for selecting a memory block to the nonvolatile memory device. The bad block detection method also includes: the tester inputs a confirmation command signal to the nonvolatile memory device; and the tester receives a ready / busy signal based on whether an erase cycle for bad block detection is performed. When a ready / busy signal having a first busy interval is received, the tester determines at least one of the plurality of memory blocks included in a plane operating in a multi-plane mode as a normal block. When a ready / busy signal having a second busy interval shorter than the first busy interval is received, the tester determines all of the plurality of memory blocks included in a plane operating in a multi-plane mode as bad blocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of one or more inventive concepts described herein will become apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a test system according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A block diagram of a configuration of a nonvolatile memory device.

[0013] Figure 3 It is shown Figure 2 A block diagram of the configuration of the control logic circuit.

[0014] Figure 4 It is shown Figure 2 A block diagram of the configuration of a memory cell array.

[0015] Figure 5 It is shown Figure 2 A block diagram of another configuration of a memory cell array.

[0016] Figure 6 is a circuit diagram of the memory block.

[0017] Figure 7 is a flowchart illustrating a bad block processing method of a nonvolatile memory device according to an embodiment of the present disclosure.

[0018] Fig. 8A is a diagram illustrating aspects of generating a busy portion of a ready / busy signal R / B when a bad block handling method is applied to a two-plane mode according to an embodiment of the present disclosure.

[0019] Figure 8B is a diagram illustrating an aspect of generating a busy portion of a ready / busy signal R / B when a bad block handling method is applied to a multi-plane mode according to an embodiment of the present disclosure.

[0020] Fig. 9 It is shown Figure 1 Flow chart of the operating method of the testing machine.

[0021] Fig. 10A is a diagram illustrating an operation in a case where a bad block does not occur in a two-plane mode according to an embodiment of the present disclosure.

[0022] Fig. 10B is a timing diagram in the case where no bad block occurs in the two-plane mode according to an embodiment of the present disclosure.

[0023] Fig.11A is a diagram illustrating an operation in the case where a bad block occurs in at least one plane in a two-plane mode according to an embodiment of the present disclosure.

[0024] Fig. 11B is a timing diagram in the case where a bad block occurs in at least one plane in a two-plane mode according to an embodiment of the present disclosure.

[0025] Fig. 12A is a diagram illustrating an operation in the case where bad blocks occur in all planes in a two-plane mode according to an embodiment of the present disclosure.

[0026] Fig. 12B is a timing diagram in the case where bad blocks occur in all planes in a two-plane mode according to an embodiment of the present disclosure.

[0027] Fig.13A is a diagram illustrating an operation in a case where a bad block does not occur in a four-plane mode according to another embodiment of the present disclosure.

[0028] Fig. 13B is a timing diagram in a case where no bad blocks occur in a four-plane mode according to another embodiment of the present disclosure.

[0029] Fig.14A is a diagram illustrating an operation in a case where a bad block occurs in at least one plane in a four-plane mode according to another embodiment of the present disclosure.

[0030] Fig. 14B is a timing diagram in the case where a bad block occurs in at least one plane in a four-plane mode according to another embodiment of the present disclosure.

[0031] Fig.15A is a diagram illustrating an operation in a case where bad blocks occur in some planes in a four-plane mode according to another embodiment of the present disclosure.

[0032] Fig. 15B is a timing diagram in the case where bad blocks occur in some planes in a four-plane mode according to another embodiment of the present disclosure.

[0033] Fig.16A is a diagram illustrating an operation in the case where bad blocks occur in all planes in a four-plane mode according to another embodiment of the present disclosure.

[0034] Fig. 16B is a timing diagram in the case where bad blocks occur in all planes in a four-plane mode according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure may be described in detail and clearly to the extent that a person of ordinary skill in the art can easily implement one or more inventive concepts described herein.

[0036] The terms used in the specification are provided to describe the embodiments without limiting the aspects of one or more inventive concepts described herein. As used in the specification, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise" and / or "comprising" when used in the specification specify the presence of steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other steps, operations, elements, components and / or their groups.

[0037] Unless otherwise defined, all terms (including technical and scientific terms) used in the specification should have the same meaning as those commonly understood by those skilled in the art in one or more fields to which one or more inventive concepts described herein belong. Unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should not be interpreted in an idealized or overly formal sense. Throughout the specification, the same reference numerals represent the same elements.

[0038] Figure 1 is a block diagram illustrating a test system according to an embodiment of the present disclosure.

[0039] Reference Figure 1 , the test system may include a tester 100 and a nonvolatile memory device 200 .

[0040] The test machine 100 may include a memory storing instructions and a processor executing the instructions to perform one or more functions attributed to (or belonging to) the test machine 100 herein. Alternatively or additionally, the test machine 100 may include circuitry (such as an application specific integrated circuit (ASIC)) that implements one or more functions attributed to the test machine 100 herein.

[0041] The tester 100 may detect a bad block of the nonvolatile memory device 200. The tester 100 may output an input signal Input to the nonvolatile memory device 200. The input signal Input may include an erase command for detecting a bad block. The tester 100 may receive an output signal Output generated from the nonvolatile memory device 200. The output signal Output may include a ready / busy signal R / B indicating a block status.

[0042] The nonvolatile memory device 200 may include a NAND flash memory. For example, the nonvolatile memory device 200 may operate in a two-plane mode. In the two-plane mode, the block (BLK (refer to Figure 5 )) may be arranged in each of the two planes, and blocks from each plane may be processed together. The non-volatile memory device 200 may include multiple memory blocks as NAND flash memory operating in a two-plane mode. Each memory block may include multiple pages. For NAND flash memory, the two-plane mode may involve operations (such as read operations or write operations) performed simultaneously on memory blocks in two different pages. Each page may include multiple memory cells. Each memory cell may store one data bit (or referred to as: bit) or two or more data bits. For NAND flash memory, the two-plane mode may involve operations (such as read operations or write operations) performed simultaneously on memory blocks in two different pages.

[0043] The tester 100 may detect bad blocks of the nonvolatile memory device 200 based on the ready / busy signal R / B generated from the nonvolatile memory device 200. Whether a bad block is detected may be determined based on the busy interval length (or referred to as the busy time length) of the ready / busy signal R / B. According to one aspect of the present disclosure, in the case where at least one but less than all of a plurality of blocks belonging to two planes operating in a two-plane mode are detected as normal blocks, the ready / busy signal R / B may have a first busy interval. In contrast, in the case where all blocks belonging to two planes operating in a two-plane mode are detected as bad blocks, the ready / busy signal R / B may have a second busy interval that is shorter than the first busy interval.

[0044] The bad block erase cycle (erase loop) is used to detect bad blocks, and may be referred to as an erase cycle herein. The bad block erase cycle consists of a block selection interval, an erase execution interval, a recovery interval, and a read verification interval. However, when a bad block is detected, the erase cycle may not proceed to the end of the erase cycle. For example, detecting a bad block may cause one or more of the block selection interval, the erase execution interval, the recovery interval, and the read verification interval to be skipped. Therefore, in the case where all blocks belonging to two planes operating in a two-plane mode are detected as bad blocks, the test system may only check whether a bad block occurs, without executing the erase cycle to the full extent for each of the detected bad blocks. That is, the erase cycle may not be executed until the maximum value (maximum value) or the maximum extent. In one example, the maximum value may be a time value corresponding to the total time of the block selection interval, the erase execution interval, the recovery interval, and the read verification interval. The test system may reduce the time loss of the process according to the bad block erase cycle by only checking whether a bad block occurs and executing the erase cycle. Therefore, once a determination is made that a block is a bad block, the maximum potential extent of processing that would otherwise be performed is not performed, which reduces the total time loss for processing a bad block erase cycle. In one example, the ready / busy signal R / B may be based on whether an erase cycle for detecting a bad block is in progress.

[0045] Figure 2 It is shown Figure 1 A block diagram of a configuration of a nonvolatile memory device.

[0046] Reference Figure 2 , the nonvolatile memory device 200 may include a memory cell array 210 , a decoder 220 , a page buffer 230 , an input / output (I / O) buffer 240 , and a control logic circuit 250 .

[0047] The memory cell array 210 may be connected to the decoder 220 through word lines WL, select lines SSL (string select lines) and GSL (ground select lines). The memory cell array 210 may be connected to the page buffer 230 through bit lines BL. The memory cell array 210 may include a plurality of memory blocks. Each memory block may include a plurality of NAND cell strings. Figure 6 The structure of the memory block included in the memory cell array 210 is described more fully.

[0048] The decoder 220 may select one of the memory blocks of the memory cell array 210 in response to the address signal ADD. The decoder 220 may provide a word line voltage corresponding to the operation mode to the word line of the selected memory block. In addition, the decoder 220 may provide a selection signal to the selection lines SSL and GSL to select the memory block.

[0049] The page buffer 230 may operate as a write driver or a sense amplifier according to an operation mode. In a programming operation, the page buffer 230 may supply a bit line voltage corresponding to data to be programmed to a selected bit line BL associated with the memory cell array 210. In a read operation, the page buffer 230 may sense data stored in a selected memory cell through the bit line BL. The page buffer 230 may latch the sensed data and may output the latched data to the outside.

[0050] In a program operation, the input / output buffer 240 may transfer a write data signal DATA to the page buffer 230. In a read operation, the input / output buffer 240 may output a read data signal DATA provided from the page buffer 230 to the outside. The input / output buffer 240 may transfer a command signal CMD and an address signal ADD received from the outside to the control logic circuit 250 or the decoder 220.

[0051] The control logic circuit 250 may control the decoder 220 and the page buffer 230 in response to the command signal CMD, the command latch enable signal CLE, the address latch enable signal ALE, or the write enable signal / WE. The control logic circuit 250 may allow the decoder 220 to generate biases in various schemes according to the program command. Specifically, the control logic circuit 250 may output information about the programming result according to the request.

[0052] Figure 3 It is shown Figure 2 A block diagram of the configuration of the control logic circuit.

[0053] Reference Figure 3 The control logic circuit 250 may include an I / O control circuit 251, a status register 252, an address register 253, a command register 254, a memory chip control circuit 255, a high voltage generator 256, a bad block table 257, a flag generator 258 and a ready / busy control circuit 259.

[0054] The I / O control circuit 251 can receive the nonvolatile memory device 200 (see Figure 1 ) required for the operation of the I / O control circuit 251. For example, the signal received by the I / O control circuit 251 may include a command signal CMD, an address signal ADD, or a data signal DATA. In addition, the I / O control circuit 251 may notify the state of the nonvolatile memory device 200 to the outside.

[0055] The status register 252 may receive a signal from the memory chip control circuit 255, and may output the received signal to the I / O control circuit 251. The address register 253 may receive an address signal ADD from the I / O control circuit 251, and may output the received signal to the bad block table 257. The command register 254 may receive a command signal CMD from the I / O control circuit 251, and may output the received signal to the memory chip control circuit 255.

[0056] The memory chip control circuit 255 may receive a signal provided from the outside. For example, the signal provided from the outside may include a command latch enable signal CLE, an address latch enable signal ALE, and a write latch enable signal / WE. The memory chip control circuit 255 may control the memory chip according to the signal provided from the outside. In addition, the memory chip control circuit 255 may output one or more control signals to the high voltage generator 256 and the ready / busy control circuit 259.

[0057] The high voltage generator 256 may receive a control signal from the memory chip control circuit 255. The high voltage generator 256 may generate a high voltage based on the received control signal. The high voltage generated by the high voltage generator 256 may be output to the memory chip. The level of the high voltage generated by the high voltage generator 256 during the busy time interval required for the bad block detection test may be consistent or substantially consistent (such as by consistently varying within a range of, for example, 2% or 5%). In one example, the voltage of the non-volatile memory device may be consistently maintained during the busy time interval (e.g., the first busy interval or the second busy interval) required for the bad block detection test.

[0058] The bad block table 257 may receive the address signal ADD output from the address register 253. The bad block table 257 may store bad block information of the memory device. The bad block table 257 may read the bad block information corresponding to the received address signal ADD. When the result of comparing the bad block information of the bad block table 257 with the address signal ADD indicates a bad block, the bad block table 257 may output a bad block flag signal BBLK.

[0059] The flag generator 258 may receive the bad block flag signal BBLK generated by the bad block table 257. The flag generator 258 may generate a flag signal FLG indicating bad block information of the memory chip based on the bad block flag signal BBLK. The flag generator 258 may output the flag signal FLG to the outside through the flag terminal.

[0060] The ready / busy control circuit 259 may output a ready / busy signal R / B indicating a ready state or a busy state of the memory chip. The ready / busy control circuit 259 may include an NMOS transistor having a source connected to ground and a drain connected to a ready / busy terminal. The gate of the NMOS transistor may be controlled by the memory chip control circuit 255. The ready / busy control circuit 259 may generate a ready / busy signal R / B based on a bad block detection result of the nonvolatile memory device 200.

[0061] Figure 4 It is shown Figure 2 A block diagram of the configuration of a memory cell array.

[0062] Reference Figure 4 , the memory cell array 210 a according to an embodiment of the present disclosure may include a user block 211 , a reserved block 212 , a bad block 213 , and a meta block 214 .

[0063] Data input from the outside may be written into the user block 211. The user block 211 may represent a plurality of user blocks in the memory cell array 210a, and the reserved block 212 may represent a plurality of reserved blocks in the memory cell array 210a. When the user block 211 satisfies the bad block condition, the reserved block 212 may be used to replace the user block 211. In other words, when the user block 211 is detected as a bad block, the reserved block 212 may be allocated as a memory block that may be used as the user block 211 to replace the detected bad block. Figure 4 2 shows an example in which the memory cell array 210 a includes one user block 211 and one reserved block 212 , but the memory cell array 210 a may include a plurality of user blocks and a plurality of reserved blocks.

[0064] The bad block 213 as an unusable memory block may include: an initial bad block determined as a bad block in the manufacturing process, or a runtime bad block determined as a bad block from an operation occurring during use. In the case where the memory block meets the bad block condition, the corresponding memory block may be designated as a bad block. The bad block condition may include a program / erase cycle count or a failure of an erase operation. For example, when the erase count of a memory block exceeds a given count, the corresponding memory block may be detected as a bad block. In addition, when the erase operation of a memory block fails, the corresponding memory block may be detected as a bad block.

[0065] The metablock 214 may store information for managing the nonvolatile memory device 200 (see Figure 1). For example, the management information may include allocation information about user blocks, reserved blocks, and bad blocks. The allocation information may include information about mapping between logical addresses and physical addresses of each of the user blocks, reserved blocks, and bad blocks. In addition, the management information may include information about program / erase cycle counts of each memory block included in the user block 211.

[0066] Figure 5 It is shown Figure 2 A block diagram of another configuration of a memory cell array.

[0067] Reference Figure 5 According to another embodiment of the present disclosure, the memory cell array 210b may include a plurality of memory chips. Each memory chip may include two planes PLN#0 and PLN#1. Each of the planes PLN#0 and PLN#1 may include a data area DAT and a reserved area RSV.

[0068] The data area DAT may be used to store user data. The reserved area RSV may include one or more reserved blocks that may be used to replace bad blocks. In an embodiment of the present disclosure, the data area DAT may include six blocks BLK0, BLK1, BLK2, BLK3, BLK4, and BLK5. The reserved area RSV may include four blocks BLK6, BLK7, BLK8, and BLK9. However, one or more inventive concepts described herein are not limited by the above configuration. For example, the number of blocks included in the data area DAT and the number of blocks included in the reserved area RSV may be changed differently.

[0069] Figure 6 is a circuit diagram of the memory block.

[0070] Figure 6 It is shown in detail Figure 5 FIG. 1 is a diagram showing a structure of a memory block BLK1. Figure 6 , a cell string CS may be formed between bit lines BL1, BL2, BL3, and BL4 (at the top) and a common source line CSL (at the bottom) to constitute a memory block BLK1. Each cell string CS may include a string selection transistor SST and a ground selection transistor GST. A memory cell MC may be included between the string selection transistor SST and the ground selection transistor GST, which are included in each cell string CS.

[0071] The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, BL3, and BL4, respectively. In addition, the string selection transistor SST may be connected to the corresponding string selection lines SSL1, SSL2, SSL3, and SSL4. The ground selection transistor GST may be connected to the common source line CSL. In addition, the ground selection transistor GST may be connected to the corresponding ground selection lines GSL1, GSL2, GSL3, and GSL4, respectively. The ground selection transistor GST may be controlled by the corresponding ground selection lines GSL1, GSL2, GSL3, and GSL4. The memory cell MC may be connected to the word line WL.

[0072] Figure 5 The circuit structure shown in the figure is only a simplified structure for the convenience of description. The actual memory block is not limited to Figure 5 That is, one memory block may include, for example, more semiconductor layers, more bit lines, and more string selection lines. Figure 6 In the example, SUB may represent a substrate.

[0073] Figure 7 is a flowchart illustrating a bad block processing method of a nonvolatile memory device according to an embodiment of the present disclosure.

[0074] In operation S110, the nonvolatile memory device 200 (see Figure 1 ) may receive a command signal CMD from the outside. The command signal CMD may include any one of a write command, a read command, and an erase command. When the command signal CMD is input to the nonvolatile memory device 200, the command latch enable signal CLE may be activated. When the command latch enable signal CLE is activated and address information is input, the address latch enable signal ALE and the write latch enable signal / WE may also be activated.

[0075] In operation S120, the nonvolatile memory device 200 may receive an address signal ADD from the outside. The address signal ADD may indicate an internal location of the nonvolatile memory device 200 where an operation corresponding to a command included in the command signal CMD received in operation S110 will be performed. The address signal ADD may be supplied when the address latch enable signal ALE is activated.

[0076] In operation S130, the nonvolatile memory device 200 may receive a confirmation command signal C_CMD from the outside. The confirmation command signal C_CMD may include a command for checking whether a bad block exists based on the address signal ADD received in operation S120.

[0077] In operation S140, the nonvolatile memory device 200 may determine whether address information of the address signal ADD received from the outside matches the address information stored in the bad block table 257 (refer to Figure 3) When the address information is consistent with the bad block information stored in the bad block table 257, the nonvolatile memory device 200 may determine that a bad block is detected.

[0078] When no bad block is detected in the nonvolatile memory device 200, the step proceeds to operation S150. In operation S150, the nonvolatile memory device 200 may perform an operation corresponding to a command included in the command signal CMD received from the outside for a block corresponding to the address information and detected as not being a bad block.

[0079] In operation S160, the nonvolatile memory device 200 may determine the ready / busy state of the normal block. The ready / busy state of the normal block may be determined based on the ready / busy signal R / B. Fig. 8A and Figure 8B How to generate a ready / busy signal according to an embodiment of the present disclosure is described more fully. Blocks included in the nonvolatile memory device 200 may proceed to subsequent one or more operations in a ready state.

[0080] In operation S170, the nonvolatile memory device 200 may perform a status check for programming. The status check may be performed only on the blocks determined to be in the ready state in operation S160. After the status check is performed on the blocks in the ready state, the operation of the nonvolatile memory device 200 for bad block detection is terminated.

[0081] When a bad block is detected in the nonvolatile memory device 200, the step proceeds to operation S180. In operation S180, the nonvolatile memory device 200 may determine the corresponding block as a status failure (i.e., the block has a failure status) without performing a bad block erase cycle to the maximum extent (e.g., until a maximum value) to which the bad block erase cycle is otherwise performed. The status failure indicates that it is impossible to program the corresponding block. After performing the status failure operation of the bad block, the operation of the nonvolatile memory device 200 for bad block detection is terminated without performing one or more intervals of the intervals (e.g., all intervals) of the bad block erase cycle.

[0082] Fig. 8A is a diagram illustrating aspects of generating a busy portion of a ready / busy signal R / B when a bad block handling method is applied to a two-plane operation according to aspects of the present disclosure.

[0083] Fig. 8A The aspect of generating the busy portion of the ready / busy signal R / B shown in FIG. 1 is for the ready / busy signal R / B in the two-plane mode according to an embodiment of the present disclosure. Fig. 8A The logic low interval of the ready / busy signal R / B shown in is a busy time generation interval in bad block detection.

[0084] Typically, when a bad block occurs, a bad block erase cycle may be performed to the maximum extent of the process (i.e., until a maximum value). In this case, operations of normal blocks may not be performed until the bad block erase cycle is completed. This may unnecessarily result in a loss of test time. However, one or more inventive concepts described herein may provide a memory device that can reduce the test time loss according to the bad block erase cycle when a bad block is detected by making the busy time of the bad block shorter than the busy time of the normal block.

[0085] Reference Fig. 8A , in the case where no bad block occurs (no bad block) (i.e., in the case where only normal blocks exist), the bad block erase cycle may be performed to the maximum extent (i.e., until the maximum value). One or more subsequent operations may not be performed until the bad block erase cycle ends. Therefore, the busy time t1 may be maintained until the bad block erase cycle ends. In the case where exactly one input address is associated with a bad block (MAT1 bad block or MAT2 bad block), the busy time t2 may be equal to the busy time t1 corresponding to the case where no bad block occurs (no bad block).

[0086] In addition, in the case where both input addresses are associated with bad blocks (MAT1 bad blocks and MAT2 bad blocks), the ready / busy signal R / B may have a busy time t3 shorter than the busy time t1 and the busy time t2, the busy time t1 corresponding to the case where no bad blocks occur (no bad blocks), and the busy time t2 corresponding to the case where exactly one input address is associated with a bad block (MAT1 bad block or MAT2 bad block). Therefore, in the case where all input addresses are associated with bad blocks (MAT1 bad blocks and MAT2 bad blocks), the nonvolatile memory device 200 according to an embodiment of the present disclosure may only check whether there are bad blocks, without performing a bad block erase cycle to the maximum extent of processing (i.e., until the maximum value). Therefore, the time loss according to the bad block erase cycle is reduced.

[0087] In some embodiments, the busy time t2 when exactly one input address is associated with a bad block (MAT1 bad block or MAT2 bad block) may be less than the busy time t1 corresponding to the case where no bad block occurs (no bad block), and greater than the busy time t3 when both input addresses are associated with bad blocks.

[0088] Figure 8B is a diagram illustrating an aspect of generating a busy portion of a ready / busy signal R / B when a bad block handling method is applied to a multi-plane mode according to an aspect of the present disclosure.

[0089] Figure 8B The aspect of generating the busy portion of the ready / busy signal R / B shown in FIG. 1 is directed to the ready / busy signal R / B in the multi-plane mode according to an embodiment of the present disclosure. Fig. 8A same, Figure 8B The logic low interval of the ready / busy signal R / B shown in is a busy time generation interval in bad block detection.

[0090] Reference Figure 8B , in the case where no bad block occurs (no bad block) (i.e., in the case where only normal blocks exist), the bad block erase cycle may be performed to the maximum extent (i.e., until the maximum value). One or more subsequent operations may not be performed until the bad block erase cycle ends. Therefore, the busy time t1 may be maintained until the bad block erase cycle ends. In addition, in the case where at least one block indicated by the input address of the multi-plane does not correspond to a bad block (for example, at least one of the MATs is not a bad block), the busy time t2 may be equal to the busy time t1 corresponding to the case where no bad block occurs (no bad block).

[0091] In addition, in the case where all blocks indicated by the input address of the multi-plane are determined to be bad blocks (for example, all MATs are bad blocks), the ready / busy signal R / B may have a busy time t3 shorter than the busy time t1 and the busy time t2, the busy time t1 corresponding to the case where no bad block occurs (no bad block), and the busy time t2 corresponding to the case where at least one of the blocks of the multi-plane is determined not to correspond to a bad block (for example, at least one of the MATs is not a bad block). Therefore, in the case where all blocks indicated by the input address included in the multi-plane are determined to be bad blocks (for example, all MATs are bad blocks), the nonvolatile memory device 200 according to an embodiment of the present disclosure can reduce the time loss according to the bad block erase cycle by only checking whether there is a bad block without performing the bad block erase cycle to the maximum extent (that is, until the maximum value).

[0092] Fig. 9 It is shown Figure 1 Flow chart of the operating method of the testing machine.

[0093] In operation S210, the testing machine 100 (refer to Figure 1 ) can input the command signal CMD to the nonvolatile memory device 200 (refer to Figure 1 The command signal CMD may include a command (such as a write command, a read command, or an erase command). When the nonvolatile memory device 200 receives the command signal CMD, the tester 100 may activate the command latch enable signal CLE, the address latch enable signal ALE, and / or the write latch enable signal / WE.

[0094] In operation S220, the tester 100 may input the address signal ADD to the nonvolatile memory device 200. When the address latch enable signal ALE of the nonvolatile memory device 200 is activated, the tester 100 may supply the address signal ADD to be input to the nonvolatile memory device 200. The address signal ADD may indicate an internal location of the nonvolatile memory device 200 where an operation is to be performed, and the operation may correspond to a command in the command signal CMD received in operation S110.

[0095] In operation S230, the tester 100 may input a confirmation command signal C_CMD to the nonvolatile memory device 200. The confirmation command signal C_CMD may include a command for checking whether a bad block exists based on the address signal ADD.

[0096] In operation S240, the tester 100 may receive a ready / busy signal R / B generated by the nonvolatile memory device 200. The tester 100 may obtain bad block information of the nonvolatile memory device 200 based on the ready / busy signal R / B. The bad block information may include information about whether the bad block exists in the nonvolatile memory device 200 and the location of the bad block. In one example, when a ready / busy signal having a first busy interval is received, the tester 100 may determine at least one of a plurality of memory blocks included in a plane operating in a multi-plane mode as a normal block. When a ready / busy signal having a second busy interval shorter than the first busy interval is received, the tester 100 may determine all of the plurality of memory blocks included in the plane operating in the multi-plane mode as bad blocks.

[0097] In operation S250, the tester 100 may control the nonvolatile memory device 200 based on the bad block information obtained from the ready / busy signal R / B. After the tester 100 determines whether a bad block exists in a block included in the nonvolatile memory device 200, the operation of the tester 100 for bad block detection is terminated.

[0098] Fig. 10A is a diagram illustrating an operation in a case where a bad block does not occur in a two-plane mode according to an embodiment of the present disclosure.

[0099] exist Fig. 10A In the embodiment, the memory cell array 210c may include valid blocks BLK0, BLK1, BLK2, BLK3, BLK4, and BLK5 capable of storing user data. Fig. 10A In the embodiment shown in FIG. 1 , the reserved block 212 (see Figure 4 ) may not be used to replace bad blocks. Instead, each reserved block 212 may be maintained as a free block (eg, BLK6, BLK7, BLK8, and BLK9) in an idle state.

[0100] Fig. 10B is a timing diagram in the case where no bad block occurs in the two-plane mode according to an embodiment of the present disclosure.

[0101] When the command signal CMD is input from the outside to the nonvolatile memory device 200 (refer to Figure 1 ), the command latch enable signal CLE may be activated. When the command latch enable signal CLE is activated and address information is input, the address latch enable signal ALE and the write latch enable signal / WE may also be activated. When the address latch enable signal ALE is activated, two-plane mode bad block address information 2PLN ADD may be supplied.

[0102] Bad block table 257 (refer to Figure 3 ) can generate a bad block flag signal BBLK based on the two-plane mode bad block address information 2PLN ADD thus supplied. The activated command latch enable signal CLE, address latch enable signal ALE and write latch enable signal / WE can also be input to the memory chip control circuit 255 (refer to Figure 3 ). The input signal input to the memory chip control circuit 255 can be output to the ready / busy control circuit 259 (refer to Figure 3 ). The ready / busy control circuit 259 may output a ready / busy signal R / B based on the input signal.

[0103] In such Fig. 10B In the case where no bad block occurs as shown in FIG, a bad block flag signal BBLK of a logic low value may be generated. Therefore, in the case where no bad block occurs (no bad block) (refer to Fig. 8A ), the busy time t1 can be carried out to the maximum extent (ie, until the maximum value of the bad block erase cycle). That is, the busy time t1 can be maintained until the bad block erase cycle ends.

[0104] Fig.11A is a diagram illustrating an operation in the case where a bad block occurs in at least one plane in a two-plane mode according to an embodiment of the present disclosure.

[0105] exist Fig.11A In the memory cell array 210d, the memory cell array 210d may include valid blocks BLK0, BLK1, BLK3, BLK4, and BLK5 capable of storing user data and one bad block BLK2. In the memory cell array 210d, the bad block BLK2 may be replaced by a block belonging to the reserved block 212 (refer to Figure 4). In addition, for the purpose of improving the reliability of the memory device, in addition to the bad block BLK2 being replaced with a block (for example, BLK6) among the blocks belonging to the reserved block 212, even if the block BLK3 adjacent to the bad block BLK2 is a valid block, the block BLK3 may also be replaced with a block (for example, BLK7) among the blocks belonging to the reserved block 212.

[0106] Fig. 11B is a timing diagram in the case where a bad block occurs in at least one plane in a two-plane mode according to an embodiment of the present disclosure.

[0107] Even in the case where a bad block occurs in at least one plane, the nonvolatile memory device 200 (see Figure 1 ) can also be Fig. 10B The command signal CMD is supplied from the outside as in the above. The command latch enable signal CLE, the address latch enable signal ALE, and the write latch enable signal / WE may be activated based on the command signal CMD. In addition, when the address latch enable signal ALE is activated, the two-plane mode bad block address information 2PLN ADD may be supplied.

[0108] Bad block table 257 (refer to Figure 3 ) can generate a bad block flag signal BBLK based on the two-plane mode bad block address information 2PLN ADD thus supplied. Fig. 11B In the case of a bad block, since a bad block occurs in at least one plane, a bad block flag signal BBLK of a logic high value may be generated. Therefore, as in the case where exactly one input address is associated with a bad block (MAT1 bad block or MAT2 bad block) (refer to Fig. 8A ), the busy time t2 can be carried out to the maximum extent (ie, until the maximum value of the bad block erase cycle). That is, the busy time t2 can be maintained until the bad block erase cycle ends.

[0109] Fig. 12A is a diagram illustrating an operation in the case where bad blocks occur in all planes in a two-plane mode according to an embodiment of the present disclosure.

[0110] exist Fig. 12A In the memory cell array 210e, the memory cell array 210e may include valid blocks BLK0, BLK1, BLK4, and BLK5 capable of storing user data and bad blocks BLK2 and BLK3. In the memory cell array 210e, the bad blocks BLK2 and BLK3 may be replaced by blocks belonging to the reserved block 212 (refer to Figure 4 ) blocks BLK6 and BLK7.

[0111] Fig. 12Bis a timing diagram in the case where bad blocks occur in two planes in the two-plane mode according to an embodiment of the present disclosure.

[0112] Even in the case where bad blocks occur in all planes operating in the two-plane mode, the nonvolatile memory device 200 (see Figure 1 ) can also be Fig. 10B The command signal CMD is supplied from the outside as in the above. The command latch enable signal CLE, the address latch enable signal ALE, and the write latch enable signal / WE may be activated based on the command signal CMD. In addition, when the address latch enable signal ALE is activated, the two-plane mode bad block address information 2PLN ADD may be supplied.

[0113] Bad block table 257 (refer to Figure 3 ) can generate a bad block flag signal BBLK based on the two-plane mode bad block address information 2PLN ADD thus supplied. Fig. 12B In the case of , because bad blocks occur in two planes operating in the two-plane mode, a bad block flag signal BBLK of a logic high value may be generated. In this case, the busy time t3 may indicate that all input addresses are associated with bad blocks (MAT1 bad blocks and MAT2 bad blocks) (refer to Fig. 8A ).

[0114] That is, in the case where all input addresses are associated with bad blocks (MAT1 bad blocks and MAT2 bad blocks), the ready / busy signal R / B may have a busy time t3 shorter than the busy time t1 and the busy time t2, the busy time t1 corresponding to the case where no bad blocks occur (no bad blocks), and the busy time t2 corresponding to the case where exactly one input address is associated with a bad block (MAT1 bad block or MAT2 bad block). In addition, in this case, the nonvolatile memory device 200 according to an embodiment of the present disclosure can reduce the time loss according to the bad block erase cycle by only checking whether there is a bad block without performing the bad block erase cycle to the maximum extent (i.e., until the maximum value).

[0115] Fig.13A is a diagram illustrating an operation in a case where a bad block does not occur in a four-plane mode according to another embodiment of the present disclosure.

[0116] exist Fig.13A In the embodiment, the memory cell array 210f may include valid blocks BLK0, BLK1, BLK2, ... BLK11 capable of storing user data. Fig.13A In the embodiment shown in FIG. 1 , the reserved block 212 (see Figure 4 ) may not be used to replace bad blocks. That is, the reserved blocks 212 may be maintained as free blocks (eg, BLK12, BLK13, ..., BLK19) in an idle state.

[0117] Fig. 13B is a timing diagram in a case where no bad blocks occur in a four-plane mode according to another embodiment of the present disclosure.

[0118] Even in the case of operating in the four-plane mode, the nonvolatile memory device 200 (see Figure 1 ) can also be Fig. 10B The command signal CMD is supplied from the outside as in the above. The command latch enable signal CLE, the address latch enable signal ALE, and the write latch enable signal / WE may be activated based on the command signal CMD. In addition, when the address latch enable signal ALE is activated, the four-plane mode bad block address information 4PLN ADD may be supplied.

[0119] Bad block table 257 (refer to Figure 3 ) can generate a bad block flag signal BBLK based on the four-plane mode bad block address information 4PLN ADD thus supplied. The activated command latch enable signal CLE, address latch enable signal ALE and write latch enable signal / WE can also be input to the memory chip control circuit 255 (refer to Figure 3 ). The input signal input to the memory chip control circuit 255 can be output to the ready / busy control circuit 259 (refer to Figure 3 ). The ready / busy control circuit 259 may output a ready / busy signal R / B based on the input signal.

[0120] In such Fig. 13B In the case where no bad block occurs as shown in , a bad block flag signal BBLK of a logic low value can be generated, so that, as in the case where no bad block occurs (no bad block), the busy time t1 can be carried out to the maximum extent (i.e., until the maximum value of the bad block erase cycle). That is, the busy time t1 can be maintained until the bad block erase cycle ends.

[0121] Fig.14A is a diagram illustrating an operation in a case where a bad block occurs in at least one plane in a four-plane mode according to another embodiment of the present disclosure.

[0122] In detail, Fig.14A 1 is a diagram showing an operation when a bad block is detected from one plane (for example, PLN#0) among four planes PLN#0 to PLN#3 operating in a four-plane mode. Fig.14AIn the memory cell array 210g, the memory cell array 210g may include valid blocks BLK0, BLK1, BLK2, BLK3, BLK5, BLK6, BLK7, BLK8, BLK9, BLK10, and BLK11 capable of storing user data and one bad block BLK4. In the memory cell array 210g, the bad block BLK4 may be replaced by a block belonging to the reserved block 212 (refer to Figure 4 ) of the blocks that are reserved. In addition, for the purpose of improving the reliability of the memory device, in addition to the bad block BLK4 being replaced with a block (for example, BLK12) of the blocks that belong to the reserved block 212, even if the blocks BLK5, BLK6, and BLK7 adjacent to the bad block BLK4 are valid blocks, the blocks BLK5, BLK6, and BLK7 may be replaced with the blocks BLK13, BLK14, and BLK15 that are each the reserved block 212.

[0123] Fig. 14B is a timing diagram in the case where a bad block occurs in at least one plane in a four-plane mode according to another embodiment of the present disclosure.

[0124] Even in the case where a bad block occurs in one of the four planes operating in the four-plane mode, the nonvolatile memory device 200 (refer to Figure 1 ) can also be Fig. 10B The command signal CMD is supplied from the outside as in the above. The command latch enable signal CLE, the address latch enable signal ALE, and the write latch enable signal / WE may be activated based on the command signal CMD. In addition, when the address latch enable signal ALE is activated, the four-plane mode bad block address information 4PLNADD may be supplied.

[0125] Bad block table 257 (refer to Figure 3 ) can generate a bad block flag signal BBLK based on the four-plane mode bad block address information 4PLN ADD thus supplied. Fig. 14B In the case of a bad block, since a bad block occurs in one plane, a bad block flag signal BBLK of a logic high value may be generated. Therefore, in the case where at least one of the plurality of blocks does not correspond to a bad block (for example, at least one of the MATs is not a bad block) (refer to Figure 8B ), the busy time t2 can be carried out to the maximum extent (ie, until the maximum value of the bad block erase cycle). That is, the busy time t2 can be maintained until the bad block erase cycle ends.

[0126] Fig.15A is a diagram illustrating an operation in the case where bad blocks occur in some planes in a four-plane mode according to another embodiment of the inventive concept.

[0127] In detail, Fig.15A2 is a diagram showing an operation when a bad block is detected from two planes (for example, PLN#0 and PLN#1) among four planes PLN#0 to PLN#3 operating in a four-plane mode. Fig.15A In the memory cell array 210h, the memory cell array 210h may include valid blocks BLK0, BLK1, BLK2, BLK3, BLK6, BLK7, BLK8, BLK9, BLK10, and BLK11 and bad blocks BLK4 and BLK5 that can store user data. In the memory cell array 210h, the bad blocks BLK4 and BLK5 may be replaced with each of them as a reserved block 212 (refer to Figure 4 ). In addition, for the purpose of improving the reliability of the memory device, in addition to the bad blocks BLK4 and BLK5 being replaced with the blocks BLK12 and BLK13 that are the reserved blocks 212, respectively, even if the blocks BLK6 and BLK7 that are adjacent to the bad blocks BLK4 and BLK5 are valid blocks, the blocks BLK6 and BLK7 may be replaced with the blocks BLK14 and BLK15 that belong to the reserved blocks 212.

[0128] Fig. 15B is a timing diagram in the case where bad blocks occur in some planes in a four-plane mode according to another embodiment of the present disclosure.

[0129] Even in the case where bad blocks occur in two planes among the four planes operating in the four-plane mode, the nonvolatile memory device 200 (refer to Figure 1 ) can also be Fig. 10B The command signal CMD is supplied from the outside as in the above. The command latch enable signal CLE, the address latch enable signal ALE, and the write latch enable signal / WE may be activated based on the command signal CMD. In addition, when the address latch enable signal ALE is activated, the four-plane mode bad block address information 4PLN ADD may be supplied.

[0130] Bad block table 257 (refer to Figure 3 ) can generate a bad block flag signal BBLK based on the four-plane mode bad block address information 4PLN ADD thus supplied. Fig. 15B In the case of, because bad blocks occur in two planes, a bad block flag signal BBLK of a logic high value may be generated. Therefore, in the case where at least one block does not correspond to a bad block (for example, at least one of MAT is not a bad block), the busy time t2 may be performed to the maximum extent (that is, until the maximum value of the bad block erase cycle). That is, the busy time t2 may be maintained until the bad block erase cycle ends.

[0131] Fig.16Ais a diagram illustrating an operation in the case where bad blocks occur in all planes in a four-plane mode according to another embodiment of the present disclosure.

[0132] exist Fig.16A In the memory cell array 210i, the memory cell array 210i may include valid blocks BLK0, BLK1, BLK2, BLK3, BLK8, BLK9, BLK10, and BLK11 capable of storing user data and bad blocks BLK4, BLK5, BLK6, and BLK7. In the memory cell array 210i, the bad blocks BLK4, BLK5, BLK6, and BLK7 may be replaced with each of them being a reserved block 212 (refer to Figure 4 ) blocks BLK12, BLK13, BLK14 and BLK15.

[0133] Fig. 16B is a timing diagram in the case where bad blocks occur in all planes in a four-plane mode according to another embodiment of the present disclosure.

[0134] Even in the case where bad blocks occur in all planes, the nonvolatile memory device 200 (see Figure 1 ) can also be Fig. 10B The command signal CMD is supplied from the outside as in the above. The command latch enable signal CLE, the address latch enable signal ALE, and the write latch enable signal / WE may be activated based on the command signal CMD. In addition, when the address latch enable signal ALE is activated, the four-plane mode bad block address information 4PLN ADD may be supplied.

[0135] Bad block table 257 (refer to Figure 3 ) can generate a bad block flag signal BBLK based on the four-plane mode bad block address information 4PLN ADD thus supplied. Fig. 16B In the case of , because bad blocks occur in all planes, a bad block flag signal BBLK of a logic high value may be generated. In this case, the busy time t3 may indicate that all blocks are determined to be bad blocks (eg, all MATs are bad blocks) (refer to Figure 8B ).

[0136] That is, in the case where all blocks are determined to be bad blocks (e.g., all MATs are bad blocks), the ready / busy signal R / B may have a busy time t3 shorter than a busy time t1 and a busy time t2, the busy time t1 corresponding to a case where no bad blocks occur (no bad blocks), and the busy time t2 corresponding to a case where at least one of the blocks of the multi-plane is determined to be not a bad block (e.g., at least one of the MATs is not a bad block). In addition, in this case, the nonvolatile memory device 200 according to an embodiment of the present disclosure can reduce the time loss according to the bad block erase cycle by only checking whether there is a bad block without performing the bad block erase cycle to the maximum extent (i.e., until the maximum value).

[0137] According to one or more inventive concepts described herein, a nonvolatile memory device can reduce a time required for bad block detection by reducing a busy time generation interval when all blocks included in a plane operating in a multi-plane mode are detected as bad blocks.

[0138] Although the one or more inventive concepts described herein have been described with reference to exemplary embodiments of the one or more inventive concepts described herein, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims.

Claims

1. A bad block detection method for a non-volatile memory device operating in a multi-plane mode, the method comprising: receiving a command signal from an external source in the nonvolatile memory device; receiving an address signal from an external source in a nonvolatile memory device; receiving a confirmation command signal from an external source in the nonvolatile memory device; detecting a bad block in a nonvolatile memory device based on address information included in the address signal; as well as generating a ready / busy signal in the nonvolatile memory device based on whether an erase cycle for detection of a bad block is being performed, wherein the nonvolatile memory device generates a ready / busy signal having a first busy interval when at least one normal block is detected from a plurality of blocks included in a plane operating in a multi-plane mode, and Wherein, when all blocks included in a plane operating in a multi-plane mode are detected as bad blocks, the nonvolatile memory device generates a ready / busy signal having a second busy interval shorter than the first busy interval.

2. The method according to claim 1, wherein: The nonvolatile memory device receives a command latch enable signal, an address latch enable signal, and a write enable signal activated based on a command signal.

3. The method according to claim 1 or 2, wherein: In the step of detecting the bad block, the nonvolatile memory device determines that the bad block is detected when the address information corresponds to the bad block information stored in the bad block table, and determines that the bad block is not detected when the address information does not correspond to the bad block information stored in the bad block table.

4. The method according to claim 1 or 2, wherein: In the step of detecting the bad block, when it is determined that the normal block is detected, the nonvolatile memory device performs a status check for programming of the nonvolatile memory device, and Wherein, in the step of detecting the bad block, when it is determined that the bad block is detected, the nonvolatile memory device determines the bad block as a status failure.

5. A bad block detection method for a non-volatile memory device, the non-volatile memory device comprising a plurality of memory blocks operating in a multi-plane mode, the method comprising: inputting a command signal into a nonvolatile memory device at a test machine; inputting an address signal for selecting a memory block among the plurality of memory blocks into the nonvolatile memory device at the test machine; inputting a confirmation command signal into the nonvolatile memory device at the test machine; The tester receives a ready / busy signal based on whether an erase cycle for bad block detection is performed, wherein, when receiving a ready / busy signal having a first busy interval, the tester determines at least one of the plurality of memory blocks included in the plane operating in the multi-plane mode as a normal block, and When receiving a ready / busy signal having a second busy interval shorter than the first busy interval, the tester determines all of the plurality of memory blocks included in the plane operating in the multi-plane mode as bad blocks.

6. A testing system comprising: A non-volatile memory device comprising a plurality of memory blocks operating in a multi-plane mode; as well as a tester configured to detect bad blocks of the nonvolatile memory device, wherein the nonvolatile memory device generates a ready / busy signal based on whether an erase cycle for detection of a bad block is being performed, wherein the nonvolatile memory device generates a ready / busy signal having a first busy interval when at least one normal block is detected from the plurality of memory blocks included in the plane operating in the multi-plane mode, and Wherein, when all of the plurality of memory blocks included in the plane operating in the multi-plane mode are detected as bad blocks, the nonvolatile memory device generates a ready / busy signal having a second busy interval shorter than the first busy interval.

7. The test system according to claim 6, wherein: The non-volatile memory device comprises: an input / output buffer configured to exchange input and / or output signals with the outside; a page buffer configured to exchange data signals with the input / output buffer; a decoder configured to receive an address signal from the input / output buffer; a control logic circuit configured to receive a command signal from the input / output buffer; and The memory cell array is connected to the page buffer through bit lines and to the decoder through selection lines and word lines.

8. The test system according to claim 7, wherein: The control logic circuit includes an input / output control circuit, a status register, an address register, a command register, a memory chip control circuit, a high voltage generator, a bad block table, a flag generator, and a ready / busy control circuit.

9. The test system according to claim 8, wherein: The memory chip control circuit receives a command latch enable signal, an address latch enable signal, and a write enable signal activated by a command signal.

10. The test system according to claim 8, wherein: The bad block table outputs a bad block flag signal to the flag generator.

11. The test system according to claim 8, wherein: The ready / busy control circuit includes an NMOS transistor having a source connected to the ground and a drain connected to the ready / busy terminal, and generates a ready / busy signal based on a bad block detection result of the nonvolatile memory device.

12. The test system according to claim 8, wherein: The voltage of the high voltage generator is uniformly maintained in the first busy interval or the second busy interval.

13. The test system according to claim 8, wherein: The voltage of the nonvolatile memory device is uniformly maintained in the first busy interval or the second busy interval.

14. The test system according to any one of claims 6 to 13, wherein: The nonvolatile memory device includes a memory cell array, and The memory cell array includes at least one of a user block, a reserved block and a meta block.

15. The test system according to any one of claims 6 to 13, wherein: Non-volatile memory devices include NAND flash memories.

16. The test system according to any one of claims 6 to 13, wherein: When the ready / busy signal having the first busy interval is generated, the nonvolatile memory device performs a status check for programming of a normal block, and Wherein, when the ready / busy signal having the second busy interval is generated, the nonvolatile memory device determines the bad block as a status failure.

17. The test system according to any one of claims 6 to 13, wherein: The multi-plane mode includes a two-plane mode or a four-plane mode.

18. The test system according to any one of claims 6 to 13, wherein: Each of the plurality of memory blocks includes a plurality of bit lines and a common source line, Wherein, a plurality of cell strings are formed between the plurality of bit lines and a common source line, Each of the plurality of cell strings includes a string selection transistor and a ground selection transistor, and The memory cell is formed between the string selection transistor and the ground selection transistor.

19. The test system according to claim 18, wherein: The string selection transistor is connected to a corresponding bit line and is connected to a corresponding string selection line.

20. The test system of claim 18, wherein: The ground selection transistor is connected to a common source line, connected to a corresponding ground selection line, and controlled by the corresponding ground selection line.

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