Dynamic adjustment of data integrity operations in memory systems based on error rate classification

Abstract

The present application relates to dynamic adjustment of data integrity operations of a memory system based on error rate classification. A memory subsystem is configured to dynamically select an option for processing encoded data retrieved from a memory cell of a memory component based on a prediction generated using signal and noise characteristics of a memory cell storing the encoded data. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing a read command in the memory component to retrieve the encoded data. A data integrity classifier configured in the memory subsystem generates a prediction based on the signal and noise characteristics. Based on the prediction, the memory subsystem selects an option for processing the encoded data from a plurality of options configured in the memory subsystem.

Description

Technical Field

[0001] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, memory systems with dynamic adjustment of data integrity operations based on error rate classification. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] An aspect of the present disclosure provides a memory subsystem, wherein the memory subsystem includes: a processing device; and at least one memory component, the memory component being enclosed in an integrated circuit package, the memory component having: a group of memory cells formed on an integrated circuit die; and a calibration circuit; wherein the processing device is configured to transmit a command to retrieve data from an address to the memory component; wherein in response to the command and during execution of the command, the calibration circuit is configured to measure signal and noise characteristics of the group of memory cells associated with encoded data retrieved from the group of memory cells; wherein the memory subsystem has a data integrity classifier and a plurality of options that can be used to process the encoded data; wherein the data integrity classifier is configured to generate a prediction based on the signal and noise characteristics; and wherein the memory subsystem is configured to select an option from the plurality of options based on the prediction, and decode the encoded data using the selected option.

[0004] Another aspect of the present disclosure provides a method, wherein the method includes: transmitting, by a processing device in a memory subsystem, a command to retrieve encoded data from an address to a memory component of the memory subsystem; in response to the command and during execution of the command in the memory component, measuring signal and noise characteristics of a group of memory cells formed on an integrated circuit die using a calibration circuit of the memory component enclosed in an integrated circuit package; generating, by a data integrity classifier configured in the memory subsystem, a prediction based on the signal and noise characteristics; selecting, by the memory subsystem, an option from the plurality of options based on the prediction; and decoding the encoded data using the selected option.

[0005] Another aspect of the present disclosure provides a non-transitory computer storage medium storing instructions that, when executed by a computing system, cause the computing system to perform a method comprising: transmitting, by a processing device in a memory subsystem, a command to retrieve encoded data from an address to a memory component of the memory subsystem, wherein in response to and during execution of the command, a calibration circuit of the memory component measures signal and noise characteristics of a group of memory cells formed on an integrated circuit die; receiving the signal and noise characteristics from the memory component as a response to the command; generating, by a data integrity classifier configured in the memory subsystem, a prediction based on the signal and noise characteristics; and selecting, by the memory subsystem, an option for processing the encoded data retrieved from the group of memory cells from the plurality of options based on the prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0007] Figure 1 An example computing system having a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 An integrated circuit memory device having a calibration circuit configured to measure signal and noise characteristics is shown according to one embodiment.

[0009] Figure 3 An example of measuring signal and noise characteristics to improve memory operation according to one embodiment is presented.

[0010] Figure 4 A data integrity classifier is shown that determines the probability of data integrity failures in data retrieved from a memory device to dynamically configure the operation of error detection and data recovery, according to one embodiment.

[0011] Figure 5 A method is presented for a memory subsystem to control data integrity operations based on classification of signal and noise characteristics associated with data retrieved from memory cells.

[0012] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0013] At least some aspects of the present disclosure are directed to a memory subsystem having a data integrity classifier configured to determine an error rate classification of data retrieved from a memory cell, thereby allowing the memory subsystem to dynamically adjust error detection and recovery operations based on the error rate classification. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0014] Integrated circuit memory cells (e.g., flash memory cells) can be programmed at a threshold voltage to store data by virtue of their state. For example, if the memory cell is configured / programmed in a state that allows a large amount of current to pass through the memory cell at the threshold voltage, the memory cell is storing a bit one; and otherwise, the memory cell is storing a bit zero. In addition, the memory cell can store multiple bits of data by being configured / programmed in different ways at multiple threshold voltages. For example, the memory cell can store multiple bits of data by having a combination of states at multiple threshold voltages; and different combinations of states of the memory cell at the threshold voltages can be interpreted to represent different states of the data bits stored in the memory cell.

[0015] However, after configuring / programming the state of an integrated circuit memory cell using a write operation to store data in the memory cell, the optimized threshold voltage for reading the memory cell may shift due to several factors such as charge loss, read disturb, cross-temperature effects (e.g., writing and reading at different operating temperatures), especially when the memory cell is programmed to store multiple bits of data.

[0016] Data may be encoded with redundant information to facilitate error detection and recovery. When data encoded with redundant information is stored in the memory subsystem, the memory subsystem may detect errors in the original encoded data retrieved from the memory subsystem, and / or recover the original unencoded data used to generate the encoded data for storage in the memory subsystem. The recovery operation may be successful (or have a high probability of success) when the original encoded data retrieved from the memory subsystem contains errors less than a threshold amount or the bit error rate in the encoded data is below a threshold. For example, error detection and data recovery may be performed using techniques such as error correction codes (ECC), low-density parity check (LDPC) codes, and the like.

[0017] Some error detection and data recovery operations may successfully identify error-free results in encoded data with a relatively large number of errors, at the expense of relatively large power consumption and / or relatively long computation time. Other error detection and data recovery operations may recover relatively small numbers of errors with less power consumption and / or short computation time.

[0018] Conventional calibration circuitry has been used to calibrate memory regions by themselves by applying read level signals to account for shifts in threshold voltages of memory cells within the memory region. During calibration, the calibration circuitry is configured to apply different test signals to the memory region to count the number of memory cells that output a specified data state for the test signal. Based on the count, the calibration circuitry determines a read level offset value as a response to a calibration command.

[0019] At least some aspects of the present disclosure address the above-referenced deficiencies and others by dynamically configuring error detection and data recovery operations based on a data integrity classification or a bit error rate classification generated from signal and noise characteristics measured by a memory device for memory cells in the memory device.

[0020] For example, a prediction model may be generated via machine learning to classify or predict error rates in raw data received from a set of memory cells. Classification may be generated by the prediction model based on signal and noise characteristics measured by the memory device during reading of raw data from memory cells in the memory device. When the error rate is classified as being in a low category, the memory subsystem uses a low-power ECC decoder and / or skips ECC decoding. When the error rate is classified as being in a high category, the memory subsystem uses a high-power ECC decoder. For example, the high-power ECC decoder may use not only hard bit data but also soft bit data to recover error-free raw data stored in the memory cell. For example, hard bit data is encoded data read from the memory cell at an optimized or controller-specified read voltage; and soft bit data is encoded data read at a voltage having a predetermined offset relative to the optimized or controller-specified read voltage.

[0021] For example, the counts and / or their associated data measured by the calibration circuitry may be used as signal and noise characteristics for the prediction model. In addition, such signal and noise characteristics may be measured in parallel for sub-regions to shorten the total time for measuring signal and noise characteristics.

[0022] Figure 1An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device.

[0025] Computing system 100 may include a host system 120 coupled to one or more memory subsystems 110 . Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0026] The host system 120 may include a processor chipset (e.g., processing device 118) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., controller 116) (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] The processing device 118 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some cases, the controller 116 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 116 controls communications on a bus coupled between the host system 120 and the memory subsystem 110. Typically, the controller 116 may send commands or requests to the memory subsystem 110 that desire to access the memory devices 130, 140. The controller 116 may further include an interface circuit system for communicating with the memory subsystem 110. The interface circuit system may convert responses received from the memory subsystem 110 into information for the host system 120.

[0029] The controller 116 of the host system 120 may communicate with the controller 115 of the memory subsystem 110 to perform operations, such as reading data, writing data, or erasing data at the memory devices 130, 140, and other such operations. In some cases, the controller 116 is integrated into the same package of the processing device 118. In other cases, the controller 116 is separate from the package of the processing device 118. The controller 116 and / or the processing device 118 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 116 and / or the processing device 118 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0030] The memory devices 130, 140 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory components include NAND (or NOT AND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion of a memory cell, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although non-volatile memory devices such as 3D cross-point type and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or, for simplicity, the controller 115) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130 (e.g., in response to commands dispatched by the controller 116 on the command bus). The controller 115 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0035] The controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] In general, the controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, the memory device 130 includes a local media controller 150 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 150) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The controller 115 may include a data integrity classifier 113 that may classify, predict, estimate, or determine the extent of an error rate in raw data retrieved from a memory cell using signal and noise characteristics measured for the memory cell by the memory component 130. In some embodiments, the controller 115 in the memory subsystem 110 includes at least a portion of the data integrity classifier 113. In other embodiments, or in combination, the controller 116 and / or the processing device 118 in the host system 120 include at least a portion of the data integrity classifier 113. For example, the controller 115, the controller 116, and / or the processing device 118 may include logic circuitry that implements the data integrity classifier 113. For example, the controller 115 or the processing device 118 (processor) of the host system 120 may be configured to execute instructions stored in a memory for performing the operations of the data integrity classifier 113 described herein. In some embodiments, the data integrity classifier 113 is implemented in an integrated circuit chip disposed in the memory subsystem 110. In other embodiments, data integrity classifier 113 may be part of firmware of memory subsystem 110, an operating system, a device driver, or an application of host system 120, or any combination thereof.

[0041] The data integrity classifier 113 may receive signal and noise characteristics measured and provided by the memory device 130 for memory cells in the memory device 130, and process the signal and noise characteristics to generate a classification indicative of error levels in raw data retrieved from memory cells in the memory device 130. Based on the classification, the controller 115 may dynamically adjust error detection and recovery operations to improve performance of the memory subsystem 110 (e.g., reduce power consumption, and / or shorten latency in read operations).

[0042] Figure 2 An integrated circuit memory device 130 is shown having a calibration circuit 145 configured to measure signal and noise characteristics according to one embodiment. For example, Figure 1The memory device 130 in the memory subsystem 110 can use Figure 2 The integrated circuit memory device 130 is implemented.

[0043] The integrated circuit memory device 130 may be enclosed in a single integrated circuit package. The integrated circuit memory device 130 includes a plurality of groups 131, ..., 133 of memory cells that may be formed in one or more integrated circuit dies. A typical memory cell in a group 131, ..., 133 may be programmed to store one or more bits of data.

[0044] Some memory cells in the integrated circuit memory device 130 may be configured to operate together for a particular type of operation. For example, memory cells on an integrated circuit die may be organized into planes, blocks, and pages. A plane contains multiple blocks; a block contains multiple pages; and a page may have multiple strings of memory cells. For example, an integrated circuit die may be the smallest unit that can independently execute a command or report status; the same concurrent operation may be performed in parallel on multiple planes in an integrated circuit die; a block may be the smallest unit to perform an erase operation; and a page may be the smallest unit to perform a data programming operation (writing data into a memory cell). The memory cells of each string are connected to a common bit line; and the control gates of the memory cells at the same position in the string in a block or page are connected to a common word line. Control signals may be applied to the word lines and bit lines to address individual memory cells.

[0045] The integrated circuit memory device 130 has a communication interface 147 to receive an address 135 from the controller 115 of the memory subsystem 110, and to provide data 137 retrieved from the memory address 135. The address decoder 141 of the integrated circuit memory device 130 converts the address 135 into a control signal to select a memory cell in the integrated circuit memory device 130; and the read / write circuit 143 of the integrated circuit memory device 130 performs an operation to determine the data stored in the addressed memory cell, or to program the memory cell to have a state corresponding to the stored data 137.

[0046] Integrated circuit memory device 130 has calibration circuitry 145 configured to determine measurements of signal and noise characteristics 139 of memory cells in a group (e.g., 131, ... or 133) and provide the signal and noise characteristics 139 to controller 115 of memory subsystem 110 via communication interface 147.

[0047] In at least some embodiments, calibration circuit 145 also provides measured signal and noise characteristics 139 to controller 115 via communication interface 147 to determine read level shift values. In some embodiments, read level shift values ​​may be used to understand, quantify, or estimate signal and noise characteristics 139. In other embodiments, statistical data of memory cells in a group or region having a particular state at one or more test voltages may be provided as signal and noise characteristics 139.

[0048] For example, calibration circuit 145 may measure signal and noise characteristics 139 by reading different responses from memory cells in a group (e.g., 131, ..., 133) by varying operating parameters for reading the memory cells (e.g., voltages applied during an operation to read data from the memory cells).

[0049] For example, the calibration circuit 145 may measure the signal and noise characteristics 139 on the fly when executing a command to read the data 137 from the address 135. Because the signal and noise characteristics 139 are measured as part of the operation to read the data 137 from the address 135, the signal and noise characteristics 139 may be provided from the integrated circuit memory device 130 to the controller 115 with a reduced or zero penalty for latency during execution of the command to read the data 137 from the address 135.

[0050] The data integrity classifier 113 of the controller 115 of the memory subsystem 110 is configured to generate an error rate classification of the data 137 using the signal and noise characteristics 139 .

[0051] For example, the data integrity classifier 113 may use a prediction model trained via machine learning to predict the probability that data 137 retrieved from a group of memory cells (e.g., 131 or 133) fails a data integrity test. For example, when the data 137 fails to decode, it fails the data integrity test. The prediction may actually be made based on the signal and noise characteristics 139. Before the test is made using an error correction code (ECC) and / or a low density parity check (LDPC) code, or even before the data 137 is passed to a decoder, the data integrity classifier 113 uses the signal and noise characteristics 139 to predict the result of the test. Based on the predicted test results, optimized operations for error detection and / or recovery with reduced power consumption and / or latency may be selected and executed.

[0052] For example, based on the outcome of the prediction, one of several conditional paths for processing of data 137 may be taken.

[0053] For example, in one conditional path, when data 137 is classified in a category that is likely to fail a test (eg, has a high error rate), data 137 may be discarded; and memory device 130 may be instructed to retry reading data 137 from the address with another optimized read voltage.

[0054] For example, in another conditional path, when data 137 is classified in a category that is likely to pass the test (e.g., has a low error rate), data 137 may be passed to a decoder that uses the hard bit data to provide the original data encoded for storage in memory device 130.

[0055] For example, in another conditional path, when data 137 is classified in a category that may require soft bit data to pass a test (e.g., has an intermediate error rate), data 137 may be passed to a decoder that uses both hard bit data and soft bit data to recover the original data that was encoded for storage in memory device 130. If soft bit data is not yet available, memory device 130 may be instructed to read soft bit data for the decoder to supplement data 137.

[0056] Therefore, when the prediction model predicts a failure, the memory subsystem 110 can initiate a read retry or read calibration without waiting for the ECC and / or LDPC operation to be completed; and the memory subsystem 110 can skip the transfer of data to be decoded, skip the decoding operation, and / or abort the ongoing decoding operation. Therefore, the overall performance of the memory subsystem 110 is improved.

[0057] The prediction model may be configured to use the signal and noise characteristics 139 of the memory cell group (e.g., 131 or 133) measured during a read operation performed on the memory cell group (e.g., 131 or 133) by the calibration circuit 145. For example, the prediction model may be pre-trained using data collected from similar memory devices, and optionally further trained in the field via reinforcement learning based on the results of ECC and / or LDPC operations for the memory subsystem. For example, when the predicted results differ from the actual test results generated from the ECC and / or LDPC operations, reinforcement learning techniques may be applied to train the prediction model to generate predictions that match the actual test results.

[0058] Optionally, the prediction model and / or data integrity classifier 113 may be configured on the memory device 130. When an ECC and / or LDPC failure is predicted, the memory device 130 may suggest a read retry to the controller 115 and predictively initiate the read retry without waiting for confirmation from the controller 115. This predictive operation of initiating a read retry may reduce the latency of the read retry and improve the performance of the memory subsystem 110.

[0059] Typically, data integrity classifier 113 may be implemented in controller 115 and / or memory device 130. Predictions generated by data integrity classifier 113 based on signal and noise characteristics may be used to initiate various processing paths, each of which may be configured as an atomic operation. For example, a read retry may be performed immediately before another command occupies the die in which a memory cell group (e.g., 131 or 133) is formed.

[0060] For example, based on the signal and noise characteristics 139, the data integrity classifier 113 may use its prediction model to classify the bit error rate in the retrieved raw data 137 as low, medium, or high. If the classified bit error rate is low, the raw data 137 may be passed to an LDPC decoder that operates on hard bit data. This LDPC decoder has relatively low complexity and correction capabilities. In some implementations, multiple decoders may be provided to decode hard bit data without using soft bit data; the decoders may have different correction capabilities and power consumption; and the classified bit error rate may be further used to select one of the decoders that is likely to successfully decode the hard bit data with minimal power consumption. If the classified bit error rate is medium, the memory device 130 may immediately begin reading the soft bit data; and another LDPC decoder that operates on hard bit data and soft bit data may be used.

[0061] If the classified bit error rate is high, memory device 130 may immediately initiate read retries, and / or automatically read calibration, reading both hard bit data and soft bit data to use an LDPC decoder with relatively high complexity and correction capabilities.

[0062] In some embodiments, data integrity classifier 113 generates not only a classification of the bit error rate of data 137, but also a confidence indicator that the classification is correct. The confidence indicator may also be used in selecting a path from a plurality of conditional processing paths.

[0063] Figure 3 An example of measuring signal and noise characteristics 139 to improve memory operation according to one embodiment is shown.

[0064] exist Figure 3 In the calibration circuit 145, different read voltages V A 、V B 、V C 、V D and V E To read the states of the memory cells in the group (eg, 131, ... or 133). In general, more or fewer read voltages may be used to generate the signal and noise characteristic 139.

[0065] Due to the different voltages applied during the read operation, the same memory cell in a group (eg, 131, . . . or 133) may show different states. Therefore, in general, at different read voltages V A 、V B 、V C 、V D and V E The count C of memory cells with a predetermined state A , C B , C C , C D and C E The predetermined state may be a state where a large amount of current passes through the memory cell, or a state where no large amount of current passes through the memory cell. A , C B , C C , C D and C E It can be called bit count.

[0066] Calibration circuit 145 may apply a read voltage V across a group of memory cells (eg, 131, . . . or 133) one at a time. A 、V B 、V C 、V D and V E to measure the bit count.

[0067] Alternatively, the group of memory cells (eg, 131, . . . or 133) may be configured into a plurality of sub-groups; and the calibration circuit 145 may be configured by applying a read voltage V A 、V B 、V C 、V D and V E The bit counts of the subgroups are measured in parallel. The bit counts of the subgroups are considered to represent the bit counts in the entire group (e.g., 131, ... or 133). Thus, the count C is obtained. A , C B , C C , C D and C E The duration can be shortened.

[0068] In some embodiments, the bit count C is measured during execution of a command to read data 137 from address 135 mapped to one or more memory cells in a group (eg, 131, . . . or 133). A , C B , C C , C D and C ETherefore, the controller 115 does not need to send a separate command to request a bit count based on C A , C B , C C , C D and C E Signal and noise characteristics139.

[0069] The difference between the bit counts of adjacent voltages indicates an error in reading the states of the memory cells in the group (eg, 133, . . . or 133).

[0070] For example, according to C A -C B Calculate the count difference D A , which is due to the voltage read from V A Change to V B The read threshold error is introduced.

[0071] Similarly, D B =C B -C C ;D C =C C -C D ; and D D =C D -C E .

[0072] Based on the count difference D A , D B , D C and D D The obtained curve 157 represents the prediction of the read threshold error E as a function of the read voltage. According to the curve 157 (and / or the count difference), the optimized read voltage V O can be calculated as the minimum read threshold error D on curve 157 MIN The point is 153.

[0073] In one embodiment, the calibration circuit 145 calculates the optimized read voltage V O And cause the read / write circuit 143 to use the optimized read voltage V O Data 137 is read from address 135.

[0074] Alternatively, the calibration circuit 145 may provide the count difference D to the controller 115 of the memory subsystem 110 via the communication interface 147. A , D B , D C and D D and / or the optimized read voltage V calculated by the calibration circuit 145 O .

[0075] Figure 3 The generation of a set of statistical data (eg, bit counts and / or count differences) for use at an optimized read voltage V O In general, a group of memory cells may be configured to store more than one bit in the memory cell; and multiple read voltages are used to read the data stored in the memory cell. A statistical data set may similarly be measured for each of the read voltages to identify a corresponding optimized read voltage, wherein the test voltage in each statistical data set is configured near the expected position of the corresponding optimized read voltage. Thus, the signal and noise characteristics 139 measured for a group of memory cells (e.g., 131 or 133) may include multiple statistical data sets measured for multiple threshold voltages, respectively.

[0076] For example, the controller 115 may instruct the memory device 130 to perform a read operation by providing the address 135 and at least one read control parameter. For example, the read control parameter may be a suggested read voltage.

[0077] Memory device 130 may perform a read operation by determining the state of a memory cell at address 135 at a read voltage, and provide data 137 according to the determined state.

[0078] During a read operation, calibration circuit 145 of memory device 130 generates signal and noise characteristics 139. Data 137 and signal and noise characteristics 139 are provided from memory device 130 to controller 115 in response. Alternatively, processing of signal and noise characteristics 139 may be performed at least in part using logic circuitry configured in memory device 130. For example, data integrity classifier 113 may be partially or fully implemented using processing logic configured in memory device 130. For example, processing logic may be implemented using complementary metal oxide semiconductor (CMOS) circuitry formed below an array of memory cells on an integrated circuit die of memory device 130. For example, processing logic may be formed on a separate integrated circuit die within an integrated circuit package of memory device 130 that is connected to an integrated circuit die having memory cells using through silicon vias (TSVs) and / or other connection techniques.

[0079] The signal and noise characteristics 139 may be determined based at least in part on the read control parameter. For example, when the read control parameter is a suggested read voltage for reading a memory cell at address 135, the calibration circuit 145 may calculate a read voltage V around the suggested read voltage. A 、V B 、V C 、V D and V E .

[0080] The signal and noise characteristics 139 may include the bit count C A , C B , C C , C D and C E Alternatively or in combination, the signal and noise characteristic 139 may include the count difference D A , D B , D C and D D .

[0081] Optionally, the calibration circuit 145 uses a method based on the count difference D A , D B , D C and D D Calculate the optimized read voltage V O ; and the controller 115 uses another different method to calculate the optimized read voltage V based on the signal and noise characteristics 139 and optionally other data not available to the calibration circuit 145 O .

[0082] When the calibration circuit 145 can be based on the count difference D generated during the read operation A , D B , D C and D D Calculate the optimized read voltage V O The signal and noise characteristics may optionally include an optimized read voltage V O Furthermore, memory device 130 may use an optimized read voltage V in the process of determining hard bit data in data 137 from a memory cell at address 135. O . The voltage V O The memory cell is read by the read voltage with a predetermined shift to obtain the soft bit data in the data 137. Alternatively, the memory device 130 uses the controller-specified read voltage provided in the read control parameter during the process of reading the data 137.

[0083] The controller 115 may be configured with more processing power than the calibration circuit 145 of the integrated circuit memory device 130. In addition, the controller 115 may have other signal and noise characteristics suitable for the memory cells in the group (e.g., 133, ... or 133). Therefore, in general, the controller 115 may calculate the optimized read voltage V O A more accurate estimate of the read time (e.g., for subsequent read operations, or for retries of the read operation) may be used.

[0084] In general, calibration circuit 145 need not provide signal and noise characteristics 139 in the form of a distribution of bit counts over a set of read voltages or in the form of a distribution of count differences over a set of read voltages. For example, calibration circuit 145 may provide an optimized read voltage V calculated by calibration circuit 145. O As signal and noise characteristics139.

[0085] The calibration circuit 145 may be configured to generate a signal and noise characteristic 139 (e.g., a bit count or a bit count difference) as a byproduct of a read operation. The generation of the signal and noise characteristic 139 may be implemented in the integrated circuit memory device 130 with little or no effect on the latency of the read operation compared to a typical read that does not generate the signal and noise characteristic 139. Thus, the calibration circuit 145 may effectively determine the signal and noise characteristic 139 as a byproduct of performing a read operation in accordance with a command from the controller 115 of the memory subsystem 110.

[0086] Generally speaking, the optimized reading voltage V O The calculation of may be performed within the memory device 130 or by a controller 115 of the memory subsystem 111 which receives the signal and noise characteristics 139 as part of a rich state response from the memory device 130 .

[0087] Figure 4 FIG. 1 shows a data integrity classifier 113 according to one embodiment, which determines the probability of data integrity failures in data retrieved from a memory device to dynamically configure the operation of error detection and data recovery. For example, the data integrity classifier 113 may use Figure 3 The measured signal and noise characteristics 139 are implemented in Figure 1 The controller 115 of the memory subsystem 110, or Figure 2 In the integrated circuit memory device 130.

[0088] exist Figure 4 , when the memory device 130 receives an address 135 to retrieve data 137 from its memory cells, the memory device 130 measures the signal and noise characteristics 139 associated with the data 137. For example, the calibration circuit 145 of the memory device 130 may be as follows: Figure 3 The approach shown in generates statistical data (eg, bit counts, count differences) and / or results derived from the statistical data (eg, optimized read voltages).

[0089] The data 137 retrieved from the memory cells of the memory device is in an encoded format that allows error detection and recovery 163 (e.g., using techniques such as error correction codes (ECC), low-density parity check (LDPC) codes, etc.). The signal and noise characteristics 139 may be provided as input to the data integrity classifier 113 to assess the probability that the data 137 has too many errors in order to successfully decode the data 137 through some or all processing paths / modules / options in the error detection and recovery 163.

[0090] For example, the memory subsystem 110 may include a low power ECC 171, a full power ECC 173, an LDPC decoder 175 that does not use soft bit data, and an LDPC decoder 177 that uses both hard bit data and soft bit data for decoding. In general, the available paths / modules / options in the memory subsystem 110 for decoding the data 137 are not limited to Figure 4 The examples shown in (e.g., 171, 173, 175, 177); different processing paths / modules / options (e.g., 171, 173, 175, 177) may be implemented; and different processing paths / modules / options (e.g., 171, 173, 175, 177) have different power consumption levels, different capabilities to recover error-free original / unencoded data from the retrieved original data 137, and / or different processing delays.

[0091] Data integrity classifier 113 may be trained (eg, via machine learning) to predict probability 161 of a data integrity failure for data 137 based on associated signal and noise characteristics 139 .

[0092] For example, probability 161 of a data integrity failure for data 137 may be in the form of an estimated bit error rate in data 137 .

[0093] For example, the probability 161 of a data integrity failure of data 137 may be in the form of a prediction of whether data 137 can be successfully decoded (e.g., via ECC or LDPC) by any one of the processing paths / modules / options (e.g., 171, 173, 175, 177), and if so, which processing path(s) / module(s) (e.g., 171, 173, 175, 177) are predicted to be able to successfully decode data 137 having associated signal and noise characteristics 139.

[0094] Based on the predicted probability 161 of data integrity failure of data 137, the memory subsystem 110 may select one of the processing paths / modules / options (e.g., 171, 173, 175, 177) with reduced power consumption, shortened processing latency, and / or a high probability of decoding success.

[0095] In some embodiments, data integrity classifier 113 is trained to directly provide predictions for optimized processing paths / modules (eg, 171 , 173 , 175 , or 177 ) used to process encoded data 137 retrieved from memory cells of memory device 130 .

[0096] In some embodiments, data integrity classifier 113 is trained to provide a prediction of a prioritized list of processing paths / modules / options (e.g., 171, 173, 175, and / or 177) that can successfully decode encoded data 137. In addition, data integrity classifier 113 may further provide an indication of a confidence level that a selected listed processing path / module / option (e.g., 171, 173, 175, and / or 177) successfully decodes data 137.

[0097] Optionally, the data integrity classifier 113 may also be trained to assess a confidence level of the prediction; and the confidence level may be used in selecting an option from available paths / modules / options (e.g., 171, 173, 175, and / or 177) for processing the encoded data 137 received from a memory unit in the memory device 130.

[0098] In general, the data integrity classifier 113 may be implemented in the memory device 130 and / or in the controller 115 of the memory subsystem 110. For example, one data integrity classifier 113 may be implemented in the memory device 130 and customized for operational decisions to be made in the memory device 130; and another data integrity classifier 113 may be implemented in the controller 115 and customized for operational decisions to be made in the controller 115. For example, the data integrity classifier 113 implemented in the controller 115 may use not only the signal and noise characteristics 139 of the data 137 received from the memory device 130, but also other information that may not be available in the memory device 130, such as charge loss, read disturbance, cross temperature effects, program / erase, data retention, etc. For example, the data integrity classifier 113 implemented in the controller 115 and the data integrity classifier 113 implemented in the memory device 130 may have different complexities and / or different levels of accuracy in their predictions. Optionally, the memory device 130 provides its prediction 161 to the controller 115 as part of a rich status report for retrieving the data 137; and the controller 115 uses the prediction 161 generated by the memory device 130 to select a path / module / option for decoding the data 137. In some embodiments, the error detection and recovery 163 (or some paths / modules / options) are implemented in the memory device 130. For example, the processing logic of the error detection and recovery 163 and the data integrity classifier 113 can be implemented using complementary metal oxide semiconductor (CMOS) circuitry formed below the memory cell array on the integrated circuit die of the memory device 130. For example, the processing logic can be formed on a separate integrated circuit die within the integrated circuit package of the memory device 130, and the separate integrated circuit die is connected to the integrated circuit die with the memory cells using through silicon vias (TSVs) and / or other connection technologies.

[0099] For example, when data integrity classifier 113 is implemented in memory device 130 , the output of data integrity classifier 113 may be used in the process of controlling the retrieval of data 137 .

[0100] For example, when the output of data integrity classifier 113 indicates that it is possible to decode encoded data 137 using a decoder (e.g., 177) that uses soft bit data, memory device 130 may automatically further read soft bit data in addition to hard bit data. However, if data integrity classifier 113 indicates that encoded data 137 can be decoded using a decoder (e.g., 175) that does not require soft bit data as input, memory device 130 may skip the operation of reading soft bit data and / or the operation of transmitting soft bit data to controller 115.

[0101] For example, when the output of the data integrity classifier 113 indicates that no available path / module / option (e.g., 171, 173, 175, and / or 177) is likely to successfully decode the data 137, the memory device 130 may automatically perform a read retry to search for an improved read voltage without waiting for a command from the controller 115. In addition, when the output of the data integrity classifier 113 indicates that no available path / module / option (e.g., 171, 173, 175, and / or 177) is likely to successfully decode the data 137, the memory device 130 may optionally skip reading the data 137.

[0102] Figure 5 A method is shown in which the memory subsystem 110 controls data integrity operations based on classification of signal and noise characteristics 139 associated with data 137 retrieved from a memory cell. Figure 5 The method may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software / firmware (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 5 The method is at least partly based on Figure 1 The controller 115 or Figure 2 The processing logic in the memory device 130 of the embodiment of the present invention is executed. Although shown in a specific sequence or order, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0103] For example, Figure 5 The method can be used Figure 2 The memory device and Figure 3 The signal-to-noise characteristics shown in Figure 4 The operations shown in Figure 1 in the computing system.

[0104] At block 301 , a processing device (eg, 115 ) in the memory subsystem 110 transmits a command to a memory device 130 of the memory subsystem 110 to retrieve encoded data 137 from an address 135 .

[0105] For example, data 137 may be in an encoded form for storage in memory cells of memory device 130 to improve reliability. Encoded data 137 has redundant information, which allows a decoder to detect errors and / or restore the original data without errors when the amount of errors in the retrieved encoded data 137 does not exceed a threshold. For example, the data may be encoded / decoded via an error correction code or a low-density parity check code.

[0106] At block 303, in response to a command and during execution of the command in memory device 130, calibration circuitry 145 of memory device 130 enclosed in an integrated circuit package measures signal and noise characteristics 139 of a group (e.g., 131 or 133) of memory cells formed on an integrated circuit die.

[0107] For example, the calibration circuit 145 is at least partially formed on an integrated circuit die, or on another integrated circuit die enclosed in an integrated circuit package.

[0108] For example, the signal and noise characteristics 139 may include statistics of the memory cells under different operating parameters, such as different voltages applied to read the memory cells in a group (eg, 131 or 133).

[0109] For example, the statistical data may include the following: A 、V B 、V C 、V D and / or V E ) is applied to the group of memory cells, and the bit count (e.g., C A , C B , C C , C D and / or C E ). Alternatively or in combination, the statistical data may include a bit difference (e.g., D A , D B , D C and / or D D ), where each bit difference is when the first read voltage (e.g., V A ) is applied to a group of memory cells, the first bit count of the memory cells in the group having a predetermined state (e.g., C A ) and when the second read voltage (eg, V B ) is applied to the group of memory cells, and a second bit count (e.g., C B )

[0110] For example, the predetermined state of the memory cell may be a state in which the memory cell is substantially conductive (e.g., has a large amount of current passing through the memory cell) when a corresponding read voltage is applied to the memory cell. Alternatively, the predetermined state of the memory cell may be a state in which the memory cell is substantially non-conductive (e.g., does not have a large amount of current passing through the memory cell) when a corresponding read voltage is applied to the memory cell.

[0111] At block 305 , a data integrity classifier 113 configured in the memory subsystem 110 generates a prediction (eg, 181 ) based on the signal and noise characteristics 139 .

[0112] At block 307 , the memory subsystem 110 selects an option from a plurality of options to decode the data 137 based on the prediction.

[0113] For example, the prediction may be based on machine learning to identify a level of bit error rate in the encoded data 137, identify the options, and / or identify the probability of the options failing to decode or successfully decoding the encoded data 137 retrieved from the memory device. The prediction may include a confidence level for the prediction.

[0114] At block 309, the encoded data is decoded using the selected options.

[0115] For example, the plurality of options may include decoders having different levels of complexity, taking different inputs, using different amounts of power to decode, and / or having different amounts of latency in the decoding process. The plurality of options may include instructing the memory device 130 to retry a read at address 135 without decoding the encoded data 137, without transmitting the encoded data 137, and / or without reading the data 137 from a memory cell in the memory device 130.

[0116] For example, the plurality of options may include use of a first decoder and use of a second decoder that consumes more energy in operation than the first decoder.

[0117] Different decoders may use different amounts of data in their decoding operations. For example, a second decoder (e.g., 177) uses both hard bit data determined from a group of memory cells at a read voltage and soft bit data determined from a group of memory cells at a voltage having a predetermined offset relative to the read voltage; and a first decoder (e.g., 175) uses hard bit data but not soft bit data.

[0118] Optionally, calibration circuit 145 is configured to calculate a read voltage (eg, V O Alternatively, the read voltage used to determine the hard bit data may be calculated and / or specified by the controller 115 of the memory subsystem 110 .

[0119] The data integrity classifier 113 may be implemented in the controller 115 of the memory subsystem 110 and / or in the memory device 130 .

[0120] When the data integrity classifier 113 is implemented in the memory device 130 , the memory device 130 may determine whether to perform an operation of reading the soft bit data based on the prediction generated by its data integrity classifier 113 .

[0121] When the data integrity classifier 113 is implemented via the processing device 117 of the memory subsystem 110, the memory subsystem 110 may be configured to instruct the memory device 130 to perform a read retry when a prediction indicates that a decoder available in the memory subsystem 110 has failed to decode the encoded data 137, without having to wait for a result from the decoder and / or without having to send the encoded data to any decoder.

[0122] When data integrity classifier 113 is implemented via a processing device (eg, 115) of memory subsystem 110, memory subsystem 110 may be configured to instruct memory device 130 to provide soft bit data when a prediction indicates that a second decoder (eg, 117) is to be used to decode the encoded data.

[0123] The data integrity classifier 113 may include instructions configured as software and / or firmware. For example, the processing device 117 may execute the data integrity classifier 113 to perform the methods discussed above.

[0124] Non-transitory computer storage media may be used to store instructions of firmware of the memory subsystem (eg, 113). When the instructions are executed by the controller 115 and / or the processing device 117, the instructions cause the controller 115 and / or the processing device 117 to perform the methods discussed above.

[0125] Figure 6 An example machine of computer system 400 is shown, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, computer system 400 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 10), or may be used to perform operations of the data integrity classifier 113 (e.g., execute instructions to perform operations corresponding to the reference Figure 1-5In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0126] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0127] The example computer system 400 includes a processing device 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system 418, which communicate with each other via a bus 430 (which may include multiple buses).

[0128] The processing device 402 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 402 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 402 is configured to execute instructions 426 for performing the operations and steps discussed herein. The computer system 400 may further include a network interface device 408 to communicate on a network 420.

[0129] The data storage system 418 may include a machine-readable storage medium 424 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 426 or software embodying any one or more of the methods or functions described herein. The instructions 426 may also reside, in whole or in part, within the main memory 404 and / or within the processing device 402 during execution thereof by the computer system 400, the main memory 404 and the processing device 402 also constituting machine-readable storage media. The machine-readable storage medium 424, the data storage system 418, and / or the main memory 404 may correspond to Figure 1 Memory subsystem 110.

[0130] In one embodiment, instructions 426 include implementing instructions corresponding to data integrity classifier 113 (e.g., reference Figure 1-5 The machine-readable storage medium 424 is a storage medium that is used to store and store instructions for performing the functions of the data integrity classifier 113 described herein. Although the machine-readable storage medium 424 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be understood to include any medium that is capable of storing or encoding an instruction set for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should accordingly be understood to include (but not limited to) solid-state memory, optical media, and magnetic media.

[0131] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to other persons skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that result in a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been demonstrated that it is sometimes convenient, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0132] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0133] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magnetic optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0134] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various these systems will be presented as set forth in the description below. In addition, the present disclosure is described without reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0135] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0136] In this specification, various functions and operations are described as being performed by or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that the intent of such expressions is that the functions are generated by the execution of computer instructions by one or more controllers or processors (e.g., microprocessors). Alternatively or in combination, the functions and operations may be implemented using dedicated circuitry with or without software instructions, such as using an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Embodiments may be implemented using hard-wired circuitry without software instructions or in combination with software instructions. Therefore, the technology is not limited to any particular combination of hardware circuitry and software, nor is it limited to any particular source of instructions executed by a data processing system.

[0137] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A memory subsystem comprising: Processing device; as well as at least one memory component enclosed in an integrated circuit package, the memory component having: A group of memory cells formed on an integrated circuit die; as well as Calibration circuit; wherein the processing device is configured to transmit a command to retrieve data from an address to the memory component; wherein in response to and during execution of the command, the calibration circuit is configured to measure signal and noise characteristics of the group of memory cells associated with encoded data retrieved from the group of memory cells; wherein the memory subsystem has a data integrity classifier and a plurality of options available for processing the encoded data; wherein the data integrity classifier is configured to generate a prediction based on the signal and noise characteristics, wherein the prediction comprises a prediction error rate in the encoded data; and Wherein the memory subsystem is configured to select an option from the plurality of options based on the prediction, and decode the encoded data using the selected option.

2. The memory subsystem of claim 1, wherein the calibration circuit is formed at least partially on the integrated circuit die.

3. The memory subsystem of claim 2, wherein the signal and noise characteristics include statistics of the memory cells under different operating parameters.

4. The memory subsystem of claim 3, wherein the different operating parameters include different voltages applied to read memory cells in the group.

5. The memory subsystem of claim 4, wherein the statistical data includes a count of memory cells in the group that have a predetermined state when the different voltages are applied across the group of memory cells.

6. The memory subsystem of claim 4, wherein the statistical data comprises count differences, each count difference being a difference between: a first count of memory cells in the group having a predetermined state when a first read voltage is applied across the group of memory cells; and A second count of memory cells in the group having the predetermined state when a second read voltage is applied across the group of memory cells.

7. The memory subsystem of claim 1, wherein the plurality of options includes a first decoder and a second decoder that consumes more energy in operation than the first decoder.

8. The memory subsystem of claim 7 , wherein the second decoder uses both hard bit data determined from the group of memory cells at a read voltage and soft bit data determined from the group of memory cells at a voltage having a predetermined offset relative to the read voltage; and the first decoder uses the hard bit data but not the soft bit data.

9. The memory subsystem of claim 8, wherein the calibration circuit is configured to calculate the read voltage for determining the hard bit data based on the signal and noise characteristics.

10. The memory subsystem of claim 8, wherein the data integrity classifier is implemented in the memory component; and the soft bit data is determined based on the prediction generated by the data integrity classifier.

11. The memory subsystem of claim 8, wherein the data integrity classifier is implemented via the processing device; and the memory subsystem is configured to instruct the memory component to perform a read retry when the prediction indicates that a decoder available in the memory subsystem has failed to decode the encoded data.

12. The memory subsystem of claim 8, wherein the data integrity classifier is implemented via the processing device; and the memory subsystem is configured to instruct the memory component to provide the soft bit data when the prediction indicates that the second decoder is to be used to decode the encoded data.

13. A method for a memory subsystem, comprising: transmitting, by a processing device in the memory subsystem, a command to retrieve encoded data from an address to a memory component of the memory subsystem; In response to the command and during execution of the command in the memory component, measuring signal and noise characteristics of a group of memory cells formed on an integrated circuit die using calibration circuitry of the memory component enclosed in an integrated circuit package; generating, by a data integrity classifier configured in the memory subsystem, a prediction based on the signal and noise characteristics, wherein the prediction includes a prediction error rate in the encoded data; selecting, by the memory subsystem, an option from a plurality of options available for processing the encoded data based on the prediction; as well as The encoded data is decoded using the selected options.

14. The method of claim 13 wherein the signal and noise characteristics include statistics of memory cells in the group read at different voltage levels.

15. The method of claim 14, wherein the plurality of options include decoders that take different inputs, use different amounts of power to decode, and have different delays in the decoding process.

16. The method of claim 15, wherein the prediction is based on machine learning to identify the options.

17. A non-transitory computer storage medium storing instructions that, when executed by a computing system, cause the computing system to perform a method comprising: transmitting, by a processing device in a memory subsystem, a command to retrieve encoded data from an address to a memory component of the memory subsystem, wherein in response to and during execution of the command, calibration circuitry of the memory component measures signal and noise characteristics of a group of memory cells formed on an integrated circuit die; receiving the signal and noise characteristics from the memory component in response to the command; generating, by a data integrity classifier configured in the memory subsystem, a prediction based on the signal and noise characteristics, wherein the prediction includes a prediction error rate in the encoded data; as well as An option is selected, by the memory subsystem based on the prediction, from a plurality of options for processing the encoded data retrieved from the group of memory cells.

18. The non-transitory computer storage medium of claim 17, wherein the plurality of options include decoding the encoded data using a different decoder, and instructing the memory component to retry a read at the address without decoding the encoded data.

19. The non-transitory computer storage medium of claim 18, wherein the prediction includes a confidence level of the prediction.

20. The non-transitory computer storage medium of claim 19, wherein the decoding is performed using an error correction code or a low density parity check code.

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