Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor chip, and a wiring substrate having a first region overlapping the semiconductor chip and a second region surrounding the first region in a plan view. In addition, the wiring substrate includes a first wiring layer, a third wiring layer, and a plurality of data wirings arranged so as to cross a boundary between the first region and the second region. In addition, the plurality of data wirings includes a first data wiring transmitting a first byte data signal, and a second data wiring transmitting a second byte data signal. In addition, in the first wiring layer, the first data wiring is arranged so as to cross the boundary. In addition, in the third wiring layer, the second data wiring is arranged so as to cross the boundary. Furthermore, in the plan view, the first data wiring and the second data wiring overlap each other.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, and the present application can be appropriately applied to, for example, a semiconductor device including a wiring substrate on which a semiconductor chip having a data communication circuit is mounted. BACKGROUND

[0002] The disclosed technology is listed below.

[0003] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-33993.

[0004] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2019-114601.

[0005] [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2019-114675.

[0006] Patent Document 1 discloses an electronic device that can perform data access between a semiconductor memory device mounted on a wiring substrate and a semiconductor device mounted on the wiring substrate. Patent Documents 2 and 3 disclose a semiconductor device including a signal wiring that transmits an input signal to a semiconductor chip, and a signal wiring that transmits an output signal from the semiconductor chip, and the latter is arranged in a wiring layer different from a wiring layer in which the signal wiring for the input signal is formed. SUMMARY

[0007] In a signal transmission path for transmitting a data signal between a semiconductor chip having a data communication circuit and a memory component, in each of a large number of signal transmission paths, it is necessary for the characteristic impedance and the maximum amount of crosstalk to be equal at a low level. In addition, it is necessary to reduce the impedance in each of a plurality of paths for supplying power to the data communication circuit. In order to miniaturize a semiconductor device having a semiconductor chip having a data communication circuit, the semiconductor chip having the data communication circuit, the signal transmission path, and the power supply path need to be arranged at a higher density. Therefore, a technology for maintaining the characteristics of the signal transmission path and the power supply path is required.

[0008] Other objects and novel features will become apparent from the description and drawings.

[0009] A semiconductor device according to one embodiment includes a semiconductor chip having a data communication circuit that transmits a data signal, and a wiring substrate having a first region overlapping the semiconductor chip and a second region surrounding the first region in a plan view. In addition, the semiconductor chip has a plurality of data electrodes each coupled to the data communication circuit and each transmitting the data signal. In addition, the wiring substrate includes a first wiring layer, a second wiring layer located in a layer lower than the first wiring layer, a third wiring layer located in a layer lower than the second wiring layer, a plurality of data terminals arranged at positions facing the plurality of data electrodes of the semiconductor chip in the first region and electrically connected to the plurality of data electrodes, respectively, and a plurality of data wirings arranged so as to cross a boundary between the first region and the second region and electrically connected to the plurality of data terminals, respectively. In addition, the plurality of data terminals includes a plurality of first data terminals each transmitting a first byte data signal, and a plurality of second data terminals each transmitting a second byte data signal. In addition, the plurality of data wirings includes a plurality of first data wirings electrically connected to the plurality of first data terminals, respectively, and a plurality of second data wirings electrically connected to the plurality of second data terminals, respectively. In addition, in the plan view, the plurality of first data terminals are arranged in a first data terminal group adjacent to each other, and the plurality of second data terminals are arranged in a second data terminal group adjacent to each other. In addition, in the first wiring layer, each of the plurality of first data wirings is arranged so as to cross the boundary between the first region and the second region. In addition, in the third wiring layer, each of the plurality of second data wirings is arranged so as to cross the boundary between the first region and the second region. In addition, in the plan view, the plurality of first data wirings and the plurality of second data wirings overlap each other. Further, in the second wiring layer, a first ground pattern supplied with a ground potential is arranged at a position overlapping each of the plurality of first data wirings and the plurality of second data wirings. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is an explanatory diagram showing a configuration example of a data communication system including a semiconductor device according to an embodiment.

[0011] FIG. 2 is a plan view seen from a mounting surface side of the semiconductor device shown in FIG. 1 on which a semiconductor chip is mounted.

[0012] FIG. 3 is a bottom view of the semiconductor device shown in FIG. 2 .

[0013] FIG. 4 is a cross-sectional view along line A-A of FIG. 2 .

[0014] FIG. 5 It is shown schematically. FIG. 4 The diagram illustrates an example configuration of the data communication circuitry for the semiconductor chip shown.

[0015] FIG. 6 It is shown FIG. 2 The diagram shows a plan view of the upper surface of the wiring substrate from which the semiconductor chip and the bottom-filled resin have been removed.

[0016] FIG. 7 yes FIG. 6 A magnified plan view of part A, from which the portion [of the image] was removed. FIG. 6 The uppermost insulating film shown in the diagram.

[0017] FIG. 8 It is shown FIG. 4 A plan view of an example layout of the second wiring layer in the wiring substrate shown.

[0018] FIG. 9 Is included FIG. 8 The wiring layer shown corresponds to FIG. 6 An enlarged plan view of part A.

[0019] FIG. 10 It is shown FIG. 4 A plan view of an example layout of the third wiring layer in the wiring substrate shown.

[0020] FIG. 11 yes FIG. 10 A magnified plan view of part A.

[0021] FIG. 12 It is shown FIG. 4 A plan view of an example layout of the fourth wiring layer in the wiring substrate shown.

[0022] FIG. 13 Is included FIG. 12 The wiring layer shown corresponds to FIG. 6 An enlarged plan view of part A.

[0023] FIG. 14 It is shown FIG. 4 A plan view of an example layout of the fifth wiring layer in the wiring substrate shown.

[0024] FIG. 15 Is included FIG. 14 The wiring layer shown corresponds to FIG. 6 An enlarged plan view of part A.

[0025] FIG. 16 yes FIG. 2A plan view of the wiring substrate shown in FIG. 1.

[0026] FIG. 17 is a plan view showing FIG. 4 A plan view of a configuration example of the seventh wiring layer and the ninth wiring layer in the wiring substrate shown in FIG. 1.

[0027] FIG. 18 is a plan view schematically showing FIG. 1 An explanatory diagram of a modification example of the data communication system shown in FIG. 1.

[0028] FIG. 19 is a plan view seen from FIG. 18 A plan view of a mounting surface side of the semiconductor device shown in FIG. 1, on which a semiconductor chip is mounted.

[0029] FIG. 20 is a plan view showing FIG. 19 A plan view of a layout example of the second wiring layer in the wiring substrate shown in FIG. 1.

[0030] FIG. 21 is a cross-sectional view showing a modification example with respect to FIG. 4 DETAILED DESCRIPTION

[0031] DESCRIPTION OF FORM, BASIC TERMINOLOGY, AND LAW

[0032] In the present application, for the sake of convenience, the description of the embodiments will be divided into a plurality of chapters and the like, but unless explicitly stated otherwise, these chapters are not independent of each other, and each part of a single example (one of which is a part of the details or the other part or all of it) is a modification example or the like before or after the description. In principle, the description of similar parts is omitted. In addition, unless explicitly stated otherwise, theoretically limited to that number, and unless it is obvious from the context, each component in the embodiments is not essential.

[0033] Similarly, in the description of the embodiments and the like, "X composed of A" and the like with respect to materials, compositions, and the like do not exclude elements other than A unless it is explicitly indicated that it is not the case and it is obvious from the context that it is not the case. For example, with respect to ingredients, it means "X including A as a main ingredient" and the like. For example, the term "silicon member" and the like is not limited to pure silicon, and needless to say, it also includes members that include a SiGe (silicon germanium) alloy, a multi-element alloy that includes silicon as a main ingredient thereof, other additives, and the like. In addition, unless otherwise stated, gold plating, Cu layer, nickel plating, and the like include not only pure materials but also members that include gold, Cu, nickel, and the like, respectively, as a main ingredient.

[0034] ​Also, a reference to a particular number or quantity can be greater than or less than that specific number, unless otherwise specifically stated, theoretically limited to that number, and unless according to the context, it would be clear that it is not. In the following description, a certain value and another value can be referred to as "the same" or "equivalent", but the meaning of "the same" or "equivalent" includes the case where they are strictly the same and the case where there is an error within a range that can be considered substantially equivalent.

[0035] In the drawings of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and the description will not be repeated in principle.

[0036] Also, in the drawings, the section line or the like can be omitted even in a cross section when the section line becomes complicated or when it is apparently distinguished from a gap. In this regard, even a hole is closed in a plane, the outline of the background can be omitted when it is apparent from the description or the like. Also, a section line or a dot pattern can be added to indicate that the area is not a void (even if it is not a cross section) or to indicate a boundary line of the area.

[0037] <DATA COMMUNICATION SYSTEM>

[0038] First, an overview of a data communication system including a semiconductor device of the present embodiment will be described. FIG. 1 is an explanatory diagram showing a configuration example of a data communication system including a semiconductor device according to the present embodiment.

[0039] As FIG. 1 As shown in, the semiconductor device PKG1 of the present embodiment includes a data communication circuit DCC for transmitting a data signal SGD between the semiconductor chip 10 and the memory devices MD1 and MD2. In FIG. 1 In the example shown in, the data communication circuit DCC transmits the data signal SGD to and from each of the memory devices MD1 and MD2. The data communication circuit DCC of the modified example can be in data communication with one memory device MD1. The memory devices MD1 and MD2 are, for example, memory devices corresponding to a standard of LPDDR4 (Low Power Double Data Rate 4) operating at a bus width of 32 bits and a transfer rate of 3.2 GB / sec.

[0040] The semiconductor device PKG1 and the memory device MD1 are electrically connected to each other via a data signal transmission path DCP for 32 bits. FIG. 1A data signal transmission path DCP is shown in bytes, and the semiconductor device PKG1 and the memory device MD1 are electrically connected via the data signal transmission path DCP for four bytes. Similarly, the semiconductor device PKG1 and the memory device MD2 are electrically connected via the data signal transmission path DCP for 4 bytes. In addition, the semiconductor device PKG1 and the memory device MD1 are electrically connected via a control signal transmission path CCP (indicated by a dashed line in FIG. 1 ) through which control signals are transmitted. The semiconductor device PKG1 and the memory device MD2 are electrically connected via a control signal transmission path CCP (indicated by a dash-dot line in FIG. 1 ) through which control signals SGC are transmitted (refer to FIG. 5 to be described later).

[0041] The control signals SGC transmitted through the control signal transmission path CCP include clock signals, address signals, and the like. Although these control signals SGC are transmitted through independent paths, two control signal transmission paths CCP are shown in FIG. 1 . FIG. 1 An example in which the memory devices MD1 and MD2 are provided outside the semiconductor device PKG1 is shown. As will be described later through a modification example, the memory devices MD1 and MD2 can be incorporated in the semiconductor device PKG1.

[0042] <semiconductor device>

[0043] Next, an exemplary configuration of the semiconductor device PKG1 shown in FIG. 2 will be described. FIG. 1 is a plan view seen from the mounting surface side of the semiconductor device shown in FIG. 3 on which a semiconductor chip is mounted. FIG. 2 is a bottom view of the semiconductor device shown in FIG. 3 . Incidentally, FIG. 4 is a plan view, but the region 2R1 is hatched to clearly show the range of the region 2R1. FIG. 2 is a cross-sectional view along the line A-A of FIG. 2 .

[0044] As shown in FIG. 2 , the semiconductor device PKG1 of the present embodiment includes a semiconductor chip 10 and a wiring substrate 20 on which the semiconductor chip 10 is mounted. The semiconductor chip 10 is mounted on an upper surface 20t of the wiring substrate 20. From FIG. 3In the plan view of the semiconductor device PKG1 as seen from the mounting surface of the semiconductor chip 10, the wiring substrate 20 includes a region 2R1 overlapping with the semiconductor chip 10 and a region 2R2 surrounding the region 2R1 (specifically, the perimeter of the region 2R1). In addition to the upper surface 20t of the wiring substrate 20, regions 2R1 and 2R2 are also provided on... FIG. 4 The lower surface 20b shown is FIG. 4 On the multiple wiring layers shown. In the thickness direction of the wiring substrate 20 ( FIG. 4 In the Z direction shown, all portions that overlap with the semiconductor chip 10 correspond to region 2R1.

[0045] like FIG. 2 As shown, the semiconductor chip 10 has a front surface (main surface, upper surface) 10t and a rear surface (main surface, bottom surface) 10b opposite to the front surface 10t. Further, in a plan view viewed from one side of the front surface 10t and the rear surface 10b to the other, the semiconductor chip 10 has four edges 10s positioned at its outer edges. FIG. 4 As shown, in the plan view of the semiconductor chip 10, the semiconductor chip 10 has a rectangular shape, the rectangular shape having a planar area smaller than the planar area of ​​the wiring substrate 20. The semiconductor chip 10 is mounted at the center of the upper surface 20t of the wiring substrate 20. Each of the four sides 10s of the semiconductor chip 10 extends along each of the four sides 20s of the wiring substrate 20.

[0046] Multiple electrodes (chip electrodes, electrode pads, and electrode portions) 1PD are arranged on the front surface 10t of the semiconductor chip 10. In this embodiment, the multiple electrodes 1PD are arranged in a matrix on the front surface 10t of the semiconductor chip 10. By arranging the multiple electrodes 1PD, which serve as external input / output terminals of the semiconductor chip 10, in a matrix form, the increase in planar area can be suppressed even if the number of electrodes included in the semiconductor chip 10 increases. Furthermore, when the electrodes 1PD used for supplying power are arranged in the central portion of the semiconductor chip 10 in the plan view, the power supply path to the core circuitry formed in the central portion of the semiconductor chip 10 can be shortened.

[0047] The front surface 10t of the semiconductor chip 10 faces the upper surface 20t of the wiring substrate 20. As described above, the following method is referred to as the face-down mounting method or flip-chip interconnect method: the semiconductor chip 10 is mounted on the wiring substrate 20 such that the surface 10t, which serves as the electrode forming surface of the semiconductor chip 10, faces the upper surface 20t, which serves as the chip mounting surface of the wiring substrate 20.

[0048] In the flip-chip connection method, the electrodes 1PD arranged on the front surface 10t of the semiconductor chip 10 and the terminals 2PD arranged on the upper surface 20t of the wiring substrate 20 are connected to each other via the protruding electrodes SB. As shown in FIG. 1, the protruding electrodes SB are connected to each of the plurality of electrodes 1PD, and the plurality of electrodes 1PD of the semiconductor chip 10 and the plurality of terminals 2PD of the wiring substrate 20 are electrically connected to each other via the plurality of protruding electrodes SB, respectively. FIG. 1 In the flip-chip connection method, the electrodes 1PD arranged on the front surface 10t of the semiconductor chip 10 and the terminals 2PD arranged on the upper surface 20t of the wiring substrate 20 are connected to each other via the protruding electrodes SB. As shown in FIG. 1, the protruding electrodes SB are connected to each of the plurality of electrodes 1PD, and the plurality of electrodes 1PD of the semiconductor chip 10 and the plurality of terminals 2PD of the wiring substrate 20 are electrically connected to each other via the plurality of protruding electrodes SB, respectively.

[0049] The protruding electrode SB is a metal member formed so as to protrude on the surface 10t of the semiconductor chip 10. In the present embodiment, the protruding electrode SB is a so-called solder bump in which a solder material is layered on the electrode 1PD with a bump under metal interposed between the solder and the electrode 1PD. The base metal film can be exemplified by, for example, a layered film of titanium (Ti), copper (Cu), and nickel (Ni) layered from the connection surface of the electrode 1PD (in some cases, a gold (Au) film is further formed on the nickel film). The solder material constituting the solder bump is, for example, a Sn-Pb solder material containing lead (Pb) or a so-called lead-free solder substantially free of Pb. Examples of the lead-free solder include, for example, tin (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), and the like. Here, the lead-free solder means a solder having a content of lead (Pb) of 0.1 wt% or less, and the content is determined as a standard of the RoHS (Restriction of Hazardous Substances) directive.

[0050] When the semiconductor chip 10 is mounted on the wiring substrate 20, the solder bump is formed in advance on both the plurality of electrodes 1PD and the plurality of terminals 2PD, and heat treatment (reflow process) is performed while bringing the solder bumps into contact with each other, thereby integrating the solder bumps with each other to form the protruding electrode SB. As a modified example of the present embodiment, a columnar bump of a solder film made of copper (Cu) or nickel (Ni) is formed on the end surface of the conductive pillar, which can be used as the protruding electrode SB.

[0051] Although not shown, as a modification example of the present embodiment, there is also a case where the rear surface 10b of the semiconductor chip faces the chip mounting surface of the wiring substrate 20 (referred to as a face-up mounting method). The electrodes 1PD of the chip 10 are arranged around the front surface 10t. The electrodes 1PD of the semiconductor chip and the terminals 2PD of the wiring substrate 20 are electrically connected to each other via wirings (not shown). When the semiconductor chip is mounted on the wiring substrate 20 in a face-down manner as in the present embodiment, the arrangement density of the 1PD among the electrodes per unit area can be improved. When the electrodes 1PD of the semiconductor chip 10 and the terminals 2PD of the wiring substrate 20 are electrically connected to each other via the protruding electrodes SB as in the present embodiment, the impedance of the transmission path between the electrodes 1PD and the terminals 2PD can be reduced compared to the impedance of the wiring connection method.

[0052] A plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip 10 (more specifically, the element formation region is provided on the element formation surface of the semiconductor substrate that is the base material of the semiconductor chip 10). The plurality of semiconductor elements are electrically connected to each other to constitute a semiconductor circuit. The semiconductor chip 10 includes a plurality of semiconductor circuits, and the plurality of semiconductor circuits include FIG. 2 the data communication circuit DCC shown in FIG. 1. The plurality of electrodes 1PD are respectively electrically connected to the plurality of semiconductor elements via wirings (not shown) formed in a wiring layer provided inside the semiconductor chip 10 (in detail, between the surface 10t and the semiconductor element formation region (not shown)).

[0053] The semiconductor chip 10 (specifically, the semiconductor substrate of the semiconductor chip 10) is made of, for example, silicon (Si). An insulating film that covers the semiconductor substrate of the semiconductor chip 10 and the wirings of the semiconductor chip 10 is formed on the surface 10t, and the surface of each of the plurality of electrodes 1PD is exposed from the insulating film in an opening formed in the insulating film. Each of the plurality of electrodes 1PD is made of a metal, and in the present embodiment, for example, made of aluminum (Al) or copper (Cu).

[0054] The wiring substrate 20 on which the semiconductor chip 10 is mounted has an upper surface 20t (see FIG. 3 ) on which the semiconductor chip 10 is mounted and a lower surface (surface, main surface, and surface to be mounted) 20b (see FIG. 4 ) opposite to the upper surface 20t. The wiring substrate 20 has a rectangular outer shape in a plan view. The wiring substrate 20 has four sides 20s constituting the outer edges of the wiring substrate 20 as seen from one side to the other side of the upper surface 20t and the lower surface 20b in the plan view.

[0055] As FIG. 4As shown, multiple conductor patterns and an insulating layer 2e for insulating between the multiple conductor patterns are provided. The multiple conductor patterns included in the wiring substrate 20 include multiple terminals 2PD, wiring 2w, via wiring 2v, through-hole wiring 2TW, pads 2LD, and a conductor plane 2PL as a large-area conductor pattern. The conductor plane 2PL includes ground patterns and power patterns, which will be described later.

[0056] The wiring substrate 20 has multiple wiring layers for electrically connecting the terminals 2PD on the upper surface 20t, which serves as the chip mounting surface, to the pads 2LD on the lower surface 20b, which also serves as the chip mounting surface. FIG. 20 In the illustrated embodiment, the wiring layer comprises ten wiring layers sequentially from the top surface 20t: wiring layers WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8, WL9, and WL10. Wiring layer WL1 is a layer with a plurality of terminals 2PD formed thereon, and may be replaced by a terminal forming layer. Similarly, wiring layer WL10 is a layer with a plurality of pads 2LD formed thereon, and may be replaced by a pad forming layer. In other words, there are wiring layers WL2, WL3 (lower than WL2), WL4 (lower than WL3), WL5 (lower than WL4), WL10 (lower than WL1), WL7 (lower than WL6), WL8 (lower than WL7), and WL9 (lower than WL9, located between WL5 (terminal forming layer) and WL6 (pad forming layer). Each wiring layer WL2-WL9 is covered by an insulating layer 2e. Multiple openings are provided in the insulating layer 2e covering each wiring layer, and vias (vias and interlayer conductive paths) 2v are buried in each of the multiple openings. Each of the wiring layers WL1, WL2, WL3, WL4, and WL5 is electrically connected vias 2v. Similarly, wiring layers WL6, WL7, WL8, WL9 and WL10 are electrically connected to each other via multiple vias at 2V.

[0057] Multiple wiring layers of the wiring substrate 20 are formed, for example, by stacking multiple wiring layers on the upper surface 2Ct and lower surface 2Cb of an insulating layer (core layer, core material, core insulating layer) 2CR made of prepreg material, wherein glass fibers are impregnated with resin by a stacking method. Wiring layer WL5 on the upper surface 2Ct and wiring layer WL6 on the lower surface 2Cb of the insulating layer 2CR are electrically connected via multiple via wiring (interlayer conductive path) 2TW embedded in multiple vias (vias), which are configured to pass through one of the upper surface 2Ct and the lower surface 2Cb to the other.

[0058] A plurality of terminals (terminal portions, pads, and semiconductor chip connection terminals) 2PD electrically connected to the semiconductor chip 10 are formed on the upper surface 20t of the wiring substrate 20. Each of the plurality of terminals 2PD is an internal interface terminal for electrically connecting the semiconductor chip 10 and the wiring substrate 20 to each other. A plurality of lands (terminals, external terminals, electrodes, and external electrodes) 2LD that are external input / output terminals of the semiconductor device PKG1 are formed on the lower surface 20b of the wiring substrate 20. The lands 2LD are external interface terminals for electrically connecting the wiring substrate 20 and an external device (for example, the mounting substrate 50 shown in FIG. 4

[0059] The plurality of terminals 2PD and the plurality of lands 2LD are electrically connected via a plurality of wirings 2w formed in the wiring substrate 20 and a plurality of via wirings 2v and a plurality of through-hole wirings 2TW that electrically connect the wiring layer WL3 and the wiring layer WL4, the via wirings 2v and the through-hole wirings 2TW being interlayer conductive paths. In the embodiment shown in FIG. 4 In the embodiment shown in

[0060] In the embodiment shown in FIG. 3 In the embodiment shown in

[0061] As shown in FIG. 3 The plurality of external terminals 30 are arranged in a matrix. Although not shown in FIG. 4 FIG. 3 ​​) are also arranged in a matrix form. In this way, such a semiconductor device is called a land grid array type semiconductor device in which a plurality of external terminals (external terminals 30 and pads 2LD) are arranged in a matrix form on a surface on which the wiring substrate 20 is mounted. The land grid array type semiconductor device is preferable because an increase in mounting area of the semiconductor device can be suppressed even if the number of external terminals increases because the mounting surface (lower surface 20b) of the wiring substrate 20 can be effectively used as a space for arranging the external terminals. In other words, a semiconductor device in which the number of external terminals increases as the function and integration level become higher can be mounted in a space-saving manner.

[0062] In FIG. 4 and FIG. 4 , a so-called BGA (ball grid array) type semiconductor package in which solder balls as a spherical solder material are used as the external terminals 30 is exemplarily shown, but there are various modification examples in the arrangement and configuration of the external terminals. For example, there are modification examples of the following structure: a plurality of pads 2LD are exposed to the lower surface 20b shown in FIG. 4 , a thin solder material is bonded to the plurality of pads 2LD exposed to the lower surface 20b or the like. These modification example packages are called land grid array types.

[0063] As shown in FIG. 1 , the underfill resin 40 is provided between the semiconductor chip 10 and the wiring substrate 20. The underfill resin 40 is provided so as to close a gap between the front surface 10t of the semiconductor chip 10 and the upper surface 20t of the wiring substrate 20. The underfill resin 40 is made of an insulating (non-conductive) material (for example, a resin material) and is provided so as to seal the electrical connection portion (the bonding portion of the plurality of protruding electrodes SB) of the semiconductor chip 10 and the wiring substrate 20. As described above, by arranging the underfill resin 40 so as to seal the connection portion of the plurality of protruding electrodes SB, stress generated in the electrical connection portion of the semiconductor chip 10 and the wiring substrate 20 can be relaxed.

[0064] <Configuration example of data communication circuit>

[0065] Next, a configuration example of the data communication circuit DCC included in the semiconductor chip 10 shown in FIG. 5 will be described. FIG. 4 is a explanatory diagram schematically showing a configuration example of the data communication circuit of the semiconductor chip shown in FIG. 5 . In FIG. 5 , a dot pattern and a hatching are shown in order to distinguish each of the plurality of electrodes 1PD and the plurality of terminals 2PD.

[0066] As shown in FIG. 1As shown in FIG. 1, the semiconductor chip 10 includes a data communication circuit DCC including a data communication circuit DCC1 for communicating with a memory device MD1 (see FIG. 2) and a data communication circuit DCC2 for communicating with a memory device MD2 (see FIG. 3). FIG. 1 ) and the data communication circuit DCC2 for communicating with the memory device MD2 (see FIG. 5 ). Each of the data communication circuits DCC1 and DCC2 includes, for example, an input / output circuit for controlling input or output of a data signal SGD and a control signal SGC between the semiconductor chip 10 and the outside of the semiconductor chip 10.

[0067] The semiconductor chip 10 is connected to the data communication circuit DCC, and the semiconductor chip 10 has a plurality of data electrodes 1PDd for transmitting a data signal. FIG. 5 Each of the data communication circuits DCC1 and DCC2 is schematically shown as being coupled with four data electrodes 1PDd. However, for example, each of the data communication circuits DCC1 and DCC2 is electrically connected with data electrodes 1PDd of 32 bits. FIG. 5 In the example shown in FIG. 1, the data communication circuit DCC1 transmits a first byte data signal SGD1 from the 0th bit to the 7th bit, a second byte data signal SGD2 from the 8th bit to the 15th bit, a third byte data signal SGD3 from the 16th bit to the 23rd bit, and a fourth byte data signal SGD4 from the 24th bit to the 31st bit. The data communication circuit DCC2 transmits a fifth byte data signal SGD5 from the 0th bit to the 7th bit, a sixth byte data signal SGD6 from the 8th bit to the 15th bit, a seventh byte data signal SGD7 from the 16th bit to the 23rd bit, and an eighth byte data signal SGD8 from the 24th bit to the 31st bit.

[0068] The semiconductor chip 10 is connected to the data communication circuit DCC, and the semiconductor chip 10 has a plurality of control electrodes 1PDc for transmitting a control signal SGC. The semiconductor chip 10 includes a plurality of power supply electrodes 1PDv for supplying a power supply potential VD to the data communication circuit DCC, and a plurality of ground electrodes 1PDg for supplying a ground potential VG to the data communication circuit DCC. In the embodiment shown in FIG. 1, the plurality of power supply electrodes 1PDv are electrically connected to each other. The plurality of ground electrodes 1PDg are electrically connected to each other. FIG. 4

[0069] The wiring substrate 20 has a plurality of data terminals 2PDd electrically connected to the plurality of data electrodes 1PDd. As shown in FIG. 2, in a region 2R1 of the wiring substrate 20, each of the plurality of terminals 2PD of the wiring substrate 20 is disposed to face the plurality of electrodes 1PD of the semiconductor chip 10. Thus, FIG. 5 FIG. 4 ​​The multiple data terminals 2PDd shown are arranged in the region 2R1 of the wiring layer WL1 facing the multiple data electrodes 1PDd, as shown. FIG. 4 As shown in the diagram, the wiring substrate 20 has a plurality of control terminals 2PDc electrically connected to a plurality of control electrodes 1PDc. The plurality of control terminals 2PDc are arranged at positions in region 2R1 of the wiring layer WL1 facing the plurality of control electrodes 1PDc, as shown in the diagram. FIG. 4 As shown in the diagram, the wiring substrate 20 has a plurality of power terminals 2PDv electrically connected to a plurality of power electrodes 1PDv. The plurality of power terminals 2PDv are arranged at locations in region 2R1 of the wiring layer WL1 facing the plurality of power electrodes 1PDv, as shown in the diagram. FIG. 4 As shown in the diagram, the wiring substrate 20 has multiple ground terminals 2PDg electrically connected to multiple ground electrodes 1PDg. The multiple ground terminals 2PDg are arranged in a region 2R1 of the wiring layer WL1 facing the multiple ground electrodes 1PDg, as shown in the diagram. FIG. 6 As shown in the figure.

[0070] <Details of Wiring Layout>

[0071] Next, a detailed description will be provided with reference to the accompanying drawings. FIG. 2 The wiring layout in the wiring layer of the wiring substrate 20 shown. FIG. 7 It is shown FIG. 6 The diagram shows a plan view of the upper surface of the wiring substrate from which the semiconductor chip and bottom filling resin have been removed. FIG. 6 yes FIG. 7 A magnified plan view of part A, from which the portion [of the image] was removed. FIG. 8 to FIG. 16 The uppermost insulating film shown. Incidentally, FIG. 7 It is a plan view, but different patterns are given depending on the type of signal or potential flowing to terminal 2PD. Additionally, as described below... FIG. 4 In, according to FIG. 6 The same rules apply to assigning different patterns to each other based on the type of signal or potential flowing through the conductor pattern or wiring.

[0072] like FIG. 7 As shown, an insulating film SR1 is formed on the uppermost wiring layer WL1 of the wiring substrate 20. The insulating film SR1 is an organic insulating film (solder resist) used to protect the upper surface 20t of the wiring substrate 20. In the wiring layer WL1, portions of the plurality of terminals 2PD corresponding to the semiconductor chip 10 in region 2R1 are exposed from the insulating film SR1. The entire region 2R2 is covered by the insulating film SR1. In the wiring layer WL1, the plurality of terminals 2PD are formed in the region 2R1 exposed from the insulating film SR1. FIG. 7 The multiple terminals 2PD shown have FIG. 5The diagram shows multiple data terminals 2PDd, multiple control terminals 2PDc, multiple power terminals 2PDv, and multiple ground terminals 2PDg. FIG. 5 In the illustrated embodiment, the plurality of terminals 2PD include a plurality of core power terminals 2PDv2. The plurality of core power terminals 2PDv2 are used to supply power potentials (and voltages) to core circuitry (e.g., arithmetic processing circuitry). FIG. 7 The terminals shown are for different power supply potentials (VD). A ground potential (VG) is supplied (see reference). FIG. 7 A grounding pattern (grounding plane) 2PLg is formed in the wiring layer WL1. In the wiring layer WL1, the grounding pattern 2PLg is formed to cover most of area 2R2. For example... FIG. 7 As shown, the grounding pattern 2PLg of the wiring layer WL1 is formed to span the boundary 2BL between zone 2R1 and zone 2R2. A portion of the grounding pattern 2PLg is formed in zone 2R1 and integrated with a portion of a plurality of grounding terminals 2PDg.

[0073] like FIG. 2 As shown, multiple terminals 2PD are regularly arranged in zone 2R1. Multiple ground terminals 2PDg, integrated with the ground pattern 2PLg, are formed in the first column closest to the boundary 2BL between zone 2R1 and zone 2R2. Multiple data terminals 2PDd and multiple control terminals 2PDc are arranged in the second to fifth columns. Multiple power terminals 2PDv are arranged in the sixth column and electrically connected to each other via wiring 2wv. Multiple ground terminals 2PDg are arranged in the seventh column and electrically connected to each other via wiring 2wg. Multiple core power terminals 2PDv2 are arranged in the eighth column and electrically connected to each other via wiring 2wv2. In zone 2R1, each data terminal of the multiple data terminals 2PDd is arranged on the outer periphery of the multiple power terminals 2PDv, in other words, on the side closer to zone 2R2. Similarly, in zone 2R1, each control terminal of the multiple control terminals 2PDc is arranged on the outer periphery of the multiple power terminals 2PDv, in other words, on the side closer to zone 2R2.

[0074] Multiple data terminals 2PDd are arranged in groups, with each byte of data signal to be transmitted as a unit. FIG. 7In the example shown, the second to fifth columns of the terminal array include: a data terminal group (first terminal group) 2PG1, arranged such that a plurality of data terminals 2PDd1 for transmitting the first byte data signal SGD1 are arranged adjacent to each other; a data terminal group (second terminal group) 2PG2, arranged such that a plurality of data terminals 2PDd2 for transmitting the second byte data signal SGD2 are arranged adjacent to each other; a data terminal group (third terminal group) 2PG3, arranged such that a plurality of data terminals 2PDd3 for transmitting the third byte data signal SGD3 are arranged adjacent to each other; and a data terminal group (fourth terminal group) 2PG4, arranged such that a plurality of data terminals 2PDd4 for transmitting the fourth byte data signal SGD4 are arranged adjacent to each other. Data terminal groups 2PG1 and 2PG2 are adjacent to each other. Terminal groups 2PG3 and 2PG4 are adjacent to each other. Each data terminal group 2PG1-2PG4 includes eight DQ terminals for transmitting DQ signals, one DM terminal for transmitting DM signals, two DQS terminals for transmitting DQS signals, and a reference terminal used for reference and electrically connected to the ground terminal 2PDg.

[0075] Multiple control terminals 2PDc are centrally arranged. The second to fifth columns of the terminal array include control terminal groups 2PGc, in which multiple control terminals 2PDc are arranged. Data terminal groups 2PG1, 2PG2, 2PG3, and PG4, as well as control terminal group 2PGc, are arranged along one side of area 2R1 (with...). FIG. 6 The semiconductor chip 10 shown has one side (one of its four sides overlapping) arranged. Control terminal group 2PGc is arranged adjacent to data terminal groups 2PG2 and 2PG3. In other words, control terminal group 2PGc is located between data terminal groups 2PG2 and 2PG3. Multiple terminals 2PDc include clock terminals for transmitting clock signals, address terminals for transmitting address signals, etc. The number of control terminals 2PDc is greater than the number of data terminals 2PDd included in each data terminal group 2PG1-2PG4.

[0076] FIG. 5 The enlarged view shown is FIG. 7 An enlarged plan view of part A in the diagram and corresponding to the part connected to... FIG. 6 The terminal layout of terminal 2PD of the data communication circuit DCC1 in the diagram. Although not shown in the enlarged view, it is similar to... FIG. 5 The same number of data terminals 2PDd and control terminals 2PDc are arranged in the same manner as the data terminals and control terminals. FIG. 8 The area shown is adjacent to part A and connected to it. FIG. 4 The data communication circuit DCC2 shown is illustrated.

[0077] FIG. 9is a plan view showing an example of a layout of the second wiring layer in the wiring substrate shown in FIG. 8 FIG. 6 is a plan view showing an example of a layout of the wiring layer included in FIG. 10 FIG. 4 is an enlarged plan view of a portion of the portion A of FIG. 11 FIG. 10 is a plan view showing an example of a layout of the third wiring layer in the wiring substrate shown in FIG. 12 FIG. 4 is an enlarged plan view at the portion A of FIG. 13 FIG. 12 is a plan view showing an example of a layout of the fourth wiring layer in the wiring substrate shown in FIG. 6 FIG. 14 is an enlarged plan view of a portion of the wiring layer included in FIG. 4 FIG. 15 is a plan view showing an example of a layout of the fifth wiring layer in the wiring substrate shown in FIG. 14 FIG. 6 is an enlarged plan view of a portion of the wiring layer included in FIG. 9 FIG. 13 is an enlarged plan view of a portion of the portion A of FIG. 9 and FIG. 13 show an enlarged plan view of a portion that overlaps with each other. In FIG. 9 and FIG. 8 , in order to distinguish the signal wiring from the ground wiring 2wg, the data wiring 2wd and the control wiring 2wc (only in FIG. 12 ) are indicated by solid lines, and the ground wiring 2wg is indicated by a dashed line.

[0078] As shown in FIG. 9 and FIG. 13 , the wiring substrate 20 has a plurality of data wirings 2wd arranged so as to span the boundary between the region 2R1 and the region 2R2, i.e., the boundary 2BL shown in FIG. 7 and FIG. 5 . Each of the plurality of data wirings 2wd is electrically connected with the plurality of data terminals 2PDd shown in FIG. 8 and transmits any one of the first to eighth byte data signals SGD1-SGD8 shown in FIG. 5 . Each of the plurality of data lines 2wd extends toward the same one of the four edges 20s of the wiring substrate 20. In the example shown in FIG. 8 , the wirings 2w extending toward one edge 20s other than the one edge 20s toward which the plurality of data wirings 2wd extend constitute a signal transmission path for transmitting signals to FIG. 12 ​​​​​​​​​Another device other than the memory devices MD1 and MD2 shown in FIG. 1 and a signal is transmitted from the other device. For this reason, in the region 2R2 of the wiring substrate 20, the region which can be confirmed as the arrangement space of the plurality of data wirings 2wd is limited.

[0079] Therefore, in the present embodiment, by arranging the data wirings 2wd in each of the wiring layers WL2 and FIG. 8 FIG. 12 the wiring layer WL4 shown in FIG. 1, the arrangement space of the data wirings 2wd is secured. As shown in FIG. 12 FIG. 9 each of the plurality of data wirings 2wd is arranged so as to cross the boundary between the region 2R1 and the region 2R2. In other words, the plurality of data wirings 2wd arranged in the wiring layer WL4 shown in FIG. 7 FIG. 7 the wiring layer WL4 are connected to the wiring layer WL4 via the data via wirings 2vd arranged in the region 2R1 of the wiring layers WL2, WL3, and are pushed from the region 2R1 in the wiring layer WL4 to the region 2R2. As shown in FIG. 7 FIG. 7 FIG. 1 FIG. 9

[0080] Incidentally, considering only the effective wiring layout of the plurality of data wirings 2wd and the plurality of control wirings 2wc, it is conceivable that, in the wiring layers WL2 and WL4, the data wirings 2wd or the control wirings 2wc adjacent to each other are alternately led out from the region 2R1 to the region 2R4.

[0081] However, as shown in FIG. 1, in the data signal transmission path DCP for transmitting the data signal SGD between the semiconductor chip 10 and each of the memory device devices MD1 and MD2, it is preferable to equalize the characteristics of the plurality of signal transmission paths belonging to the same byte. The characteristics include the characteristic impedance of the signal transmission path, the maximum value of crosstalk, and the like. Therefore, in the wiring substrate 20, from the viewpoint of equalizing the characteristics of the plurality of signal transmission paths belonging to the same byte, the plurality of wirings 2wd for transmitting the signals of the same byte are led out by the same wiring layer. FIG. 13

[0082] That is, the plurality of data wirings 2wd1 are arranged in the wiring layer WL2 shown in FIG. 5 ​​​​​​​​In the wiring layer WL2 shown, multiple data routes 2wd2 are arranged in... FIG. 5 In the wiring layer WL4 shown. Therefore, the first byte data signal SGD1 (refer to) is transmitted. FIG. 7 Multiple data wirings 2wd1, and the transmission of the second byte data signal SGD2 (see...) FIG. 5 Multiple data traces 2wd2 are routed from zone 2R1 in the same wiring layer WL2 or WL4 to zone 2R2, respectively. Therefore, the characteristics of the signal transmission paths can be made equal on a byte-by-byte basis. Furthermore, since the data terminal groups 2PG1 and 2PG2 (see [link to data]) are connected to each other and arranged adjacently, [the signal transmission path characteristics can be made equal on a byte-by-byte basis]. FIG. 9 The data cablings 2wd1 and 2wd2 are arranged in different cabling layers WL2 or WL4, therefore FIG. 13 The signal transmission paths of the first byte data signal SGD1 and the second byte data signal SGD2 shown can reduce the parallel operation distance. Therefore, crosstalk noise caused by the parallel operation of data wiring 2wd can be reduced.

[0083] As by FIG. 9 and FIG. 13 A comparison reveals that, in the plan view, multiple data routing 2wd1 (see...) FIG. 9 ) and multiple data cabling 2wd2 (see FIG. 5 Overlapping. By arranging cabling in different wiring layers (WL2) or different wiring layers (WL4) in an overlapping manner, the cabling arrangement space can be increased. For example, as... FIG. 5 As shown, a large number of vias 2v are arranged in area 2R1 of wiring layer WL2. The multiple vias 2v include data vias 2wd electrically connected to data vias 2d, control vias 2vc electrically connected to control vias 2wc, and vias supplied with power potential VD (see reference). FIG. 7 The power via is 2VV and has a ground potential of VG (see [reference]). FIG. 13 The grounding via wiring 2vg, and the connection to the core power terminal 2PDv2 (see...) FIG. 13 The core power via 2V2 is for electrical connection. Data via 2VD includes: data via 2VD1 connected to data via 2WD1, and data via 2WD2 connected to data via 2WD2 (see reference). FIG. 13 Data via 2vd2, data via 2vd3 connected to data via 2wd3, and data via 2wd4 connected to data via 2wd4 (see...) FIG. 9 Data via routing 2VD4. On the other hand, such as... FIG. 9 As shown, the plurality of vias 2v arranged in area 2R1 of wiring layer WL4 do not include FIG. 13The plurality of data via wirings 2vd1 and 2vd3 and the plurality of control via wirings 2vc shown in FIG. 10 and FIG. 5 As can be seen by comparing

[0084] As can be seen by comparing FIG. 11 and 11 As shown in FIG. 9 and FIG. 13 , a majority of the wiring layer WL3 is covered with a ground pattern 2PLg to which a ground potential VG is supplied (see FIG. 9 ). The ground pattern 2PLg is arranged at least in the region 2R2. FIG. 9 The ground pattern 2PLg shown in

[0085] As shown in FIG. 9 and 13 , a ground line 2wg is arranged between adjacent data lines 2wd in the region 2R2. Thus, crosstalk noise between adjacent data wirings 2wd can be reduced. In the example shown in FIG. 13 and 13 , two data wirings 2wd are adjacent to each other due to a space limitation, and one ground wiring 2wg is arranged on both sides of the two data wirings 2wd. However, from the viewpoint of reducing crosstalk noise, it is more preferable to arrange one data line 2wd and one ground line 2wg alternately.

[0086] Similarly, a plurality of data wirings 2wd3 are arranged in the wiring layer WL2 shown in FIG. 5 , and a plurality of data wirings 2wd4 are arranged in the wiring layer WL4 shown in FIG. 5 . Thus, since the plurality of data wirings 2wd3 transmitting a third byte data signal SGD3 (see FIG. 9 ) and the plurality of data wirings 2wd4 transmitting a fourth byte data signal SGD4 (see FIG. 13 ) are respectively led from the region 2R1 to the region 2R2 in the same wiring layer, the characteristics of the signal transmission paths can be equalized at the byte terminals.

[0087] As can be seen by comparing FIG. 10 and FIG. 11 , in a plan view, the plurality of data wirings 2wd3 and the plurality of data wirings 2wd4 overlap each other. As shown in FIG. 9 and11 As shown, the grounding pattern 2PLg is arranged in areas 2R1 and 2R2. FIG. 13 The grounding pattern 2PLg shown is inserted in FIG. 5 The multiple data wirings 2wd3 shown are FIG. 8 The multiple data routes 2wd3 and 2wd4 shown are thus included. Therefore, even when data routes 2wd3 and 2wd4 overlap, crosstalk noise between data routes 2wd3 and 2wd4 can be suppressed.

[0088] Connected to FIG. 5 The signal transmission path of the data communication circuit DCC2 shown is the same as the signal transmission path described above. For example... FIG. 5 As shown, the fifth byte data signal SGD5 is transmitted (refer to...). FIG. 12 Multiple data wiring 2wd5 and transmission of the seventh byte data signal SGD7 (see) FIG. 5 Each data route in the multiple data routes 2wd7 is routed from zone 2R1 to zone 2R2 in the routing layer WL2. For example... FIG. 5 As shown, the sixth byte data signal SGD6 is transmitted (see...). FIG. 5 Multiple data wirings 2wd6 and the transmission of the eighth byte data signal SGD8 (see) FIG. 8 Each data route in the multiple data routes 2wd8 is led from zone 2R1 to zone 2R2 in the routing layer WL4. Therefore, when connected to... FIG. 8 The signal transmission path of the data communication circuit DCC2 shown can unify the characteristics of the signal transmission path byte by byte and ensure the layout space of the wiring.

[0089] like FIG. 12 and 9 As shown, each of the multiple control routes 2wc is arranged between multiple data routes 2wd1 and multiple data routes 2wd3 in the wiring layer WL2. FIG. 4 As shown, each of the other multiple control routes 2wc is arranged between multiple data routes 2wd5 and multiple data routes 2wd7 in the wiring layer WL2. As a modified example of this embodiment, some or all of the multiple control routes 2wc can be arranged in... FIG. 8 The wiring layer WL4 shown is used. However, to improve the flexibility of wiring layout in the wiring substrate 20, it is preferable that a large number of signal wirings (data wirings 2wd and control wirings 2wc) arranged with narrow pitch are led from region 2R1 in the wiring layer located as high as possible to region 2R2 (in other words, the wiring layer is located closer to...). FIG. 8The semiconductor chip shown is located at point 10. When all the multiple control wirings 2wc are as shown in this embodiment from FIG. 12 When area 2R1 in the wiring layer WL2 shown is led out to area 2R2, control wiring 2wc (see...) FIG. 12 It does not need to be placed in FIG. 12 In the wiring layer WL4 shown. Therefore, as FIG. 10 As shown, margin spaces are generated between data routing 2wd2 and data routing 2wd4 and between data routing 2wd6 and data routing 2wd8, respectively, and grounding pattern 2GP4 can be arranged in the margin spaces.

[0090] exist FIG. 13 In this example, multiple grounding patterns 2GP4 are separated from each other. However, as a modified example, a large-area grounding pattern 2PLg (see, for example, [reference needed]) is used. FIG. 12 ) can be formed in the following areas: where no other routing 2w or via routing 2v is formed in routing layer WL4 (see FIG. 12 In this example, FIG. 14 The multiple grounding patterns 2GP4 shown are integrally formed with the grounding pattern 2PLg.

[0091] Next, we will describe FIG. 7 The grounding pattern 2GP4 shown is FIG. 14 The power supply pattern 2VP is shown. The wiring substrate 20 has electrical connections to multiple power supply terminals 2PDv (see...). FIG. 7 Multiple power supply patterns 2VP (reference) FIG. 7 ) and electrically connected to multiple ground terminals 2PDg (see FIG. 12 Multiple grounding patterns 2GP are arranged in wiring layer WL5. Multiple power patterns 2VP are arranged in wiring layer WL5, including power pattern 2VP5, which extends to span regions 2R1 and 2R2. Power pattern 2VP5 is located in region 2R1 and... FIG. 14 Each of the multiple power terminals 2PDv shown overlaps. FIG. 7 The multiple grounding patterns 2GP shown are arranged in the wiring layer WL4, and include a grounding pattern 2GP4 extending across regions 2R1 and 2R2. In regions 2R1 and 2R2, the grounding pattern 2GP4 is connected to... FIG. 5 The power pattern 2VP5 shown overlaps and extends in the direction of extension of the power pattern 2VP.

[0092] like FIG. 12 As shown, each of the plurality of data terminals 2PDd is arranged along one side of the outer edge of region 2R1. Therefore, for... FIG. 14The power supply terminals 2PDv, which are supplied with the data communication circuits DCC1 and DCC2 shown in FIG. 6 with the power supply potential VD, are also arranged along the same side as the data terminals 2PDd. Here, in order to stably supply the power supply potential VD in the supply path of the power supply potential VD, it is preferable that a large-area power supply pattern 2VP be formed at a position close to the data communication circuits DCC1 and DCC2. By increasing the area of the power supply pattern 2VP5 and increasing the number of paths for supplying the power supply potential VD to the power supply pattern 2VP5, the impedance of the power supply path can be reduced, mainly the inductance.

[0093] In order to reduce the impedance of the power supply path, it is preferable that a ground pattern 2GP4, which is supplied with the ground potential VG, be provided at a position facing the power supply pattern 2VP5.

[0094] In the present embodiment, as described with reference to FIG. 12 , a margin space is generated between the data wiring 2wd2 and the data wiring 2wd4, and between the data wiring 2wd5 and the data wiring 2wd8, respectively, and the ground pattern 2GP4 can be arranged in the margin space. Then, as shown in FIG. 12 , by arranging the power supply pattern 2VP, which extends along the ground pattern 2GP4, at a position overlapping the ground pattern 2GP4 (see FIG. 14 ), the area of the power supply pattern 2VP5 is increased, and by arranging the ground pattern 2GP4 and the power supply pattern 2VP5 at positions facing each other, the impedance of the power supply pattern 2VP5 can be greatly reduced.

[0095] However, in the present embodiment, the plurality of data wirings 2wd2 and the plurality of data wirings 2wd4 formed in the wiring layer WL4 shown in FIG. 12 do not overlap the power supply pattern 2VP shown in FIG. 14 . Similarly, the plurality of data wirings 2wd6 and the plurality of data wirings 2wd8 formed in the wiring layer WL4 shown in FIG. 15 do not overlap the power supply pattern 2VP5 shown in FIG. 14 .

[0096] A plurality of ground patterns 2GP are arranged in the wiring layer WL5 shown in FIG. 12 , and include the ground pattern 2GP5, which is arranged to be adjacent to the power supply pattern 2VP5 in the region 2R2. As shown in FIG. 14 , in the present embodiment, the ground pattern 2GP5 also functions as the ground pattern 2PLg, which is formed to cover a large portion of the region 2R2. In the region 2R2, the ground pattern 2GP5 is arranged to be adjacent to the power supply pattern 2VP5. FIG. 15Each of the multiple data routes 2wd2 and multiple data routes 2wd4 in the wiring layer WL4 shown overlaps with the ground pattern 2GP5 formed in the wiring layer WL5, see [link to documentation]. FIG. 12 and 15 In this example, because in FIG. 14 Electromagnetic waves scattered around the power supply pattern 2VP5 or FIG. 9 The electromagnetic waves scattered around each data trace in data traces 2wd2 and 2wd4 shown can be FIG. 9 The grounding pattern 2GP5 shown is shielded, so crosstalk noise between data cabling 2wd4 can be reduced.

[0097] As described above, in this embodiment, multiple control wirings 2wc (refer to...) FIG. 12 ) was arranged in FIG. 14 The wiring layer WL2 shown provides a way to enable wiring in the wiring layer WL4 (see...) FIG. 14 The space for the grounding pattern 2GP4 is arranged in zone 2R1 and zone 2R2. Therefore, in zone 2R1 and zone 2R2, the wiring layer WL5 (see...) is formed. FIG. 13 The power supply pattern 2VP5 in (refer to) FIG. 4 It overlaps with each of the multiple control lines 2wc formed in the wiring layer WL2 and extends in the extension direction of the multiple control lines 2wc.

[0098] Furthermore, when a large number of control wirings 2wc are arranged in wiring layer WL2, the spacing between the wirings 2w in region 2R2 of wiring layer WL2 needs to be narrowed. Therefore, a portion of the multiple control wirings 2wc and... FIG. 15 The portion of the multiple data routes 2wd2 or multiple data routes 2wd4 shown in zone 2R2 overlaps.

[0099] As described above, in this embodiment, the insulating layer 2CR, which serves as the core insulating layer, is disposed... FIG. 5 As shown, wiring layers WL5 and WL6 are positioned such that WL5 is disposed on the upper surface 2Ct of the insulating layer 2CR, and WL6 is disposed on the lower surface. Wiring layers WL5 and WL6 are electrically connected via a plurality of through-holes 2TW penetrating the insulating layer 2CR. FIG. 4 As shown, the plurality of via wirings 2TW includes a plurality of power via wirings 2TWv electrically connected to the power pattern 2VP5.

[0100] Considering the power supply potential VD (see...) FIG. 4). It is preferable that the number of power supply vias 2TWv be large. By increasing the number of power supply vias 2TWv, the impedance of the supply path of the power supply potential VD can be reduced (mainly, the inductance). In this case, the characteristics of the power supply path can be improved. In the present embodiment, the power supply pattern 2VP5 is extended to span each of the regions 2R1 and 2R2. Therefore, a plurality of power supply vias 2TWv connected to the power supply pattern 2VP5 are formed in the regions 2R1 and 2R2, respectively. In other words, according to the present embodiment, the power supply potential VD can be supplied from the region 2R2 around the semiconductor chip 10 (see FIG. 16 ) in addition to the region 2R1 overlapping the semiconductor chip 10 (see FIG. 16 ), so that the impedance of the power supply path can be reduced and the power supply characteristics can be improved.

[0101] In order to reduce the impedance of the path for supplying the power supply potential to the plurality of power supply vias 2TWv, it is preferable that the power supply external terminals 30v for the power supply be arranged in the regions 2R1 and 2R2, respectively, as shown in FIG. 2 . FIG. 16 is a plan view showing a configuration example of the seventh wiring layer and the ninth wiring layer of the wiring substrate shown in FIG. 4 .

[0102] As shown in FIG. 4 , in the wiring substrate 20, a plurality of external terminals 30 are connected to the lower surface 20b on which the semiconductor chip 10 (see FIG. 16 ) is mounted (see FIG. 14 ). The plurality of external terminals 30 include a plurality of power supply external terminals 30v electrically connected to the power supply pattern 2VP5. The plurality of power supply external terminals 30v are connected to the regions 2R1 and 2R2, respectively. In this way, by providing each of the regions 2R1 and 2R2 with the arrangement of the external terminals 30 on the lower surface 20b of the wiring substrate 20, the impedance of the power supply path can be reduced and the power supply characteristics can be improved.

[0103] In order to reduce the impedance of the power supply path from the power supply external terminals 30v shown in FIG. 4 to the power supply pattern 2VP5 shown in FIG. 17 , it is preferable that any one of the wiring layers WL6, WL7, WL8, and WL9 shown in FIG. 17 form the large-area power supply pattern 2VP shown in FIG. 4 . FIG. 14 is a plan view showing a configuration example of the seventh wiring layer and the ninth wiring layer of the wiring substrate shown in FIG. 1 . For example, in the wiring layer WL7 and the wiring layer WL9, the large-area power supply patterns 2VP7 and 2VP9 are formed at positions overlapping the power supply pattern 2VP5 shown in FIG. 16 .

[0104] As described with reference to FIG. 8 , the semiconductor device PKG1 of the present embodiment is a device for communicating data signals with the memory devices MD1 and MD2 as external devices. Therefore, FIG. 12 The plurality of external terminals shown in FIG. 8 are provided with external terminals 30 for transmitting data signals. More specifically, the plurality of external terminals 30 include a plurality of data external terminals 30d1 electrically connected to the plurality of data wirings 2wd1 (refer to FIG. 12 ), a plurality of data external terminals 30d2 electrically connected to the plurality of data wirings 2wd2 (refer to FIG. 8 ), a plurality of data external terminals 30d3 electrically connected to the plurality of data wirings 2wd3 (refer to FIG. 12 ), and a plurality of data external terminals 30d4 electrically connected to the plurality of data wirings 2wd4 (refer to FIG. 8 ). The plurality of external terminals 30 include a plurality of data external terminals 30d5 electrically connected to the plurality of data wirings 2wd5 (refer to FIG. 12 ), a plurality of data external terminals 30d6 electrically connected to the plurality of data wirings 2wd6 (refer to FIG. 18 ), a plurality of data external terminals 30d7 electrically connected to the plurality of data wirings 2wd7 (refer to FIG. 1 ), and a plurality of data external terminals 30d8 electrically connected to the plurality of data wirings 2wd8 (refer to

[0105] Several modification examples have been described in the above embodiment, but in the following, typical modification examples other than the modification examples described in the above embodiment will be described.

[0106] <First Modification Example>

[0107] FIG. 19 is a explanatory diagram schematically showing a modification example of the data communication system shown in FIG. 18 . FIG. 20 is a plan view seen from the mounting surface side of the semiconductor device shown in FIG. 19 on which the semiconductor chip is mounted. FIG. 20 is a plan view showing an example of the layout of the second wiring layer in the wiring substrate shown in FIG. 19 . In FIG. 18 , a region overlapping the memory devices MD1 and MD2 shown in FIG. 1 is indicated by a double-dot chain line.

[0108] FIG. 19 the semiconductor device PKG2 shown in FIG. 20The semiconductor device PKG1 shown in FIG. 1A is different from the semiconductor device PKG2 shown in FIG. 2A in that the memory devices MD1 and MD2 are incorporated in the semiconductor device PKG2. Each of the memory devices (memory components) MD1 and MD2 has a memory circuit MDC for transmitting a data signal SGD to and from the data communication circuit DCC. As shown in FIG. 1A, the memory device MD1 is mounted on the upper surface 20t of the wiring substrate 20A. As shown in FIG. 1A, the memory device MD2 is mounted on the upper surface 20t of the wiring substrate 20A. FIG. 4 As shown in FIG. 2A, each of the memory devices (memory components) MD1 and MD2 is mounted on the upper surface 20t of the wiring substrate 20A.

[0109] In the case of the semiconductor device PKG2, since the memory devices MD1 and MD2 are mounted on the upper surface 20t of the wiring substrate 20A, as shown in FIG. 2A, the plurality of data wirings 2wd1 and 2wd3 and the control wiring 2wc in the wiring layer WL2 are led to a region overlapping with the memory device MD1. In other words, in a plan view, in the wiring layer WL2, a portion of each of the plurality of data wirings 2wd1 and 2wd3 and the control wiring 2wc overlaps with the memory device MD1. Thus, each of the plurality of data wirings 2wd1, the plurality of data wirings 2wd3, and the plurality of control wirings 2wc does not pass through the memory device MD1. In other words, in the wiring layer WL2, the plurality of data wirings 2wd1 and 2wd3 and the control wiring 2wc are led to a region overlapping with the memory device MD1. FIG. 18 FIG. 4 In the case of each of the wiring layer WL3, the wiring layer WL4, and the wiring layer WL5 shown in FIG. 2A, each of the plurality of data wirings 2wd1 and 2wd3 and the control wiring 2wc is coupled with the memory circuit MDC (see FIG. 2B). FIG. 18

[0110] Similarly, in the wiring layer WL2, each of the plurality of data wirings 2wd5 and 2wd7 and the other control wiring 2wc is led to a region where the plurality of data wirings 2wd5 and 2wd7 and the other control wiring 2wc overlap with the memory device MD2. In other words, in a plan view, in the wiring layer WL2, a portion of each of the plurality of data wirings 2wd5 and 2wd7 and the other control wiring 2wc overlaps with the memory device MD2. Thus, each of the plurality of data wirings 2wd5, the plurality of data wirings 2wd7, and the plurality of other control wirings 2wc does not pass through the memory device MD2. In other words, in the wiring layer WL2, the plurality of data wirings 2wd5 and 2wd7 and the other control wiring 2wc are led to a region overlapping with the memory device MD2. FIG. 18 FIG. 1 In the case of each of the wiring layer WL3, the wiring layer WL4, and the wiring layer WL5 shown in FIG. 2A, each of the plurality of data wirings 2wd5 and 2wd7 and the other control wiring 2wc is coupled with the memory circuit MDC (see FIG. 2B).

[0111] Except for the differences described above, FIG. 21 and 19 The semiconductor device PKG2 shown in FIG. 2A is identical to the semiconductor device PKG1 shown in FIG. 1A except for the differences described above. Thus, the description of the overlapping parts is omitted. FIG. 4

[0112] <Second Modification Example> ​​​​

[0113] FIG. 21 is a cross-sectional view showing a modification example of FIG. 4 FIG. 4 The semiconductor device PKG3 shown in FIG. 4 is different from the wiring substrate 20 shown in FIG. 16 has a plurality of through-wiring 20TW shown in FIG. 14 The wiring substrate 20B has a six-layer configuration. In this example, the wiring layer WL6 of the wiring substrate 20B performs the same function as the wiring layer WL10 of the wiring substrate 20 shown in FIG. 16 In the wiring substrate 20B, the layout of the plurality of external terminals 30 is the same as that of the wiring substrate 20 shown in FIG. 21 . That is, the plurality of external terminals 30 includes a plurality of power external terminals 30v electrically connected to the power pattern 2VP5 (see FIG. 4 ). The plurality of power external terminals 30v are respectively connected to the regions 2R1 and 2R2. Therefore, the impedance of the power path can be reduced, and the power characteristics can be improved.

[0114] In addition to the above-described differences, ​ the semiconductor device PKG3 shown in ​ is the same as the semiconductor device PKG1 shown in

[0115] <Third Modification Example>

[0116] In addition, for example, although various types of modification examples have been described as described above, the above-described modification examples can be combined.

[0117] Although the present application proposed by the present inventors has been specifically described based on the embodiments, the present application is not limited to the above embodiments, and it is self-evident that various modifications can be made without departing from the gist thereof.​

Claims

1. A semiconductor device comprising: a semiconductor chip having a data communication circuit that transmits a data signal; and a wiring substrate having: a first region that overlaps the semiconductor chip, and a second region that surrounds the first region in a plan view, wherein the semiconductor chip has a plurality of data electrodes each coupled to the data communication circuit and each transmitting the data signal, wherein the wiring substrate includes: a first wiring layer, a second wiring layer located in a layer lower than the first wiring layer, a third wiring layer located in a layer lower than the second wiring layer, a plurality of data terminals arranged at positions in the first region facing the plurality of data electrodes of the semiconductor chip and respectively electrically connected to the plurality of data electrodes, and a plurality of data wirings arranged so as to straddle a boundary between the first region and the second region and respectively electrically connected to the plurality of data terminals, wherein the plurality of data terminals includes: a plurality of first data terminals each transmitting a first byte data signal, and a plurality of second data terminals each transmitting a second byte data signal, wherein the plurality of data wirings includes: a plurality of first data wirings respectively electrically connected to the plurality of first data terminals, and a plurality of second data wirings respectively electrically connected to the plurality of second data terminals, wherein, in a plan view, a first data terminal group in which the plurality of first data terminals are arranged adjacent to each other and a second data terminal group in which the plurality of second data terminals are arranged adjacent to each other are arranged adjacent to each other, wherein, in the first wiring layer, each of the plurality of first data wirings is arranged so as to straddle the boundary between the first region and the second region, wherein, in the third wiring layer, each of the plurality of second data wirings is arranged so as to straddle the boundary between the first region and the second region, wherein, in a plan view, the plurality of first data wirings and the plurality of second data wirings overlap each other, and wherein, in the second wiring layer, a first ground pattern to which a ground potential is supplied is arranged at a position overlapping each of the plurality of first data wirings and the plurality of second data wirings.

2. The semiconductor device according to claim 1, wherein the plurality of data terminals includes: a plurality of third data terminals each transmitting a third byte data signal, and a plurality of fourth data terminals each transmitting a fourth byte data signal, wherein the plurality of data wirings includes: a plurality of third data wirings respectively electrically connected to the plurality of third data terminals, and a plurality of fourth data wirings respectively electrically connected to the plurality of fourth data terminals, wherein, in a plan view, a first data terminal group in which the plurality of first data terminals are arranged adjacent to each other and a second data terminal group in which the plurality of second data terminals are arranged adjacent to each other are arranged adjacent to each other, wherein, in a plan view, a third data terminal group and a fourth data terminal group are arranged adjacent to each other, in the third data terminal group, the plurality of third data terminals are arranged adjacent to each other, in the fourth data terminal group, the plurality of fourth data terminals are arranged adjacent to each other, wherein, in the first wiring layer, each of the plurality of third data wirings is arranged so as to cross the boundary between the first region and the second region, wherein, in the third wiring layer, each of the plurality of fourth data wirings is arranged so as to cross the boundary between the first region and the second region, wherein, in a plan view, the plurality of third data wirings and the plurality of fourth data wirings overlap each other, and wherein, in the second wiring layer, the first ground pattern is arranged at a position overlapping each of the plurality of third data wirings and the plurality of fourth data wirings.

3. The semiconductor device according to claim 2, wherein the semiconductor chip includes: a plurality of power supply electrodes each supplying a power supply potential to the data communication circuit, and a plurality of ground electrodes each supplying the ground potential to the data communication circuit, wherein the wiring substrate includes: a plurality of power supply terminals arranged in the first region at positions facing the plurality of power supply electrodes of the semiconductor chip and electrically connected to the plurality of power supply electrodes, respectively, a plurality of ground terminals arranged in the first region at positions facing the plurality of ground electrodes of the semiconductor chip and electrically connected to the plurality of ground electrodes, respectively, a plurality of power supply patterns electrically connected to the plurality of power supply terminals, respectively, a plurality of ground patterns electrically connected to the plurality of ground terminals, respectively, and a fourth wiring layer in a layer lower than the third wiring layer, wherein, in the first region, each of the plurality of data terminals is arranged at a position more outward than the plurality of power supply terminals, wherein the plurality of power supply patterns have: a first power supply pattern arranged so as to cross the boundary between the first region and the second region in the fourth wiring layer, wherein, in the first region, the first power supply pattern overlaps the plurality of power supply terminals, wherein the plurality of ground patterns have: a second ground pattern arranged so as to cross the boundary between the first region and the second region in the third wiring layer, and wherein, in each of the first region and the second region, the second ground pattern overlaps the first power supply pattern and extends in an extension direction of the first power supply pattern.

4. The semiconductor device according to claim 3, wherein, in the second region, neither of the plurality of second data wirings arranged in the third wiring layer and the plurality of third data wirings arranged in the third wiring layer overlaps the first power supply pattern arranged in the fourth wiring layer.

5. The semiconductor device according to claim 4, wherein the plurality of ground patterns include: a third ground pattern arranged in the fourth wiring layer and arranged so as to be adjacent to the first power pattern in the second region, and wherein, in the second region, each of the data wirings arranged in the third wiring layer and the data wirings arranged in the fourth wiring layer overlaps the third ground pattern arranged in the fourth wiring layer.

6. The semiconductor device according to claim 3, wherein the semiconductor chip includes a plurality of control electrodes coupled with the data communication circuit, and each control electrode transmits a control signal, wherein the wiring substrate has: a plurality of control terminals arranged in the first region at positions facing the plurality of control electrodes of the semiconductor chip, and respectively electrically connected with the plurality of control electrodes, and a plurality of control wirings arranged so as to straddle the boundary between the first region and the second region, and respectively electrically connected with the plurality of control terminals, wherein in the first region, each of the plurality of control terminals is arranged at a position more outward than the plurality of power terminals, wherein, in a plan view, a control terminal group in which the plurality of control terminals are arranged adjacent to each other is arranged adjacent to each of the second data terminal group and the third data terminal group, and wherein the first data terminal group, the second data terminal group, the third data terminal group, the fourth data terminal group, and the control terminal group are arranged along one side of the first region.

7. The semiconductor device according to claim 6, wherein in the first wiring layer, each of the plurality of control wirings is arranged between the plurality of first data wirings and the fourth data wiring.

8. The semiconductor device according to claim 7, wherein, in each of the first region and the second region, the first power pattern arranged in the fourth wiring layer overlaps each of the plurality of control wirings arranged in the first wiring layer, and extends in an extending direction of each of the plurality of control wirings.

9. The semiconductor device according to claim 6, wherein, in the second region, a portion of the plurality of control wirings overlaps one of: a portion of the plurality of second data wirings, and a portion of the plurality of third data wirings.

10. The semiconductor device according to claim 3, wherein the wiring substrate includes: a core insulating layer having a surface in which the fourth wiring layer is formed, and a plurality of via wirings each penetrating the core insulating layer, wherein the plurality of via wirings includes a plurality of power via wirings each electrically connected with the first power pattern, and wherein the plurality of power via wirings includes: a first power via wiring formed in the first region, and a second power via wiring formed in the second region.

11. The semiconductor device according to claim 10, wherein a plurality of external terminals are connected on a surface of the wiring substrate opposite to a surface on which the semiconductor chip is mounted, wherein the plurality of external terminals include a plurality of power supply external terminals each electrically connected with the first power supply pattern, and wherein the plurality of power supply external terminals include: a first power supply external terminal connected in the first region, and a second power supply external terminal connected in the second region.

12. The semiconductor device according to claim 6, further comprising: a memory component having a memory circuit, the data signal being transmitted between the memory circuit and the data communication circuit, wherein the semiconductor chip and the memory component are mounted on a first surface of the wiring substrate, and wherein each of the plurality of first data wirings, the plurality of third data wirings, and the plurality of control wirings is coupled with the memory circuit without passing through each of the second wiring layer, the third wiring layer, and the fourth wiring layer.

13. The semiconductor device according to claim 3, wherein a plurality of external terminals are connected on a surface of the wiring substrate opposite to a surface on which the semiconductor chip is mounted, and wherein the plurality of external terminals include: a plurality of first external terminals each electrically connected with the plurality of first data wirings, a plurality of second external terminals each electrically connected with the plurality of second data wirings, a plurality of third external terminals each electrically connected with the plurality of third data wirings, and a plurality of fourth external terminals each electrically connected with the plurality of fourth data wirings.

14. The semiconductor device according to claim 3, wherein the wiring substrate includes a terminal formation layer in a layer higher than the first wiring layer, and the plurality of data terminals, the plurality of power supply terminals, and the plurality of ground terminals are formed in the terminal formation layer, and wherein the plurality of ground patterns include: a fourth ground pattern formed in the second region of the terminal formation layer, and overlapping each of the plurality of data wirings.

15. The semiconductor device according to claim 3, wherein the wiring substrate includes a terminal formation layer in a layer higher than the first wiring layer, and the plurality of data terminals, the plurality of power supply terminals, and the plurality of ground terminals are formed in the terminal formation layer, and wherein the plurality of ground patterns include: a fourth ground pattern formed in the second region of the terminal formation layer, and overlapping each of the plurality of data wirings.

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