Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a first active pattern on a substrate, a first gate electrode crossing the first active pattern, a pair of source / drain patterns in an upper portion of the first active pattern and respectively at opposite sides of the first gate electrode, a first gate cap pattern on the first gate electrode, an interlayer insulating layer on the source / drain patterns, a first active contact and a second active contact penetrating the interlayer insulating layer and respectively connected to the pair of source / drain patterns, and a first interconnection layer on the first active contact and the second active contact. The first interconnection layer can include a first insulating structure covering a top surface of the second active contact, and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate cap pattern between the first active contact and the second active contact.

Description

[0001] Korean Patent Application No. 10-2020-0026158 entitled "Semiconductor Device and Manufacturing Method Thereof" filed on March 2, 2020, with the Korean Intellectual Property Office, which is herein incorporated by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments relate to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0003] Semiconductor devices are important elements in the electronic industry due to their small size, multi-functionality, and / or low cost characteristics. Semiconductor devices can include memory devices for storing data, logic devices for processing data, and hybrid devices including both memory and logic elements. High reliability, high performance, and / or multiple functions can provide fast speed and / or low power consumption for electronic devices. As such, the complexity and / or integration density of semiconductor devices are increasing. SUMMARY

[0004] Embodiments relate to a semiconductor device including a first active pattern on a substrate, a first gate electrode crossing the first active pattern, a pair of source / drain patterns disposed in an upper portion of the first active pattern and disposed at opposite sides of the first gate electrode, respectively, a first gate cap pattern on the first gate electrode, an interlayer insulating layer on the pair of source / drain patterns, a first active contact and a second active contact penetrating the interlayer insulating layer and connected to the pair of source / drain patterns, respectively, and a first interconnection layer on the first active contact and the second active contact. The first interconnection layer can include a first insulating structure covering a top surface of the second active contact, and a first interconnection line covering a top surface of the first active contact and extending over the first insulating structure, and covering a top surface of the first gate cap pattern between the first active contact and the second active contact.

[0005] Embodiments also relate to a semiconductor device including: an active pattern on a substrate; a first gate electrode crossing the active pattern; a pair of source / drain patterns disposed in an upper portion of the active pattern and respectively disposed at opposite sides of the first gate electrode; a first gate cap pattern on the first gate electrode; an interlayer insulating layer on the pair of source / drain patterns; a first active contact and a second active contact penetrating the interlayer insulating layer and respectively connected to the pair of source / drain patterns, an upper portion of the first active contact protruding above a top surface of the first gate cap pattern; and a first interconnection layer on the first active contact and the second active contact, the first interconnection layer including: an insulating structure covering a top surface of the second active contact; and an interconnection line covering a top surface of the first active contact and extending over the insulating structure, and covering a side surface of the upper portion of the first active contact.

[0006] Embodiments also relate to a method of manufacturing a semiconductor device including: patterning a substrate to form an active pattern; forming a gate electrode crossing the active pattern; forming a pair of source / drain patterns in an upper portion of the active pattern, the pair of source / drain patterns respectively formed at opposite sides of the gate electrode; forming a gate cap pattern on the gate electrode; forming a first interlayer insulating layer on the pair of source / drain patterns; forming a first active contact and a second active contact penetrating the first interlayer insulating layer and respectively connected to the pair of source / drain patterns; forming an insulating structure covering a top surface of the second active contact; and forming an interconnection line on the first active contact, the gate cap pattern, and the insulating structure, the interconnection line in contact with a top surface of the first active contact and a top surface of the gate cap pattern. BRIEF DESCRIPTION OF DRAWINGS

[0007] Features will become apparent to those of ordinary skill in the art upon examination of the following details description of example embodiments in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is an equivalent circuit diagram illustrating an SRAM cell according to an example embodiment.

[0009] Figure 2 is a plan view illustrating a semiconductor device according to an example embodiment.

[0010] Figures 3A-3E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of Figure 2 , respectively.

[0011] Figure 4 is an enlarged cross-sectional view of a portion "M" of Figure 3B

[0012] Figure 5 , Figure 7 ​、 Figure 9 and Figure 11 are plan views showing a method of manufacturing a semiconductor device according to an example embodiment.

[0013] Figure 6A 、 Figure 8A 、 Figure 10A and Figure 12A are cross-sectional views taken along lines A-A' of Figure 5 、 Figure 7 、 Figure 9 and Figure 11 respectively.

[0014] Figure 6B 、 Figure 8B 、 Figure 10B and Figure 12B are cross-sectional views taken along lines B-B' of Figure 5 、 Figure 7 、 Figure 9 and Figure 11 respectively.

[0015] Figure 8C 、 Figure 10C and Figure 12C are cross-sectional views taken along lines C-C' of Figure 7 、 Figure 9 and Figure 11 respectively.

[0016] Figure 8D 、 Figure 10D and Figure 12D are cross-sectional views taken along lines D-D' of Figure 7 、 Figure 9 and Figure 11 respectively.

[0017] Figure 13A 、 Figure 13B and Figure 13C are cross-sectional views taken along lines B-B', lines C-C' and lines D-D' of Figure 2 to show a semiconductor memory device according to an example embodiment. DETAILED DESCRIPTION

[0018] Figure 1 is an equivalent circuit diagram showing an SRAM cell according to an example embodiment.

[0019] Reference is made to Figure 1According to example embodiments, an SRAM cell can include a first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first access transistor TA1, and a second access transistor TA2. The first pull-up transistor TU1 and the second pull-up transistor TU2 can be p-type metal-oxide-semiconductor (PMOS) transistors. The first pull-down transistor TD1 and the second pull-down transistor TD2, and the first access transistor TA1 and the second access transistor TA2 can be n-type metal-oxide-semiconductor (NMOS) transistors.

[0020] A first source / drain electrode of the first pull-up transistor TU1 (i.e., either the source or the drain of the first pull-up transistor TU1) and a first source / drain electrode of the first pull-down transistor TD1 can be connected to a first node N1. A second source / drain electrode of the first pull-up transistor TU1 (i.e., the other of the source and the drain of the first pull-up transistor TU1) can be connected to a power supply line VDD, and a second source / drain electrode of the first pull-down transistor TD1 can be connected to a ground line VSS. A gate electrode of the first pull-up transistor TU1 and a gate electrode of the first pull-down transistor TD1 can be electrically connected to each other. The first pull-up transistor TU1 and the first pull-down transistor TD1 can constitute a first inverter. The connected gate electrodes of the first pull-up transistor TU1 and the first pull-down transistor TD1 can correspond to an input terminal of the first inverter, and the first node N1 can correspond to an output terminal of the first inverter.

[0021] A first source / drain electrode of the second pull-up transistor TU2 and a first source / drain electrode of the second pull-down transistor TD2 can be connected to a second node N2. A second source / drain electrode of the second pull-up transistor TU2 can be connected to the power supply line VDD, and a second source / drain electrode of the second pull-down transistor TD2 can be connected to the ground line VSS. A gate electrode of the second pull-up transistor TU2 and a gate electrode of the second pull-down transistor TD2 can be electrically connected to each other. Thus, the second pull-up transistor TU2 and the second pull-down transistor TD2 can constitute a second inverter. The connected gate electrodes of the second pull-up transistor TU2 and the second pull-down transistor TD2 can correspond to an input terminal of the second inverter, and the second node N2 can correspond to an output terminal of the second inverter.

[0022] The first inverter and the second inverter can be combined with each other to form a latch structure. Thus, the gate electrode of the first pull-up transistor TU1 and the gate electrode of the first pull-down transistor TD1 can be electrically connected to the second node N2, and the gate electrode of the second pull-up transistor TU2 and the gate electrode of the second pull-down transistor TD2 can be electrically connected to the first node N1. The first source / drain electrode of the first access transistor TA1 can be connected to the first node N1, and the second source / drain electrode of the first access transistor TA1 can be connected to the first bit line BL1. The first source / drain electrode of the second access transistor TA2 can be connected to the second node N2, and the second source / drain electrode of the second access transistor TA2 can be connected to the second bit line BL2. The gate electrode of the first access transistor TA1 and the gate electrode of the second access transistor TA2 can be electrically combined to the word line WL. This structure is merely an example of the SRAM cell according to the example embodiment.

[0023] Figure 2 is a plan view showing a semiconductor device according to an example embodiment. Figures 3A-3E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of Figure 2 , respectively. Figure 4 is an enlarged cross-sectional view of a portion "M" of Figure 3B . For example, Figure 2 is a plan view showing an example of an SRAM cell configured to have the circuit structure shown in Figure 1 .

[0024] Referring to Figure 2 , a base 100 having at least one memory cell region MEC (e.g., an SRAM cell) can be provided. The base 100 can also have a peripheral region PER. The peripheral region PER can be a region on which transistors (e.g., constituting a processor core or an I / O terminal) are disposed. The transistors in the peripheral region PER can operate at a higher power than the transistors in the memory cell region MEC. Hereinafter, the memory cell region MEC will be described in more detail with reference to Figure 1 , Figure 2 , Figures 3A-3D , and Figure 4 .

[0025] A device isolation layer ST can be disposed on the base 100. The device isolation layer ST can define a first active pattern API and a second active pattern AP2. The base 100 can be a semiconductor base (e.g., of silicon, germanium, or silicon-germanium) or a compound semiconductor base. The device isolation layer ST can be formed of or include an insulating material (e.g., silicon oxide).

[0026] The first active pattern AP1 and the second active pattern AP2 can be portions of the substrate 100. Trenches TR can be defined between the first active pattern AP1 and the second active pattern AP2 adjacent to each other. The device isolation layer ST can fill the trenches TR. The first active pattern AP1 and the second active pattern AP2 can have upper portions protruding vertically above the device isolation layer ST. Each of the upper portions of the first active pattern AP1 and the second active pattern AP2 can be a fin structure protruding vertically above the device isolation layer ST. Thus, each of the first active pattern AP1 and the second active pattern AP2 can be an active fin.

[0027] The first channel pattern CH1 and the first source / drain pattern SD1 can be provided in the upper portion of each of the first active pattern AP1. The second channel pattern CH2 and the second source / drain pattern SD2 can be provided in the upper portion of each of the second active pattern AP2. The first source / drain pattern SD1 can be a p-type impurity region. The second source / drain pattern SD2 can be an n-type impurity region. Each of the first channel pattern CH1 can be interposed between a pair of the first source / drain pattern SD1, and each of the second channel pattern CH2 can be interposed between a pair of the second source / drain pattern SD2.

[0028] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. In an example embodiment, the first source / drain pattern SD1 and the second source / drain pattern SD2 can have top surfaces located at substantially the same level as a top surface of the first channel pattern CH1 and the second channel pattern CH2. In another example embodiment, a top surface of the first source / drain pattern SD1 and a top surface of the second source / drain pattern SD2 can be located at a level higher than a level of the top surface of the first channel pattern CH1 and the second channel pattern CH2.

[0029] The first source / drain pattern SD1 and the second source / drain pattern SD2 can include semiconductor elements that are the same as or different from the semiconductor elements of the substrate 100. In an example embodiment, the first source / drain pattern SD1 can be formed of or include a semiconductor material whose lattice constant is greater than the lattice constant of the substrate 100. In this case, the first source / drain pattern SD1 can exert compressive stress on the first channel pattern CH1. In an example embodiment, the first source / drain pattern SD1 can be formed of or include silicon germanium (SiGe). The second source / drain pattern SD2 can be formed of or include the same semiconductor material as the semiconductor material of the substrate 100. For example, the second source / drain pattern SD2 can be formed of or include silicon (Si).

[0030] The first to fourth gate electrodes GE1 to GE4 extending in the first direction D1 can be disposed to cross the first and second active patterns AP1 and AP2. When viewed in a plan view, the first to fourth gate electrodes GE1 to GE4 can be superposed on the first and second channel patterns CH1 and CH2. In an example embodiment, the first to fourth gate electrodes GE1 to GE4 can be formed of or include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) or a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0031] Referring to Figure 3C , the second and fourth gate electrodes GE2 and GE4 can be aligned side by side with each other in the first direction D1. An insulating pattern SP can be interposed between the second and fourth gate electrodes GE2 and GE4 to separate them from each other.

[0032] Similarly, as Figure 2 indicated, the first and third gate electrodes GE1 and GE3 can be aligned side by side with each other in the first direction D1. An insulating pattern SP can be interposed between the first and third gate electrodes GE1 and GE3 to separate them from each other.

[0033] Referring back to Figure 3CThe second gate electrode GE2 can be disposed on the first top surface TS1 of the first channel pattern CH1 and at least one first side surface SW1 of the first channel pattern CH1. The fourth gate electrode GE4 can be disposed on the second top surface TS2 of the second channel pattern CH2 and at least one second side surface SW2 of the second channel pattern CH2. Accordingly, the transistor according to the present embodiment can be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrodes are disposed to three-dimensionally surround the channel pattern.

[0034] As shown in, for example, FIG. 1A and described in further detail below, a pair of gate spacers GS can be disposed on opposite side surfaces of each of the first to fourth gate electrodes GE1 to GE4. The gate spacers GS can extend along the first to fourth gate electrodes GE1 to GE4 and in the first direction D1. A top surface of the gate spacers GS can be higher than top surfaces of the first to fourth gate electrodes GE1 to GE4. The top surface of the gate spacers GS can be coplanar with a top surface of a first interlayer insulating layer 110, which will be described below. The gate spacers GS can be formed of or include at least one of SiO2, SiCN, SiCON, and SiN. In an example embodiment, the gate spacers GS can include a multi-layer structure composed of at least two of SiO2, SiCN, SiCON, and SiN. Figure 3A The gate dielectric pattern GI can be disposed between the first to fourth gate electrodes GE1 to GE4 and the first and second active patterns AP1 and AP2. The gate dielectric pattern GI can extend along bottom surfaces of the first to fourth gate electrodes GE1 to GE4, respectively.

[0035] Referring to

[0036] , the gate dielectric pattern GI can cover the first top surface TS1 of the first channel pattern CH1 and at least one first side surface SW1 of the first channel pattern CH1. The gate dielectric pattern GI can cover the second top surface TS2 of the second channel pattern CH2 and at least one second side surface SW2 of the second channel pattern CH2. Figure 3C The gate dielectric pattern GI can be formed of or include at least one of a high-k dielectric material. For example, the high-k dielectric material can be formed of or include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0037] The gate dielectric pattern GI can be formed of or include at least one of a high-k dielectric material. For example, the high-k dielectric material can be formed of or include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0038] A gate cap pattern GP can be disposed on the first to fourth gate electrodes GE1 to GE4, respectively. The gate cap pattern GP can extend along the first to fourth gate electrodes GE1 to GE4 and in the first direction D1. The gate cap pattern GP can be disposed between a pair of gate spacers GS. The gate cap pattern GP can be formed of, or include, a material having etch selectivity with respect to the first and second interlayer insulating layers 110 and 120. For example, the gate cap pattern GP can be formed of, or include, at least one of SiON, SiCN, SiCON, and SiN.

[0039] The first interlayer insulating layer 110 can be disposed on the substrate 100. The first interlayer insulating layer 110 can cover the gate spacers GS (e.g., at side surfaces thereof) as well as the first and second source / drain patterns SD1 and SD2. A top surface of the first interlayer insulating layer 110 can be substantially coplanar with a top surface of the gate cap pattern GP and a top surface of the gate spacers GS.

[0040] The first to eighth active contacts AC1 to AC8 can be disposed. The first to eighth active contacts AC1 to AC8 can be disposed to penetrate the first interlayer insulating layer 110 and can be joined to the first and second source / drain patterns SD1 and SD2. As shown in, for example, Figure 3D The first to eighth active contacts AC1 to AC8 can have a top surface that is coplanar with a top surface of the first interlayer insulating layer 110.

[0041] Each of the first to eighth active contacts AC1 to AC8 can be a self-aligned contact. For example, the first to eighth active contacts AC1 to AC8 can be formed in a self-aligned manner by the gate cap pattern GP and the gate spacers GS. For example, the first to eighth active contacts AC1 to AC8 can cover at least a portion of side surfaces of the gate spacers GS.

[0042] A silicide pattern SC can be disposed between the first to eighth active contacts AC1 to AC8 and the first and second source / drain patterns SD1 and SD2. The first to eighth active contacts AC1 to AC8 can be electrically connected to the first and second source / drain patterns SD1 and SD2 through the silicide pattern SC. The silicide pattern SC can be formed of, or include, at least one of a metal silicide (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide).

[0043] The first gate contact GC1 can be disposed on the third gate electrode GE3, and the second gate contact GC2 can be disposed on the second gate electrode GE2. The first gate contact GC1 can be disposed to penetrate the first interlayer insulating layer 110, the gate spacer GS, and the gate cap pattern GP, and can be bonded to the third gate electrode GE3. The second gate contact GC2 can be disposed to penetrate the first interlayer insulating layer 110, the gate spacer GS, and the gate cap pattern GP, and can be bonded to the second gate electrode GE2.

[0044] The first gate contact GC1 and the second gate contact GC2 can have a top surface that is coplanar with a top surface of the first interlayer insulating layer 110. A bottom surface of each of the first gate contact GC1 and the second gate contact GC2 can be located at a level higher than a level of bottom surfaces of the first to eighth active contacts AC1 to AC8.

[0045] Referring to Figure 3A , the first gate contact GC1 and the second active contact AC2 can be connected to each other to constitute a single object (hereinafter, a contact structure UC). The third gate electrode GE3 can be directly connected to the first source / drain pattern SD1 located adjacent to the third gate electrode GE3 through the contact structure UC. The second gate contact GC2 and the fifth active contact AC5 can also be connected to each other to constitute a single contact structure.

[0046] Each of the first to eighth active contacts AC1 to AC8 and the first and second gate contacts GC1 and GC2 can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM can be formed of, or include, at least one metal among, for example, aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM can cover side surfaces and a bottom surface of the conductive pattern FM. The barrier pattern BM can include at least one of a metal layer and a metal nitride layer. The metal layer can be formed of, or include, at least one among titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer can be formed of, or include, at least one among titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0047] A second interlayer insulating layer 120 can be disposed on the first interlayer insulating layer 110. In an example embodiment, the first interlayer insulating layer 110 and the second interlayer insulating layer 120 can be formed of or include silicon oxide.

[0048] A first interconnection layer M1 can be disposed in the second interlayer insulating layer 120. The first interconnection layer M1 can include a first bit line BL1, a second bit line BL2, and a power supply line VDD. The first bit line BL1, the second bit line BL2, and the power supply line VDD can extend in the second direction D2 and be parallel to each other. A line width of the power supply line VDD can be greater than a line width of each of the first bit line BL1 and the second bit line BL2.

[0049] The first bit line BL1, the second bit line BL2, and the power supply line VDD of the first interconnection layer M1 can be directly disposed on the first to eighth active contacts AC1 to AC8 and the first and second gate contacts GC1 and GC2. The interconnection lines BL1, BL2, and VDD of the first interconnection layer M1 can have a bottom surface located at the same level as a bottom surface of the second interlayer insulating layer 120. The contacts AC1 to AC8, GC1, and GC2 can have a top surface located at the same level as a top surface of the first interlayer insulating layer 110. Accordingly, the interconnection lines BL1, BL2, and VDD of the first interconnection layer M1 can be in direct contact with the contacts AC1 to AC8, GC1, and GC2 disposed thereunder.

[0050] The first interconnection layer M1 can include insulating structures IP1 and IP2 disposed in a lower portion thereof. For example, a first insulating structure IP1 and a pair of second insulating structures IP2 can be disposed on one SRAM cell shown in FIG. 1B. Figure 2 In an example embodiment, one of the pair of second insulating structures IP2 can be disposed under the first bit line BL1, and the other of the pair of second insulating structures IP2 can be disposed under the second bit line BL2.

[0051] The first interconnection layer M1 can have a node open region NO and a node close region NC. The node open region NO can be a region in which the interconnection lines BL1, BL2, and VDD of the first interconnection layer M1 can be directly connected to the contacts AC1 to AC8, GC1, and GC2 thereunder. The node close region NC can be a region in which the interconnection lines BL1, BL2, and VDD of the first interconnection layer M1 cannot be connected to the contacts AC1 to AC8, GC1, and GC2 placed thereunder. The node close region NC can be a region in which the interconnection lines BL1, BL2, and VDD are disconnected from the contacts AC1 to AC8, GC1, and GC2 placed thereunder.

[0052] For example, each of the first insulating structure IP1 and the second insulating structure IP2 can be disposed in the node-closed region NC. Each of the first insulating structure IP1 and the second insulating structure IP2 can not overlap the node-open region NO. Accordingly, each of the first insulating structure IP1 and the second insulating structure IP2 can be separated (or offset) from the node-open region NO.

[0053] For example, referring to Figure 2 and Figure 3A , the first insulating structure IP1 can be disposed in the node-closed region NC of the first interconnection layer M1. The first insulating structure IP1 can directly cover the top surface of the contact structure UC, which is composed of the first gate contact GC1 and the second active contact AC2. Due to the first insulating structure IP1, the power line VDD can not be in contact with the top surface of the contact structure UC. Accordingly, due to the first insulating structure IP1, the power line VDD can be disconnected from the contact structure UC.

[0054] The first insulating structure IP1 can not be disposed in the node-open region NO of the first interconnection layer M1. Accordingly, the fourth active contact AC4 of the node-open region NO can be directly connected to the power line VDD disposed on the fourth active contact AC4. The power line VDD of the node-open region NO can be connected to the fourth active contact AC4 under the power line VDD.

[0055] As another example, referring to Figure 2 and Figure 3B , the second insulating structure IP2 can be disposed in the node-closed region NC of the first interconnection layer M1. The second insulating structure IP2 can directly cover the top surface of the fifth active contact AC5 and the top surface of the eighth active contact AC8. Due to the second insulating structure IP2, the second bit line BL2 can not be in contact with the top surface of the fifth active contact AC5 and the top surface of the eighth active contact AC8. Accordingly, the second bit line BL2 can be disconnected from the fifth active contact AC5 and the eighth active contact AC8 by the second insulating structure IP2.

[0056] The second insulating structure IP2 can not be disposed in the node-open region NO of the first interconnection layer M1. Accordingly, the seventh active contact AC7 of the node-open region NO can be directly connected to the second bit line BL2 disposed on the seventh active contact AC7. The second bit line BL2 of the node-open region NO can be connected to the seventh active contact AC7 under the second bit line BL2.

[0057] In the node-open region NO, the second bit line BL2 can be disposed to be in direct contact not only with the top surface of the seventh active contact AC7 but also with the top surface of the gate spacer GS and the top surface of the gate cap pattern GP.

[0058] As other examples, referring to Figure 2 and Figure 3C , the first insulating structure IP1 and the second insulating structure IP2 can be disposed in the node-closed region NC of the first interconnect layer M1. The first insulating structure IP1 can be disposed under the power supply line VDD, and the second insulating structure IP2 can be disposed under the first bit line BL1. Due to the first insulating structure IP1, the second gate contact GC2 under the power supply line VDD can not be connected to the power supply line VDD.

[0059] The second interlayer insulating layer 120 can have a first height H1. The first height H1 can be a distance between a bottom surface and a top surface of the second interlayer insulating layer 120. In the node-open region NO, the second bit line BL2 can have a same height (e.g., the first height H1) as a height of the second interlayer insulating layer 120. In the node-closed region NC, each of the first bit line BL1 and the power supply line VDD can have a second height H2. The second height H2 can be less than the first height H1. Due to the insulating structures IP1 and IP2, a height of the interconnect lines in the node-closed region NC can be reduced.

[0060] A ratio H2 / H1 of the second height H2 to the first height H1 can be in a range of 0.7 to 0.9. In an example embodiment, the ratio H2 / H1 of the second height H2 to the first height H1 can be in a range of 0.75 to 0.89. For example, the first height H1 can be about 30 nm, and the second height H2 can be about 25 nm.

[0061] As a comparative example, in a case where the first interconnect layer M1 further includes a via plug additionally disposed under the interconnect lines, the first height H1 can have an increased value. In this case, the ratio H2 / H1 of the second height H2 to the first height H1 can become less than 0.7. In contrast, according to an example embodiment, due to the omission of the via from the first interconnect layer M1, the ratio H2 / H1 of the second height H2 to the first height H1 can have a relatively large value.

[0062] Due to the reduction of the height of the interconnect lines in the node-closed region NC, a parasitic capacitance between adjacent ones of the interconnect lines can be reduced. For example, a capacitance between the first bit line BL1 and the power supply line VDD can be reduced as the height of each of the first bit line BL1 and the power supply line VDD is reduced. As a result, the insulating structures IP1 and IP2 can help to improve electrical characteristics of the first interconnect layer M1.

[0063] As other examples, referring to Figure 2 and Figure 3DThe second insulating structure IP2 can be disposed under the second bit line BL2 in the node-closed region NC of the first interconnection layer M1. Since the insulating structure is not disposed in the node-open region NO, the first bit line BL1 and the power supply line VDD can have a bottom surface located at the same level as a bottom surface of the second interlayer insulating layer 120. Due to the second insulating structure IP2, the eighth active contact AC8 under the second bit line BL2 can not be connected to the second bit line BL2.

[0064] In the node-open region NO, the third active contact AC3 under the first bit line BL1 can be directly connected to the first bit line BL1, and the sixth active contact AC6 under the power supply line VDD can be directly connected to the power supply line VDD. A portion of the bottom surface of the power supply line VDD can be in contact with a top surface of the sixth active contact AC6, and another portion of the bottom surface of the power supply line VDD can be in contact with a top surface of the first interlayer insulating layer 110.

[0065] Although not shown, at least one interconnection layer including a second interconnection layer can be disposed on the first interconnection layer M1. For example, the second interconnection layer can include a ground line VSS and a word line WL.

[0066] The first active pattern AP1 and the second active pattern AP2 and the first to fourth gate electrodes GE1 to GE4 described above can constitute a memory transistor. Figure 2 and Figures 3A-3D The memory transistor can include the first pull-up transistor TU1, the first pull-down transistor TD1, the second pull-up transistor TU2, the second pull-down transistor TD2, the first access transistor TA1, and the second access transistor TA2 previously described with reference to Figure 1

[0067] According to an example embodiment, the interconnection lines BL1, BL2, and VDD of the first interconnection layer M1 can be directly connected to the contacts AC1 to AC8, GC1, and GC2 thereunder, and thus, connection resistance between the interconnection lines BL1, BL2, and VDD and the contacts AC1 to AC8, GC1, and GC2 can be reduced. Thus, the interconnection lines BL1, BL2, and VDD of the first interconnection layer M1 can be directly connected to the contacts AC1 to AC8, GC1, and GC2 without any via plugs. The node-closed region NC can be defined by disposing the insulating structures IP1 and IP2 in the lower portion of the first interconnection layer M1. This can enable a simple implementation of a desired connection structure between the interconnection lines BL1, BL2, and VDD and the contacts AC1 to AC8, GC1, and GC2. In addition, this can enable an efficient reduction of parasitic capacitance between adjacent ones of the interconnection lines. Thus, according to an example embodiment, electrical characteristics of a semiconductor device can be improved.

[0068] ​In an example embodiment, referring to Figure 4 The interconnection lines BL1, BL2 and VDD of the first interconnection layer M1 can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM can be formed of or include at least one of a metal material (e.g., copper), and the barrier pattern BM can be formed of or include at least one of a metal nitride (e.g., tantalum nitride (TaN)).

[0069] In an example embodiment, the second insulating structure IP2 can include a plurality of stacked insulating layers. For example, the second insulating structure IP2 can include a first insulating layer IL1, a second insulating layer IL2, and a third insulating layer IL3. The first insulating layer IL1 and the third insulating layer IL3 can be formed of or include silicon oxide, and the second insulating layer IL2 can be formed of or include silicon nitride. In another example embodiment, the second insulating structure IP2 can have only a single insulating layer.

[0070] The second bit line BL2 can extend in the second direction D2 and can be in contact with the second insulating structure IP2, the gate cap pattern GP, the gate spacer GS, and the seventh active contact AC7. The barrier pattern BM of the second bit line BL2 can directly cover the top surface ACt of the seventh active contact AC7, the top surface GSt of the gate spacer GS, the top surface GPt of the gate cap pattern GP, the side surface IPs of the second insulating structure IP2, and the top surface IPt of the second insulating structure IP2.

[0071] In the node open region NO, the barrier pattern BM of the second bit line BL2 can be disposed to be in direct contact not only with the top surface ACt of the seventh active contact AC7 but also with the top surface GSt of the gate spacer GS and the top surface GPt of the gate cap pattern GP.

[0072] Hereinafter, the peripheral region PER will be described in more detail with reference to Figure 2 and Figure 3E The at least one peripheral active pattern PAP can be disposed on the substrate 100. The peripheral active pattern PAP can have a width greater than the widths of the first active pattern AP1 and the second active pattern AP2 of the memory cell region MEC.

[0073] A pair of peripheral source / drain patterns PSD and a peripheral channel pattern PCH between the peripheral source / drain patterns PSD can be disposed in an upper portion of the peripheral active pattern PAP. The peripheral source / drain patterns PSD can be epitaxial patterns formed by a selective epitaxial growth process. The peripheral channel pattern PCH can have a length in the second direction D2 that is greater than the length of the first active pattern AP1 in the second direction D2. Figure 3A and Figure 3BThe first channel pattern CH1 and the second channel pattern CH2 shown are each longer in the second direction D2. Therefore, the transistor in the peripheral region PER can be a long-channel transistor.

[0074] The peripheral gate electrode PGE can be configured to intersect with the peripheral active pattern PAP and can extend in the first direction D1. The width of the peripheral gate electrode PGE in the second direction D2 can be greater than that of the peripheral active pattern PAP. Figure 3A and Figure 3B The width of each of the first gate electrode GE1 to the fourth gate electrode GE4 shown in the second direction D2 is large.

[0075] A gate cap pattern GP can be disposed on the peripheral gate electrode PGE. The gate cap pattern GP may not completely cover the upper portion of the peripheral gate electrode PGE. For example, the topmost point PGEt of the peripheral gate electrode PGE may not be covered by the gate cap pattern GP and may be exposed. The topmost point PGEt of the peripheral gate electrode PGE may be coplanar with the top surface of the gate cap pattern GP. The topmost point PGEt of the peripheral gate electrode PGE may be positioned between the gate cap pattern GP and the gate spacer GS.

[0076] Because the peripheral gate electrode PGE has a relatively large width, the topmost part of the peripheral gate electrode PGE, PGEt, can be exposed through the process of forming the gate cap pattern GP.

[0077] A peripheral active contact (PAC) can be configured to connect to at least one peripheral source / drain pattern (PSD). The top surface of the peripheral active contact (PAC) can be coplanar with the top surface of the gate cap pattern (GP).

[0078] The power line VDD of the first interconnect layer M1 can extend in the second direction D2 to cover the top surface of the peripheral active contact PAC. The peripheral active contact PAC can be directly connected to the power line VDD without the need for an additional via plug.

[0079] If the exposed topmost PGEt comes into contact with a conductor of the first interconnect layer M1 (e.g., the power line VDD), a process failure (e.g., a short circuit) will occur. According to an example embodiment, a third insulating structure IP3 may be disposed on the peripheral gate electrode PGE. The third insulating structure IP3 may cover the top surface of the gate cap pattern GP. The third insulating structure IP3 may not cover the peripheral active contact PAC. Due to the third insulating structure IP3, the topmost PGEt of the peripheral gate electrode PGE may not be connected to the power line VDD. Therefore, due to the third insulating structure IP3 disposed on the peripheral gate electrode PGE, process failures that would occur if the exposed topmost PGEt of the peripheral gate electrode PGE came into contact with the power line VDD can be prevented.

[0080] Figure 5 ,Figure 7 、 Figure 9 and Figure 11 are plan views showing a method of manufacturing a semiconductor device according to an example embodiment. Figure 6A 、 Figure 8A 、 Figure 10A and Figure 12A are cross-sectional views taken along lines A-A' of Figure 5 、 Figure 7 、 Figure 9 and Figure 11 . Figure 6B 、 Figure 8B 、 Figure 10B and Figure 12B are cross-sectional views taken along lines B-B' of Figure 5 、 Figure 7 、 Figure 9 and Figure 11 . Figure 8C 、 Figure 10C and Figure 12C are cross-sectional views taken along lines C-C' of Figure 7 、 Figure 9 and Figure 11 . Figure 8D 、 Figure 10D and Figure 12D are cross-sectional views taken along lines D-D' of Figure 7 、 Figure 9 and Figure 11 .

[0081] Referring to Figure 5 、 Figure 6A and Figure 6B , a base 100 having a memory cell region MEC can be provided. The base 100 can be patterned to form trenches TR defining first active patterns API and second active patterns AP2. Thus, the trenches TR can be formed between the first active patterns API and the second active patterns AP2. The first active patterns API and the second active patterns AP2 can be formed on the memory cell region MEC.

[0082] A device isolation layer ST can be formed on the base 100 to fill the trenches TR. The device isolation layer ST can be formed of or include an insulating material (e.g., silicon oxide). The device isolation layer ST can be recessed to expose upper portions of the first active patterns API and the second active patterns AP2. Thus, the upper portions of the first active patterns API and the second active patterns AP2 can vertically protrude above the device isolation layer ST.

[0083] Referring to Figure 7 and Figures 8A-8DA sacrificial pattern PP can be formed to cross the first active pattern AP1 and the second active pattern AP2. The sacrificial pattern PP can be a linear pattern extending in the first direction D1. For example, the formation of the sacrificial pattern PP can include forming a sacrificial layer on the substrate 100, forming a hard mask pattern MA on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MA as an etching mask. The sacrificial layer can be formed of or include polysilicon.

[0084] A pair of gate spacers GS can be formed on opposite side surfaces of each of the sacrificial patterns PP. The formation of the gate spacers GS can include conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer can be formed of or include at least one of SiCN, SiCON, and SiN. In an example embodiment, the gate spacer layer can be a multi-layer structure composed of at least two of SiCN, SiCON, and SiN.

[0085] A first source / drain pattern SD1 can be formed in the upper portion of the first active pattern AP1. A pair of the first source / drain patterns SD1 can be formed at both sides of each of the sacrificial patterns PP. For example, the first recessed regions RS1 can be formed by etching the upper portion of the first active pattern AP1 using the hard mask pattern MA and the gate spacers GS as etching masks. During the etching of the upper portion of the first active pattern AP1, the device isolation layer ST between the first active patterns AP1 can be partially recessed (see, for example, Figure 8D ).

[0086] The first source / drain pattern SD1 can be formed by a selective epitaxial growth process in which the inner side surfaces of the first recessed regions RS1 of the first active pattern AP1 are used as seed layers. As a result of the formation of the first source / drain pattern SD1, a first channel pattern CH1 can be defined between the pair of the first source / drain patterns SD1. In an example embodiment, the selective epitaxial growth process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The first source / drain pattern SD1 can be formed of or include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. Each of the first source / drain patterns SD1 can be a multi-layer structure including a plurality of semiconductor layers.

[0087] In an example embodiment, the first source / drain pattern SD1 can be doped in-situ during a selective epitaxial growth process. In another example embodiment, after the first source / drain pattern SD1 is formed, an ion implantation process can be performed to implant impurities into the first source / drain pattern SD1. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0088] A second source / drain pattern SD2 can be formed in the upper portion of the second active pattern AP2. A pair of second source / drain patterns SD2 can be formed at both sides of each of the sacrificial patterns PP. For example, the second recessed regions RS2 can be formed by etching the upper portion of the second active pattern AP2 using the hard mask pattern MA and the gate spacers GS as etch masks (e.g., see Figure 8D ).

[0089] The second source / drain pattern SD2 can be formed by a selective epitaxial growth process in which the inner side surfaces of the second recessed regions RS2 of the second active pattern AP2 are used as seed layers. As a result of the formation of the second source / drain pattern SD2, a second channel pattern CH2 can be defined between the pair of second source / drain patterns SD2. In an example embodiment, the second source / drain pattern SD2 can be formed of or include the same semiconductor material (e.g., Si) as the substrate 100. The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type).

[0090] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be sequentially formed by different processes. Accordingly, the first source / drain pattern SD1 and the second source / drain pattern SD2 can not be formed at the same time.

[0091] Referring to Figure 9 and Figures 10A-10D , the first interlayer insulating layer 110 can be formed to cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the hard mask pattern MA, and the gate spacers GS (e.g., at the side surfaces of the gate spacers GS). In an example embodiment, the first interlayer insulating layer 110 can be formed of or include silicon oxide.

[0092] The first interlayer insulating layer 110 can be planarized to expose the top surfaces of the sacrificial patterns PP. The planarization of the first interlayer insulating layer 110 can be performed using an etch-back or a chemical mechanical polishing (CMP) process. The planarization process can be performed to completely remove the hard mask pattern MA. Accordingly, the first interlayer insulating layer 110 can have a top surface that is coplanar with the top surfaces of the sacrificial patterns PP and the top surfaces of the gate spacers GS.

[0093] The first to fourth gate electrodes GE1 to GE4 can be formed instead of the sacrificial pattern PP. For example, the exposed sacrificial pattern PP can be selectively removed so that empty spaces can be formed as a result of the removal of the sacrificial pattern PP. The gate dielectric pattern GI, the gate electrodes GE1 to GE4, and the gate cap pattern GP can be formed in the empty spaces from which the sacrificial pattern PP is removed.

[0094] The forming of the gate electrodes GE1 to GE4 and the gate cap pattern GP can include forming a gate metal layer in the empty spaces, recessing the gate metal layer, forming a gate cap layer on the recessed gate metal layer, and planarizing the gate cap layer to expose a top surface of the first interlayer insulating layer 110.

[0095] The insulating pattern SP can be formed by removing a portion of the gate electrodes GE1 to GE4 and filling the removed portion with an insulating material. The gate electrodes GE1 to GE4 can be divided into the first to fourth gate electrodes GE1 to GE4 by the insulating pattern SP.

[0096] The first to eighth active contacts AC1 to AC8 can be formed to penetrate the first interlayer insulating layer 110 and to be electrically connected to the first and second source / drain patterns SD1 and SD2. The first and second gate contacts GC1 and GC2 can be formed to penetrate the first interlayer insulating layer 110 and the gate cap pattern GP and to be electrically connected to the third and second gate electrodes GE3 and GE2, respectively.

[0097] The first to eighth active contacts AC1 to AC8 and the first and second gate contacts GC1 and GC2 can be simultaneously formed through a middle-of-line (MOL) process. For example, the first contact holes can be formed in the first interlayer insulating layer 110 through a first lithography process. The first contact holes can be formed to define the first to eighth active contacts AC1 to AC8. The first contact holes can be formed to expose the first and second source / drain patterns SD1 and SD2. The first contact holes can be formed in a self-aligned manner using the gate spacers GS and the gate cap pattern GP as a mask.

[0098] The second contact holes can be formed through a second lithography process. The second contact holes can be formed to define the first and second gate contacts GC1 and GC2. The second contact holes can be formed to expose a top surface of the second gate electrode GE2 and a top surface of the third gate electrode GE3.

[0099] For example, a portion of the first contact hole defining the second active contact AC2 can be overlapped with a portion of the second contact hole defining the first gate contact GC1. In this case, the first and second contact holes overlapped with each other can form a single contact hole.

[0100] The first to eighth active contacts AC1-AC8 and the first and second gate contacts GC1 and GC2 can be formed by sequentially filling the first and second contact holes with a barrier layer and a conductive layer. In an example embodiment, the second active contact AC2 and the first gate contact GC1 can be formed as a single contact structure UC. A silicide pattern SC can be formed on the first and second source / drain patterns SD1 and SD2 exposed through the first contact hole.

[0101] Referring to Figure 11 and Figures 12A-12D The first and second insulating structures IP1 and IP2 can be formed on the node close region NC. For example, an insulating layer can be formed on the first interlayer insulating layer 110, e.g., to cover the first interlayer insulating layer 110. A photoresist pattern PR defining the node close region NC can be formed on the insulating layer, and the first and second insulating structures IP1 and IP2 can be formed by patterning the insulating layer using the photoresist pattern PR as an etching mask.

[0102] The node open region NO can be defined by an area on which the first and second insulating structures IP1 and IP2 are not disposed. A top surface of the first interlayer insulating layer 110 of the node open region NO and a top surface of the gate cap pattern GP of the node open region NO can not be covered by the first and second insulating structures IP1 and IP2, and can be exposed to the outside.

[0103] Referring back to Figure 2 and Figures 3A-3D A second interlayer insulating layer 120 can be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 can cover the first and second insulating structures IP1 and IP2.

[0104] A first interconnection layer M1 can be formed in the second interlayer insulating layer 120 through a back end of line (BEOL) process. The formation of the first interconnection layer M1 can include forming first, second, and power lines BL1, BL2, and VDD extending in the second direction D2 and parallel to each other.

[0105] Each of the first bit lines BL1, the second bit lines BL2, and the power supply lines VDD can be formed by a single damascene process. For example, the second interlayer insulating layer 120 can be patterned to form interconnection holes extending in the second direction D2 and parallel to each other. The interconnection holes on the node open region NO can be formed to expose top surfaces of the contact members AC1 to AC8, GC1, and GC2. The interconnection holes on the node close region NC can be formed to expose the first insulating structures IP1 and the second insulating structures IP2. The interconnection lines BL1, BL2, and VDD of the first interconnection layer M1 can be formed by sequentially filling the interconnection holes with a barrier layer and a conductive layer. The barrier layer filling the interconnection holes can directly cover the top surfaces of the contact members AC1 to AC8, GC1, and GC2 exposed in the node open region NO.

[0106] In a general BEOL process, the first interconnection layer M1 can be formed by a dual damascene process that simultaneously forms via plugs and interconnection lines. In contrast, according to an example embodiment, since the first interconnection layer M1 includes only interconnection lines without any via plugs, the first interconnection layer M1 can be formed by performing a single damascene process only once. Thus, it can be possible to simplify the manufacturing process and reduce the occurrence of process failures.

[0107] Figure 13A Figure 13B and Figure 13C are cross-sectional views taken along lines B-B', lines C-C', and lines D-D' of Figure 2 to illustrate a semiconductor memory device according to an example embodiment. For a concise description, elements previously described with reference to Figures 1-4 may be identified by the same reference numerals without repeating overlapping descriptions thereof, and features different from those of the previous embodiments will be described in more detail below.

[0108] With reference to Figure 2 , Figure 13A , Figure 13B and Figure 13C , a level of a top surface of the first interlayer insulating layer 110 of the node open region NO can be lower than a level of a top surface of the first interlayer insulating layer 110 of the node close region NC. A level of a top surface of the gate cap pattern GP of the node open region NO can be lower than a level of a top surface of the gate cap pattern GP of the node close region NC. Thus, a portion of the first interlayer insulating layer 110 covered with the first insulating structures IP1 and the second insulating structures IP2 can have a higher top surface than another portion not covered with the first insulating structures IP1 and the second insulating structures IP2. A portion of the gate cap pattern GP covered with the first insulating structures IP1 and the second insulating structures IP2 can have a higher top surface than another portion not covered with the first insulating structures IP1 and the second insulating structures IP2.

[0109] ​For example, in the node open region NO, the top surfaces of the contact pieces AC1 to AC8, GC1, and GC2 can be higher than the top surface of the gate cap pattern GP and the top surface of the first interlayer insulating layer 110. For example, referring to Figure 13A The top surface of the seventh active contact piece AC7 can be higher than the top surface GPt1 of the gate cap pattern GP on the fourth gate electrode GE4. The seventh active contact piece AC7 can include an upper portion UP that protrudes above the gate cap pattern GP and the first interlayer insulating layer 110. Not only the top surface UPT of the seventh active contact piece AC7 but also an upper side surface USW of the seventh active contact piece AC7 can be exposed. The second bit line BL2 can cover the top surface UPT and the upper side surface USW of the seventh active contact piece AC7.

[0110] Referring to Figure 13A and Figure 13B The top surface GPt1 of the gate cap pattern GP that is not covered with the first and second insulating structures IP1 and IP2 can be lower than the top surface GPt2 of the gate cap pattern GP that is covered with the first and second insulating structures IP1 and IP2.

[0111] Referring to Figure 13C The sixth active contact piece AC6 can include an upper portion that protrudes above the first interlayer insulating layer 110. The power supply line VDD can cover the top surface and the upper side surface USW of the sixth active contact piece AC6.

[0112] A method of manufacturing a semiconductor device according to the present embodiment will be described in more detail below.

[0113] Referring back to Figure 11 and Figures 12A-12D The first and second insulating structures IP1 and IP2 can be formed by etching the insulating layer using the photoresist pattern PR as an etching mask. The first interlayer insulating layer 110 and the gate cap pattern GP exposed through the photoresist pattern PR can be over-etched during the etching process. Thus, the top surfaces of the first interlayer insulating layer 110 and the gate cap pattern GP exposed by the photoresist pattern PR can be lowered.

[0114] According to the present embodiment, the interconnection lines of the first interconnection layer M1 can be disposed in contact with the top surfaces and side surfaces of the protruding upper portions of the contact pieces. Thus, the interconnection lines can be in contact with the protruding upper portions of the contact pieces in a three-dimensional manner. Thus, the contact area between the interconnection lines and the contact pieces can be increased, and this can enable the connection resistance between the interconnection lines and the contact pieces to be reduced. Thus, according to the example embodiment, it can be possible to improve the electrical characteristics of the semiconductor device.

[0115] In the semiconductor device according to the example embodiment, the interconnection line of the first interconnection layer can be directly connected to the underlying contact, and thus, it can be possible to reduce connection resistance between the interconnection line and the contact. Further, it can be possible to omit a via plug between the interconnection line and the contact, and thus, it can be possible to prevent process failure (e.g., contact failure caused by misalignment). By providing the insulating structure, it can be possible to easily control connection or disconnection between the interconnection line and the contact. Thus, it can be possible to improve electrical characteristics and reliability characteristics of the semiconductor device.

[0116] As described above, embodiments relate to a semiconductor device including a field effect transistor and a manufacturing method thereof. Embodiments can provide a semiconductor device including a field effect transistor having improved electrical characteristics and reliability characteristics and a manufacturing method thereof.

[0117] Example embodiments have been disclosed herein, although specific terminology has been employed, the terminology is used in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics, and / or elements described in conjunction with specific embodiments can be used alone or in combination with one another, in any suitable combination, unless specifically stated otherwise, as will be apparent to one of ordinary skill in the art from the present disclosure. Thus, one of ordinary skill in the art will understand that the various changes can be made to the forms and details of the embodiments described without departing from the spirit and scope of the application as set forth in the following claims.

Claims

1. A semiconductor device, the semiconductor device comprising: The first active pattern is located on the substrate; The first gate electrode intersects with the first active pattern; A pair of source / drain patterns are disposed in the upper part of the first active pattern and respectively disposed on opposite sides of the first gate electrode; The first gate cover pattern is located on the first gate electrode; An interlayer insulating layer is located on the pair of source / drain patterns; The first active contact and the second active contact penetrate the interlayer insulation layer and are respectively connected to the pair of source / drain patterns; as well as The first interconnect layer is located on the first active contact and the second active contact. The first interconnect layer includes: a first insulating structure that contacts the top surface of the second active contact; and a first interconnect line that covers the top surface of the first active contact and extends on the first insulating structure, and covers the top surface of the first gate cover pattern between the first active contact and the second active contact. The first interconnect also covers the side and top surfaces of the first insulating structure.

2. The semiconductor device according to claim 1, wherein, The ratio of the height of the first interconnect on the first insulating structure to the height of the first interconnect on the first active contact is in the range of 0.7 to 0.

9.

3. The semiconductor device according to claim 1, wherein, The first interconnect is spaced apart from the second active contact by a first insulating structure.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The first interconnect layer includes: a node open region defining connection to a first active contact and a second active contact; and a node closed region defining disconnection from the first active contact and the second active contact. The first insulation structure is located in the node closure area.

5. The semiconductor device according to claim 1, wherein, The first interconnect extends in a predetermined direction to further cover the top surface of the interlayer insulation layer.

6. The semiconductor device according to claim 1, wherein: The first interconnect includes a conductive pattern and a blocking pattern surrounding the conductive pattern, and The blocking pattern directly covers the top surface of the first active contact and the top surface of the first gate cover pattern.

7. The semiconductor device according to claim 1, wherein, The first insulation structure comprises multiple stacked insulation layers.

8. The semiconductor device according to claim 1, further comprising: The second active pattern is located on the substrate; The second gate electrode intersects with the second active pattern; A gate spacer is located on one side of the second gate electrode; as well as The second gate cap pattern is located on the second gate electrode, wherein: The width of the second gate electrode is greater than the width of the first gate electrode. The very top of the second gate electrode is positioned between the second gate cap pattern and the gate spacer, and The first interconnect layer also includes a second insulating structure covering the topmost part of the second gate cover pattern and the second gate electrode.

9. The semiconductor device according to claim 1, wherein: The first interconnect layer also includes a second interconnect line, which is configured to extend adjacent to and parallel to the first interconnect line. The ratio of the height of the first interconnecting line on the first insulating structure to the height of the second interconnecting line between its bottom and top surfaces is in the range of 0.7 to 0.

9.

10. A semiconductor device, the semiconductor device comprising: Active pattern, located on the substrate; The first gate electrode intersects with the active pattern; A pair of source / drain patterns are disposed in the upper part of the active pattern and respectively disposed on opposite sides of the first gate electrode; The first gate cover pattern is located on the first gate electrode; An interlayer insulating layer is located on the pair of source / drain patterns; The first active contact and the second active contact penetrate the interlayer insulating layer and are respectively connected to the pair of source / drain patterns. The upper part of the first active contact protrudes above the top surface of the first gate cover pattern. as well as A first interconnect layer is located on a first active contact and a second active contact, the first interconnect layer including: an insulating structure covering the top surface of the second active contact; And interconnecting lines that cover the top surface of the first active contact and extend over an insulating structure, and cover the side surface of the upper portion of the first active contact.

11. The semiconductor device of claim 10, further comprising: The second gate electrode intersects with the active pattern; as well as The second gate cap pattern is located on the second gate electrode, wherein: An insulating structure covers the top surface of the second gate cap pattern, and The top surface of the second gate cover pattern is higher than the top surface of the first gate cover pattern.

12. The semiconductor device according to claim 10, wherein, The interconnect also covers the top surface of the first gate cover pattern located between the first active contact and the second active contact.

13. The semiconductor device according to claim 10, wherein, The ratio of the height of the interconnect on the insulating structure to the height of the interconnect on the first active contact is in the range of 0.7 to 0.

9.

14. The semiconductor device according to any one of claims 10 to 13, wherein, The top surface of the interlayer insulation layer that is not covered by the insulation structure is lower than the top surface of the first active contact and the top surface of the second active contact.

15. A method for manufacturing a semiconductor device, the method comprising the following steps: Patterning the substrate to form an active pattern; Form a gate electrode that intersects with the active pattern; A pair of source / drain patterns are formed in the upper part of the active pattern, the pair of source / drain patterns being formed on opposite sides of the gate electrode; A gate cap pattern is formed on the gate electrode; A first interlayer insulating layer is formed on the pair of source / drain patterns; A first active contact and a second active contact are formed that penetrate the first interlayer insulation layer and are respectively connected to the pair of source / drain patterns; An insulating structure is formed that contacts the top surface of the second active contact. as well as Interconnects are formed on a first active contact, a gate cover pattern, and an insulating structure. The interconnects are in contact with the top surface of the first active contact and the top surface of the gate cover pattern, and the interconnects also cover the side surface and the top surface of the insulating structure.

16. The method according to claim 15, wherein, The steps involved in forming the insulation structure include: An insulating layer is formed on the first interlayer insulating layer and covers the first active contact and the second active contact; A photoresist pattern is formed on the insulating layer to define the node closure area; and A photoresist pattern is used as an etching mask to etch the insulating layer.

17. The method according to claim 16, wherein, An etching step is performed on the insulating layer to etch the gate cap pattern and the first interlayer insulating layer exposed by the photoresist pattern, thereby lowering the top surface of the gate cap pattern and the first interlayer insulating layer.

18. The method according to claim 15, wherein, Interconnects are formed using a single damascene process, which includes: A second interlayer insulation layer is formed on the first interlayer insulation layer and the insulation structure; Patterning the second interlayer insulating layer to form interconnect vias; and A barrier layer and a conductive layer are sequentially formed in the interconnect.

19. The method according to claim 18, wherein, Interconnect holes are formed to expose the top surface of the first active contact not covered by the insulating structure and the top surface of the gate cover pattern.

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