Display device

Abstract

A display device includes a substrate including a display region and a non-display region of a periphery of the display region; a pixel configured on the display region; a first bank configured on the non-display region and including a first sub-bank and a second sub-bank configured on the first sub-bank; a first power line configured on the non-display region and connected to the pixel through between the first sub-bank and the second sub-bank; and a bridge pattern configured under the first sub-bank and connected with the first power line.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] Typically, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs, include display devices for displaying images. The display device generates the image and presents it to the user through a display screen.

[0003] The display device may include a display panel having a plurality of pixels for generating images, a driving unit for driving the plurality of pixels, and power supply wiring for supplying voltage to the plurality of pixels. The plurality of pixels receive a driving voltage through the power supply wiring and are controlled by the driving unit, thereby enabling the driving of the plurality of pixels. Summary of the Invention

[0004] The purpose of this invention is to provide a display device that can reduce power supply failures.

[0005] An embodiment of the present invention relates to a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a pixel disposed on the display area; a first dam disposed on the non-display area and including a first sub-dam and a second sub-dam disposed on the first sub-dam; a first power line disposed on the non-display area and connected to the pixel via the first sub-dam and the second sub-dam; and a bridging pattern disposed below the first sub-dam and connected to the first power line.

[0006] An embodiment of the present invention relates to a display device comprising: a substrate including a display area and a non-display area surrounding the display area; a pixel disposed on the display area; a first dam disposed on the non-display area; a second dam disposed between the first dam and the display area; a first power line disposed on the non-display area, extending through the first dam and below the second dam, and connected to the pixel; and a bridging pattern disposed below the first dam and extending outward beyond the first dam to connect to the first power line.

[0007] (Invention Effects)

[0008] According to an embodiment of the present invention, a bridging pattern can be disposed below the first sub-dike, and a first power supply line extending above the first sub-dike can be connected to the bridging pattern. With this structure, even if the first power supply line on the first sub-dike is damaged, a first voltage can still be applied to multiple pixels through the bridging pattern, thus reducing power supply malfunctions. Attached Figure Description

[0009] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention.

[0010] Figure 2 It is an exemplary representation Figure 1 A cross-sectional view of the display device shown.

[0011] Figure 3 It is an exemplary representation Figure 2 The diagram shows a cross-section of the display panel.

[0012] Figure 4 yes Figure 3 The diagram shows a floor plan of the display panel.

[0013] Figure 5 It is an exemplary representation Figure 4 The image shown is composed of a cross-section of a certain pixel.

[0014] Figure 6 It is an exemplary representation from Figure 5 The diagram shows a cross-section from the first power line to the pixel connected to the first power line.

[0015] Figure 7 yes Figure 6 An enlarged view of the first region AA1 shown.

[0016] Figure 8 Viewed from a two-dimensional perspective Figure 6 The plan view of the first region AA1 is shown.

[0017] Figure 9 and Figure 10 This is a diagram illustrating the cross-sectional configuration of a display device according to other embodiments of the present invention.

[0018] Figures 11 to 14 This is a diagram of the bridging patterns involved in various embodiments of the present invention.

[0019] (Symbol Explanation)

[0020] DD: Display device; DP: Display panel; PX: Pixel; OLED: Light-emitting element; TR: Transistor; SUB: Substrate; PL1: First power line; PL2: Second power line; DM1: First dam; DM2: Second dam; DM1_1: First sub-dam; DM1_2: Second sub-dam; DM1_3: Third sub-dam; DM2_1: Fourth sub-dam; DM2_2: Fifth sub-dam; BP: Bridging pattern; INS1: First insulating layer; INS2: Second insulating layer; INS3: Third insulating layer. Detailed Implementation

[0021] In this specification, when it is mentioned that a certain component (or region, layer, part, etc.) is located on, connected to or combined with other components, it means that it can be directly configured / connected / combined with other components, or a third component can be configured therein.

[0022] The same symbols refer to the same constituent elements. In addition, the thickness, proportions, and dimensions of the constituent elements in the various figures are exaggerated for the purpose of effectively illustrating the technical content.

[0023] "And / or" includes one or more combinations of all relevant constituent elements that can be defined.

[0024] The terms "first," "second," etc., can be used to describe various constituent elements, but the constituent elements described should not be limited to these terms. These terms are used only for the purpose of distinguishing one constituent element from another. For example, without departing from the scope of this invention, a first constituent element can be named a second constituent element, and similarly, a second constituent element can be named a first constituent element. Singular expressions include plural expressions unless explicitly stated otherwise in the text.

[0025] Additionally, terms such as "below," "on the lower side," "above," and "on the upper side" are used to explain the connection relationships between the components in the diagram. These terms are relative concepts and are explained based on the direction shown in the diagram.

[0026] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by those skilled in the art. Furthermore, terms defined in commonly used dictionaries shall be interpreted as having a consistent meaning in the relevant technical context, and are hereby explicitly defined, provided they are not interpreted as having an ideal or overly formal meaning.

[0027] Terms such as “including” or “having” should be understood as referring to the presence of features, figures, steps, operations, constituent elements, components, or combinations thereof as recorded in the instruction manual, and do not preclude the existence or additional possibilities of one or more other features, figures, steps, operations, constituent elements, components, or combinations thereof.

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention.

[0030] Reference Figure 1The display device DD according to embodiments of the present invention may have a rectangular shape, having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, it is not limited to this, and the display device DD may also have various shapes such as circles or polygons.

[0031] Hereinafter, the direction that substantially intersects the plane defined by the first direction DR1 and the second direction DR2 will be defined as the third direction DR3. Furthermore, in this specification, "when viewed from a plane" can refer to the state observed from the third direction DR3.

[0032] The upper surface of the display device DD can be defined as the display surface DS, which can have a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the display device DD can be provided to the user through the display surface DS.

[0033] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA, and the border of the display device DS printed using predetermined colors may be defined.

[0034] The display device DD can be used in large electronic devices such as televisions, monitors, or external advertising billboards. Additionally, the display device DD can also be used in small to medium-sized electronic devices such as personal computers, laptops, personal digital terminals, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are merely illustrative embodiments, and it can be used in other electronic devices without departing from the scope of the invention.

[0035] Figure 2 It is an exemplary representation Figure 1 A cross-sectional view of the display device shown.

[0036] Reference Figure 2 The display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, a padding layer CUL, and a first adhesive layer AL1 to a fourth adhesive layer AL4.

[0037] The input sensing unit (ISP), anti-reflective layer (RPL), and window (WIN) can be configured on the display panel (DP). The panel protective film (PPF) and the cushioning layer (CUL) can be configured below the display panel (DP).

[0038] The display panel DP can be a flexible display panel. For example, the display panel DP may include multiple electronic components disposed on a flexible substrate. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA, similar to a display device DD.

[0039] In one embodiment of the present invention, the display panel DP can be a light-emitting display panel, and there is no particular limitation. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the case where the display panel DP is an organic light-emitting display panel will be described.

[0040] The input sensing unit (ISP) can be configured on the display panel (DP). The ISP may include multiple sensor units (not shown) for sensing external input. The sensor units may sense external input capacitively. The ISP can be manufactured directly on the display panel (DP) during the manufacturing process. However, it is not limited to this; the ISP can also be manufactured as a separate panel from the display panel (DP) and attached to it via an adhesive layer.

[0041] An anti-reflective layer (RPL) can be disposed on the input sensing unit (ISP). The RPL can be defined as an external light reflection prevention film. The RPL reduces the reflectivity of external light incident from above the display device (DD) toward the display panel (DP). For example, the RPL may include a phase retarder and / or a polarizer.

[0042] The window (WIN) can be mounted on the anti-reflective layer (RPL). The window protects the display panel (DP), input sensor (ISP), and anti-reflective layer (RPL) from external scratches and impacts. The window can also be optically transparent.

[0043] A panel protective film (PPF) can be disposed below the display panel (DP). The panel protective film (PPF) can be defined as a protective substrate. The panel protective film (PPF) protects the lower part of the display panel (DP). The panel protective film (PPF) can include flexible plastic materials. For example, the panel protective film (PPF) can include polyethylene terephthalate (PET).

[0044] A cushioning layer (CUL) can be disposed beneath the panel protective film (PPF). The CUL can absorb external impacts applied to the lower part of the display device (DD) to protect the display panel (DP). The CUL may include a foam sheet with a predetermined elasticity.

[0045] The first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF. The display panel DP and the panel protective film PPF can be bonded together through the first adhesive layer AL1.

[0046] The second adhesive layer AL2 can be disposed between the anti-reflective layer RPL and the input sensing unit ISP. The second adhesive layer AL2 can bond the anti-reflective layer RPL and the input sensing unit ISP together.

[0047] The third adhesive layer AL3 can be disposed between the window WIN and the anti-reflective layer RPL. The third adhesive layer AL3 can bond the window WIN and the anti-reflective layer RPL together.

[0048] The fourth adhesive layer AL4 can be disposed between the panel protective film PPF and the cushioning layer CUL. The fourth adhesive layer AL4 can bond the panel protective film PPF and the cushioning layer CUL together.

[0049] Figure 3 It is an exemplary representation Figure 2 The diagram shows a cross-section of the display panel.

[0050] Reference Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0051] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include a flexible plastic material. For example, the substrate SUB may include polyimide (PI).

[0052] The display element layer DP-OLED can be disposed on the display area DA. The thin film encapsulation layer TFE can be disposed on the circuit element layer DP-CL to cover the display element layer DP-OLED.

[0053] Multiple pixels can be configured in the DP-CL circuit element layer and the DP-OLED display element layer. Each pixel can include a transistor configured in the DP-CL circuit element layer and a light-emitting element configured in the DP-OLED display element layer and connected to the transistor. The pixel configuration will be described in detail below.

[0054] Figure 4 yes Figure 3 The diagram shows a floor plan of the display panel.

[0055] Reference Figure 4The display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, an emission driver EDV, a printed circuit board PCB, and a timing controller T-CON.

[0056] The display panel DP may have a rectangular shape, having a long side extending in a first direction DR1 and a short side extending in a second direction DR2. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0057] The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple light-emitting lines EL1 to ELm, multiple first control lines CSL1, multiple second control lines CSL2, a first power line PL1, a second power line PL2, multiple connection lines CNL, and multiple pads (PD1, PD2). m and n are natural numbers. The lines can be configured on the circuit element layer DP-CL.

[0058] Pixel PX can be configured in the display area DA. The scan driver unit SDV, data driver unit DDV, and light emission driver unit EDV can be configured in the non-display area NDA. The scan driver unit SDV and the light emission driver unit EDV can be configured in the non-display area NDA, respectively adjacent to the long side of the display panel DP.

[0059] The data driver unit (DDV) can be fabricated as an integrated circuit chip and mounted on the display panel (DP). The data driver unit (DDV) can be positioned on a non-display area (NDA) adjacent to one of the short sides of the display panel (DP). However, it is not limited to this; the data driver unit (DDV) can also be mounted on a flexible circuit board connected to the display panel (DP) and connected to the display panel (DP) via the flexible circuit board. Example, when viewed in a planar plane, the data driver unit (DDV) can be adjacent to the lower end of the display panel (DP).

[0060] Scan lines SL1 to SLm can extend along the second direction DR2 and connect to each pixel PX and the scan drive unit SDV. Data lines DL1 to DLn can extend along the first direction DR1 and connect to each pixel PX and the data drive unit DDV. Light emission lines EL1 to Elm can extend along the second direction DR2 and connect to each pixel PX and the light emission drive unit EDV.

[0061] The first power line PL1 can be configured in the non-display area NDA. The first power line PL1 can extend along the bezel of the display panel DP. The first power line PL1 can be adjacent to the long side of the display panel DP. Alternatively, the first power line PL1 can be adjacent to the other short side of the display panel DP where the data driver unit DDV is not configured. The first power line PL1 can be configured on a more outer edge than the scan driver unit SDV and the light emission driver unit EDV.

[0062] The first power line PL1 can receive a first voltage. For ease of explanation, the connection relationship is not shown, but the first power line PL1 can extend to the display area DA and connect to each pixel PX, and the first voltage can be provided to each pixel PX through the first power line PL1.

[0063] The second power line PL2 can extend along the first direction DR1 and be disposed in the non-display area NDA. The second power line PL2 can be disposed between the display area DA and the light-emitting drive unit EDV. However, it is not limited to this; the second power line PL2 can also be disposed between the display area DA and the scan drive unit SDV. The second power line PL2 can receive a second voltage having a level higher than the first voltage.

[0064] Each connecting line CNL can extend along the second direction DR2 and be arranged along the first direction DR1. Each connecting line CNL can be connected to the second power line PL2 and each pixel PX. A second voltage can be applied to each pixel PX through the interconnected second power line PL2 and each connecting line CNL.

[0065] The first control line CSL1 can be connected to the scan driver unit SDV, and when viewed in a flat surface, it can extend towards the lower end of the display panel DP. The second control line CSL2 can be connected to the light-emitting driver unit EDV, and when viewed in a flat surface, it can extend towards the lower end of the display panel DP. The data driver unit DDV can be disposed between the first control line CSL1 and the second control line CSL2.

[0066] Multiple pads (PD1, PD2) may include multiple first pads PD1 configured on the display panel DP and multiple second pads PD2 configured on the printed circuit board PCB. The data drive unit DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 may be connected to the first pads PD1.

[0067] Data lines DL1 to DLn can be connected to corresponding first pads PD1 among a plurality of first pads PD1 via the data driver unit DDV. For example, data lines DL1 to DLn can be connected to the data driver unit DDV, and the data driver unit DDV can be connected to the first pads PD1 corresponding to data lines DL1 to DLn respectively.

[0068] A timing controller T-CON can be configured on a printed circuit board (PCB). The timing controller T-CON can be manufactured as an integrated circuit chip and mounted on the PCB.

[0069] Multiple second pads PD2 can be disposed on one side of the printed circuit board (PCB) adjacent to the display panel (DP). The second pads PD2 can be connected to the first pads PD1. Although not shown, the flexible circuit board can be connected to the multiple first pads PD1 and the multiple second pads PD2 to connect the printed circuit board (PCB) to the display panel (DP).

[0070] The timing controller T-CON can be connected to a corresponding second pad PD2 among a plurality of second pads PD2. The timing controller T-CON can be connected to the first pad PD1, which is connected to the data drive unit DDV, the first control line CSL1, and the second control line CSL2, through the corresponding second pad PD2.

[0071] Although not shown, the voltage generation unit can be disposed on a printed circuit board (PCB) and connected to a corresponding second pad PD2 among a plurality of second pads PD2. The voltage generation unit can be connected to the first pad PD1, which is connected to the first power line PL1 and the second power line PL2, through the corresponding second pad PD2.

[0072] The timing controller T-CON can control the operation of the scan driver unit (SDV), the data driver unit (DDV), and the light emission driver unit (EDV). The timing controller T-CON can generate scan control signals, data control signals, and light emission control signals in response to control signals received from an external source.

[0073] The scan control signal can be provided to the scan driver unit SDV via the first control line CSL1. The light emission control signal can be provided to the light emission driver unit EDV via the second control line CSL2. The data control signal can be provided to the data driver unit DDV. The timing controller T-CON can receive image signals from the outside and convert the image signal data format into a format that conforms to the interface specification of the data driver unit DDV before providing it to the data driver unit DDV.

[0074] The scan drive unit SDV can generate multiple scan signals in response to the scan control signal. The scan signals can be applied to each pixel PX via scan lines SL1 to SLm. The scan signals can be applied to each pixel PX sequentially.

[0075] The data driving unit (DDV) can generate multiple data voltages corresponding to the image signal in response to a data control signal. Each data voltage can be applied to each pixel (PX) via data lines DL1 to DLn. The light emission driving unit (EDV) can generate multiple light emission signals in response to a light emission control signal. Each light emission signal can be applied to each pixel (PX) via light emission lines EL1 to Elm.

[0076] Each pixel (PX) can receive a data voltage in response to a scan signal. Each pixel (PX) can emit light with a brightness corresponding to the data voltage in response to a light emission signal, thereby displaying an image. The emission time of each pixel (PX) can be controlled according to the light emission signal.

[0077] Figure 5 It is an exemplary representation Figure 4 The image shown is composed of a cross-section of a certain pixel.

[0078] Reference Figure 5 A pixel (PX) may include an OLED (Organic Light Emitting Device) and a transistor (TR) connected to the OLED. The OLED may include a first electrode (AE), a second electrode (CE), a hole control layer (HCL), an electron control layer (ECL), and an emissive layer (EML). The first electrode (AE) may be an anode, and the second electrode (CE) may be a cathode. An OLED can be defined as an organic light-emitting element.

[0079] The display area DA may include a light-emitting area PXA corresponding to each pixel PX and a non-light-emitting area NPXA surrounding the light-emitting area PXA. The light-emitting element OLED can be disposed in the light-emitting area PXA, and the transistor TR can be disposed in the non-light-emitting area NPXA.

[0080] Transistor (TR) and light-emitting element (OLED) can be disposed on substrate (SUB). Buffer layer (BFL) is disposed on substrate (SUB), and buffer layer (BFL) may include inorganic material.

[0081] A semiconductor layer SM can be configured on the buffer layer BFL, which contains transistors TR. The semiconductor layer SM can comprise inorganic or organic semiconductors, such as amorphous or polycrystalline silicon. Alternatively, the semiconductor layer SM can comprise oxide semiconductors. Although in Figure 5 Although not illustrated, the semiconductor layer SM may include a source region, a drain region, and a channel region between the source and drain regions.

[0082] An insulating layer INS can be configured on the buffer layer BFL to cover the semiconductor layer SM. The insulating layer INS may include inorganic materials. A gate electrode GE of a transistor TR, overlapping the semiconductor layer SM, can be configured on the insulating layer INS. The gate electrode GE can be configured to overlap with the channel region of the semiconductor layer SM.

[0083] A first insulating layer INS1 can be configured on the insulating layer INS to cover the gate electrode GE. The first insulating layer INS1 may include organic and / or inorganic materials.

[0084] The source electrode SE and drain electrode DE of transistor TR are configured separately on the first insulating layer INS1. The source electrode SE can be connected to the source region of semiconductor layer SM through a first contact hole CH1 defined in insulating layer INS and the first insulating layer INS1. The drain electrode DE can be connected to the drain region of semiconductor layer SM through a second contact hole CH2 defined in insulating layer INS and the first insulating layer INS1.

[0085] The source electrode SE can be used Figure 4 The connecting line CNL shown is connected to the second power supply line PL2. The source electrode SE can receive the second voltage through the second power supply line PL2 and the connecting line CNL.

[0086] A second insulating layer INS2 can be disposed on the first insulating layer INS1 to cover the source electrode SE and drain electrode DE of the transistor TR. The second insulating layer INS2 may include an organic material. A connection electrode CNE can be disposed on the second insulating layer INS2. The connection electrode CNE can be connected to the drain electrode DE through a third contact hole CH3 defined in the second insulating layer INS2.

[0087] A third insulating layer INS3 can be configured on the second insulating layer INS2 to cover the connection electrode CNE. A first electrode AE ​​can be configured on the third insulating layer INS3. The first electrode AE ​​can be connected to the connection electrode CNE through a fourth contact hole CH4 defined in the third insulating layer INS3.

[0088] The first electrode AE ​​can be connected to the electrode CNE and the transistor TR. Figure 4 The connecting line CNL and the second power supply line PL2 are shown. The first electrode AE ​​can receive the second voltage through the connecting electrode CNE and the transistor TR.

[0089] A pixel definition film (PDL) for exposing a predetermined portion of the first electrode AE ​​can be configured on the first electrode AE ​​and the third insulating layer INS3. An opening PX_OP for exposing the predetermined portion of the first electrode AE ​​can be defined on the pixel definition film (PDL).

[0090] The hole control layer (HCL) can be disposed on the first electrode (AE) and the pixel definition film (PDL). The HCL can be disposed together in the light-emitting region (PXA) and the non-light-emitting region (NPXA). The HCL may include a hole transport layer and may also include a hole injection layer.

[0091] The emissive layer (EML) can be configured on the hole control layer (HCL). The EML can be configured in the region corresponding to the opening PX_OP. That is, the EML can be formed separately in each pixel PX. The EML can include organic and / or inorganic materials. The EML can generate one of red, green, and blue light. However, it is not limited to this; the EML can also generate white light using a combination of organic materials that generate red, green, and blue light.

[0092] An electronic control layer (ECL) can be disposed on the light-emitting layer (EML). An electronic control layer (ECL) can also be disposed on a hole control layer (HCL) to cover the light-emitting layer (EML). That is, the electronic control layers (ECL) can be jointly disposed in the light-emitting region (PXA) and the non-light-emitting region (NPXA). The electronic control layer (ECL) may include an electron transport layer and may also include an electron injection layer.

[0093] The second electrode CE can be configured on the electronic control layer ECL. The second electrode CE can also be configured in each pixel PX. Figure 4 The first power supply line PL1 is shown as connected. The second electrode CE can receive the first voltage through the first power supply line PL1.

[0094] A thin-film encapsulation layer (TFE) can be disposed on the second electrode (CE). The thin-film encapsulation layer (TFE) may include a first encapsulation layer (EN1) disposed on the second electrode (CE), a second encapsulation layer (EN2) disposed on the first encapsulation layer (EN1), and a third encapsulation layer (EN3) disposed on the second encapsulation layer (EN2). The first encapsulation layer (EN1) and the third encapsulation layer (EN3) may be inorganic insulating layers, and the second encapsulation layer (EN2) may be an organic insulating layer.

[0095] The first encapsulation layer EN1 and the third encapsulation layer EN3 protect the pixel PX from moisture and oxygen. The second encapsulation layer EN2 protects the pixel PX from foreign matter such as dust particles. The aforementioned input sensing unit (ISP) can be configured on the thin-film encapsulation layer TFE.

[0096] The layer from the buffer layer BFL to the third insulating layer INS3 can be defined as the circuit element layer DP-CL. The layer from the first electrode AE ​​to the second electrode CE can be defined as the display element layer DP-OLED.

[0097] A first voltage can be applied to the second electrode CE. A second voltage can be applied to the first electrode AE ​​of the light-emitting element OLED via the transistor TR. Holes and electrons injected into the light-emitting layer EML combine to form excitons, which transition to the ground state while the light-emitting element OLED emits light. By emitting light through the light-emitting element OLED, an image can be displayed.

[0098] Figure 6 It is an exemplary representation from Figure 5 The diagram shows a cross-section extending from the first power line to the pixel connected to the first power line. Figure 7 yes Figure 6 An enlarged view of the first region AA1 shown. Figure 8 Observing on a plane Figure 6 The plan view of the first region AA1 is shown.

[0099] Illustratively, in Figure 7 The components below the first insulating layer INS1 are omitted. Additionally, in Figure 8 The image illustrates, exemplified by a portion of the first power line PL1, the bridging pattern BP, and a portion of the first sub-dam DM1_1.

[0100] Reference Figure 6 Pixel PX can be configured on the display area DA of the substrate SUB. The first power line PL1 and the second power line PL2 can be configured on the non-display area NDA of the substrate SUB.

[0101] The second power line PL2 can be configured on the first insulation layer INS1, and the second insulation layer INS2 can be configured on the second power line PL2. Although not in Figure 6 As shown, however, the second power line PL2 can be connected via... Figure 4 The connecting line CNL shown is connected to the transistor TR.

[0102] The buffer layer BFL, the insulating layer INS, and the first insulating layer INS1 can be disposed on the display area DA and extend toward the non-display area NDA. The buffer layer BFL and the insulating layer INS can extend longer toward the non-display area NDA than the first insulating layer INS1.

[0103] The second insulating layer INS2 and the third insulating layer INS3 can be disposed on the display area DA and extend toward the non-display area NDA. The second insulating layer INS2 and the third insulating layer INS3 can extend toward a portion of the non-display area NDA adjacent to the boundary between the display area DA and the non-display area NDA. The first insulating layer INS1 can extend longer toward the non-display area NDA than the second insulating layer INS2 and the third insulating layer INS3.

[0104] The pixel definition layer (PDL) can be configured on the display area (DA). The hole control layer (HCL) and electron control layer (ECL) configured on the display area (DA) can extend toward the non-display area (NDA) and be configured on the third insulating layer (INS3).

[0105] The display device DD may include a first barrier DM1, a second barrier DM2, and a bridging pattern BP. The first barrier DM1, the second barrier DM2, and the bridging pattern BP may be configured on a non-display area NDA. The first barrier DM1, the second barrier DM2, and the bridging pattern BP may be configured on a first insulating layer INS1 within the non-display area NDA. The first barrier DM1, the second barrier DM2, and the bridging pattern BP may be configured away from the borders of the second insulating layer INS2 and the third insulating layer INS3.

[0106] The second barrier DM2 can be configured between the display area DA and the first barrier DM1. Specifically, the second barrier DM2 can be configured between the border of the second insulating layer INS2 and the third insulating layer INS3 and the first barrier DM1.

[0107] Reference Figure 6 and Figure 7 The bridging pattern BP can be disposed below the first barrier DM1. The bridging pattern BP can be disposed between the first insulating layer INS1 and the first barrier DM1. The bridging pattern BP can extend outward beyond the first barrier DM1. Therefore, both sides of the bridging pattern BP can be exposed to the outside of the first barrier DM1.

[0108] The bridging pattern BP can include a conductive material. The bridging pattern BP can be formed by simultaneously patterning the same material as the second power line PL2 and the source-drain electrodes of the transistor TR.

[0109] The first power line PL1 can be disposed on an insulating layer INS that extends longer than the first insulating layer INS1 in the non-display area NDA. The first power line PL1 can extend on the first insulating layer INS1 in the non-display area NDA. The first power line PL1 can extend toward the edge of the second insulating layer INS2.

[0110] The first power line PL1 can extend through the first dike DM1. The first power line PL1 can contact and be electrically connected to the bridging pattern BP exposed to the outside of the first dike DM1. A portion of the bridging pattern BP disposed on the first insulating layer INS1 adjacent to the first dike DM1 can be connected to the first power line PL1.

[0111] The first power line PL1 can be disposed below the second dike DM2 and extend below the second dike DM2. Specifically, the first power line PL1 can extend above the second insulating layer INS2, passing between the second dike DM2 and the first insulating layer INS1.

[0112] The first power line PL1 can be disposed on the border of the second insulating layer INS2 and on a portion of the second insulating layer INS2 adjacent to the border of the second insulating layer INS2. The first power line PL1 can be formed by simultaneously patterning the same material as the connecting electrode CNE.

[0113] The second electrode CE of the OLED light-emitting element can extend into the non-display area NDA and be disposed on the hole control layer HCL. The second electrode CE can also extend into the non-display area NDA and be disposed on the border of the electron control layer ECL, the hole control layer HCL, and the third insulating layer INS3.

[0114] The second electrode CE can extend into the non-display area NDA, thereby being disposed on the first power line PL1 between the bezel of the second dam DM2 and the second insulating layer INS2. The second electrode CE can contact the first power line PL1 and be electrically connected to the first power line PL1. As a result, the first power line PL1 can be electrically connected to the pixel PX.

[0115] The first encapsulation layer EN1 can extend into the non-display area NDA. The first encapsulation layer EN1 can be disposed on the second electrode CE, the first power line PL1, the first barrier DM1, and the second barrier DM2 in the non-display area NDA.

[0116] The second encapsulation layer EN2 can extend into the non-display area NDA. The second encapsulation layer EN2 can be configured up to the second layer DM2. The first encapsulation layer EN1 can extend further into the non-display area NDA than the second encapsulation layer EN2.

[0117] During the manufacturing of the display device DD, a free-flowing organic material can be solidified to form a second encapsulation layer EN2. Even if the free-flowing organic material flows into the non-display area NDA, it will be stopped by the second barrier DM2. Although not shown, organic material that crosses the second barrier DM2 can be further stopped by the first barrier DM1.

[0118] The third encapsulation layer EN3 can extend into the non-display area NDA. The third encapsulation layer EN3 can be disposed on the first encapsulation layer EN1 and the second encapsulation layer EN2 in the non-display area NDA.

[0119] The first sub-dike DM1 may include a first sub-dike DM1_1, a second sub-dike DM1_2 disposed on the first sub-dike DM1_1, and a third sub-dike DM1_3 disposed on the second sub-dike DM1_2. The first sub-dike DM1_1 may include the same material as the second insulating layer INS2. The second sub-dike DM1_2 may include the same material as the third insulating layer INS3. The third sub-dike DM1_3 may include the same material as the pixel definition film PDL.

[0120] The second sub-dike DM2 may include a fourth sub-dike DM2_1 and a fifth sub-dike DM2_2 disposed on the fourth sub-dike DM2_1. The fourth sub-dike DM2_1 may include the same material as the second sub-dike DM1_2. The fifth sub-dike DM2_2 may include the same material as the third sub-dike DM1_3.

[0121] The first sub-dam DM1_1 and the second insulating layer INS2 can be formed simultaneously using the same material through patterning. The second sub-dam DM1_2, the fourth sub-dam DM2_1, and the third insulating layer INS3 can be formed simultaneously using the same material through patterning. The third sub-dam DM1_3, the fifth sub-dam DM2_2, and the pixel definition film PDL can be formed simultaneously using the same material through patterning.

[0122] However, this is only an illustrative example; the first sub-dike DM1_1, the second sub-dike DM1_2, and the third sub-dike DM1_3 can also be formed using materials different from those used for the fourth sub-dike DM2_1 and the fifth sub-dike DM2_2. Furthermore, the first sub-dike DM1_1, the second sub-dike DM1_2, and the third sub-dike DM1_3 can also be formed using materials different from those used for the second insulating layer INS2, the third insulating layer INS3, and the pixel definition film PDL.

[0123] The first power line PL1 can extend between the first sub-dam DM1_1 and the second sub-dam DM1_2, and between the fourth sub-dam DM2_1 and the first insulating layer INS1. The bridging pattern BP can be disposed below the first sub-dam DM1_1, thereby being disposed between the first insulating layer INS1 and the first sub-dam DM1_1. The first power line PL1 can be disposed on the portion of the bridging pattern BP exposed to the outside of the first sub-dam DM1_1, thereby contacting the bridging pattern BP.

[0124] Reference Figure 8 The first power line PL1 and the first sub-dike DM1_1 can extend intersecting each other. For example, the first power line PL1 can extend in the first direction DR1. The first sub-dike DM1_1 can extend in the second direction DR2, intersecting the first power line PL1.

[0125] With the second direction DR2 as a reference, the width of the bridging pattern BP can be greater than the width of the first power line PL1. With the first direction DR1 as a reference, the width of the bridging pattern BP can be greater than the width of the first sub-dam DM1_1. The portion of the bridging pattern BP exposed to the outside of the first sub-dam DM1_1 can overlap with and contact the first power line PL1.

[0126] Reference Figure 6 and Figure 7When the non-display area NDA decreases, the widths of the first dike DM1 and the second dike DM2 may also become narrower. The narrower the width of the first dike DM1, the narrower the width of the upper surface of the first sub-dike DM1_1 may also be.

[0127] When the first power line PL1 is formed on the upper surface of a structure that protrudes upwards, such as the first sub-dike DM1_1, the narrower the width of the upper surface of the first sub-dike DM1_1, the more likely the first power line PL1 on the upper surface of the first sub-dike DM1_1 is to break (non-electrical connection). Therefore, a power supply malfunction may occur, which may result in the inability to properly apply power to each pixel PX.

[0128] However, in the embodiments of the present invention, even if the first power line PL1 disposed on the upper surface of the first sub-dike DM1_1 becomes broken, the first power line PL1 can still be electrically connected through the bridging pattern BP. Therefore, the first voltage can be normally applied to each pixel PX through the first power line PL1, thereby reducing power supply failures.

[0129] Figure 9 and Figure 10 This is a diagram illustrating the cross-sectional configuration of a display device according to other embodiments of the present invention.

[0130] Figure 9 and Figure 10 Examples of the same Figure 6 The corresponding cross-section. Below, in conjunction with... Figure 6 The different compositions shown are the main features, illustrating... Figure 9 and Figure 10 The configurations of the display devices DD_1 and DD_2 are shown. Furthermore, the same configurations are illustrated using the same symbols.

[0131] Reference Figure 9 A recessed portion RES can be defined on the first insulating layer INS1 of the display device DD_1. When viewed in a plane, the recessed portion RES can be defined on the upper surface of the first insulating layer INS1 that overlaps with the first dike DM1. The width of the recessed portion RES can be greater than the width of the first dike DM1 when viewed in a plane.

[0132] A bridging pattern BP can be configured in the recess RES. Since the bridging pattern BP is configured in the recess RES, the bridging pattern BP can be configured more stably in the first insulating layer INS1.

[0133] A first dam DM1 can be configured on the bridging pattern BP. As previously mentioned, a first power line PL1 can be configured on the portion of the bridging pattern BP that is exposed to the outside of the first dam DM1, thereby contacting the bridging pattern BP.

[0134] Reference Figure 10An opening OP can be defined in the first insulating layer INS1 of the display device DD_2. When viewed in a plane, the opening OP can overlap with the first dike DM1. The width of the opening OP can be greater than the width of the first dike DM1 when viewed in a plane.

[0135] A bridging pattern BP can be configured in the opening OP. Because the bridging pattern BP is configured in the opening OP, it can be configured more stably in the first insulating layer INS1.

[0136] A first dam DM1 can be configured on the bridging pattern BP. Inside the opening OP, a first power line PL1 can be configured on the portion of the bridging pattern BP that is exposed to the outside of the first dam DM1, thereby making contact with the bridging pattern BP.

[0137] Figures 11 to 14 This is a diagram illustrating the bridging patterns involved in various embodiments of the present invention.

[0138] Illustratively, Figures 11 to 14 Showing with Figure 8 The corresponding floor plan. Below, in conjunction with... Figure 8 The different compositions shown are the main features, illustrating... Figures 11 to 14 The bridging patterns BP_1 to BP_4 are shown. Furthermore, the same configurations are illustrated using the same symbols.

[0139] Reference Figure 11 The first power line PL1 can extend along the first direction DR1, and the first sub-dam DM1_1 can extend along the second direction DR2. Based on the second direction DR2, the width of the bridging pattern BP_1 can be smaller than the width of the first power line PL1. Based on the first direction DR1, the width of the bridging pattern BP_1 can be larger than the width of the first sub-dam DM1_1. The portion of the bridging pattern BP_1 exposed outside the first sub-dam DM1_1 can contact the first power line PL1.

[0140] Reference Figure 12 The bridging pattern BP_2 can extend in the first direction DR1 and may include multiple sub-bridging patterns SBP arranged in the second direction DR2. Two sub-bridging patterns SBP are illustrated, but the number of sub-bridging patterns SBP is not limited to this and may be more than two.

[0141] With the second direction DR2 as a reference, the width of each sub-bridging pattern SBP can be smaller than the width of the first power line PL1. With the first direction DR1 as a reference, the length of each sub-bridging pattern SBP can be greater than the width of the first sub-dam DM1_1. The portion of each sub-bridging pattern SBP exposed to the outside of the first sub-dam DM1_1 can contact the first power line PL1.

[0142] Reference Figure 13 The bridging pattern BP_3 may have a width smaller than the first power line PL1 based on the second direction DR2, and may have a width larger than the first sub-dam DM1_1 based on the first direction DR1. The bridging pattern BP_3 extends into a continuous curved shape. At least one first opening OP1_1 may be defined in the bridging pattern BP_3. The first opening OP1_1 may have an elliptical shape, but its shape is not limited to this.

[0143] Reference Figure 14 The bridging pattern BP_4 can have a width larger than the first power line PL1 based on the second direction DR2, and a width larger than the first sub-dam DM1_1 based on the first direction DR1. Multiple first openings OP1_2 can be defined in the bridging pattern BP_4. The first openings OP1_2 can be arranged in a matrix and can have a quadrilateral shape.

[0144] Although not illustrated, the first opening OP1_2 can also be defined in... Figure 11 In the bridging pattern BP_1 shown. Additionally... Figures 11 to 14 The bridging patterns BP_1 to BP_4 shown can also be applied to Figure 9 and Figure 10 The display devices DD_1 and DD_2 are shown.

[0145] The above description refers to the embodiments; however, those skilled in the art should understand that various modifications and alterations can be made to the present invention without departing from the spirit and scope of the invention as set forth in the claims. Furthermore, the embodiments disclosed in this invention are not intended to limit the technical concept of the invention, and should be interpreted as including all technical concepts within the scope of the claims and their equivalents within the scope of the claims.

Claims

1. A display device comprising: a substrate including a display region and a non-display region of a periphery of the display region; a pixel provided over the display region; a first bank provided over the non-display region and including a first sub-bank and a second sub-bank provided over the first sub-bank; a second bank provided over the non-display region between the display region and the first bank, a first power supply line provided over the non-display region, and in contact with both sides of the first sub-bank through between the first sub-bank and the second sub-bank, and connected to the pixel; and a bridge pattern provided below the first sub-bank and connected to the first power supply line, wherein the bridge pattern extends outward from both sides of the first sub-bank, and the first power supply line is in contact with both sides of the bridge pattern.

2. The display device according to claim 1, wherein the first power supply line extends in a first direction, and a width of the bridge pattern is larger than a width of the first power supply line with a second direction intersecting the first direction as a reference.

3. The display device according to claim 2, wherein the first sub-bank extends in the second direction, and a width of the bridge pattern is larger than a width of the first sub-bank with the first direction as a reference.

4. The display device according to claim 3, wherein the first power supply line is in contact with the bridge pattern exposed to an outside of the first sub-bank.

5. The display device according to claim 1, wherein the bridge pattern includes a conductive substance.

6. The display device according to claim 1, wherein the pixel includes: a light-emitting element provided over the display region and including a first electrode, a second electrode, and a light-emitting layer provided between the first electrode and the second electrode; and a transistor provided over the display region and connected to the first electrode, the second electrode extends to the non-display region and is connected to the first power supply line.

7. The display device according to claim 6, further comprising: a second power supply line connected to the transistor, the first power supply line receives application of a first voltage, and the second power supply line receives application of a second voltage having a level higher than the first voltage.

8. The display device according to claim 1, wherein the first power supply line is provided below the second bank.

9. The display device according to claim 8, wherein the first bank further includes a third sub-bank provided over the second sub-bank, the second bank includes: a fourth sub-bank; and a fifth sub-bank provided over the fourth sub-bank, the second sub-bank includes a same substance as the fourth sub-bank, the third sub-bank includes a same substance as the fifth sub-bank.

10. The display device according to claim 9, further comprising: a first insulating layer provided over the substrate, the first bank and the second bank are provided over the first insulating layer, and the bridge pattern is provided between the first insulating layer and the first sub-bank.

11. The display device according to claim 10, wherein ​ The first power line extends between the fourth subbank and the first insulating layer.

12. The display device according to claim 10, wherein The bridge pattern is arranged in a recess defined in an upper surface of the first insulating layer.

13. The display device according to claim 10, wherein The bridge pattern is arranged in an opening defined in the first insulating layer.

14. The display device according to claim 1, wherein The first power line extends in a first direction, and the first subbank extends in a second direction intersecting the first direction, With the second direction as a reference, a width of the bridge pattern is smaller than a width of the first power line, and with the first direction as a reference, the width of the bridge pattern is larger than a width of the first subbank.

15. The display device according to claim 14, wherein The bridge pattern includes a plurality of sub-bridge patterns extending in the first direction and arranged in the second direction.

16. The display device according to claim 1, wherein At least one first opening is defined in the bridge pattern.

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