Embedded device

Abstract

The embedded device includes a first insulating layer; a second insulating layer on the first insulating layer; a lower electrode contact in the first insulating layer in a first region; a first structure in the second insulating layer and contacting the lower electrode contact, the first structure having a lower electrode, a magnetic tunnel junction, and an upper electrode; a first metal wiring structure through the first and second insulating layers in a second region; a third insulating layer on the second insulating layer; a bit line structure through the third insulating layer and the second insulating layer in the first region, the bit line structure having a first height and contacting the upper electrode; and a second metal wiring structure through the third insulating layer in the second region, the second metal wiring structure contacting the first metal wiring structure and having a second height that is lower than the first height.

Description

Technical Field

[0001] The example implementation relates to a semiconductor device and a method of manufacturing the same. More specifically, the example implementation relates to an embedded device including a magnetoresistive random access memory (MRAM) device and a method of manufacturing the same. Background Technology

[0002] Embedded devices can be provided in which magnetic tunnel junction (MTJ) modules can be inserted into the back-end process (BEOL) routing of the logic device. In this case, the BEOL routing layout can be designed to add the MTJ module without changing the layout and / or architecture of the logic device. Summary of the Invention

[0003] According to an example embodiment, an embedded device is provided, which may include a first molded insulating layer, a second molded insulating layer, a lower electrode contact, a first structure, a first metal wiring structure, a third molded insulating layer, a bit line structure, and a second metal wiring structure. The first molded insulating layer may be formed on a substrate including a first region and a second region. The second molded insulating layer may be formed on the first molded insulating layer. The lower electrode contact may be formed in the first molded insulating layer in the first region. The first structure may be formed in the second molded insulating layer in the first region. The first structure may contact the upper surface of the lower electrode contact. The first structure may include a stacked lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode. The first metal wiring structure may pass through the first and second molded insulating layers in the second region. The third molded insulating layer may be formed on the second molded insulating layer. The bit line structure may pass through the upper portion of the second molded insulating layer and the third molded insulating layer in the first region, and the bit line structure contacts the upper electrode. The second metal wiring structure may pass through the third molded insulating layer in the second region, and the second metal wiring structure may contact the first metal wiring structure. The second metal wiring structure may have a second height in a vertical direction, and the bit line structure may have a first height in a vertical direction higher than the second height.

[0004] According to an example embodiment, an embedded device is provided, which may include a first molded insulating layer, a second molded insulating layer, a lower electrode contact, a first structure, a first metal wiring structure, a third molded insulating layer, a bit line structure, and a second metal wiring structure. The first molded insulating layer may be formed on a substrate including a first region and a second region. The second molded insulating layer may be formed on the first molded insulating layer. The lower electrode contact may be formed in the first molded insulating layer in the first region. The first structure may be formed in the second molded insulating layer in the first region. The first structure may contact the upper surface of the lower electrode contact. The first structure may include a stacked lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode. The first metal wiring structure may pass through the first and second molded insulating layers in the second region. The third molded insulating layer may be formed on the second molded insulating layer. The bit line structure may pass through the upper portion of the second molded insulating layer and the third molded insulating layer in the first region. The bit line structure may contact the upper electrode. The second metal wiring structure may pass through the third molded insulating layer in the second region. The second metal wiring structure may contact the first metal wiring structure. The height of the bit line structure in the vertical direction may be different from the height of the second metal wiring structure in the vertical direction. The shape of the bitline structure is different from the shape of the second metal wiring structure.

[0005] According to an example embodiment, an embedded device is provided, which may include a substrate, a lower electrode contact, a first structure, a first metal wiring structure, a bit line structure, and a second metal wiring structure. The substrate may include a first region and a second region. The lower electrode contact may contact the substrate in the first region. The first structure may contact the upper surface of the lower electrode contact. The first structure may include a stacked lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode. The first metal wiring structure may be formed on the substrate in the second region. The upper surface of the first metal wiring structure may be higher than the upper surface of the first structure. The bit line structure may contact the upper electrode of the first structure. The second metal wiring structure may contact the first metal wiring structure. The height of the bit line structure in the vertical direction may differ from the height of the second metal wiring structure in the vertical direction.

[0006] vertical direction Attached Figure Description

[0007] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0008] Figure 1 and Figure 2 This is a cross-sectional view showing an embedded device according to an example embodiment;

[0009] Figure 3 yes Figures 1-2 A perspective view of the bit line structure and metal wiring structure in an embedded device;

[0010] Figure 4 yes Figures 1-2 A plan view of the upper surface of the bit line structure and metal wiring structure in an embedded device;

[0011] Figure 5 This is a plan view of the area of ​​the embedded device according to the example implementation;

[0012] Figures 6 to 18 This is a cross-sectional view illustrating multiple stages in a method for manufacturing an embedded device according to an exemplary embodiment;

[0013] Figure 19 and Figure 20 This is a cross-sectional view showing an embedded device according to an example embodiment;

[0014] Figure 21 yes Figures 19-20 A perspective view of the bit line structure and metal wiring structure in an embedded device;

[0015] Figure 22 and Figure 23 This is a cross-sectional view illustrating multiple stages in a method for manufacturing an embedded device according to an exemplary embodiment;

[0016] Figure 24 This is a cross-sectional view showing an embedded device according to an example embodiment; and

[0017] Figures 25 to 29 This is a cross-sectional view illustrating multiple stages in a method for manufacturing an embedded device according to an example embodiment. Detailed Implementation

[0018] In the following text, the two directions parallel to the substrate and perpendicular to each other are referred to as the first direction and the second direction, respectively. The direction in which the bit lines of the embedded device extend is described as the second direction.

[0019] Figure 1 and Figure 2 The images are cross-sectional views along the first and second directions, respectively, illustrating an embedded device according to an example embodiment. Figure 3 They are shown respectively Figures 1-2 A perspective view of the bit line structure and metal wiring structure in an embedded device. Figure 4 A plan view of the upper surface of the bit line structure and metal wiring structure in an embedded device is shown. Figure 5 This is a plan view of the area of ​​an embedded device according to an example implementation.

[0020] Figure 1 It is a cross-sectional view cut in the first direction. Figure 2 It is a cross-sectional view cut in the second direction.

[0021] Reference Figure 5 The embedded device 10 may include an MRAM region 3 and a logic device region 4. The MRAM region 3 may include an MRAM cell region 1 and a core / peripheral region 2. Hereinafter, the MRAM cell region 1 is referred to as the first region including the MTJ module, and the logic device region 4 and the core / peripheral region 2 are referred to as the second region excluding the MTJ module.

[0022] Reference Figure 1 and Figure 2 A circuit pattern can be formed on the substrate 100, which includes a first region I and a second region II. A lower insulating layer 102 can cover the circuit pattern. A first lower wiring can be formed in the lower insulating layer 102.

[0023] Substrate 100 may include III-V compounds, such as silicon, germanium, silicon-germanium, or GaP, GaAs, GaSb. In some example embodiments, substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0024] The circuit pattern formed on the substrate 100 in the first region I may include selection devices (e.g., selection transistors) constituting memory cells. The circuit pattern formed on the substrate 100 in the second region II may include a plurality of logic transistors constituting logic circuits or peripheral circuits.

[0025] In an example embodiment, the lower insulating layer 102 may include multiple insulating interlayers, and the first lower wiring may be formed as a multilayer within the insulating interlayers. The lower insulating layer 102 may include, for example, silicon oxide. In some example embodiments, an etch stop layer may be further formed between the insulating interlayers. The first lower wiring may include contact plugs and conductive patterns. The first lower wiring may include, for example, polysilicon or metal.

[0026] An upper insulating layer 104 may be formed on a lower insulating layer 102. A second lower wiring 109 may be formed in the upper insulating layer 104 on the first region I and the second region II. The second lower wiring 109 may include a contact plug 109a and a lower conductive pattern 109b on the contact plug 109a. The upper surface of the upper insulating layer 104 and the upper surface of the second lower wiring 109 may be coplanar with each other.

[0027] In an example implementation, the lower conductive pattern 109b included in the second lower wiring 109 can directly contact the lower electrode contact 116 of the MTJ module. The second lower wiring 109 may include metal.

[0028] In an example implementation, the second lower wiring 109 may include a first blocking pattern 108a and a first conductive pattern 108b. The first blocking pattern 108a may be formed around the sidewalls and bottom of the first conductive pattern 108b. The first blocking pattern 108a may include metal nitrides such as tungsten nitride, tantalum nitride, and titanium nitride, and / or metals such as tantalum and titanium. The first conductive pattern 108b may include copper.

[0029] The contact plug 109a may have a cylindrical shape. In an example embodiment, in a cross-sectional view, the contact plug 109a may have a first width W1 in a first direction and may also have a first width W1 in a second direction. The upper surface of the contact plug 109a may be, for example, a circular shape with a diameter having a first width W1, as seen from the top view. Hereinafter, in the cross-sectional view, the width in each of the first and second directions may be the maximum width in each of the first and second directions.

[0030] The lower conductive pattern 109b may have a second width W2 in the first direction, which is greater than the first width W1. In an example embodiment, the lower conductive pattern 109b may be linear. The vertical height of the second lower wiring 109 may be a second height h2.

[0031] As described above, the contact plug 109a may have a first width W1 in the first direction, and the lower conductive pattern 109b may have a second width W2 in the first direction. Furthermore, the second lower wiring 109 may have a second height h2. In the example embodiment, the second height h2 may be approximately... To about Within a certain range. The ratio of the first width W1 to the second width W2 can be approximately 1:1.05 to approximately 1:1.5. The first width W1 can be approximately... To about Within the range. The dimension of the second lower wiring 109 can be referred to as the first design rule.

[0032] The first etch stop layer 112 and the first molding insulating layer 114 may be stacked on the upper insulating layer 104 and the second lower wiring 109 in the first region I and the second region II. The first molding insulating layer 114 may include an oxide, such as silicon oxide. The first etch stop layer 112 may include, for example, silicon nitride or silicon carbon nitride.

[0033] The lower electrode contact 116 can penetrate the first molded insulating layer 114 and the first etch stop layer 112 in the first region I to contact the second lower wiring 109. In an example embodiment, the lower electrode contact 116 may include a barrier pattern 116a and a conductive pattern 116b.

[0034] The first structure 138 can be formed on the lower electrode contact 116. The first structure 138 can be formed on the lower electrode contact 116 and the first molded insulating layer 114 adjacent to the lower electrode contact 116. Therefore, the first structure 138 can, for example, completely cover the upper surface of the lower electrode contact 116.

[0035] The first structure 138 may have a cylindrical shape in which the lower electrode 118, MTJ structure 132, intermediate electrode 124a, and upper electrode 126a are sequentially stacked. The lower electrode contact 116 and the first structure 138 may serve as an MTJ module. For example, in some exemplary embodiments, the intermediate electrode may not be included in the first structure 138.

[0036] In an example embodiment, the sidewalls of the first structure 138 may have an inclination such that the width of the first structure 138, for example, in a first and / or second direction, may gradually increase downwards (i.e., towards the substrate 100). In some example embodiments, the sidewalls of the first structure 138 may be vertical.

[0037] In an example embodiment, the upper surface of the first molded insulating layer 114 may not be flat. The upper surface of the first molded insulating layer 114 between the first structures 138 may be lower than the bottom of the first structure 138. Therefore, the upper surface of the first molded insulating layer 114 between the first structures 138 may include recessed portions, for example, recessed portions bent toward the substrate 100. In an example embodiment, the upper surface of the first molded insulating layer 114 in the second region II may be lower than the upper surface of the first molded insulating layer 114 in the first region I.

[0038] The lower electrode 118 may include at least one of a metal (e.g., titanium, tantalum) and a metal nitride (e.g., titanium nitride or tantalum nitride).

[0039] The MTJ structure 132 may include a stacked first magnetic pattern 132a, a tunnel barrier pattern 132b, and a second magnetic pattern 132c.

[0040] In an exemplary embodiment, the first magnetic pattern 132a can be used as a fixed layer having a fixed magnetization direction. In an exemplary embodiment, the first magnetic pattern 132a may include a fixed pattern, a lower ferromagnetic pattern, an antiferromagnetic coupling spacer pattern, and an upper ferromagnetic pattern. In this case, the fixed pattern may include, for example, ferromanganese (FeMn), iridium manganese (IrMn), platinum manganese (PtMn), manganese oxide (MnO), manganese sulfide (MnS), manganese telluride (MnTe), manganese fluoride (MnF2), ferric fluoride (FeF2), ferric chloride (FeCl2), iron oxide (FeO), cobalt chloride (CoCl2), cobalt oxide (CoO), nickel chloride (NiCl2), nickel oxide (NiO), chromium (Cr), etc. The upper and lower ferromagnetic patterns may include ferromagnetic materials, for example, at least one of iron (Fe), nickel (Ni), and cobalt (Co). The antiferromagnetic coupling spacer pattern may include, for example, at least one of ruthenium (Ru), iridium (Ir), and rhodium (Rh).

[0041] In an example embodiment, the second magnetic pattern 132c can be used as a free layer with a variable magnetization direction. In this case, the second magnetic pattern 132c can include ferromagnetic materials, such as iron (Fe), cobalt (Co), nickel (Ni), chromium (Cr), and platinum (Pt). The second magnetic pattern 132c can further include, for example, boron (B) or silicon (Si). These can be used alone or in combination of two or more. For example, the second magnetic pattern 132c can include composite materials, such as CoFe, NiFe, FeCr, CoFeNi, PtCr, CoCrPt, CoFeB, NiFeSiB, CoFeSiB, etc.

[0042] The tunnel barrier pattern 132b can be formed between the first magnetic pattern 132a and the second magnetic pattern 132c. Therefore, the first magnetic pattern 132a and the second magnetic pattern 132c do not need to be in direct contact with each other.

[0043] In an example implementation, the tunnel barrier pattern 132b may include a metal oxide with insulating properties. For example, the tunnel barrier pattern 132b may include magnesium oxide (MgOx) or aluminum oxide (AlOx).

[0044] The intermediate electrode 124a may include at least one of a metal (e.g., titanium, tantalum) and a metal nitride (e.g., titanium nitride or tantalum nitride).

[0045] The upper electrode 126a may include, for example, tungsten, copper, platinum, nickel, silver, gold, etc. For example, the upper electrode 126a may include tungsten.

[0046] The capping layer 140 can be conformally formed on the surfaces of the first structure 138 and the first molded insulating layer 114 in the first region I and the second region II. The capping layer 140 can cover the sidewalls of the first structure 138 and the upper surface of the first molded insulating layer 114. The capping layer 140 can have a substantially uniform thickness. The capping layer 140 can contact the sidewalls of the first structure 138 to protect the first structure 138. The capping layer 140 can include, for example, silicon nitride, silicon oxide, etc.

[0047] The upper surface of the cover layer 140 formed on the first molded insulating layer 114 may have a recessed portion that is lower than the bottom of the first structure 138. That is, the recessed portion of the cover layer 140 can be formed by transferring (e.g., drawing) the recessed portion of the upper surface of the first molded insulating layer 114.

[0048] A second molded insulating layer 142 may be formed on the cover layer 140 in the first region I and the second region II. The second molded insulating layer 142 may fill the gaps between the first structures 138. The second molded insulating layer 142 may include an oxide, such as silicon oxide.

[0049] The upper surface of the second molded insulating layer 142 may be higher than the top surface of the first structure 138. In an example embodiment, the thickness of the second molded insulating layer 142 disposed on the upper surface of the first structure 138 (e.g., its height along a direction perpendicular to the upper surface of the substrate) may be approximately To about Within the range.

[0050] In exemplary embodiments, the upper surfaces of the second molded insulating layer 142 in the first region I and the second region II may be substantially flat. In some exemplary embodiments, the upper surface of the second molded insulating layer 142 in the second region II may be lower than the upper surface of the second molded insulating layer 142 in the first region I.

[0051] A first trench 144 may be formed on a portion of the second molded insulating layer 142 in the second region II. A first via 146 may communicate with the bottom of the first trench 144, for example, the first via 146 may be in fluid communication with the first trench 144 to define an combined opening, and the first via 146 may pass through the second molded insulating layer 142 and the first etch stop layer 112 to expose the upper surface of the second lower wiring 109. The first trench 144 may have a second width W2 in a first direction, and the first via 146 may have a first width W1 in the first direction.

[0052] The second blocking pattern 152a and the second conductive pattern 152b can be formed in the first through hole 146 and the first trench 144.

[0053] The second blocking pattern 152a may be conformally formed on the sidewalls and bottom of the first trench 144 and the first through-hole 146. A second conductive pattern 152b may be formed on the second blocking pattern 152a to fill the first through-hole 146 and the first trench 144. The conductive material filling the first through-hole 146 may be used as the first via contact 153a. The conductive material filling the first trench 144 may be used as the first metallic wiring 153b. The second blocking pattern 152a may include at least one of the materials used to form the first blocking pattern 108a. The second conductive pattern 152b may include copper. The first via contact 153a may contact the second lower wiring 109, thereby allowing the first via contact 153a to be electrically connected to the second lower wiring 109.

[0054] The first path contact 153a and the first metal wiring 153b can be used as the first metal wiring structure 153. The upper surface of the second molded insulating layer 142 and the upper surface of the first metal wiring 153b can be substantially coplanar with each other, and the upper surfaces of the second molded insulating layer 142 and the first metal wiring 153b can have the same height in the vertical direction. Therefore, the height of the structure in which the first molded insulating layer 114, the cover layer 140 and the second molded insulating layer 142 are stacked can be substantially the same as the height of the first metal wiring structure 153.

[0055] The first path contact 153a may have a cylindrical shape. In an example embodiment, the upper surface of the first path contact 153a may have a first width W1 in each of the first and second directions. The upper surface of the first path contact 153a may be a circular shape with a diameter having a first width W1.

[0056] The first metal wiring 153b may have a second width W2 in a first direction. The first metal wiring 153b may have a linear shape. Furthermore, the first metal wiring structure 153 may have a second height h2 in the vertical direction. That is, the first metal wiring structure 153 may have a first design rule.

[0057] In the example embodiment, the upper surface of the MTJ module may be lower than the upper surface of the first metal wiring structure 153. The vertical height of the MTJ module may be lower than the vertical height h2 of the first metal wiring structure 153. A second molded insulating layer 142 may be formed on the MTJ module.

[0058] As described above, an MTJ module can be formed in the first molded insulating layer 114, the cover layer 140, and the second molded insulating layer 142 on the first region I. A first metal wiring structure 153, including a first through contact 153a and a first metal wiring 153b, can be formed in the first molded insulating layer 114, the cover layer 140, and the second molded insulating layer 142 on the second region II.

[0059] The second etch stop layer 154 may cover the upper surface of the second molded insulating layer 142 and the first metal wiring structure 153 in the first region I and the second region II. The third molded insulating layer 156 may be stacked on the second etch stop layer 154.

[0060] The third molding insulating layer 156 may include an oxide, such as silicon oxide. The second etch stop layer 154 may include, for example, silicon nitride, silicon carbon nitride, etc. The upper surface of the third molding insulating layer 156 in the first region I and the second region II may be substantially flat.

[0061] The second trench 164 may be formed on a portion of the third molded insulating layer 156 in the second region II. Furthermore, the second via 166 may communicate with the bottom of the second trench 164, and the second via 166 may pass through the third molded insulating layer 156 and the second etch stop layer 154 to expose the upper surface of the first metal wiring 153b.

[0062] The second groove 164 may have a second width W2 in the first direction. The second through hole 166 may have a first width W1 in each of the first and second directions. The second groove 164 may extend in the second direction.

[0063] A third blocking pattern 180a and a third conductive pattern 180b can be formed in the second via 166 and the second trench 164. The third blocking pattern 180a can be conformally formed on the sidewalls and bottom of the second trench 164 and the second via 166. The third conductive pattern 180b can be formed to fill the second via 166 and the second trench 164 on the third blocking pattern 180a. The metallic material filling the second via 166 can be used as a second via contact 186a. The metallic material filling the second trench 164 can be used as a second metallic wiring 186b.

[0064] The second path contact 186a and the second metal wiring 186b can be used as the second metal wiring structure 186. The second path contact 186a can contact the first metal wiring 153b, such that the second path contact 186a can be electrically connected to the first metal wiring 153b. The first metal wiring structure 153 and the second metal wiring structure 186 can be electrically connected to each other.

[0065] exist Figure 3 and Figure 4 In the middle, the second pathway contact 186a is shown on the right.

[0066] Reference Figure 3 and Figure 4The upper surface of the second passage contact 186a may have a first width W1 in each of the first and second directions. That is, the upper surface of the second passage contact 186a may have a circular shape with a diameter equal to the first width W1. The second passage contact 186a may also have a cylindrical shape, for example, a cylindrical shape along the longitudinal direction of the vertical direction.

[0067] The second metal wiring 186b may have a second width W2 in the first direction. For example, as Figure 3 As shown, the second metal wiring 186b can have a rectangular prism shape, having a longitudinal direction along the second direction, a second width W2 along the first direction, and a second upper height h2a along the vertical direction. For example, the second metal wiring 186b can extend continuously along the second direction to connect to a plurality of second path contacts 186a. For example, as... Figure 3 As shown, in the first direction, the second width W2 can be greater than the first width W1. For example, the bottom of the second metal wiring 186b can completely overlap in the first and second directions and extend beyond the second passage contact 186a.

[0068] The second metal wiring structure 186 may have a second height h2 in the vertical direction. That is, the second metal wiring structure 186 may have a first design rule. The second path contact 186a may have a second lower height h2b in the vertical direction, and the second metal wiring 186b may have a second upper height h2a in the vertical direction, that is, the second height h2 may be equal to the sum of the second upper height h2a and the second lower height h2b.

[0069] The third trench 160 may be formed on a portion of the third molded insulating layer 156 in the first region I. Furthermore, the bit line contact hole 162 may communicate with the bottom of the third trench 160, and the bit line contact hole 162 may pass through the third molded insulating layer 156, the second etch stop layer 154, the second molded insulating layer 142, and the capping layer 140 to expose the upper surface of the upper electrode 126a.

[0070] The third groove 160 may have a second width W2 in the first direction. The bit line contact hole 162 may have a first width W1 in the first direction and a third width W3 in the second direction that is greater than the first width W1.

[0071] A fourth blocking pattern 180c and a fourth conductive pattern 180d can be formed in the bit line contact hole 162 and the third trench 160. The fourth blocking pattern 180c can be conformally formed on the sidewalls and bottom of the third trench 160 and the bit line contact hole 162. The fourth conductive pattern 180d can be formed to fill the bit line contact hole 162 and the third trench 160 on the fourth blocking pattern 180c. The conductive material filling the bit line contact hole 162 can be used as a bit line contact 182a. The conductive material filling the third trench 160 can be used as a bit line 182b. Bit line contacts 182a and bit lines 182b can be used as a bit line structure 182. The upper surfaces of the third molded insulating layer 156, the second metal wiring structure 186, and the bit line structure 182 can be coplanar with each other.

[0072] When the fourth barrier pattern 180c and the third barrier pattern 180a are formed using the same process, the fourth barrier pattern 180c and the third barrier pattern 180a may comprise the same material. Since the fourth conductive pattern 180d and the third conductive pattern 180b are formed using the same process, the fourth conductive pattern 180d and the third conductive pattern 180b may comprise the same material. For example, the fourth conductive pattern 180d may comprise copper.

[0073] Bit line contact 182a can contact upper electrode 126a, thereby bit line contact 182a can be electrically connected to upper electrode 126a.

[0074] exist Figure 3 and Figure 4 In the middle, bit line contact 182a is shown on the left.

[0075] Reference Figure 3 and Figure 4 The upper surface of the bit line contact 182a may have a first width W1 in a first direction and a third width W3 in a second direction. That is, the upper surface of the bit line contact 182a may have an elliptical shape with a longer length in the second direction. The bit line contact 182a may have a cylindrical shape, for example, an elliptical cylindrical shape along the longitudinal direction of the vertical direction.

[0076] Bit line 182b may extend in a second direction. Bit line 182b may have a second width W2 in the first direction. For example, as... Figure 3 As shown, bit line 182b may have a rectangular prism shape, having a longitudinal direction along the second direction, a second width W2 along the first direction, and a first upper height h1a along the vertical direction. For example, bit line 182b may extend continuously along the second direction to connect to a plurality of bit line contacts 182a.

[0077] Bit line structure 182 may have a first height h1 in the vertical direction. The first height h1 may be higher than a second height h2; for example, the total first height h1 may be greater than the total second height h2. Bit line contact 182a may have a first lower height h1b, and bit line 182b may have a first upper height h1a. The first lower height h1b of bit line contact 182a may be higher than the second lower height h2b of second via contact 186a; for example, the total first lower height h1b may be greater than the total second lower height h2b. Furthermore, the bottom of bit line structure 182 may be lower than the bottom of second metal wiring structure 186; for example, the distance between the bottom of bit line structure 182 and the top of substrate 100 may be less than the distance between the bottom of second metal wiring structure 186 and the top of substrate 100. Figures 1-2 ).

[0078] As described above, when viewed at the same horizontal level, the bit line structure 182 can have a shape different from that of the second metal wiring structure 186. For example, the top surface of the bit line contact 182a and the top surface of the second passage contact 186a have different shapes. Furthermore, the bit line structure 182 can have a height different from that of the second metal wiring structure 186. For example, the heights of the bit line contact 182a and the second passage contact 186a along the vertical direction are different. The bit line contact 182a can have a shape different from that of the second passage contact 186a. In particular, the height of the bit line contact 182a can be higher than the height of the second passage contact 186a. The bottom of the bit line contact 182a can be lower than the bottom surface of the second passage contact 186a. In this case, the width of the bit line contact 182a in the second direction can be greater than the width of the second passage contact 186a. That is, the volume of the bit line contact 182a can be greater than the volume of the second passage contact 186a.

[0079] When bit line contact 182a and second path contact 186a are formed simultaneously, the metal material can easily fill bit line contact hole 162 (i.e., a larger hole that accommodates a larger contact volume). Therefore, defects in bit line contact 182a can be reduced.

[0080] As described above, since the height of the bit line contact 182a is greater than the height of the second path contact 186a (and extends lower), the upper surface of the MTJ module (i.e., below the bit line contact 182a) can be lower than the upper surface of the first metal wiring structure 153 (i.e., below the second path contact 186a). Therefore, the MTJ module can be disposed within the height of the portion forming the first metal wiring structure 153. Thus, even if the MTJ module is formed, the layout of the wiring structure can be maintained.

[0081] Furthermore, the stacked structure including the MTJ module and bit line structure 182 can be disposed within the height of the stacked portion of the first metal wiring structure 153 and the second metal wiring structure 186. Therefore, even if bit line 182b is formed, the layout of the wiring structure does not need to be changed. Thus, the MTJ module and bit line structure 182 can be formed in the first region I while minimizing changes in the process used to form the logic device (e.g., the wiring process of the logic structure).

[0082] Figures 6 to 18 This is a cross-sectional view illustrating multiple stages in a method for manufacturing an embedded device according to an example embodiment.

[0083] Reference Figure 6 The selection device included in the memory cell can be formed on the substrate 100 in the first region I. A plurality of logic transistors included in the logic circuit or peripheral circuit can be formed on the substrate 100 in the second region II.

[0084] The lower insulating layer 102 may be formed on the substrate 100 of the first region I and the second region II to cover the selection device and the logic transistor. A first lower wiring including contact plugs and conductive patterns may be further formed in the lower insulating layer 102.

[0085] An upper insulating layer 104 may be formed on a lower insulating layer 102. A second lower wiring 109, including a contact plug 109a and a lower conductive pattern 109b, may be formed in the upper insulating layer 104 on the first region I and the second region II.

[0086] In the example embodiment, the contact plug 109a and the lower conductive pattern 109b can be formed by a damascene process. For example, a portion of the upper insulating layer 104 can be etched to form trenches and vias. The vias can communicate with the trenches and can expose the conductive pattern of the first lower wiring. The order in which the trenches and vias are formed is not limited. That is, the trenches can be formed first. Alternatively, the vias can be formed first. A first barrier layer and a first metal layer can be formed on the trenches, vias, and upper insulating layer 104. The first barrier layer and the first metal layer can be planarized until the upper surface of the upper insulating layer 104 can be exposed to form the second lower wiring 109. The second lower wiring 109 may include the first barrier pattern 108a and the first conductive pattern 108b.

[0087] The first etch stop layer 112 can be formed on the upper insulating layer 104 and the second lower wiring 109 in the first region I and the second region II.

[0088] Reference Figure 7A first molding insulating layer 114 can be formed on the first etch stop layer 112. The first molding insulating layer 114 and the first etch stop layer 112 in the first region I can be etched to form a lower electrode contact hole through the first molding insulating layer 114 and the first etch stop layer 112. A lower electrode contact 116 can be formed in the lower electrode contact hole. The lower electrode contact 116 can contact the second lower wiring 109 in the first region I.

[0089] Reference Figure 8 The lower electrode layer 117, the MTJ layer 120, and the intermediate electrode layer 124 can be sequentially formed on the first molded insulating layer 114 and the lower electrode contact 116. The upper electrode layer 126 and the adhesive layer 128 can be sequentially formed on the intermediate electrode layer 124. The mask pattern 130 can be formed on the adhesive layer 128.

[0090] The MTJ layer 120 may include a stacked first magnetic layer 120a, a tunnel barrier layer 120b, and a second magnetic layer 120c. In some example embodiments, the intermediate electrode layer 124 may not be formed.

[0091] The adhesive layer 128 can be formed to readily attach the mask pattern 130 thereon. In an example embodiment, the adhesive layer 128 may include a nitride, such as a silicon nitride, silicon oxide nitride, etc.

[0092] The mask pattern 130 can be configured to face the lower electrode contact 116. The mask pattern 130 can be formed only in the first region I, and may not be formed in the second region II. The mask pattern 130 can be cylindrical. In an example embodiment, multiple mask patterns 130 can be arranged regularly. In an example embodiment, the mask pattern 130 may include, for example, silicon oxide.

[0093] Reference Figure 9 The mask pattern 130 can be used as an etching mask to anisotropically etch the adhesive layer 128 and the upper electrode layer 126. The anisotropic etching process may include a reactive ion etching (RIE) process. When performing the etching process, the upper electrode 126a and the adhesive layer pattern can be formed on the intermediate electrode layer 124.

[0094] The intermediate electrode layer 124, MTJ layer 120, and lower electrode layer 117 can be sequentially etched using the structure in which the upper electrode 126a, adhesive layer pattern, and mask pattern 130 are stacked as an etching mask. Furthermore, the upper portion of the first molded insulating layer 114 can be partially etched.

[0095] Therefore, a first structure 138 comprising a stack of a lower electrode 118, an MTJ structure 132, an intermediate electrode 124a, and an upper electrode 126a can be formed on the first molded insulating layer 114. Grooves can be formed on the upper surface of the first molded insulating layer 114 between the first structures 138.

[0096] In an example embodiment, during the etching process, the etching rate of the first molding insulating layer 114, which does not have the mask pattern 130 in the second region II, can be higher than the etching rate of the first molding insulating layer 114 in the first region I. Therefore, the upper surface of the first molding insulating layer 114 in the second region II can be lower than the upper surface of the first molding insulating layer 114 in the first region I.

[0097] In the etching process, the mask pattern 130 and the adhesive layer pattern can be removed. In the example embodiment, the upper portion of the upper electrode 126a can be partially etched.

[0098] Reference Figure 10 A cover layer 140 may be conformally formed on the surfaces of the first structure 138 and the first molded insulating layer 114. A second molded insulating layer 142 may be formed on the cover layer 140.

[0099] The capping layer 140 may cover the upper surfaces of the first structure 138 and the first molded insulating layer 114. The capping layer 140 may be formed to have a uniform thickness. In an example embodiment, the capping layer 140 may be formed by an atomic layer deposition process or a chemical vapor deposition process.

[0100] In an example embodiment, the upper surface of the cover layer 140 formed on the first molded insulating layer 114 may be lower than the bottom of the first structure 138, and therefore the upper surface of the cover layer 140 formed on the first molded insulating layer 114 may have a recessed portion. In some example embodiments, the upper surface of the cover layer 140 in the second region II may be substantially the same as or lower than the cover layer 140 formed on the first molded insulating layer 114 in the first region I.

[0101] The second molded insulating layer 142 can be formed to fill the gaps between the first structures 138.

[0102] In a subsequent polishing process, a portion of the second molded insulating layer 142 may be consumed. In this case, for example, when the upper surface of the first structure 138 is exposed, defects may occur. Therefore, the second molded insulating layer 142 can be formed to fully cover the first structure 138, thereby preventing defects from occurring. In an example embodiment, the upper surface of the second molded insulating layer 142 may be higher than the top surface of the first structure 138. In an example embodiment, the thickness of the second molded insulating layer 142 disposed on the top surface of the first structure 138 may be approximately To about Within the range.

[0103] In example embodiments, the upper surface of the second molded insulating layer 142 in the first region I and the second region II may be substantially flat. In some example embodiments, the upper surface of the second molded insulating layer 142 in the first region I may be higher than the upper surface of the second molded insulating layer 142 in the second region II.

[0104] Reference Figure 11 A first trench 144 may be formed on the upper portion of the second molded insulating layer 142 in the second region II. A first via 146 may be formed to pass through the second molded insulating layer 142, the cover layer 140, the first molded insulating layer 114, and the first etch stop layer 112 formed below the first trench 144.

[0105] In an example embodiment, the upper portion of the second molded insulating layer 142 in the second region II may be partially etched to form a first trench 144 extending in one direction. The first trench 144 may have a second width W2 in the first direction.

[0106] An etch mask exposing a portion of the first trench 144 can be formed on the second molding insulating layer 142. The second molding insulating layer 142, the cover layer 140, the first molding insulating layer 114, and the first etch stop layer 112 formed beneath the first trench 144 can be sequentially etched using the etch mask to form a first via 146. The first via 146 may have a first width W1 in each of a first direction and a second direction. As described above, the first trench 144 can be formed first. Alternatively, the first via 146 can be formed first, followed by the first trench 144.

[0107] Reference Figure 12 A second barrier layer 150a may be conformally formed on the surfaces of the first trench 144 and the first through-hole 146, as well as on the upper surface of the second molded insulating layer 142. A second conductive layer 150b may be formed on the second barrier layer 150a to fill the first trench 144 and the first through-hole 146.

[0108] Reference Figure 13 The upper surfaces of the second conductive layer 150b and the second barrier layer 150a can be planarized until the upper surface of the second molded insulating layer 142 can be exposed to form a second barrier pattern 152a and a second conductive layer pattern 152b that fill the first trench 144 and the first through hole 146.

[0109] Planarization processes may include chemical mechanical polishing (CMP). After performing a CMP process, the upper electrode 126a in the first region I may not be exposed. In an example embodiment, only the upper surface of the second molded insulating layer 142 may be exposed in the first region. For example, the thickness of the second molded insulating layer 142 disposed on the top surface of the first structure 138 may be approximately [thickness missing]. To about Within the range.

[0110] In some example implementations, the upper surface of the second molded insulating layer 142 and a portion of the cover layer 140 may be exposed in the first region I.

[0111] Through the above processes, a first via contact 153a can be formed to fill the first through hole 146, and a first metal wiring 153b can be formed to fill the first trench 144. The first via contact 153a and the first metal wiring 153b can be used as a first metal wiring structure 153. The vertical height of the first metal wiring structure 153 can be approximately... To about Within the range.

[0112] Reference Figure 14 A second etch stop layer 154 can be formed on the second molded insulating layer 142 and the first metal wiring 153b. A third molded insulating layer 156 can be formed on the second etch stop layer 154.

[0113] Reference Figure 15 and Figure 16 A third trench 160 can be formed on the third molded insulating layer 156 in the first region I, and a second trench 164 can be formed on the third molded insulating layer 156 in the second region II. A bit line contact hole 162 can pass through the third molded insulating layer 156, the second etch stop layer 154, the second molded insulating layer 142, and the capping layer 140 below the third trench 160 in the first region I. The bit line contact hole 162 can expose the upper electrode 126a. Furthermore, a second via 166 can pass through the third molded insulating layer 156 and the second etch stop layer 154 below the second trench 164 in the second region II. The second via 166 can expose the first metal wiring 153b.

[0114] The bit line contact hole 162 may have a first width W1 in a first direction and a third width W3 in a second direction. In a plan view, the bit line contact hole 162 may have an elliptical shape, the width of which in the second direction is greater than its width in the first direction. The second through hole 166 may have a first width W1 in both the first and second directions. In a plan view, the second through hole 166 may have a circular shape. The bottom of the bit line contact hole 162 may be lower than the bottom of the second through hole 166.

[0115] In an example embodiment, an etching mask for forming bit line contact holes 162 and second vias 166 may be formed on a third molded insulating layer 156 in the first region I and the second region II. In the etching mask, the exposed portion for forming the bit line contact holes 162 may be larger than the exposed portion for forming the second vias 166.

[0116] The third molding insulating layer 156, the second etch stop layer 154, the second molding insulating layer 142, and the cover layer 140 can be etched sequentially using an etching mask to form a bit line contact hole 162 exposing the upper electrode 126a in the first region and a second via 166 exposing the first metal wiring 153b in the second region II. During the etching process, the first metal wiring 153b may not be etched, thus the second molding insulating layer 142 in the second region II may not be etched. Therefore, the bottom of the bit line contact hole 162 may be lower than the bottom of the second via 166.

[0117] Subsequently, the third molded insulating layer 156 in the first region I and the second region II can be partially etched to form a third trench 160 in the first region I and a second trench 164 in the second region II. The second trench 164 and the third trench 160 can extend in a second direction. Each of the second trench 164 and the third trench 160 can have a second width W2 in a first direction. The third molded insulating layer 156 can be exposed at the bottom of the second trench 164 and the third trench 160.

[0118] As described above, firstly, bit line contact hole 162 and second through hole 166 can be formed, and then second trench 164 and third trench 160 can be formed. However, the process sequence is not limited to this.

[0119] Reference Figure 17 and Figure 18 The third barrier layer 168a may be conformally formed on the third trench 160, the second trench 164, the bit line contact hole 162, the second through hole 166, and the upper surface of the second molded insulating layer 142. The third conductive layer 168b may be formed to fill the third trench 160, the second trench 164, the bit line contact hole 162, and the second through hole 166 on the third barrier layer 168a.

[0120] The third conductive layer 168b may include a metallic material, such as copper. The copper layer may be formed by an electroplating process.

[0121] Because the bit line contact hole 162 in the first region I has a bottom that is lower than the bottom of the second via 166, it may be difficult to completely fill the bit line contact hole 162 with a third conductive layer 168b comprising metal. When the third conductive layer 168b is formed using the same process, the second via 166 can be completely filled with metal. However, the bit line contact hole 162 may not be completely filled with metal, or the metal filling the bit line contact hole 162 may have seams or gaps therein. In such cases, the operation or reliability of the embedded device may fail.

[0122] Conversely, according to the example embodiment, as the width of the bit line contact hole 162 increases in the second direction, the internal volume of the bit line contact hole 162 can increase. Therefore, metal can be easily filled into the bit line contact hole 162, and operational or reliability failures in the embedded device can be reduced.

[0123] Refer again Figure 1 and Figure 2 The third conductive layer 168b and the third barrier layer 168a can be planarized until the upper surface of the third molded insulating layer 156 can be exposed to form a third barrier pattern 180a and a third conductive pattern 180b in the second trench 164 and the second via 166, and a fourth barrier pattern 180c and a fourth conductive pattern 180d in the third trench 160 and the bit line contact hole 162. The planarization process may include a chemical mechanical polishing process.

[0124] Through the above process, in the first region I, a bit line contact 182a can be formed in the bit line contact hole 162, and a bit line 182b can be formed in the third trench 160. In the second region II, a second via contact 186a can be formed in the second through hole 166, and a second metal wiring 186b can be formed in the second trench 164. The bit line contact 182a and the bit line 182b can be used as a bit line structure 182, and the second via contact 186a and the second metal wiring 186b can be used as a second metal wiring structure 186.

[0125] The above processes can be used to manufacture embedded devices. In embedded devices, defects caused by the metal included in the bit line structure 182 can be reduced.

[0126] Figure 19 and Figure 20 This is a cross-sectional view showing an embedded device according to an example embodiment. Figure 21 It shows Figures 19-20 A perspective view of the bit line structure and metal wiring structure in an embedded device.

[0127] Figure 19 It is a cross-sectional view taken in the first direction. Figure 20It is a cross-sectional view taken in the second direction. Besides the bitline structure, Figure 19 The embedded device shown can be used with Figure 1 and 2 The embedded devices shown are basically the same. Therefore, identical descriptions are omitted, and the bit line structure is described in detail.

[0128] Reference Figures 19 to 21 The third trench 160a can pass through the third molded insulating layer 156, the second etch stop layer 154, the second molded insulating layer 142, and the cover layer 140 in the first region I. The third trench 160a can expose the upper electrode 126a. That is, a bit line contact hole communicating with the third trench 160a can be avoided.

[0129] The third trench 160a may have a second width W2 in the first direction. That is, the third trench 160a may have a width substantially the same as the width of the second trench 164 at the same level in the second region II. The third trench 160a may extend in the second direction.

[0130] The fourth blocking pattern 180c and the fourth conductive pattern 180d can be formed in the third trench 160a. The fourth blocking pattern 180c and the fourth conductive pattern 180d formed in the third trench 160a can be used as bit line 182'. For example, as... Figure 21 As shown, bit line 182' can have a rectangular prism shape, having a longitudinal direction along the second direction, a second width W2 along the first direction, and a first height h1 along the vertical direction. The lower surface of bit line 182' can directly contact the upper electrode 126a, as shown. Figure 20 As shown. Bit line 182' can extend in the second direction.

[0131] In this case, bit line 182' can be used as a bit line structure, so bit line and bit line structure can use the same reference numerals. Since the bit line structure 182' in the first region I and the second metal wiring structure 186 in the second region II can be formed by the same process, bit line structure 182 and second metal wiring structure 186 can include the same material.

[0132] When viewed at the same horizontal level, the bit line structure 182' can have a shape different from that of the second metal wiring structure 186. Specifically, the first height h1 of the bit line structure 182' can be higher than the second height h2 of the second metal wiring structure 186. The second width W2 of the bit line structure 182' in the first direction can be greater than the width W1 of the second via contact 186a of the second metal wiring structure 186. That is, the width of the bit line structure 182' in the first direction can be substantially the same as the width of the second metal wiring 186b of the second metal wiring structure 186 in the first direction.

[0133] As described above, the width of the bit line structure 182' can be extended. Therefore, when the bit line structure 182' and the second via contact 186a and the second metal wiring 186b are formed simultaneously, the metal material can be easily filled into the third trench 160a used to form the bit line structure 182'. Thus, defects in the bit line structure 182' can be reduced.

[0134] Figure 22 and Figure 23 This is a cross-sectional view illustrating multiple stages in a method for manufacturing an embedded device according to an example embodiment.

[0135] First, you can execute the reference. Figures 6 to 14 The process is shown. Thereafter, refer to... Figure 22 and Figure 23 A third trench 160a can be formed in the first region through the third molded insulating layer 156, the second etch stop layer 154, the second molded insulating layer 142, and the cover layer 140. A second trench 164 can be formed on the third molded insulating layer 156 in the second region II. A second via 166 can be formed in the second region II below the second trench 164 through the third molded insulating layer 156 and the second etch stop layer 154 to expose the first metal wiring 153b. The second etch stop layer 154 can also serve as a barrier layer for metal diffusion.

[0136] The second groove 164 and the third groove 160a may have a second width W2 in the first direction. The bottom of the third groove 160a may be lower than the bottom of the second through hole 166.

[0137] In an example embodiment, an etching mask for forming a third trench 160a and a second via 166 may be formed on a third molded insulating layer 156 in the first region I and the second region II. The exposed portion of the etching mask in the first region I may extend in a second direction, and the upper surface of the exposed portion of the etching mask in the second region II may have a circular shape.

[0138] The third molding insulating layer 156, the second etch stop layer 154, the second molding insulating layer 142, and the cover layer 140 can be etched sequentially using an etching mask to form a third trench 160a in the first region and a second via 166 in the second region. The third trench 160a can expose the upper electrode 126a, and the second via 166 can expose the first metal wiring 153b. During the etching process, the first metal wiring 153b may not be etched, thus the second molding insulating layer 142 in the second region II may not be etched. Therefore, the bottom of the third trench 160a may be lower than the bottom of the second via 166.

[0139] Subsequently, the upper portion of the third molded insulating layer 156 in the second region II can be etched to form a second trench 164 communicating with the second through-hole 166 in the second region II. The second trench 164 and the third trench 160a can extend in a second direction. Each of the second trench 164 and the third trench 160a can have a second width W2 in a first direction.

[0140] Refer again Figure 19 and Figure 20 A third barrier layer may be conformally formed on the surfaces of the third trench 160a, the second trench 164, and the second via 166, as well as on the upper surface of the second molded insulating layer 142. A third conductive layer may be formed on the third barrier layer to fill the third trench 160a, the second trench 164, and the second via 166.

[0141] The bottom of the third trench 160a in the first region I may be lower than the bottom of the second via 166. However, the width of the third trench 160a in the second direction can be increased, thereby increasing the volume of the third trench. Therefore, metal can easily fill the third trench 160a. The metal can adequately fill the third trench 160a, thus reducing operational and / or reliability failures of the embedded device.

[0142] Subsequently, the third conductive layer and the third barrier layer can be planarized until the upper surface of the third molded insulating layer 156 can be exposed to form a bit line structure 182' in the third trench 160a and a second metal wiring structure 186 in the second trench 164 and the second via 166. Embedded devices can be manufactured through the above process.

[0143] Figure 24 This is a cross-sectional view showing an embedded device according to an example embodiment.

[0144] In addition to bitline structure 182” Figure 24 The embedded devices shown are Figure 1 and Figure 2 The embedded devices shown are the same. Therefore, identical descriptions are omitted, and the description focuses primarily on bit line structure 182.

[0145] Reference Figure 24 , as reference Figure 1 As shown, a lower insulating layer 102 and a first lower wiring can be formed on the substrate 100 in the first region and the second region II. An upper insulating layer 104 can be formed on the lower insulating layer 102. A second lower wiring 109 can be formed in the upper insulating layer 104 in the first region I and the second region II. Furthermore, a first etch stop layer 112 and a first molding insulating layer 114 can be stacked on the upper insulating layer 104 and the second lower wiring 109 in the first region I and the second region II.

[0146] The first via contact 153a and the first metal wiring 153b can be formed in the second region II through the first molded insulating layer 114 and the first etch stop layer 112. The first via contact 153a and the first metal wiring 153b can be used as the first metal wiring structure 153.

[0147] The first metal wiring structure 153 can have the following characteristics: Figure 1 The shape of the first metal wiring structure shown is the same. That is, the first metal wiring 153b may have a second width W2, and the first via contact 153a may have a first width W1. However, with Figure 1 Unlike the example shown, a cover layer may not be formed on the side of the first metal wiring structure 153.

[0148] The second etch stop layer 190 may be formed on the first molded insulating layer 114 and the first metal wiring structure 153. In an example embodiment, the second etch stop layer 190a in the first region I may have a first thickness, and the second etch stop layer 190b formed in the second region II may have a second thickness less than the first thickness.

[0149] The lower electrode contact 116 can be formed in the first region I through the second etch stop layer 190, the first molding insulating layer 114, and the first etch stop layer 112. That is, the height of the lower electrode contact 116 can be greater than the thickness of the first molding insulating layer 114. In addition, the upper surface of the lower electrode contact 116 can be higher than the upper surface of the first metal wiring structure 153.

[0150] The first structure 138 can be formed on the lower electrode contact 116. The first structure 138 can be compared with a reference. Figure 1 The first structure shown is the same.

[0151] The capping layer 140 can be conformally formed on the first structure 138 and the second etch stop layer 190 in the first region I and the second region II. A second molded insulating layer 142 can be formed on the capping layer 140 in the first region I and the second region II. In an example embodiment, the upper surface of the second molded insulating layer 142 in the first region I and the second region II can be substantially flat. The second molded insulating layer 142 can have sufficient height for housing a metal wiring structure within the second molded insulating layer 142. In an example embodiment, the thickness of the second molded insulating layer 142 can be approximately... to approximately Within the range.

[0152] A third trench 160b may be formed in the first region I through the upper portion of the second molded insulating layer 142 to expose the upper electrode 126a of the first structure 138. The third trench 160b may have a second width W2 in the first direction and may extend in the second direction.

[0153] A fourth blocking pattern and a fourth conductive pattern can be formed in the third trench 160b. The conductive material filling the third trench 160b can be used as a bit line 182". In this case, the bottom of the bit line 182" can directly contact the upper electrode 126a of the first structure 138. The bit line 182" can be used as a bit line structure 182", and bit line contact can be avoided.

[0154] The second trench 164 can pass through the upper part of the second molded insulating layer 142 in the second region II. The second via 166 can communicate with the bottom of the second trench 164 and can pass through the second molded insulating layer 142, the second etch stop layer 190, and the cover layer 140. The second via 166 can expose the upper surface of the first metal wiring 153b.

[0155] The second via contact 186a can be formed in the second via hole 166, and the metal material filling the second trench 164 can be used as the second metal wiring 186b. The second via contact 186a and the second metal wiring 186b can be used as the second metal wiring structure 186. The second via contact 186a can contact the first metal wiring 153b, such that the second via contact 186a can be electrically connected to the first metal wiring 153b. The first metal wiring structure 153 and the second metal wiring structure 186 can be electrically connected to each other.

[0156] The upper surfaces of the second molded insulating layer 142, the second metal wiring structure 186, and the bit line structure 182" can be coplanar. The height of the bit line structure 182" can be less than the height of the second metal wiring structure 186. For example, the height of the bit line structure 182" can be substantially the same as the height of the second metal wiring 186b. Moreover, the width of the bit line structure 182" in the first direction can be greater than the width of the second via contact 186a in the first direction. The bit line structure 182" can have a second width W2 in the first direction. Therefore, the metal material used to form the bit line structure 182" can be easily filled in the third trench 160b. Thus, defects in the bit line structure 182" can be reduced.

[0157] Figures 25 to 29 This is a cross-sectional view illustrating multiple stages in a method for manufacturing an embedded device according to an example embodiment.

[0158] Reference Figure 25 First, you can execute the reference. Figure 6The process is shown. Afterwards, a first molded insulating layer 114 can be formed on the first etch stop layer 112.

[0159] A portion of the first molded insulating layer 114 in the second region II can be etched to form a first trench. Through-holes communicating with the first trench can be formed to expose the upper surface of the second lower wiring 109.

[0160] A first barrier layer and a first conductive layer can be formed in the first trench and the first via. Subsequently, the first conductive layer and the first barrier layer can be planarized until the upper surface of the first molded insulating layer 114 can be exposed to form a first barrier pattern and a first conductive pattern in the first trench and the first via. Through the above process, a first via contact 153a can be formed in the first via, and a first metallic wiring 153b can be formed in the first trench.

[0161] Reference Figure 26 The second etch stop layer 190 can be formed on the first molded insulating layer 114 and the first metal wiring 153b. A portion of the second etch stop layer 190, the first molded insulating layer 114, and the first etch stop layer 112 in the first region I can be etched to form a lower electrode contact hole exposing the second lower wiring 109. A lower electrode contact 116 can be formed in the lower electrode contact hole.

[0162] Reference Figure 27 A lower electrode layer, an MTJ layer, and an intermediate electrode layer can be sequentially formed on the first molded insulating layer 114 and the lower electrode contact 116. An upper electrode layer and an adhesive layer can be sequentially formed on the intermediate electrode layer. A mask pattern can then be formed on the adhesive layer, and the mask pattern can be used as an etching mask to sequentially etch the adhesive layer, upper electrode layer, intermediate electrode layer, MTJ layer, and lower electrode layer. Therefore, a first structure 138 comprising a stack of a lower electrode, an MTJ structure, an intermediate electrode, and an upper electrode 126a can be formed on the lower electrode contact 116.

[0163] During the etching process, the second etch stop layer 190 may not be completely removed in the first region I and the second region II. Furthermore, the second etch stop layer 190b in the second region II may be etched more extensively than the second etch stop layer 190a in the first region I.

[0164] Reference Figure 28 The capping layer 140 may be conformally formed on the surfaces of the first structure 138 and the second etch stop layer 190. A second molded insulating layer 142 may be formed on the capping layer 140.

[0165] Reference Figure 29A third trench 160b exposing the upper electrode 126a can be formed in the first region I, penetrating the upper portion of the second molded insulating layer 142. Furthermore, a second trench 164 can be formed in the second region II, penetrating the upper portion of the second molded insulating layer 142. A second via 166 can be formed below the second trench, penetrating the second molded insulating layer 142, the capping layer 140, and the second etch stop layer 190. The second via 166 can expose the first metal wiring 153b.

[0166] The second groove 164 and the third groove 160b may have a second width W2 in the first direction. The bottom of the third groove 160b may be higher than the bottom of the second through hole 166.

[0167] Refer again Figure 24 A third barrier layer can be conformally formed on the surfaces of the third trench 160b, the second trench 164, the second via 166, and the second molded insulating layer 142. A third conductive layer can be formed on the third barrier layer to fill the third trench 160b, the second trench 164, and the second via 166. Then, the third barrier layer and the third conductive layer can be planarized until the upper surface of the second molded insulating layer 142 can be exposed. Therefore, a bitline structure 182" can be formed in the third trench 160b, and a second metal wiring structure 186 can be formed in the second trench 164 and the second via 166. Through the above process, an embedded device can be manufactured.

[0168] The embedded device in each implementation can be used in electronic products, such as mobile devices, memory cards, and computers.

[0169] By summarizing and reviewing, the example implementation provides an embedded device with high reliability and excellent electrical characteristics. According to the implementation, defects caused by insufficient metal filling at the bottom of the bitline structure can be reduced in the embedded device. The embedded device offers high flexibility in layout design. Furthermore, the embedded device can exhibit high reliability and excellent electrical characteristics.

[0170] That is, according to the implementation, the bitline structure can be stacked on the MTJ module to be within the height of two adjacent and simultaneously formed cell wirings, wherein the height of the bitline structure is greater than the height of the adjacent cell wirings at the same level. Therefore, when forming metal wirings for the bitline structure, the lower part of the bitline structure can have a greater width and volume than the adjacent cell wirings at the same level, thereby facilitating metal filling and preventing defects.

[0171] This document has disclosed exemplary embodiments, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0172] Korean Patent Application No. 10-2020-0019519, filed on February 18, 2020, with the Korean Intellectual Property Office and entitled "Embedded Device and Method of Manufacturing the Same", is incorporated herein by reference in its entirety.

Claims

1. An embedded device, comprising: A first molded insulating layer on a substrate, the substrate comprising a first region and a second region; A second molded insulating layer on top of the first molded insulating layer; The lower electrode contact is in the first molded insulating layer, and the lower electrode contact is on the first region of the substrate; A first structure is formed in the second molded insulating layer and contacts the upper surface of the lower electrode contact. The first structure includes a stack of a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode. A first metal wiring structure passes through the first molded insulating layer and the second molded insulating layer in the second region of the substrate; A third molded insulating layer on the second molded insulating layer; Bit line structure, including bit line contact and bit line and passing through the upper portion of the second molded insulating layer and the third molded insulating layer in the first region, the bit line structure having a first height in the vertical direction and contacting the upper electrode of the first structure; as well as A second metal wiring structure includes a second via contact and a second metal wiring that passes through the third molded insulating layer in the second region. The second metal wiring structure contacts the first metal wiring structure, and the second metal wiring structure has a second height in the vertical direction, the second height being less than the first height of the bit line structure. The upper surface of the second passage contact has a circular shape, the circular shape having a first width in each of a first direction and a second direction perpendicular to each other, and The upper surface of the bit line contact has an elliptical shape, the elliptical shape having a first width in the first direction and a third width in the second direction, the third width being greater than the first width.

2. The embedded device according to claim 1, wherein, The bit line contact is at a higher height in the vertical direction than the second path contact is at a higher height in the vertical direction.

3. The embedded device according to claim 1, wherein, The bit line and the second metal wiring extend in the second direction.

4. The embedded device according to claim 3, wherein, The bit line has a second width in the first direction that is greater than the first width.

5. The embedded device according to claim 4, wherein, The width of the bit line in the first direction is the same as the width of the second metal wiring in the first direction.

6. The embedded device according to claim 5, wherein, The bottom of the bit line structure is lower than the bottom of the second metal wiring structure.

7. The embedded device according to claim 1, wherein, The second molded insulating layer is on the top surface of the first structure, and the thickness from the top surface of the first structure to the upper surface of the second molded insulating layer is in the range of 100 Å to 800 Å.

8. The embedded device according to claim 1, wherein, The first height is 100 Å to 800 Å higher than the second height.

9. The embedded device according to claim 1, wherein, The second height is in the range of 500 Å to 5000 Å.

10. An embedded device, comprising: A first molded insulating layer on a substrate, the substrate comprising a first region and a second region; A second molded insulating layer on top of the first molded insulating layer; The lower electrode contact is located in the first molded insulating layer in the first region; A first structure, in the second molded insulating layer in the first region, the first structure contacts the upper surface of the lower electrode contact, and the first structure includes a stacked lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode; A first metallic wiring structure passes through the first molded insulation layer and the second molded insulation layer in the second region; A third molded insulating layer on the second molded insulating layer; Bit line structure, including bit line contacts and bit lines, passes through the third molded insulating layer in the first region and through the upper portion of the second molded insulating layer, the bit line structure contacting the upper electrode of the first structure; as well as The second metal wiring structure includes a second path contact and a second metal wiring and passes through the third molded insulating layer in the second region, the second metal wiring structure contacting the first metal wiring structure; Wherein, the height of the bit line structure in the vertical direction is different from the height of the second metal wiring structure in the vertical direction, and The shape of the bit line structure differs from the shape of the second metal wiring structure. The upper surface of the second passage contact has a circular shape, the circular shape having a first width in each of a first direction and a second direction perpendicular to each other, and The upper surface of the bit line contact has an elliptical shape, the elliptical shape having a first width in the first direction and a third width in the second direction, the third width being greater than the first width.

11. The embedded device according to claim 10, wherein: The bit line contact is at a higher height in the vertical direction than the second path contact is at a higher height in the vertical direction.

12. The embedded device according to claim 11, wherein, The second metal wiring structure has a second height in the vertical direction, and the bit line structure has a first height in the vertical direction that is higher than the second height.

13. The embedded device according to claim 10, wherein, The bit line and the second metal wiring extend in the second direction.

14. The embedded device according to claim 13, wherein, The bit line has a second width in the first direction that is greater than the first width.

15. An embedded device, comprising: The substrate includes a first region and a second region; The lower electrode contact is located on the substrate in the first region; A first structure contacts the upper surface of the lower electrode, the first structure comprising a stacked lower electrode, a magnetic tunnel junction (MTJ) structure and an upper electrode; A first metal wiring structure, on the substrate in the second region, wherein the upper surface of the first metal wiring structure is higher than the upper surface of the first structure; Bit line structure, including bit line contact and bit line and contact the upper electrode of the first structure; as well as The second metal wiring structure includes a second path contact and a second metal wiring that contacts the first metal wiring structure. The height of the bit line structure in the vertical direction is different from the height of the second metal wiring structure in the vertical direction. The upper surface of the second passage contact has a circular shape, the circular shape having a first width in each of a first direction and a second direction perpendicular to each other, and The upper surface of the bit line contact has an elliptical shape, the elliptical shape having a first width in the first direction and a third width in the second direction, the third width being greater than the first width.

16. The embedded device according to claim 15, wherein, The height of the bit line structure in the vertical direction is 100 Å to 800 Å higher than the height of the second metal wiring structure in the vertical direction.

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