Electronic device and method of manufacturing the same

Abstract

The present invention provides an electronic device including a semiconductor memory. The semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines above the first lines, the second lines extending in a second direction intersecting the first direction; a plurality of memory cells arranged at an intersection of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first direction and the second direction; and a heat sink located between two memory cells adjacent to each other in a diagonal direction relative to the first direction and the second direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0026550, filed on Mar. 3, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] This patent document relates to a semiconductor device, its application in an electronic device or system, and a method of manufacturing the semiconductor device. Background Art

[0004] Recently, as electrical devices tend to be miniaturized, low-power, high-performance, and multifunctional, there has been a demand in the art for semiconductor devices that can store information in various electrical devices such as computers, portable communication devices, and the like, and thus the semiconductor devices have been studied. Such semiconductor devices can store data using the characteristic of switching between different resistance states according to an applied voltage or current. For example, the semiconductor devices include RRAM (resistive random access memory), PRAM (phase change random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), electric fuses, and the like. Summary of the invention

[0005] The technology disclosed in this patent document includes various embodiments, which relates to an electronic device capable of facilitating manufacturing and ensuring reliability and operating characteristics, and to a manufacturing method thereof.

[0006] In one embodiment, an electronic device includes a semiconductor memory, which includes: a plurality of first lines extending in a first direction; a plurality of second lines above the first lines, the second lines extending in a second direction intersecting the first direction; a plurality of storage cells arranged at an intersection area between the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first direction and the second direction; and a heat sink located between two storage cells adjacent to each other in a diagonal direction relative to the first direction and the second direction.

[0007] In another embodiment, a method for manufacturing an electronic device including a semiconductor memory, the method comprising: forming a plurality of stacked structures extending in a first direction over a substrate, each of the stacked structures comprising a first line and an initial memory cell; forming a first covering layer on two side walls of the stacked structures in a second direction intersecting the first direction; forming a second covering layer, the second covering layer sealing an upper portion of a space between the first covering layers formed on the side walls of the two stacked structures facing each other in the second direction; forming a conductive layer over the stacked structures, the first covering layer and the second covering layer; forming a plurality of mask patterns extending in the second direction over the conductive layer; etching the conductive layer, the stacked structures, the first covering layer and the second covering layer using the mask patterns as etching barriers to form a second line, a memory cell, a first covering layer pattern and a second covering layer pattern, wherein a width between two adjacent memory cells in the first direction is less than a width between the second covering layer patterns in the first direction; and forming a heat sink in the space between the second covering layer patterns.

[0008] These and other aspects, embodiments and associated advantages are described in more detail in the drawings, the description and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1A to FIG. 8D is a diagram illustrating a semiconductor memory and a method of manufacturing the same according to an embodiment of the present disclosure.

[0010] 9A to 10D is a diagram illustrating a semiconductor memory and a method for manufacturing the same according to another embodiment of the present disclosure.

[0011] Fig.11 is a configuration diagram of a microprocessor implementing a storage circuit based on the disclosed technology.

[0012] Fig.12 is a configuration diagram of a processor implementing a storage circuit based on the disclosed technology.

[0013] Fig.13 is a configuration diagram of a system implementing a storage circuit based on the disclosed technology.

[0014] Fig.14 is a configuration diagram of a memory system implementing a memory circuit based on the disclosed technology. DETAILED DESCRIPTION

[0015] Various examples and embodiments of the disclosed technology are described in detail below with reference to the accompanying drawings.

[0016] The drawings may not necessarily be drawn to scale, and in some cases, the proportions of at least some structures in the drawings may have been exaggerated in order to clearly illustrate certain features of the described examples or embodiments. When a particular example is shown in the drawings or specification as having two or more layers in a multilayer structure, the relative positional relationship of these layers or the order in which these layers are arranged reflects the specific embodiments and examples of the described or illustrated examples, and different relative positional relationships or the order in which these layers are arranged are possible. In addition, the examples of the described or illustrated multilayer structures may not reflect all the layers present in the particular multilayer structure (for example, one or more additional layers may exist between the two illustrated layers). As a specific example, when the first layer in the described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly on the second layer or substrate, but may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or substrate.

[0017] Before describing the embodiments, a memory device to which the embodiments can be applied will be briefly described.

[0018] The embodiments may be applied to a memory device in which memory cells are arranged at intersections between lower and upper lines that cross each other.

[0019] Here, the memory cell may require heat or generate heat during the operation of the memory device. For example, the memory cell may include a phase change material. For reference, the phase change material may switch between an amorphous state and a crystalline state due to Joule heat generated by a current flowing therethrough. When the phase change material is in an amorphous state, the phase change material may be in a relatively high resistance state, and when the phase change material is in a crystalline state, the phase change material may be in a relatively low resistance state. The resistance difference of the phase change material may be used to store data in the memory cell.

[0020] However, such heat generated in the memory cell may be transferred to the periphery of the memory cell and cause thermal interference, which affects the phase change material of the memory cell adjacent to the memory cell, so that the resistance state of the adjacent memory cell may change. That is, due to the thermal interference, an error may occur in the operation of the memory device, and therefore, the reliability of the memory device may be deteriorated.

[0021] Hereinafter, a memory device and a method of manufacturing the same which can solve the above-mentioned problems by reducing heat transfer between memory cells adjacent to each other during operation of the memory device will be proposed.

[0022] FIG. 1A to FIG. 8D 1 is a diagram showing a semiconductor memory and a method for manufacturing the same according to an embodiment of the present disclosure. When necessary, a plan view at a specific height and a cross-sectional view taken along a predetermined line of the plan view are shown. Specifically, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A This is a plan view of a semiconductor memory device viewed from above. Figure 1B , Figure 2B and Figure 3B Along Figure 1A , Figure 2A and Figure 3A A cross-sectional view taken along line A1-A1'. Figure 4B and Figure 4C Along Figure 4A A cross-sectional view taken along lines A2-A2' and A3-A3'. Figure 5B and Figure 5C Along Figure 5A The sectional views taken along the lines A2-A2' and A3-A3' are Figure 5D is a plan view at the height of the upper surface of the storage unit. Figure 6B and Figure 6C Along Fig. 6A The sectional views taken along the lines A2-A2' and A3-A3' are Fig.6D is a plan view at the height of the upper surface of the storage unit. Figure 7B and Figure 7C Along Fig. 7A The sectional views taken along the lines A2-A2' and A3-A3' are Fig.7D is a plan view at the height of the upper surface of the storage unit. Figure 8B and Figure 8C Along Fig. 8A The sectional views taken along the lines A2-A2' and A3-A3' are Fig.8D is a plan view at the height of the upper surface of the storage unit. Figure 5E and Fig. 5F It is used to illustrate FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5D Cross-sectional view of the intermediate process between.

[0023] First, a manufacturing method will be described with reference to the drawings.

[0024] refer to Figure 1A and Figure 1B , a substrate 100 may be provided. The substrate 100 may include a semiconductor material such as silicon. In addition, a desired lower structure (not shown) may be formed in the substrate 100. For example, a transistor constituting an integrated circuit may be formed in the substrate 100.

[0025] Subsequently, the following structure may be formed over the substrate 100: a first line 110 and an initial memory cell 120 are stacked therein. Hereinafter, the structure in which the first line 110 and the initial memory cell 120 are stacked therein will be referred to as stacked structures 110 and 120. The stacked structures 110 and 120 may have a line shape extending in a first direction, for example, a direction intersecting the line A1-A1'. A plurality of stacked structures 110 and 120 may be arranged to be spaced apart from each other in a second direction (for example, a direction parallel to the line A1-A1') intersecting the first direction. The first direction and the second direction are perpendicular to a third direction, and the first line 110 and the initial memory cell 120 are stacked over the substrate 100 in the third direction. In this embodiment, two stacked structures 110 and 120 are shown, but the number of stacked structures 110 and 120 arranged in the second direction may be variously modified.

[0026] The stacked structures 110 and 120 may be formed by sequentially forming a conductive layer for the first line 110 and one or more material layers for the initial memory cell 120 over the substrate 100, and etching the conductive layer and the material layer using a linear mask pattern (not shown) extending in the first direction. Thus, the first line 110 and the initial memory cell 120 may overlap each other in a plan view and may be aligned with each other in a third direction.

[0027] The first line 110 may include a conductive material, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu) or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. The first line 110 may be used as a word line or a bit line.

[0028] The initial memory cell 120 may include various materials and may have any of various layer structures as long as it can store data according to a voltage or current applied to the first line 110 and the second line to be described below. In the present embodiment, the initial memory cell 120 may store data using a variable resistance characteristic that switches between different resistance states. In one embodiment, the initial memory cell 120 may include a lower electrode layer 121, a selection element layer 123, an intermediate electrode layer 125, a variable resistance layer 127, and an upper electrode layer 129.

[0029] The lower electrode layer 121 and the upper electrode layer 129 may be located at both ends of the initial memory cell 120, for example, at the bottom and the top in the third direction, respectively, and transmit the voltage required for the operation of the initial memory cell 120 to other layers of the initial memory cell 120. The intermediate electrode layer 125 may electrically connect the selection element layer 123 and the variable resistance layer 127 while physically separating the two. One or more of the lower electrode layer 121, the intermediate electrode layer 125, and the upper electrode layer 129 may include a conductive material, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof. Alternatively, one or more of the lower electrode layer 121, the intermediate electrode layer 125, and the upper electrode layer 129 may include a carbon electrode layer.

[0030] The selection element layer 123 can prevent current leakage between memory cells. The initial memory cell 120 can be patterned in a subsequent process to be transformed into an island memory cell, and the island memory cell can be located at the intersection between the first line 110 and the second line. Here, when the memory cells share the first line 110 or the second line, current leakage may occur between the memory cells through the shared line. Therefore, the selection element layer 123 can play a role in preventing such current leakage. To this end, the selection element layer 123 can have a switching characteristic, which is used to block or almost not allow current to flow therein when the value of the applied voltage is less than a predetermined threshold, and allow the current flowing therein to increase sharply when the value of the applied voltage is equal to or higher than a predetermined threshold. The threshold value can be referred to as a threshold voltage, and the selection element layer 123 can realize an on state or an off state based on the threshold voltage.

[0031] The selection element layer 123 may include: a diode, an OTS (bidirectional threshold switch) material such as a chalcogenide material, a MIEC (mixed ion electron conduction) material such as a metal-containing chalcogenide material, a MIT (metal insulator transition) material such as NbO2 or VO2, or a tunneling insulating material with a relatively wide band gap such as SiO2 or Al2O3.

[0032] The variable resistance layer 127 may be a part of the initial memory cell 120 storing data. To this end, the variable resistance layer 127 may have a variable resistance characteristic that switches between different resistance states according to an applied voltage or current. The variable resistance layer 127 may have a single-layer structure or a multi-layer structure that includes at least one of materials used for RRAM, PRAM, MRAM, or FRAM, etc. For example, the variable resistance layer 127 may include: a metal oxide such as a perovskite-based oxide or a transition metal oxide, a phase change material such as a chalcogenide-based material, a ferromagnetic material, or a ferroelectric material, etc. For example, when the variable resistance layer 127 includes a phase change material, the resistance state of the variable resistance layer 127 may change due to heat.

[0033] In this embodiment, the initial memory cell 120 includes a lower electrode layer 121, a selection element layer 123, an intermediate electrode layer 125, a variable resistance layer 127, and an upper electrode layer 129 stacked sequentially. However, the embodiment is not limited thereto. In another embodiment, at least one of the layers 121, 123, 125, and 129 may be omitted except for the variable resistance layer 127. Alternatively, their stacking order may be changed. For example, the positions of the variable resistance layer 127 and the selection element layer 123 may be reversed. Alternatively, in addition to the layers 121, 123, 125, 127, and 129, the initial memory cell 120 may also include one or more other layers (not shown).

[0034] Subsequently, the first cover layer 130 may be formed over the substrate 100 having the stack structures 110 and 120 formed thereon. In other words, the first cover layer 130 may be formed along the contour of the resulting structure including the stack structures 110 and 120 formed over the substrate 100.

[0035] The first cover layer 130 may be formed using a film and / or a process having excellent step coverage characteristics. For example, the first cover layer 130 may be formed by an ALD (atomic layer deposition) method. Thus, the first cover layer 130 may be formed along the side surfaces (or sidewalls) and the upper surface of the stacked structures 110 and 120. In addition, the first cover layer 130 may have a thin thickness so that it does not completely fill the space between the stacked structures 110 and 120.

[0036] The first capping layer 130 may protect the initial memory cell 120 in subsequent processes. The first capping layer 130 may include an insulating material and may have a single-layer structure or a multi-layer structure. For example, the first capping layer 130 may include silicon oxide, silicon nitride, insulating metal oxide, insulating metal nitride, or a combination thereof.

[0037] refer to Figure 2A and Figure 2B , you can Figure 1A and Figure 1B A second capping layer 140 is formed over the resulting structure.

[0038] The second capping layer 140 may be formed using a film and / or a process having a poor step coverage characteristic. For example, the second capping layer 140 may be formed by a deposition method using HDP (high density plasma). Therefore, the second capping layer 140 may be formed to be thick only above the upper portion of the stacked structures 110 and 120. In other words, the second capping layer 140 may be formed only above the upper surface of the stacked structures 110 and 120 and the sidewalls of the upper portions of the stacked structures 110 and 120. The second capping layer 140 may have an overhang, the side of which protrudes more toward the space between the stacked structures 110 and 120 in the second direction than the first capping layer 130 on the sidewalls of the initial memory cell 120. The overhangs of the second capping layer 140 formed above two adjacent stacked structures 110 and 120 may contact each other (see P1) to close the space between the two adjacent stacked structures 110 and 120. As a result, a first air gap AG1 surrounded by the first cover layer 130 and the second cover layer 140 may be formed. A side surface (or sidewall) and a lower surface of the first air gap AG1 may be defined by the first cover layer 130 formed along the upper surface of the substrate 100 and the side surfaces of the two adjacent stack structures 110 and 120 facing each other, and an upper surface of the first air gap AG1 may be defined by the second cover layer 140. For ease of description, Figure 2A In the plan view of FIG. 1 , the first air gap AG1 is indicated by a thick dashed line. The first air gap AG1 may extend along a first direction similar to Figure 1A and Figure 1B The space between two adjacent stacked structures 110 and 120 described in FIG.

[0039] The second capping layer 140 may include an insulating material. For example, the second capping layer 140 may include silicon oxide, silicon nitride, insulating metal oxide, insulating metal nitride, or a combination thereof. The second capping layer 140 may be formed of a material different from that of the first capping layer 130 .

[0040] refer to Figure 3A and Figure 3B , a planarization process such as a chemical mechanical polishing (CMP) process may be performed until the upper surface of the initial memory cell 120 (e.g., the upper surface of the upper electrode layer 129) is exposed. As a result, the first capping layer 130 and the second capping layer 140 on the upper surface of the initial memory cell 120 may be removed, thereby forming a first capping layer pattern 130A and a second capping layer pattern 140A between the two adjacent stack structures 110 and 120.

[0041] The first capping layer pattern 130A may be formed along the side surfaces of the two adjacent stack structures 110 and 120 facing each other and the upper surface of the substrate 100 between the two adjacent stack structures 110 and 120. The second capping layer pattern 140A may have a line shape extending in the first direction while closing the space between the two adjacent stack structures 110 and 120. The upper surface of the first capping layer pattern 130A and the upper surface of the second capping layer pattern 140A may form a flat surface together with the upper surface of the initial memory cell 120. That is, the upper surface of the first capping layer pattern 130A and the upper surface of the second capping layer pattern 140A may be flush with the upper surface of the upper electrode layer 129.

[0042] During the planarization process, the first air gap AG1 under the second capping layer pattern 140A may remain.

[0043] refer to FIG. 4A to FIG. 4C , you can FIG. 3A to FIG. 3B A conductive layer 150 for forming a second line is formed over the resulting structure of (i.e., over a flat surface formed by the upper surface of the first capping layer pattern 130A, the upper surface of the second capping layer pattern 140A, and the upper surface of the initial memory cell 120). The conductive layer 150 includes a conductive material, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), or tantalum (Ta), a metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN), or a combination thereof.

[0044] The conductive layer 150 may have a plate shape, which covers Figure 3A and Figure 3B Therefore, the conductive layer 150 may include a first portion located on the upper surfaces of the initial memory cell 120 and the first capping layer pattern 130A and a second portion located on the second capping layer pattern 140A.

[0045] Subsequently, a mask pattern 160 for patterning the conductive layer 150 and the initial memory cells 120 may be formed over the conductive layer 150. The mask pattern 160 may have a line shape extending in the second direction.

[0046] refer to FIG. 5A to FIG. 5D , the conductive layer 150 and the initial memory cell 120 may be etched using the mask pattern 160 as an etching barrier. As a result, the second line 150A and the memory cell 120A may be formed. The second line 150A may extend in the second direction. Figure 5ATwo second lines 150A are shown, but a plurality of second lines 150A may be arranged to be spaced apart from each other in the first direction. The memory cell 120A may be disposed between the first line 110 and the second line 150A in the third direction and at the intersection of the first line 110 and the second line 150A. The mask pattern 160 used in the etching process may be removed by the etching process.

[0047] The memory cell 120A may include a stacked structure of a lower electrode 121A, a selection element pattern 123A, an intermediate electrode 125A, a variable resistance pattern 127A, and an upper electrode 129A. The memory cell 120A may have an island shape. Two side walls of the memory cell 120A facing each other in the first direction may be aligned with the second line 150A, and two side walls of the memory cell 120A facing each other in the second direction may be aligned with the first line 110. When the first line 110 is used as a word line, the second line 150A may be used as a bit line. Conversely, when the first line 110 is used as a bit line, the second line 150A may be used as a word line. Figure 5A Two second lines 150A spaced apart from each other in the first direction and 2×2 memory cells 120A arranged in a matrix form in the first and second directions are shown However, the number of second lines 150A and the number of memory cells 120A may be variously modified.

[0048] During the etching process, portions of the first and second capping layer patterns 130A and 140A exposed between the two second lines 150A may also be etched. The etched first capping layer pattern 130A and the etched second capping layer pattern 140A will be referred to as a final first capping layer pattern 130B and a final second capping layer pattern 140B, respectively. The final first capping layer pattern 130B may be located only on each of the two sidewalls of the memory cell 120A facing each other in the second direction. The final second capping layer pattern 140B may be located on an upper portion of the final first capping layer pattern 130B between two adjacent memory cells 120A in the second direction.

[0049] Meanwhile, a portion where the second line 150A overlaps with the memory cell 120A and the final first covering layer pattern 130B will be referred to as a first portion 150A1, and another portion where the second line 150A overlaps with the final second covering layer pattern 140B will be referred to as a second portion 150A2. A distance between two memory cells 120A in the first direction and / or between the first portions 150A1 will be referred to as a first distance D1, and a distance between the final second covering layer patterns 140B in the first direction and / or between the second portions 150A2 will be referred to as a second distance D2. Here, the second distance D2 may be greater than the first distance D1. FIG. 5E to FIG. 5F Describe the reasons.

[0050] The process of etching the conductive layer 150 and the initial memory cell 120 may be performed by a combination of anisotropic etching and isotropic etching. During anisotropic etching, byproducts such as polymers may be redeposited on the side surfaces of the object that has been etched. Isotropic etching is performed to remove the byproducts and form a pattern having a vertical profile. However, during the etching process, the objects to be etched on the A2-A2' line are the conductive layer 150 and the initial memory cell 120, while the objects to be etched on the A3-A3' line are the conductive layer 150 and the second covering layer pattern 140A. The second covering layer pattern 140A is an element that closes the space between two adjacent initial memory cells 120, and thus the second covering layer pattern 140A may have a much smaller thickness than the two adjacent initial memory cells 120. Therefore, in the middle of the process of etching the initial memory cell 120, the second covering layer pattern 140A may be completely etched before the initial memory cell 120 is fully etched, and thus the first air gap AG1 under the second covering layer pattern 140A may be exposed. Figure 5E and Fig. 5F The left side of shows the state just after the second covering layer pattern 140A is completely etched. At this time, the gaps between the etched second covering layer patterns 140A and the etched conductive layer 150 thereon, and the gaps between the etched portions of the initial memory cell 120 and the etched conductive layer 150 thereon may be substantially the same (see D1). However, when the remaining portions of the initial memory cell 120 are further etched, isotropic etching of the side surfaces of the etched second covering layer pattern 140A and the etched conductive layer 150 thereon may be further performed in comparison with the initial memory cell 120. This is because no material will be re-deposited on the side surfaces of the etched second covering layer pattern 140A and the side surfaces of the etched conductive layer 150 thereon. That is, as Figure 5E and Fig. 5F As shown on the right side of FIG. 1 , the gap between the etched portions of the initial memory cell 120 and the gap between the etched conductive layer 150 thereon can be substantially maintained (see D1). On the other hand, the etched second capping layer pattern 140A and the side of the etched conductive layer 150 thereon can be further etched by isotropic etching (see dotted lines). Therefore, the gap between the etched second capping layer pattern 140A and the gap between the etched conductive layer 150 thereon can be increased. As a result, as shown in FIG. FIG. 5A to FIG. 5D As shown, the first distance D1 and the second distance D2 may be different from each other.

[0051] refer to FIG. 6A to FIG. 6D , you can FIG. 5A to FIG. 5D A third capping layer 170 is formed over the resulting structure.

[0052] The third covering layer 170 may be formed using a film and / or a process having excellent step coverage characteristics. For example, the third covering layer 170 may be formed by an ALD method. Therefore, the third covering layer 170 may be formed along the side surface and the upper surface of the stacked structures 120A and 150A (where the memory cell 120A and the second line 150A are stacked in the third direction), and may be formed along the side surface and the upper surface of the stacked structures 140B and 150A (where the final second covering layer pattern 140B and the second line 150A are stacked in the third direction). The third covering layer 170 may be formed to have a small thickness and not be able to completely fill the space between the two adjacent stacked structures 120A and 150A in the first direction and the space between the two adjacent stacked structures 140B and 150A. In addition, although not shown, the third covering layer 170 may be further formed on the upper surface of the final first covering layer pattern 130B exposed in the process and / or the upper surface of the first line 110.

[0053] Although not shown, the third capping layer 170 may be formed on both sidewalls of the memory cell 120A in the first direction. The third capping layer 170 may protect the memory cell 120A in a subsequent process by surrounding the entire sidewall of the memory cell 120A together with the final first capping layer pattern 130B. The third capping layer 170 may include an insulating material and may have a single-layer structure or a multi-layer structure. For example, the third capping layer 170 may include silicon oxide, silicon nitride, insulating metal oxide, insulating metal nitride, or a combination thereof. The third capping layer 170 may be formed of the same material as the final first capping layer pattern 130B.

[0054] Subsequently, a fourth capping layer 180 may be formed over the resulting structure in which the third capping layer 170 is formed.

[0055] The fourth covering layer 180 may be formed using a film and / or a process having poor step coverage characteristics. For example, the fourth covering layer 180 may be formed by a deposition method using HDP. Therefore, the fourth covering layer 180 may be formed to be thick only above the upper portion of the stacked structures 120A and 150A. That is, the fourth covering layer 180 may be formed only above the upper surface of the stacked structures 120A and 150A and the sidewalls of the upper portion of the stacked structures 120A and 150A. Moreover, the fourth covering layer 180 may be formed to cover the upper surface of the stacked structures 140B and 150A and part or all of the sidewalls. The fourth covering layer 180 may have an overhang, the side of which protrudes more toward the space between the two adjacent stacked structures 120A and 150A in the first direction than the third covering layer 170 formed on the sidewalls of the two adjacent stacked structures 120A and 150A. The overhanging portions of the fourth cover layer 180 on the side walls of the two adjacent stack structures 120A and 150A in the first direction may contact each other (see P2) to close the space between the two adjacent stack structures 120A and 150A in the first direction. In addition, the fourth cover layer 180 may have an overhanging portion whose side surface protrudes more toward the space between the two adjacent stack structures 140B and 150A in the first direction than the third cover layer 170 formed on the side walls of the two adjacent stack structures 140B and 150A. However, as FIG. 5A to FIG. 5D As shown, since the distance between the two adjacent stacked structures 140B and 150A (see D2) is greater than the distance between the two adjacent stacked structures 120A and 150A (see D1), the overhanging portions of the fourth cover layer 180 on the sidewalls of the two adjacent stacked structures 140B and 150A may not contact each other. Therefore, an opening E1 may be formed in the fourth cover layer 180.

[0056] As a result of the process, a second air gap AG2 may be formed. The second air gap AG2 may be surrounded by the third cover layer 170 and the fourth cover layer 180 between the two adjacent stack structures 120A and 150A in the first direction. More specifically, between the two adjacent stack structures 120A and 150A in the first direction, the side surface and the lower surface of the second air gap AG2 may be defined by the third cover layer 170 formed along the upper surface of the first line 110 and the side surfaces of the two adjacent stack structures 120A and 150A in the first direction, and the upper surface of the second air gap AG2 may be defined by the fourth cover layer 180. The second air gap AG2 may have a line shape extending in the second direction between the two adjacent stack structures 120A and 150A in the first direction. Therefore, the second air gap AG2 may be connected to the first air gap AG1 in the region between the two adjacent stack structures 140B and 150A in the first direction. That is, the intersection region of the first air gap AG1 and the second air gap AG2 may be formed in the region between the two adjacent stack structures 140B and 150A in the first direction. As a result, in a plan view, the first air gap AG1 and the second air gap AG2 may have a cross shape as a whole between the four memory cells 120A arranged in a 2×2 matrix. The intersection region of the first air gap AG1 and the second air gap AG2 may overlap with the opening E1 of the fourth cover layer 180, and thus may not be closed by the fourth cover layer 180. The opening E1 may be located at the center between the four memory cells 120A arranged in a 2×2 matrix, and may be located within the fourth cover layer 180.

[0057] The fourth capping layer 180 may include an insulating material. For example, the fourth capping layer 180 may include silicon oxide, silicon nitride, insulating metal oxide, insulating metal nitride, or a combination thereof. The fourth capping layer 180 may be formed of the same material as the final second capping layer pattern 140B.

[0058] refer to FIG. 7A to FIG. 7D A planarization process such as a CMP process may be performed until the upper surface of the second line 150A is exposed. As a result, the third capping layer 170 and the fourth capping layer 180 on the upper surface of the second line 150A may be removed to form a third capping layer pattern 170A and a fourth capping layer pattern 180A.

[0059] The third covering layer pattern 170A may be formed along the side surfaces of the two adjacent stacked structures 120A and 150A in the first direction and the upper surface of the first line 110 between the two adjacent stacked structures 120A and 150A in the first direction. In addition, the third covering layer pattern 170A may be formed along the side surfaces of the two adjacent stacked structures 140B and 150A in the first direction. The fourth covering layer pattern 180A may close the space between each two adjacent stacked structures 120A and 150A in the first direction and have the shape of a line extending in the second direction. The fourth covering layer pattern 180A may have an opening E1 without closing the upper part of the space between the two adjacent stacked structures 140B and 150A in the first direction. The upper surface of the third covering layer pattern 170A and the upper surface of the fourth covering layer pattern 180A may form a flat surface together with the upper surface of the second line 150A. That is, the upper surface of the third capping layer pattern 170A and the upper surface of the fourth capping layer pattern 180A may be flush with the upper surface of the second line 150A.

[0060] During the planarization process, the second air gap AG2 under the fourth capping layer pattern 180A may remain together with the first air gap AG1.

[0061] refer to FIG. 8A to FIG. 8D , the heat sink 190 may be formed by injecting a material having high thermal conductivity into the first air gap AG1 and the second air gap AG2 through the opening E1.

[0062] The heat sink 190 may absorb heat generated from the memory cell 120A, especially from the variable resistance pattern 127A, to reduce or block heat transfer from the memory cell 120A to its adjacent memory cell 120A. The heat sink 190 may include a metal with high thermal conductivity, such as silver, copper, lead, tin, magnesium, zinc, iron, gold, aluminum, iridium, molybdenum, nickel, platinum, beryllium, cadmium, cobalt, titanium, or tungsten. The heat sink 190 may include a metal compound with high thermal conductivity, such as titanium nitride or tungsten nitride. A heat dissipation pattern (not shown) may be connected to the heat sink 190 to release heat absorbed by the heat sink 190 to the outside.

[0063] The material injected into the opening E1 to form the heat sink 190 may be a flowable material. In this case, a process of curing the flowable material may be further performed in a subsequent process. At this time, by adjusting the viscosity of the flowable material to a relatively high value, the flowable material may be prevented from flowing too much into the first air gap AG1 and the second air gap AG2. Therefore, the heat sink 190 may be formed to have a columnar shape in the intersection region of the first air gap AG1 and the second air gap AG2. In one embodiment, the side surface of the heat sink 190 is substantially perpendicular to the upper surface of the substrate 100. However, in another embodiment, the heat sink 190 may have an inclined side surface so that the width of the heat sink 190 may increase from top to bottom in the third direction in a plan view. The slope of the inclined side surface may depend on the viscosity of the flowable material. In a plan view, the flat area of ​​the heat sink 190 may be greater than the flat area of ​​the opening E1, and may also be equal to or greater than the flat area of ​​the intersection region of the first air gap AG1 and the second air gap AG2. The heat sink 190 may be located at the center of the four memory cells 120A arranged in a 2×2 matrix.

[0064] Therefore, it can be FIG. 8A to FIG. 8D The memory device is manufactured as shown.

[0065] Reference again FIG. 8A to FIG. 8D The memory device of this embodiment may include: a plurality of first lines 110 formed above a substrate 100 and extending in a first direction; a plurality of second lines 150A formed above the first lines 110 and extending in a second direction; and a plurality of memory cells 120A formed in a third direction in an intersection region of the first lines 110 and the second lines 150A between the first lines 110 and the second lines 150A.

[0066] Here, the heat sink 190 having a columnar shape may be located at the center of the four storage cells 120A arranged in a 2×2 matrix. That is, the heat sink 190 may be located between two adjacent storage cells 120A in a diagonal direction relative to the first direction and the second direction. The heat generated from the storage cells 120A may move in a direction toward the heat sink 190 (i.e., in a diagonal direction relative to the first direction and the second direction). Because the heat sink 190 has a high thermal conductivity, the heat moves toward the heat sink 190. Therefore, thermal interference caused by heat transfer between the storage cells 120A may be significantly reduced or prevented.

[0067] The first air gap AG1 extending in the first direction may be provided between two adjacent storage cells 120A arranged in the second direction, and the second air gap AG2 extending in the second direction may be provided between two adjacent storage cells 120A arranged in the first direction. Since the first air gap AG1 and the second air gap AG2 are filled with air having low thermal conductivity, heat transfer between the storage cells 120A arranged in the first direction and the second direction may be reduced or prevented. In particular, as described above, since heat is concentrated to the heat sink 190, heat transfer in the first direction and the second direction may be further reduced or prevented.

[0068] The heat sink 190 may be disposed in each intersection region of the first air gap AG1 and the second air gap AG2. Therefore, both side surfaces or side walls of the memory cell 120A in the second direction may be electrically insulated from the heat sink 190 while being protected by the final first capping layer pattern 130B, and both side surfaces or side walls of the memory cell 120A in the first direction may be electrically insulated from the heat sink 190 while being protected by the third capping layer pattern 170A.

[0069] The upper portion of the first air gap AG1 between two adjacent memory cells 120A arranged in the second direction may be closed by the final second overlay pattern 140B attached to the upper portion of the final first overlay pattern 130B. Moreover, the upper portion of the second air gap AG2 between two adjacent memory cells 120A arranged in the first direction may be closed by the fourth overlay pattern 180A attached to the upper portion of the third overlay pattern 170A. However, the intersection area of ​​the first air gap AG1 and the second air gap AG2 may be opened by the opening E1 formed in the fourth overlay pattern 180A. The upper surface of the fourth overlay pattern 180A formed after the second line 150A is formed may be at a higher position in the third direction than the upper surface of the final second overlay pattern 140B formed after the initial memory cell 120 is formed.

[0070] like Fig. 8A and Figure 8C As shown, the uppermost portion of the heat sink 190 may be surrounded by the fourth capping layer pattern 180A. Figure 8C and Fig.8D As shown, except for the uppermost portion of the heat dissipation body 190 , at least a portion of the lower portion of the heat dissipation body 190 may be surrounded by the first air gap AG1 and the second air gap AG2 .

[0071] The memory device manufactured as described above can obtain the following effects.

[0072] First, by arranging a heat sink at the center of the memory cells arranged in a 2×2 matrix along the first direction and the second direction, the heat generated from the memory cells can be concentrated to the heat sink, thereby reducing the heat transfer between the memory cells. In addition, by providing an air gap between the memory cells in the first direction and the second direction, the heat transfer between the memory cells in the first direction and the second direction can be further reduced. As a result, since the thermal interference of the memory device can be reduced or prevented, the operating characteristics of the memory device can be ensured, and the reliability of the memory device can be improved.

[0073] Furthermore, the manufacturing process of the memory device is simplified by performing a process using a step coverage characteristic of an insulating material during a process of forming a heat sink and an air gap without adding an additional mask and etching process.

[0074] 9A to 10D is a diagram illustrating a semiconductor memory and a method for manufacturing the same according to another embodiment of the present disclosure. Fig.9A It is a floor plan. Fig. 9B and Fig. 9C Along the Fig.9A A sectional view taken along the lines A2-A2' and A3-A3', and Fig.9D is a plan view at the height of the upper surface of the storage unit. Fig. 10A It is a floor plan. Fig. 10B and Fig. 10C Along the Fig. 10A A sectional view taken along the lines A2-A2' and A3-A3', and Fig. 10D is a plan view at the height of the upper surface of the storage unit. FIG. 1A to FIG. 8D The described embodiments and 9A to 10D The differences between the present embodiments are shown.

[0075] First, by executing the above embodiment FIG. 1A to FIG. 5D The process can be obtained with FIG. 5A to FIG. 5D The structure is the same as the structure shown.

[0076] Then, refer to 9A to 9D The third cover layer 270 may be formed to have a certain thickness so that the third cover layer 270 completely fills the space between the stack structures 120A and 150A adjacent in the first direction but does not completely fill the space between the stack structures 140B and 150A adjacent in the first direction.

[0077] The third capping layer 270 may be formed by using a film and / or a process having excellent step coverage characteristics. FIG. 5A to FIG. 5DAn insulating material is deposited on the resulting structure, and a planarization process is performed until the upper surface of the second line 150A is exposed. The deposition process may be performed until the space between the adjacent stack structures 120A and 150A in the first direction is completely filled with the insulating material and at least a portion of the space between the adjacent stack structures 140B and 150A in the first direction is retained. As described above, since the distance D1 between the adjacent stack structures 120A and 150A in the first direction is smaller than the distance D2 between the adjacent stack structures 140B and 150A in the first direction, during the deposition process of the insulating material using a film and / or a process having excellent step coverage characteristics, the space between the adjacent stack structures 120A and 150A in the first direction may be first filled with the insulating material. When the deposition is stopped by filling the space between the adjacent stack structures 120A and 150A in the first direction, a structure such as Figures 9A to 9D A space defined by the third cover layer 270 between the stack structures 140B and 150A adjacent in the first direction will be referred to as an opening E2.

[0078] refer to FIG. 10A to FIG. 10D , the heat sink 290 may be formed by injecting a material having high thermal conductivity through the opening E2.

[0079] Therefore, it can be FIG. 10A to FIG. 10D The memory device is manufactured as shown.

[0080] Reference again FIG. 10A to FIG. 10D The memory device of this embodiment may include: a plurality of first lines 110 formed above a substrate 100 and extending in a first direction; a plurality of second lines 150A formed above the first lines 110 and extending in a second direction; and a plurality of memory cells 120A formed in a third direction in an intersection region of the first lines 110 and the second lines 150A between the first lines 110 and the second lines 150A.

[0081] Here, the heat sink 290 having a columnar shape may be located at the center between four memory cells 120 arranged in a 2×2 matrix.

[0082] The first air gap AG1 extending in the first direction may be provided between two adjacent memory cells 120A arranged in the second direction. On the other hand, the third cover layer 270, instead of the air gap, may fill the space between the two adjacent memory cells 120A arranged in the first direction. In order to make the degree of heat transfer between the memory cells 120A in the first direction equal to or close to the degree of heat transfer between the memory cells 120A in the second direction, the third cover layer 270 may be formed with an insulating material having a thermal conductivity less than or equal to that of air. For example, the third cover layer 270 may be formed with a low-k material.

[0083] The two side surfaces or side walls of the memory cell 120A in the second direction can be electrically insulated from the heat sink 290 while being protected by the final first covering layer pattern 130B, and the two side surfaces or side walls of the memory cell 120A in the first direction can be electrically insulated from the heat sink 290 while being protected by the third covering layer 270.

[0084] The uppermost portion of the heat radiating body 290 may be surrounded by the third cover layer 270. Except for the uppermost portion of the heat radiating body 290, at least a portion of the lower portion of the heat radiating body 290 may face the air gap AG1 in the first direction and may face the third cover layer 270 in the second direction.

[0085] The above and other memory circuits or semiconductor memory devices manufactured based on the disclosed technology can be applied to various devices or systems. Figures 11 to 14 Some devices or systems are provided that include the memory device disclosed herein.

[0086] Fig.11 is a configuration diagram of a microprocessor implementing a storage circuit based on the disclosed technology.

[0087] refer to Fig.11 , the microprocessor 1000 may perform a series of processing tasks for controlling and adjusting receiving data from various external devices, processing the data, and outputting the processing results to the external devices. The microprocessor 1000 may include a storage unit 1010, an operation unit 1020, a control unit 1030, etc. The microprocessor 1000 may be various data processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), and an application processor (AP).

[0088] The storage unit 1010 is a component that stores data in the microprocessor 1000, such as a processor register or registers, etc. The storage unit 1010 may include various registers, such as a data register, an address register, and a floating point register, etc. The storage unit 1010 may perform the following functions: temporarily storing data to be operated by the operation unit 1020, result data of performing the operation, and an address where the data for performing the operation is stored.

[0089] The memory cell 1010 may include one or more of the semiconductor devices described above according to the embodiments. For example, the memory cell 1010 may include: a plurality of first lines extending in a first direction; a plurality of second lines above the first lines, the second lines extending in a second direction intersecting the first direction; a plurality of memory cells arranged at the intersection of the first line and the second line between the first line and the second line in a third direction perpendicular to the first direction and the second direction; and a heat sink located between two memory cells adjacent to each other in a diagonal direction relative to the first direction and the second direction. In this way, the reliability and operating characteristics of the memory cell 1010 can be improved, and its manufacturing process can be facilitated. As a result, the operating characteristics of the microprocessor 1000 can be improved.

[0090] The operation unit 1020 may perform four arithmetic operations or logic operations according to the result of decoding the command by the control unit 1030. The operation unit 1020 may include at least one arithmetic logic unit (ALU) and the like.

[0091] The control unit 1030 may receive signals from the storage unit 1010, the operation unit 1020, and external devices of the microprocessor 1000, extract and decode commands from the received signals, control input and output of signals of the microprocessor 1000, and execute processing represented by a program.

[0092] The microprocessor 1000 according to this embodiment may further include a cache memory unit 1040 that may temporarily store data to be input from an external device other than the storage unit 1010 or data to be output to an external device. In this case, the cache memory unit 1040 may exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

[0093] Fig.12 is a configuration diagram of a processor implementing a storage circuit based on the disclosed technology.

[0094] refer to Fig.12 , the processor 1100 may include the above Fig.11The processor 1100 may include a core unit 1110 used as a microprocessor, a cache memory unit 1120 for temporarily storing data, and a bus interface 1130 for transmitting data between internal and external devices. The processor 1100 may include various systems on chip (SoCs) such as a multi-core processor, a graphics processing unit (GPU), and an application processor (AP).

[0095] The core unit 1110 of this embodiment is a part that performs arithmetic logic operations on data input from an external device, and may include a storage unit 1111, an operation unit 1112, and a control unit 1113. The storage unit 1111, the operation unit 1112, and the control unit 1113 may be connected to Fig.11 The storage unit 1010, the computing unit 1020 and the control unit 1030 shown are substantially the same.

[0096] The cache memory unit 1120 is a part that temporarily stores data, thereby compensating for the difference in data processing speed between the core unit 1110 operating at a high speed and the external device operating at a low speed. The cache memory unit 1120 may include a primary storage part 1121 and a secondary storage part 1122. In addition, in the case where a high storage capacity is required, the cache memory unit 1120 may include a tertiary storage part 1123. If necessary, the cache memory unit 1120 may include a larger number of storage parts. That is, the number of storage parts included in the cache memory unit 1120 may be changed according to the design. The speeds of storing and distinguishing data in the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 may be the same or different. In the case where the speeds of the respective storage parts 1121, 1122, and 1123 are different, the speed of the primary storage part 1121 may be the fastest. At least one of the primary storage part 1121, the secondary storage part 1122, and the tertiary storage part 1123 of the cache memory unit 1120 may include one or more of the above-mentioned semiconductor devices according to the embodiments. For example, the cache memory unit 1120 may include: a plurality of first lines extending in a first direction; a plurality of second lines above the first lines, the second lines extending in a second direction intersecting the first direction; a plurality of storage units arranged at the intersection area between the first lines and the second lines in a third direction perpendicular to the first direction and the second direction; and a heat sink located between two storage units adjacent to each other in a diagonal direction relative to the first direction and the second direction. In this way, in the cache memory unit 1120, reliability and operating characteristics can be improved, and the manufacturing process can be simplified. As a result, the operating characteristics of the processor 1100 are improved.

[0097] Although in this embodiment it is shown that the primary storage part 1121, the secondary storage part 1122 and the tertiary storage part 1123 are all configured inside the cache memory unit 1120, at least one of the primary storage part 1121, the secondary storage part 1122 and the tertiary storage part 1123 of the cache memory unit 1120 may be configured outside the core unit 1110, and the difference in data processing speed between the core unit 1110 and the external device may be compensated.

[0098] The bus interface 1130 is a component that connects the core unit 1110 , the cache unit 1120 , and external devices and allows data to be efficiently transferred.

[0099] The processor 1100 according to the present embodiment may include a plurality of core units 1110, and the plurality of core units 1110 may share a cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or connected through a bus interface 1130. The plurality of core units 1110 may be configured in the same manner as the configuration of the above-described core units 1110. The storage portion in each core unit 1110 may be configured to be shared with a storage portion outside the core unit 1110 through the bus interface 1130.

[0100] The processor 1100 according to this embodiment may further include: an embedded storage unit 1140 that stores data; a communication module unit 1150 that can send data to an external device and receive data from an external device in a wired or wireless manner; a memory control unit 1160 that drives an external storage device; and a media processing unit 1170 that processes data processed in the processor 1100 or data input from an external input device, and outputs the processed data to an external interface device, etc. In addition, the processor 1100 may include a plurality of modules and devices. In this case, the plurality of modules may exchange data with the core unit 1110 and the cache memory unit 1120 and with each other through the bus interface 1130.

[0101] The embedded storage unit 1140 may include not only volatile memory but also non-volatile memory. The volatile memory may include one or more of DRAM (dynamic random access memory), mobile DRAM, SRAM (static random access memory), and memory having functions similar to the above-mentioned memory. The non-volatile memory may include ROM (read-only memory), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and one or more of memory having functions similar to the above-mentioned memory.

[0102] The communication module unit 1150 may include a module that can be connected to a wired network, a module that can be connected to a wireless network, or may include both. The wired network module may include a local area network (LAN), a universal serial bus (USB), Ethernet, a power line communication (PLC), and various devices such as sending and receiving data through a transmission line. The wireless network module may include an infrared data association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), wireless LAN, Zigbee, ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), broadband CDMA (WCDMA), ultra-wideband (UWB), and various devices such as sending and receiving data without a transmission line.

[0103] The memory control unit 1160 manages and processes data transmitted between the processor 1100 and an external storage device operating according to different communication standards. The memory control unit 1160 may include various memory controllers, such as devices that can control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), SSD (Solid State Drive), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), USB (Universal Serial Bus), Secure Digital (SD) Card, Mini Secure Digital (mSD) Card, Micro Secure Digital (micro SD) Card, Secure Digital High Capacity (SDHC) Card, Memory Stick Card, Smart Media (SM) Card, Multimedia Card (MMC), Embedded MMC (eMMC) and Compact Flash (CF) Card, etc.

[0104] The media processing unit 1170 may process data processed in the processor 1100 or data input from an external interface device in the form of images, voices, and others, and output the data to the external interface device. The media processing unit 1170 may include one or more of the following: a graphics processing unit (GPU), a digital signal processor (DSP), a high-definition audio device (HD audio), and a high-definition multimedia interface (HDMI) controller, etc.

[0105] Fig.13 is a configuration diagram of a system implementing a storage circuit based on the disclosed technology.

[0106] refer to Fig.13 , the system 1200 as a device for processing data can perform input, processing, output, communication, storage, etc. to perform a series of operations on data. The system 1200 may include a processor 1210, a main storage device 1220, an auxiliary storage device 1230, and an interface device 1240, etc. The system 1200 of this embodiment may be various electronic systems operated using a processor, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a recorder, telematics, an audio-visual (AV) system, and a smart TV, etc.

[0107] The processor 1210 may decode an input command, process operations and comparisons on data stored in the system 1200, and control these operations. The processor 1210 may be substantially the same as the microprocessor 1000 or the processor 1100 described above.

[0108] The main memory device 1220 is a storage device that can temporarily store, call and execute program codes or data from the auxiliary memory device 1230 when the program is executed, and can save the stored content even when the power is cut off. The auxiliary memory device 1230 is a storage device for storing program codes or data. Although the auxiliary memory device 1230 is slower than the main memory device 1220, the auxiliary memory device 1230 can store a larger amount of data. The main memory device 1220 or the auxiliary memory device 1230 may include one or more of the above-mentioned semiconductor devices according to the embodiments. For example, the main memory device 1220 or the auxiliary memory device 1230 may include: a plurality of first lines extending in a first direction; a plurality of second lines above the first line, the second line extending in a second direction intersecting the first direction; a plurality of storage cells arranged between the first line and the second line in a third direction perpendicular to the first direction and the second direction at the intersection area of ​​the first line and the second line; and a heat sink located between two storage cells adjacent to each other in a diagonal direction relative to the first direction and the second direction. As such, in the main memory device 1220 or the auxiliary memory device 1230, reliability and operating characteristics can be improved, and a manufacturing process thereof can be simplified. As a result, operating characteristics of the system 1200 are improved.

[0109] In addition, in addition to the above-mentioned semiconductor device or in the case where the above-mentioned semiconductor device is not included, the main memory device 1220 or the auxiliary memory device 1230 may further include a storage system (see Fig.14 1300).

[0110] The interface device 1240 can execute command and data exchange between the system 1200 of this embodiment and external devices. The interface device 1240 can be a keypad, a keyboard, a mouse, a speaker, a microphone, a display, various human-computer interaction devices (HID), a communication device, or a combination thereof. The communication device can communicate with the above Fig.12 The communication module unit 1150 is basically the same.

[0111] Fig.14 is a configuration diagram of a memory system implementing a memory circuit based on the disclosed technology.

[0112] refer to Fig.14, the storage system 1300 may include: a memory 1310 having a non-volatile characteristic as a component for storing data; a controller 1320 for controlling the memory 1310; an interface 1330 for connecting with an external device; and a buffer memory 1340 for temporarily storing data to effectively transfer data between the interface 1330 and the memory 1310. The storage system 1300 may simply represent a memory for storing data, and may also represent a data storage device for long-term preservation of stored data. The storage system 1300 may be a disk type such as a solid state disk (SSD), or may be a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), or a compact flash (CF) card, etc.

[0113] The memory 1310 or the buffer memory 1340 may include one or more of the above-mentioned semiconductor devices according to the embodiments. For example, the memory 1310 or the buffer memory 1340 may include: a plurality of first lines extending in a first direction; a plurality of second lines above the first lines, the second lines extending in a second direction intersecting the first direction; a plurality of storage units arranged between the first lines and the second lines in a third direction perpendicular to the first direction and the second direction at the intersection area of ​​the first lines and the second lines; and a heat sink located between two adjacent storage units in a diagonal direction relative to the first direction and the second direction. Thus, in the memory 1310 or the buffer memory 1340, reliability and operating characteristics can be improved, and the manufacturing process can be simplified. As a result, the operating characteristics of the memory system 1300 are improved.

[0114] The memory 1310 or the buffer memory 1340 may include one or more of various memories such as a nonvolatile memory and a volatile memory in addition to the above-mentioned semiconductor device or without including the above-mentioned semiconductor device.

[0115] The controller 1320 may control data exchange between the memory 1310 and the interface 1330. To this end, the controller 1320 may include a processor 1321 for performing operations such as processing a command input from the outside of the memory system 1300 through the interface 1330, and the like.

[0116] The interface 1330 performs the exchange of commands and data between the storage system 1300 and the external device. In the case where the storage system 1300 is a card type or a disk type, the interface 1330 may be compatible with an interface used in a device having a card type or a disk type, or may be compatible with an interface used in a device similar to the above devices. The interface 1330 may be compatible with one or more interfaces having different types from each other.

[0117] Based on the above-mentioned memory device disclosed in this document Figures 11 to 14 The features of the examples of electronic devices or systems can be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or portable computers, game consoles, smart TVs, TV set-top boxes, multimedia servers, digital cameras with or without wireless communication capabilities, and watches or other wearable devices with wireless communication capabilities.

[0118] Although the patent document contains many details, these details should not be interpreted as limitations on any invention scope or the scope that can be claimed, but rather as descriptions of specific features of specific embodiments of specific inventions. Certain features described in the context of different embodiments in this patent document may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination, respectively. Moreover, although the features may be described as working in certain combinations and even initially claimed in this way, one or more features of the combination may be deleted from the claimed combination in some cases, and the claimed combination may be directed to a variant of a sub-combination or a sub-combination.

[0119] Similarly, although operations are depicted in a particular order in the drawings, this should not be understood as requiring that these operations should be performed in the particular order shown or in a sequential order or that all illustrated operations should be performed in order to obtain the desired results. In addition, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0120] Only some embodiments and examples are described. Other embodiments, enhancements, and variations can be made based on what is described and illustrated in this patent document.

Claims

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: a plurality of first lines extending in a first direction; a plurality of second lines above the first lines, the second lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at a crossing region of the first line and the second line between the first line and the second line in a third direction perpendicular to the first direction and the second direction; a first air gap located between two adjacent memory cells in the second direction; a second air gap located between two adjacent memory cells in the first direction; and A heat sink is located between two adjacent storage units in a diagonal direction relative to the first direction and the second direction and overlaps an intersection region of the first air gap and the second air gap.

2. The electronic device according to claim 1, wherein: The heat sink has a columnar shape.

3. The electronic device according to claim 1, wherein: The first air gap extends in the first direction, The second air gap extends in the second direction.

4. The electronic device according to claim 1, wherein: The semiconductor memory further comprises: A first covering layer pattern, which is located on two side walls of the storage unit in the second direction; a second capping layer pattern that closes an upper portion of a space between the first capping layer patterns on side walls of two adjacent memory cells in the second direction; a third covering layer pattern located on two sidewalls of the memory cell in the first direction; and A fourth capping layer pattern closes an upper portion of a space between the third capping layer patterns on the sidewalls of two adjacent memory cells in the first direction.

5. The electronic device according to claim 4, wherein: The uppermost portion of the heat sink is surrounded by the fourth covering layer pattern.

6. The electronic device according to claim 5, wherein: The spaces between the first covering layer patterns and the spaces between the third covering layer patterns are filled with air, and At least a portion of the lower portion of the heat sink is surrounded by the air.

7. The electronic device according to claim 1, wherein: Both side walls of the memory cell in the first direction are aligned with the second line, and Both sidewalls of the memory cell in the second direction are aligned with the first line.

8. The electronic device according to claim 7, wherein: In the first direction, a portion of the second line overlapping the memory cell has a first width, and a portion of the second line overlapping a space between two adjacent memory cells in the second direction has a second width, and The first width is greater than the second width.

9. The electronic device according to claim 1, wherein: The memory cell includes a phase change material.

10. The electronic device according to claim 1, further comprising a microprocessor, the microprocessor comprising: a control unit configured to receive a signal including a command from outside the microprocessor and perform extraction and decoding of the command or control input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result of decoding the command by the control unit; and a storage unit configured to store data used to perform the operation, data corresponding to a result of performing the operation, or an address of data on which the operation is performed, The semiconductor memory is a part of the storage unit in the microprocessor.

11. The electronic device according to claim 1, further comprising a processor, the processor comprising: a core unit configured to execute an operation corresponding to a command input from outside the processor by using data based on the command; a cache memory unit configured to store data used to perform the operation, data corresponding to a result of performing the operation, or an address of data on which the operation is performed; and a bus interface connected between the core unit and the cache memory unit and configured to transmit data between the core unit and the cache memory unit; The semiconductor memory is part of the cache memory unit in the processor.

12. The electronic device according to claim 1, further comprising a processing system, the processing system comprising: a processor configured to decode a command received by the processor and control an operation on information based on a result of decoding the command; an auxiliary storage device configured to store a program for decoding the command and the information; a main storage device configured to call the program and the information from the auxiliary storage device and store them, so that the processor can use the program and the information to perform the operation when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device, and the main memory device and an external device, The semiconductor memory is a part of the auxiliary memory device or the main memory device in the processing system.

13. The electronic device according to claim 1, further comprising a storage system, the storage system comprising: a memory configured to store data and retain the stored data regardless of the presence or absence of power; a memory controller configured to control data input to and data output from the memory according to a command input from the outside; a buffer memory configured to buffer data exchanged between the memory and the external part; and an interface configured to perform communication between at least one of the memory, the memory controller, and the buffer memory and the outside, The semiconductor memory is a part of the memory or the buffer memory in the storage system.

14. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises: a plurality of first lines extending in a first direction; a plurality of second lines above the first lines, the second lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at a crossing region of the first line and the second line between the first line and the second line in a third direction perpendicular to the first direction and the second direction; a heat sink located between two adjacent storage units in a diagonal direction relative to the first direction and the second direction; an air gap located between two adjacent memory cells in the second direction; and a third covering layer located between two adjacent memory cells in the first direction, wherein the air gap extends in the first direction, The third covering layer extends in the second direction, and The heat sink is in contact with the air gap in the first direction and in contact with the third cover layer in the second direction.

15. The electronic device according to claim 14, wherein: The semiconductor memory further comprises: A first covering layer pattern, which is located on two side walls of the storage unit in the second direction; a second capping layer pattern that closes an upper portion of a space between the first capping layer patterns on sidewalls of two adjacent memory cells in the second direction; and A third covering layer fills a space between two adjacent memory cells in the first direction.

16. The electronic device according to claim 15, wherein: When the heat sink is located beside the two adjacent storage cells in the first direction, the uppermost portion of the heat sink is surrounded by the third cover layer.

17. The electronic device according to claim 16, wherein: The spaces between the first covering layer patterns are filled with air, and The heat sink is in contact with the air in the first direction and is in contact with the third cover layer in the second direction.

18. The electronic device according to any one of claims 14 to 17, wherein: The thermal conductivity of the third covering layer is less than or equal to the thermal conductivity of air.

19. A method for manufacturing an electronic device, the electronic device comprising a semiconductor memory, the method comprising: forming a plurality of stacked structures extending in a first direction over a substrate, each of the stacked structures comprising a first line and an initial memory cell; forming a first covering layer on two side walls of the stacked structure in a second direction intersecting the first direction; forming a second cover layer that closes an upper portion of a space between the first cover layers formed on side walls of the two stacked structures facing each other in the second direction; forming a conductive layer over the stacked structure, the first cover layer, and the second cover layer; forming a plurality of mask patterns extending in the second direction over the conductive layer; Using the mask pattern as an etching barrier layer to etch the conductive layer, the stacked structure, the first capping layer, and the second capping layer to form a second line, a memory cell, a first capping layer pattern, and a second capping layer pattern, wherein a width between two adjacent memory cells in the first direction is smaller than a width between the second capping layer patterns in the first direction; and A heat sink is formed in the space between the second capping layer patterns.

20. The method according to claim 19, after the step of forming the second line, the memory cell, the first capping layer pattern and the second capping layer pattern, further comprising: forming a third capping layer pattern on sidewalls of the second line, the memory cell, the first capping layer pattern, and the second capping layer pattern in the first direction, and forming a fourth capping layer pattern, and The fourth covering layer pattern closes the upper portion of the space between the third covering layer patterns formed on the storage unit in the first direction, and the fourth covering layer pattern has an opening, which makes the upper portion of the space between the third covering layer patterns formed on the side wall of the second covering layer pattern in the first direction open.

21. The method according to claim 20, wherein: The step of forming the heat sink comprises: A material for forming the heat sink is injected through the opening.

22. The method according to claim 19, after the step of forming the second line, the memory cell, the first capping layer pattern and the second capping layer pattern, further comprising: forming a third capping layer on sidewalls of the second line, the memory cell, the first capping layer pattern, and the second capping layer pattern in the first direction, and The third covering layer fills the space between the memory cells in the first direction, but does not completely fill the space between the second covering layer patterns in the first direction.

23. The method according to claim 22, wherein: The step of forming the heat sink comprises: A material for forming the heat sink is injected into a space between the second capping layer patterns in the first direction.

24. The method according to claim 22, wherein: The space between the first covering layers closed by the second covering layer is filled with air, and The thermal conductivity of the third covering layer is less than or equal to the thermal conductivity of the air.

25. The method of claim 19, wherein: The heat sink has a columnar shape.

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