Semiconductor Device and Method of Forming the Same

Abstract

A semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure located within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is located between the barrier structure and the copper structure. The barrier structure is located between the substrate and the dielectric structure. Embodiments of the present application also provide a method for forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic devices, such as mobile phones, laptop computers, desktop computers, tablet computers, watches, gaming systems, and various other industrial, commercial, and consumer electronic products. Semiconductor devices typically include a semiconductor portion and a wiring portion formed within the semiconductor portion. Summary of the Invention

[0003] Some embodiments of the present application provide a semiconductor device, including: a first deep trench isolation (DTI) structure located within a substrate, wherein: the first deep trench isolation structure includes a barrier structure, a dielectric structure, and a copper structure; the dielectric structure is located between the barrier structure and the copper structure; and the barrier structure is located between the substrate and the dielectric structure.

[0004] Some other embodiments of the present application provide a semiconductor device, including: a photodiode located within a substrate; a first dielectric layer located over the substrate, wherein: a first portion of the first dielectric layer is located over the photodiode; the first portion of the first dielectric layer has a tapered sidewall; and a first portion of the substrate separates the first portion of the first dielectric layer from the photodiode; and a first deep trench isolation (DTI) structure, wherein: the first deep trench isolation structure includes a barrier structure, a dielectric structure, and a copper structure; the dielectric structure is located between the barrier structure and the copper structure; and the barrier structure is located between the substrate and the dielectric structure.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, including: forming a first dielectric layer over a substrate; forming a first trench extending through the first dielectric layer and into the substrate; forming a first barrier layer over the first dielectric layer and within the first trench; forming a second dielectric layer over the first barrier layer and within the first trench; and forming a first copper layer over the second dielectric layer and within the first trench. Description of the Drawings

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figures 1 to 5 Cross-sectional views of semiconductor devices at various manufacturing stages in accordance with some embodiments are shown.

[0008] Figure 6A Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0009] Figure 6B Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0010] Figure 7A Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0011] Figure 7B Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0012] Figures 8 to 10 Shows cross-sectional views of semiconductor devices in various manufacturing stages according to some embodiments.

[0013] Figure 11A Shows a top view of a semiconductor device in a manufacturing stage according to some embodiments.

[0014] Figure 11B Shows according to some embodiments along Figure 11A A cross-sectional view of the semiconductor device taken along line B-B.

[0015] Figures 12 to 14 Shows cross-sectional views of semiconductor devices in various manufacturing stages according to some embodiments.

[0016] Figure 15A Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0017] Figure 15B Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0018] Figure 15C Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0019] Figures 16 to 17 Shows cross-sectional views of semiconductor devices in various manufacturing stages according to some embodiments.

[0020] Figure 18A Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments.

[0021] Figure 18B Shows a cross-sectional view of a semiconductor device in a manufacturing stage according to some embodiments. Detailed Description

[0022] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] In addition, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. In addition to the orientation shown in the figures, spatially relative terms are intended to include different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0024] A semiconductor device has a first deep trench isolation (DTI) structure in a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is located between the barrier structure and the copper structure. The barrier structure is located between the substrate and the dielectric structure. In some embodiments, the first DTI structure is laterally offset from a first component, such as a first photodiode in the substrate. Compared to a DTI structure without a copper structure, the first DTI structure reflects an increased amount of radiation, such as near-infrared (NIR) radiation, that propagates away from the first component and returns to the first component. Implementing a semiconductor device having the first DTI structure thus reduces the amount of crosstalk between components of the semiconductor device compared to a semiconductor device having a DTI structure without a copper structure, where a lower amount of crosstalk particularly improves the resolution of an image generated based on light detected by components in the substrate.

[0025] Figures 1 to 18B A semiconductor device 100 at various manufacturing stages is shown in accordance with some embodiments. Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8 、 Figure 9 、 Figure 10 、Figure 12 , Figure 13 , Figure 14 , Figure 15A , Figure 15B , Figure 15C , Figure 16 , Figure 17 , Figure 18A and Figure 18B show a cross-sectional view of the semiconductor device 100. Figure 11A shows a top view of the semiconductor device 100, and Figure 11B shows a cross-sectional view of the semiconductor device 100 taken along line B-B of Figure 11A .

[0026] In some embodiments, the sensor is implemented by the semiconductor device 100. The sensor includes at least one of an image sensor, a proximity sensor, a time-of-flight (ToF) sensor, an indirect ToF (iToF) sensor, a back-illuminated (BSI) sensor, a complementary metal-oxide-semiconductor (CMOS) image sensor, a back-side CMOS image sensor, or other types of sensors. Other structures and / or configurations of the semiconductor device 100 and / or the sensor are within the scope of the present invention.

[0027] Figure 1 shows a semiconductor device 100 according to some embodiments. The semiconductor device 100 includes a first substrate 102, an interconnect structure 122, and a second substrate 118. In some embodiments, the first substrate 102 corresponds to the device wafer of the semiconductor device 100, and the second substrate 118 corresponds to the carrier wafer of the semiconductor device 100. The first substrate 102 has a first side 126 and a second side 124, where the first side 126 corresponds to the back side of the first substrate 102, and the second side 124 corresponds to the front side of the first substrate 102.

[0028] The first substrate 102 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. The first substrate 102 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimony, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. The first substrate 102 includes at least one of single-crystalline silicon, crystalline silicon having a <100> crystal orientation, crystalline silicon having a <110> crystal orientation, crystalline silicon having a <111> crystal orientation, or other suitable materials. The first substrate 102 has at least one doped region. Other structures and / or configurations of the first substrate 102 are within the scope of the present invention.

[0029] In some embodiments, semiconductor device 100 includes components 104 in a first substrate 102. Components 104 are formed by at least one of doping, ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, components 104 include photodiodes, such as at least one of a pinned-layer photodiode, a phototransistor, a photogate, or other suitable components. At least some of components 104 may be different from each other to have at least one of different heights, thicknesses, widths, material compositions, etc. Any number of components 104 in the first substrate 102 may be contemplated.

[0030] At least some of components 104 include at least one of germanium, indium, phosphorus, BF2, arsenic, antimony, fluorine, InAs, InSb, GaSb, GaAs, InP, silicide, or other suitable materials. Components 104 are configured to sense radiation projected onto the first substrate 102, such as incident light. At least some of components 104 may include materials having a relatively high absorbance for NIR wavelengths, such as radiation having a wavelength between about 700 nanometers and about 2500 nanometers. Other structures and / or configurations of components 104 are within the scope of the present invention.

[0031] Interconnect structure 122 includes one or more interconnect layers, such as at least one of a first interconnect layer 106, a second interconnect layer 108, a third interconnect layer 110, or a fourth interconnect layer 112. One or more interconnect layers of interconnect structure 122 include patterned dielectric layers and / or conductive layers that provide interconnects between at least one of the various doped components, circuits, input / outputs, etc. of semiconductor device 100, such as wiring. In some embodiments, interconnect structure 122 includes an interlayer dielectric and a multi-layer interconnect structure, such as at least one of contacts, vias, metal lines, or other types of structures. Other structures and configurations of interconnect structure 122 are within the scope of the present invention. For illustrative purposes, interconnect structure 122 includes wire 120, wherein the position and configuration of such wire may vary according to design requirements. Interconnect structure 122 is located on top of the first substrate 102, in direct contact with the first substrate 102, or in indirect contact with the first substrate 102.

[0032] The second substrate 118 includes at least one of an epitaxial layer, an SOI structure, a wafer, or a die formed from a wafer. The second substrate 118 includes at least one of silicon, germanium, carbide, arsenide, gallium, arsenic, phosphide, indium, antimony, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or other suitable materials. The second substrate 118 includes at least one of single-crystalline silicon, crystalline silicon having a <100> crystal orientation, crystalline silicon having a <110> crystal orientation, crystalline silicon having a <111> crystal orientation, or other suitable materials. The second substrate 118 has at least one doped region. Other structures and / or configurations of the second substrate 118 are within the scope of the present invention.

[0033] In some embodiments, the second substrate 118 is bonded to the interconnect structure 122, such as by at least one of one or more bonding layers, adhesives, bonding processes, or other suitable techniques. In some embodiments where one or more bonding layers are used to bond the second substrate 118 to the interconnect structure 122, the one or more bonding layers are located between the second substrate 118 and the interconnect structure 122. The second substrate 118 is at least one of above the interconnect structure 122, in direct contact with the interconnect structure 122, or in indirect contact with the interconnect structure 122.

[0034] Figure 2 An inverted semiconductor device 100 is shown in accordance with some embodiments. An inversion operation is performed such that the first substrate 102 is above at least one of the interconnect structure 122 or the second substrate 118. As Figure 2 shown, the top surface of the first substrate 102 corresponds to the back side or the first side 126 of the first substrate 102, and the bottom surface of the first substrate 102 corresponds to the front side or the second side 124 of the first substrate 102. In some embodiments, such as after the inversion operation, a portion of the first substrate 102 on the first side 126 of the first substrate 102 is removed to reduce the thickness of the first substrate 102. The component 104 is configured to sense radiation, such as incident light, projected onto the first substrate 102 along the direction 202.

[0035] Figure 3Shows a mask layer 302 formed over a first substrate 102 according to some embodiments. The mask layer 302 is at least one of being located above the first substrate 102, in direct contact with the first substrate 102, or in indirect contact with the first substrate 102. In some embodiments, the mask layer 302 is a hard mask layer. The mask layer 302 includes at least one of an oxide, a nitride, a metal, or other suitable materials. The mask layer 302 is formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced-pressure CVD (RPCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), spin coating, growth, or other suitable techniques. Other structures and / or configurations of the mask layer 302 are within the scope of the present invention.

[0036] Figure 4 Shows a mask layer 302 patterned to form a patterned mask layer 402 over a first substrate 102. According to some embodiments, a photoresist (not shown) is used to form the patterned mask layer 402. A photoresist is formed over the mask layer 302 by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The photoresist includes a photosensitive material, wherein the properties of the photoresist (such as solubility) are affected by light. The photoresist is a negative photoresist or a positive photoresist. For a negative photoresist, when irradiated by a light source, the areas of the negative photoresist become insoluble, such that when a solvent is applied during a subsequent development stage, the unirradiated areas of the negative photoresist are removed. Thus, the pattern formed in the negative photoresist is a negative image of the pattern defined by the opaque areas (such as a mask) between the light source and the negative photoresist. In a positive photoresist, the irradiated areas of the positive photoresist become soluble and are removed by applying a solvent during development. Thus, the pattern formed in the positive photoresist is a positive image of the opaque areas (such as a mask) between the light source and the positive photoresist. One or more etchants are selective such that one or more etchants remove or etch away one or more layers exposed or uncovered by the photoresist at a rate greater than the rate at which the one or more etchants remove or etch away the photoresist. Thus, the openings in the photoresist allow one or more etchants to form corresponding openings in one or more layers below the photoresist, thereby transferring the pattern in the photoresist to one or more layers below the photoresist. After the pattern transfer, the photoresist is stripped or washed away.

[0037] The etching process for removing portions of the mask layer 302 to form the patterned mask layer 402 is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable materials. In some embodiments, the etching process implemented to remove portions of the mask layer 302 and form the patterned mask layer 402 also removes at least some of the first substrate 102, such as portions of the first substrate 102 that are beneath the openings in the patterned mask layer 402. Other processes and / or techniques for forming the patterned mask layer 402 are within the scope of the present invention.

[0038] Figure 5 Illustrated is the use of the patterned mask layer 402 to form a recess 502 in the first substrate 102 according to some embodiments. In some embodiments, an etching process is implemented to form the recess 502, where the openings in the patterned mask layer 402 allow one or more etchants to be applied during the etching process to remove portions of the first substrate 102, while the patterned mask layer 402 protects or shields portions of the first substrate 102 that are covered by the patterned mask layer 402. The etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable materials. Other processes and / or techniques for forming the recess 502 are within the scope of the present invention.

[0039] One or more recesses are located above the component 104. Any number of recesses 502 above the component 104 can be contemplated. Portions of the first substrate 102 are retained above the component 104 to separate the recesses 502 from the component 104. Other structures and / or configurations of the recesses 502 are within the scope of the present invention.

[0040] Figure 6A Illustrated is the removal of the patterned mask layer 402 according to some embodiments. After forming the recess 502, the patterned mask layer 402 is removed. The patterned mask layer 402 is removed by at least one of chemical mechanical polishing (CMP), etching, or other suitable techniques. The etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable materials. Other processes and / or techniques for removing the patterned mask layer 402 are within the scope of the present invention.

[0041] The portion of the first substrate 102 that defines the groove 502 has at least one of a first tapered sidewall 604 or a second tapered sidewall 606. At least one first tapered sidewall 604 has a first slope, such as a negative slope, or the second tapered sidewall 606 has a second slope, such as a positive slope. In some embodiments, the second slope is opposite in polarity to the first slope. In some embodiments, the groove 502 has a triangular shape. In some embodiments, the cross-sectional area of the groove 502 decreases along the direction 202 such that the width of the upper portion of the groove 502 is greater than the width of the lower portion of the groove 502. Other structures and / or configurations of the groove 502 are within the scope of the present invention.

[0042] In some embodiments, the first substrate 102 having a specific crystal orientation (such as crystalline silicon having at least one of <100>, <110>, or <111> crystal orientations) enables an etching process to form the sidewalls 604, 606. In some embodiments, portions of the first substrate 102 have different crystal orientations, such as at least one of <100>, <110>, or <111> crystal orientations, where the etching rate of the etching process is different between the different crystal orientations at least due to the different densities of the different crystal orientations, thereby producing the sidewalls 604, 606 formed by the etching process.

[0043] In some embodiments, a first portion of the first substrate 102 having the first tapered sidewall 604 and the second tapered sidewall 606 has a first crystal orientation, such as <111> crystal orientation, and a second portion of the first substrate 102 that is removed to form the groove 502 has a second crystal orientation, such as <100> crystal orientation. In some embodiments, the density of the first crystal orientation (such as surface density) is greater than the density of the second crystal orientation (such as surface density), such that the etching process removes the second portion of the first substrate 102 while little to no removal of the first portion of the first substrate 102 occurs because the etching rate of the second portion of the first substrate 102 is higher than the etching rate of the first portion of the first substrate 102. Other processes and / or techniques for forming the sidewalls that define the groove 502 are within the scope of the present invention.

[0044] The distance 602 between the top surface of the component 104 and at least one of the uppermost portion of the groove 502 or the top surface of the first substrate 102 is less than or equal to about 40,000 angstroms. The distance 608 between two adjacent grooves 502 is between about zero angstroms and about 20,000 angstroms. Other structures and / or configurations of the groove 502 are within the scope of the present invention relative to other elements, components, etc. Figure 6BA cross-sectional view of a semiconductor device 100 is shown in accordance with some embodiments in which at least some of the recesses 502 are directly adjacent to each other. In some embodiments, the recesses in a set of recesses 502a are directly adjacent to each other, such as in a serrated configuration. In some embodiments, at least some of the recesses in one or more sets of recesses 502a are located over the component 104.

[0045] Figure 7A A first dielectric layer 702 formed over a first substrate 102 is shown in accordance with some embodiments. In some embodiments, the first dielectric layer 702 is in direct contact with the top surface of the first substrate 102 and / or the sidewalls defined in the first substrate 102, such as the sidewalls defining the recesses 502. In some embodiments, the first dielectric layer 702 is in indirect contact with the top surface of the first substrate 102 and / or the sidewalls defined in the first substrate 102. Other structures and / or configurations of the first dielectric layer 702 are within the scope of the present invention.

[0046] In some embodiments, the semiconductor device 100 includes a buffer layer (not shown) located between the first substrate 102 and the first dielectric layer 702, such as formed over the first substrate 102 before forming the first dielectric layer 702. The buffer layer is in direct contact with the top surface of the first substrate 102 and / or the sidewalls defined in the first substrate 102, such as the sidewalls defining the recesses 502, or in indirect contact with the top surface of the first substrate 102 and / or the sidewalls defined in the first substrate 102.

[0047] The buffer layer includes at least one of an anti-reflection coating, SiO2, HfSiON, HfSiO x , HfAlO x , HfO2, ZrO2, La2O3, Y2O3, or other suitable materials. The buffer layer is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the buffer layer includes a single layer configured to provide adhesion between the first dielectric layer 702 and the first substrate 102. According to some embodiments, the buffer layer includes multiple layers, wherein the outer layer of the multiple layers is configured to provide adhesion to the first dielectric layer 702. When the semiconductor device 100 includes a buffer layer, the first dielectric layer 702 is located over the buffer layer, in direct contact with the top surface of the buffer layer, or in indirect contact with the top surface of the buffer layer, at least one of which. Other structures and / or configurations of the buffer layer are within the scope of the present invention.

[0048] The first dielectric layer 702 comprises at least one of SiO, SiO2, SiN, Si3N4, MgO, Al2O3, Yb2O3, ZnO, Ta2O5, ZrO2, HfO2, TeO2, TiO2, or other suitable materials. The first dielectric layer 702 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The first dielectric layer 702 is formed in at least one of the grooves 502 or above the top surface of the first substrate 102. The distance 708 between the top surface of the first dielectric layer 702 and the top surface of the first substrate 102 is less than or equal to about 10,000 angstroms.

[0049] A first portion 702a of the first dielectric layer 702 is located in the groove 502. The first portion 702a of the first dielectric layer 702 has a third tapered sidewall 704, which is aligned with the first tapered sidewall 604 of the first substrate 102. When the semiconductor device 100 includes a buffer layer above the first substrate 102, a portion of the buffer layer separates the third tapered sidewall 704 of the first portion 702a of the first dielectric layer 702 from the first tapered sidewall 604 of the first substrate 102.

[0050] The first portion 702a of the first dielectric layer 702 has a fourth tapered sidewall 706, which is aligned with the second tapered sidewall 606 of the first substrate 102. When the semiconductor device 100 includes a buffer layer above the first substrate 102, a portion of the buffer layer separates the fourth tapered sidewall 706 of the first portion 702a of the first dielectric layer 702 from the second tapered sidewall 606 of the first substrate 102. The first portion 702a of the first dielectric layer 702 is located above the component 104. At least one of a portion of the buffer layer or a first portion 102a of the first substrate 102 separates the first portion 702a of the first dielectric layer 702 from the component 104.

[0051] The first portion 702a of the first dielectric layer 702 in the groove 502 is a HA structure 710, such as at least in part due to at least one of the third tapered sidewall 704, the first tapered sidewall 604, the fourth tapered sidewall 706, or the second tapered sidewall 606. The HA structure 710 directs more radiation to the component 104 below the first portion 702a of the first dielectric layer 702 compared to portions of the first dielectric layer 702 and the first substrate 102 that do not have one or more tapered sidewalls. One or more additional portions of the first dielectric layer 702 in the groove 502 in the first substrate 102 are similarly configured HA structures 710 located above the component 104. Other structures and / or configurations of the HA structure 710 are within the scope of the present invention.

[0052] The distance 712 between two adjacent HA structures 710 is between about zero angstroms and about 20,000 angstroms. Other structures and / or configurations of the HA structure 710 are within the scope of the present invention relative to other elements, components, etc. Figure 7B A cross-sectional view of a semiconductor device 100 is shown according to some embodiments in which at least some HA structures 710 are directly adjacent to each other. In some embodiments, the HA structures in a group of HA structures 710a are directly adjacent to each other, such as in a zigzag configuration. In some embodiments, at least some of the HA structures in one or more groups of HA structures 710a are located on top of the component 104.

[0053] Figure 8 A photoresist 802 formed over a first dielectric layer 702 is shown according to some embodiments. The photoresist 802 is at least one of being located on top of the first dielectric layer 702, in direct contact with the first dielectric layer 702, or in indirect contact with the first dielectric layer 702. The photoresist 802 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The photoresist 802 includes a photosensitive material, where the properties (such as solubility) of the photoresist 802 are affected by light. The photoresist 802 is a negative photoresist or a positive photoresist.

[0054] Figure 9 A photoresist 802 patterned to form a patterned photoresist 902 over the first dielectric layer 702 is shown according to some embodiments. The patterned photoresist 902 has openings that expose portions of the first dielectric layer 702. In some embodiments, the openings in the patterned photoresist 902 are located between the components 104 such that the openings are not located on top of the components 104 or are laterally offset from the components 104. In some embodiments, the openings in the patterned photoresist 902 are located between two adjacent components 104 such that the openings are located over a portion of the first substrate 102 between the first component 104 and the second component 104. According to some embodiments, the openings in the patterned photoresist 902 are located over portions of the components 104.

[0055] Figure 10FIG. 1002 shows trenches 1002 formed using patterned photoresist 902 according to some embodiments. The trenches 1002 extend through the first dielectric layer 702 and into the first substrate 102. The trenches 1002 are laterally offset from the components or are located between at least two of the components 104. In some embodiments, the trenches 1002 are located between two adjacent components 104, a second portion 102b of the first substrate 102 separates the trenches 1002 from the first of the two adjacent components 104, and a third portion 102c of the first substrate 102 separates the trenches 1002 from the second of the two adjacent components 104. In some embodiments, an etching process is implemented to form the trenches 1002, wherein the openings in the patterned photoresist 902 allow one or more etchants to be applied during the etching process to remove portions of the first dielectric layer 702 and / or the first substrate 102, while the patterned photoresist 902 protects or shields the portions of the first dielectric layer 702 and / or the first substrate 102 covered by the patterned photoresist 902. The etching process is at least one of a dry etching process, a wet etching process, an anisotropic etching process, an isotropic etching process, or another suitable etching process. The etching process uses at least one of HF, diluted HF, HCl2, H2S, or other suitable materials. Other processes and / or techniques for forming the trenches 1002 are within the scope of the present invention.

[0056] Figures 11A to 11B FIG. 174 shows removal of the patterned photoresist 902 according to some embodiments. After forming the trenches 1002, the patterned photoresist 902 is removed. The patterned mask layer 402 is removed by at least one of CMP, etching, or other suitable techniques. In some embodiments, removal of the patterned mask layer 402 exposes the top surface of the first dielectric layer 702 (as Figure 11A shown).

[0057] The portion of the first substrate 102 that defines the trenches 1002 has a first sidewall 1004 and a second sidewall 1006 (as Figure 11B shown). In some embodiments, at least some of the first sidewalls 1004 are tapered and / or at least some of the second sidewalls 1006 are tapered. The first sidewall 1004 has a first slope, such as a negative slope, and / or the second sidewall 1006 has a second slope, such as a positive slope. In some embodiments, the second slope is opposite in polarity to the first slope.

[0058] The portion of the trench 1002 defined in the first dielectric layer 702 has a third sidewall 1008 and a fourth sidewall 1010. In some embodiments, at least some of the third sidewall 1008 are tapered and / or at least some of the fourth sidewall 1010 are tapered. The third sidewall 1008 has a first slope, such as a negative slope, and / or the fourth sidewall 1010 has a second slope, such as a positive slope. In some embodiments, the second slope is opposite in polarity to the first slope. In some embodiments, the cross-sectional area of the trench 1002 decreases along the direction 202, such that the width of the upper portion of the trench 1002 is greater than the width of the lower portion of the trench 1002.

[0059] According to some embodiments, at least some of the sidewalls defining the trench 1002 (such as at least some of the first sidewall 1004, at least some of the second sidewall 1006, at least some of the third sidewall 1008, and / or at least some of the fourth sidewall 1010) extend vertically (such as in a direction parallel to the direction 202). Other structures and / or configurations of the trench 1002 are within the scope of the present invention.

[0060] In some embodiments, the lowermost portion of the trench 1002 is lower than the uppermost portion of the component 104. According to some embodiments, the lowermost portion of the trench 1002 is higher than the lowermost portion of the component 104. According to some embodiments, the lowermost portion of the trench 1002 is lower than the lowermost portion of the component 104. According to some embodiments, the lowermost portion of the trench 1002 is flush with or coplanar with the lowermost portion of the component 104. Other structures and / or configurations of the trench 1002 relative to the component 104, other elements, components, etc. are within the scope of the present invention.

[0061] Figure 12 A first barrier layer 1202 formed above the first dielectric layer 702 and in the trench 1002 is shown according to some embodiments. In some embodiments, the first barrier layer 1202 is in direct contact with the top surface of the first dielectric layer 702 and / or the first substrate 102 and / or the sidewalls defined in the first dielectric layer 702 (such as the sidewalls defining the trench 1002). In some embodiments, the first barrier layer 1202 is in indirect contact with the top surface of the first dielectric layer 702 and / or the first substrate 102 and / or the sidewalls defined in the first dielectric layer 702. Other structures and / or configurations of the first barrier layer 1202 relative to other elements, components, etc. are within the scope of the present invention.

[0062] The first barrier layer 1202 includes at least one of aluminum oxide, Al2O3, hafnium oxide, tantalum nitride, or other suitable materials. The first barrier layer 1202 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques.

[0063] A first portion of the first barrier layer 1202 is located in the trench 1002. The first portion of the first barrier layer 1202 has a fifth sidewall 1204, and at least one of the first sidewall 1004 of the first substrate 102 or the third sidewall 1008 of the first dielectric layer 702 is aligned with the fifth sidewall 1204. The first portion of the first barrier layer 1202 in the trench 1002 has a sixth sidewall 1206, and at least one of the second sidewall 1006 of the first substrate 102 or the fourth sidewall 1010 of the first dielectric layer 702 is aligned with the sixth sidewall 1206. Other structures and / or configurations of the first barrier layer 1202 are within the scope of the present invention with respect to other elements, components, etc.

[0064] Figure 13 A second dielectric layer 1302 formed above the first barrier layer 1202 and in the trench 1002 is shown according to some embodiments. In some embodiments, the second dielectric layer 1302 is in direct contact with the first barrier layer 1202. In some embodiments, the second dielectric layer 1302 is in indirect contact with the first barrier layer 1202. The first barrier layer 1202 is located between the second dielectric layer 1302 and at least one of the first substrate 102 or the first dielectric layer 702. Other structures and / or configurations of the second dielectric layer 1302 are within the scope of the present invention with respect to other elements, components, etc.

[0065] The second dielectric layer 1302 includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, fluorinated silicon glass (FSG), or other suitable materials. The second dielectric layer 1302 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. The coefficient of thermal expansion of the second dielectric layer 1302 is between about 1 and about 20 (such as between about 2.5 and about 16). Other structures and / or configurations of the second dielectric layer 1302 are within the scope of the present invention.

[0066] A first portion of the second dielectric layer 1302 is located in the trench 1002. The first portion of the second dielectric layer 1302 has a seventh sidewall 1304, and the ninth sidewall 1308 of the first portion of the first barrier layer 1202 is aligned with the seventh sidewall 1304. The first portion of the second dielectric layer 1302 in the trench 1002 has an eighth sidewall 1306, and the tenth sidewall 1310 of the first portion of the first barrier layer 1202 is aligned with the eighth sidewall 1306. Other structures and / or configurations of the second dielectric layer 1302 are within the scope of the present invention with respect to other elements, components, etc.

[0067] Figure 14Shows a first copper layer 1402 formed above a second dielectric layer 1302 and in a trench 1002 according to some embodiments. In some embodiments, the first copper layer 1402 is in direct contact with the second dielectric layer 1302. In some embodiments, the first copper layer 1402 is in indirect contact with the second dielectric layer 1302. The second dielectric layer 1302 is located between the first copper layer 1402 and the first barrier layer 1202. Other structures and / or configurations of the first copper layer 1402 are within the scope of the present invention relative to other elements, components, etc.

[0068] The first copper layer 1402 is formed by at least one of plating processes, PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. In some embodiments, the plating process is carried out with a current density of at least about 3 milliamperes per square centimeter (such as at least about 5 milliamperes per square centimeter). In some embodiments, the initial current density of the plating process is at least about 3 milliamperes per square centimeter (such as at least about 5 milliamperes per square centimeter). In some embodiments, the current density of the plating process increases to at least about 3 milliamperes per square centimeter (such as at least about 5 milliamperes per square centimeter) within a threshold duration after the start of the plating process. The threshold duration is less than or equal to at least one of about 5 milliseconds, about 10 milliseconds, about 100 milliseconds, about 1 second, or other suitable durations. Carrying out the plating process with a current density and / or initial current density of at least about 3 milliamperes per square centimeter (e.g., at least about 5 milliamperes per square centimeter) inhibits the formation of voids in the first copper layer 1402. Thus, compared to other copper layers and / or structures formed with a current density and / or initial current density less than 3 milliamperes per square centimeter (and / or less than 5 milliamperes per square centimeter), the plating process with a current density and / or initial current density of at least about 3 milliamperes per square centimeter (such as at least about 5 milliamperes per square centimeter) provides a reduction in the porosity of the first copper layer 1402. In some embodiments, a seed layer (not shown) is formed above the second dielectric layer 1302 and in the trench 1002 before carrying out the plating process. The seed layer includes at least one of copper or other suitable materials. Other processes and / or techniques for forming the first copper layer 1402 are within the scope of the present invention.

[0069] The second dielectric layer 1302 protects the first barrier layer 1202 from damage, such as during the formation of the first copper layer 1402. In some embodiments, the second dielectric layer 1302 is at least one of inhibiting damage to the first barrier layer 1202 during the plating process or preventing the plating solution used in the plating process from dissolving the first barrier layer 1202.

[0070] A first portion 1402a of the first copper layer 1402 is located in the trench 1002. The first portion 1402a of the first copper layer 1402 has an eleventh sidewall 1404, and a thirteenth sidewall 1408 of a first portion of the second dielectric layer 1302 is aligned with the eleventh sidewall 1404. The first portion 1402a of the first copper layer 1402 in the trench 1002 has a twelfth sidewall 1406, and a fourteenth sidewall 1410 of a first portion of the second dielectric layer 1302 is aligned with the twelfth sidewall 1406. Other structures and / or configurations of the first copper layer 1402 are within the scope of the present invention with respect to other elements, components, etc.

[0071] In some embodiments, a first portion of the first barrier layer 1202 in the trench 1002, a first portion of the second dielectric layer 1302 in the trench 1002, and a first portion 1402a of the first copper layer 1402 in the trench 1002 form a DTI structure 1502 (as Figure 15A shown) that extends through the first dielectric layer 702 and / or to the first substrate 102. The DTI structure 1502 is a backside DTI (BDTI) structure or a different type of DTI structure. The semiconductor device 100 includes one or more DTI structures 1502. Any number of DTI structures 1502 can be considered. The DTI structure 1502 is laterally offset from a component or is located at least in part between two components 104. In some embodiments, the DTI structure 1502 is located between two adjacent components 104, a second portion 102b of the first substrate 102 separates the DTI structure 1502 from a first component of the two adjacent components 104, and a third portion 102c of the first substrate 102 separates the DTI structure 1502 from a second component 104 of the two adjacent components 104.

[0072] Figures 15A to 15B Removal of a first portion of the semiconductor device 100 according to some embodiments is shown. In some embodiments, the first portion is removed by at least one of CMP, etching, or other suitable techniques. The first portion includes a top of the semiconductor device 100 located above the first dielectric layer 702, such as at least one of a portion of the first barrier layer 1202 located above the first dielectric layer 702, a portion of the second dielectric layer 1302 located above the first dielectric layer 702, or a portion of the first copper layer 1402 located above the first dielectric layer 702. In some embodiments, removal of the first portion of the semiconductor device 100 exposes at least one of a top surface 1504 of the first dielectric layer 702 or a top surface 1506 of the DTI structure 1502.

[0073] The width 1508 of the DTI structure 1502 is between about 600 angstroms and about 67,000 angstroms. The length 1510 of the DTI structure 1502 is between about 3,000 angstroms and about 200,000 angstroms. The length 1510 of the DTI structure 1502 is at least about 3 times (such as at least about 5 times) the width 1508 of the DTI structure 1502, such that the DTI structure has a relatively high aspect ratio. Other structures and / or configurations of the DTI structure 1502 are within the scope of the present invention.

[0074] Figure 15B An enlarged view of a portion 1502a of the semiconductor device 100 (depicted in Figure 15A ) is shown in accordance with some embodiments. The portion 1502a includes at least a portion of the DTI structure 1502. The DTI structure 1502 includes at least one of a barrier structure 1512, a dielectric structure 1514, or a copper structure 1516. The barrier structure 1512 includes a portion of the first barrier layer 1202. The dielectric structure 1514 includes a portion of the second dielectric layer 1302. The copper structure 1516 includes a portion of the first copper layer 1402. The dielectric structure 1514 is located between the barrier structure 1512 and the copper structure 1516. The barrier structure 1512 is located between the dielectric structure 1514 and the first substrate 102. The thickness 1518 of the barrier structure 1512 is at least about 0.01 times (such as at least about 0.02 times) the width 1508 of the DTI structure 1502 ( Figure 15A ). The thickness 1520 of the dielectric structure 1514 is at least about 0.005 times (such as at least about 0.01 times) the width 1508 of the DTI structure 1502 ( Figure 15A ). Other structures and / or configurations of the DTI structure 1502 are within the scope of the present invention.

[0075] Figure 15C An enlarged view of a portion 1502a of the semiconductor device 100 is shown in accordance with some embodiments in which the dielectric structure 1514 is a multi-layer structure. The dielectric structure 1514 includes any number of dielectric layers, such that an interface is defined between the layers. In some embodiments, each layer of the dielectric structure 1514 (such as at least one of layer 1514a, layer 1514b between layer 1514a and the copper structure 1516, etc.) has a coefficient of thermal expansion of about 1 to about 20 (such as between about 2.5 and 16). Each layer of the dielectric structure 1514 includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, FSG, or other suitable materials. In some embodiments, layer 1514a is different from layer 1514b. In some embodiments, layer 1514a includes a portion of the second dielectric layer 1302, and layer 1514b includes a portion of another dielectric layer formed above the second dielectric layer 1302 before forming the first copper layer 1402. Other structures and / or configurations of the DTI structure 1502 are within the scope of the present invention.

[0076] In some embodiments, the dielectric structure 1514 protects the first substrate 102 from damage caused by the expansion of the copper structure 1516, thereby improving the performance of the semiconductor device 100 and / or reducing the dark current amount in the semiconductor device 100. In some embodiments, the dielectric structure 1514 serves as a stress release layer to release the stress caused by the difference in the coefficients of thermal expansion between the first substrate 102 and the copper structure 1516.

[0077] Figure 16 A third dielectric layer 1602 formed over the first dielectric layer 702 is shown in accordance with some embodiments. The third dielectric layer 1602 is at least one of over the top surface 1506 of the DTI structure 1502, in direct contact with the top surface 1506 of the DTI structure 1502, or in indirect contact with the top surface 1506 of the DTI structure 1502. The third dielectric layer 1602 is at least one of over the top surface 1504 of the first dielectric layer 702, in direct contact with the top surface 1504 of the first dielectric layer 702, or in indirect contact with the top surface 1504 of the first dielectric layer 702. The third dielectric layer 1602 includes at least one of SiO, SiO2, SiN, Si3N4, MgO, Al2O3, Yb2O3, ZnO, Ta2O5, ZrO2, HfO2, TeO2, TiO2, or other suitable materials. The third dielectric layer 1602 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. Other structures and / or configurations of the third dielectric layer 1602 are within the scope of the present invention.

[0078] Figure 17Shows a color filter layer 1702 formed over a third dielectric layer 1602 according to some embodiments. The color filter layer 1702 is at least one of being located above the third dielectric layer 1602, in direct contact with the top surface of the third dielectric layer 1602, or in indirect contact with the top surface of the third dielectric layer 1602. The color filter layer 1702 includes at least one of a pigment-dispersed color resist (PDCR) material, a photosensitive substance, a photoinitiator substance, a multifunctional monomer, one or more additives, a leveling agent, an adhesion promoter, a resin, a polymer soluble in an alkaline solution, a color paste, a pigment, a dispersant, a solvent, or other suitable materials. The color filter layer 1702 filters certain wavelengths of radiation. In some embodiments, different portions of the color filter layer 1702 have different material compositions so as to be able to filter different wavelengths. A first portion 1702a of the color filter layer 1702 is located above a first component 104, has a first material composition, and filters a first wavelength. A second portion 1702b of the color filter layer 1702 is located above a second component 104, has a second material composition, and filters a second wavelength different from the first wavelength. A third portion 1702c of the color filter layer 1702 is located above a third component 104, has a third material composition, and filters a third wavelength different from the first wavelength and / or the second wavelength. The color filter layer 1702 is formed by at least one of PVD, sputtering, CVD, LPCVD, ALCVD, UHVCVD, RPCVD, ALD, MBE, LPE, spin coating, growth, or other suitable techniques. Other structures and / or configurations of the color filter layer 1702 are within the scope of the present invention.

[0079] Figure 18A Shows a lens array 1802 formed over the color filter layer 1702 according to some embodiments. In some embodiments, the lens array 1802 is at least one of being located above the color filter layer 1702, in direct contact with the top surface of the color filter layer 1702, or in indirect contact with the top surface of the color filter layer 1702. In some embodiments, the lens array 1802 is formed by at least one of thermal reflow, microplastic embossing, microdroplet jetting, lithography, reactive ion etching, machining, or other suitable techniques. The lenses of the lens array 1802 are at least one of microlenses or other suitable lenses. The lens array 1802 includes at least one of a first lens 1802a above a first component 104, a second lens 1802b above a second component 104, or a third lens 1802c above a third component 104. In some embodiments, one or more lenses of the lens array 1802 are located above one or more portions of the first dielectric layer 702 having tapered sidewalls, such as one or more HA structures 710. Other structures and / or configurations of the lens array 1802 are within the scope of the present invention.

[0080] In some embodiments, radiation is projected onto semiconductor device 100, such as in direction 202 or in at least one of different directions. At least some of the radiation passes through at least one of lens array 1802, color filter layer 1702, third dielectric layer 1602, first dielectric layer 702, or some of first substrate 102, and is sensed, detected, or converted into at least one of electrons by component 104. Compared to other sensors that do not implement HA structure 710, HA structure 710 provides an increase in the amount of radiation of at least one of the radiation sensed, detected, or converted by component 104. Implementing HA structure 710 reduces the reflection or deflection of radiation away from component 104 that is incident on component 104 by first substrate 102. In some embodiments, the radiation includes NIR radiation, such as radiation having a wavelength between about 700 nanometers and about 2500 nanometers. Other wavelengths of radiation directed to component 104 by HA structure 710 are within the scope of the present invention.

[0081] In some embodiments, the DTI structure 1502 prevents or mitigates at least one of crosstalk between components 104. The DTI structure 1502 prevents or mitigates at least one of radiation from propagating from one component 104 to an adjacent component 104 or away from a component 104 when there is no adjacent component 104. Radiation propagating away from the component 104 is reflected back to the component 104 by the DTI structure 1502. Generally, when the radiation is redirected back to the component 104, the component 104 detects more radiation. Implementing the DTI structure 1502 with a copper structure (such as the copper structure 1516) provides an increase in the amount of radiation reflected back to the component 104 compared to other sensors that do not implement the DTI structure 1502 with a copper structure. The increase in the amount of radiation reflected by the DTI structure 1502 is at least due to the improved reflectivity of the DTI structure 1502 with copper compared to other DTI structures that do not include copper and / or due to the reduced porosity of the DTI structure 1502 compared to other DTI structures with a higher porosity. In some embodiments, the copper structure of the DTI structure 1502 can reflect at least about 95% of the radiation (such as NIR radiation) flowing towards the DTI structure 1502. In some embodiments, the reduced porosity of the DTI structure 1502 is at least due to forming the DTI structure 1502 with copper. The reduced porosity of the DTI structure 1502 is at least due to implementing a plating process to form a first copper layer 1402 (using which the DTI structure 1502 is formed) with a current density or an initial current density of at least about 3 milliamperes per square centimeter (such as at least about 5 milliamperes per square centimeter). Implementing the DTI structure 1502 with a copper structure (such as the copper structure 1516) can reduce crosstalk between components 104 compared to other sensors that do not implement the DTI structure 1502 with a copper structure, such as reducing NIR crosstalk between components 104 (such as components 104 configured to detect NIR radiation) by about 40%.

[0082] Figure 18B A cross-sectional view of a semiconductor device 100 is shown in accordance with some embodiments in which HA structures 710 are directly adjacent to each other. In some embodiments, at least some of the HA structures between two adjacent DTI structures 1502 of a group of HA structures 710 are directly adjacent to each other, for example, in a zigzag configuration.

[0083] In some embodiments, a semiconductor device is provided. The semiconductor device includes a first deep trench isolation (DTI) structure located within a substrate. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is located between the barrier structure and the copper structure. The barrier structure is located between the substrate and the dielectric structure.

[0084] In some embodiments, the thermal expansion coefficient of the dielectric structure is between about 2.5 and about 16.

[0085] In some embodiments, the dielectric structure includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or fluorinated silicon glass.

[0086] In some embodiments, the barrier structure includes at least one of aluminum oxide, hafnium oxide, or tantalum nitride.

[0087] In some embodiments, a semiconductor device includes: a first dielectric layer located over a substrate, wherein a first sidewall of a first portion of the first dielectric layer is aligned with a first sidewall of a first sidewall of the barrier structure.

[0088] In some embodiments, a second portion of the first dielectric layer has a tapered sidewall aligned with a tapered sidewall of a first portion of the substrate.

[0089] In some embodiments, a semiconductor device includes: a photodiode located within the substrate, wherein a first DTI structure is laterally offset from the photodiode.

[0090] In some embodiments, a semiconductor device includes: a second DTI structure located within the substrate and laterally offset from the photodiode, wherein the photodiode is located between the first DTI structure and the second DTI structure.

[0091] In some embodiments, the second DTI structure includes a second barrier structure, a second dielectric structure, and a second copper structure. The second dielectric structure is located between the second barrier structure and the second copper structure, and the second barrier structure is located between the substrate and the second dielectric structure.

[0092] In some embodiments, a semiconductor device is provided. The semiconductor device includes a photodiode located within a substrate. The semiconductor device includes a first dielectric layer located over the substrate. A first portion of the first dielectric layer is located over the photodiode. The first portion of the first dielectric layer has a tapered sidewall. A first portion of the substrate separates the first portion of the first dielectric layer from the photodiode. The semiconductor device includes a first deep trench isolation (DTI) structure. The first DTI structure includes a barrier structure, a dielectric structure, and a copper structure. The dielectric structure is located between the barrier structure and the copper structure. The barrier structure is located between the substrate and the dielectric structure.

[0093] In some embodiments, the first portion of the substrate has a first tapered sidewall aligned with the tapered sidewall of the first portion of the first dielectric layer.

[0094] In some embodiments, a second portion of the first dielectric layer is located over the photodiode, the second portion of the first dielectric layer has a tapered sidewall; and the first portion of the substrate has a second tapered sidewall aligned with the tapered sidewall of the second portion of the first dielectric layer.

[0095] In some embodiments, a first tapered sidewall of a first portion of a substrate has a first slope, a second tapered sidewall of the first portion of the substrate has a second slope, and the second slope is opposite in polarity to the first slope.

[0096] In some embodiments, a first DTI structure is laterally offset from a photodiode.

[0097] In some embodiments, a second portion of the substrate separates the first DTI structure from the photodiode.

[0098] In some embodiments, a semiconductor device includes a second DTI structure that is laterally offset from a photodiode. The photodiode is located between the first DTI structure and the second DTI structure. The second DTI structure includes a second barrier structure, a second dielectric structure, and a second copper structure. The second dielectric structure is located between the second barrier structure and the second copper structure, and the second barrier structure is located between the substrate and the second dielectric structure.

[0099] In some embodiments, a semiconductor device includes a lens array, wherein a first lens of the lens array is located over a first portion of a first dielectric layer.

[0100] In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a first dielectric layer over a substrate. The method includes forming a first trench that extends through the first dielectric layer and into the substrate. The method includes forming a first barrier layer over the first dielectric layer and in the first trench. The method includes forming a second dielectric layer over the first barrier layer and in the first trench. The method includes forming a first copper layer over the second dielectric layer and in the first trench.

[0101] In some embodiments, forming the first copper layer includes performing an electroplating process with a current density of at least about 5 milliamperes per square centimeter.

[0102] In some embodiments, the method includes forming a first recess in the substrate, wherein forming the first dielectric layer includes forming a first portion of the first dielectric layer in the first recess, and the first portion of the first dielectric layer is located over a photodiode in the substrate.

[0103] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

[0104] While the subject matter has been described in language specific to structural features or method steps, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or steps described above. Rather, the specific features and steps described above are disclosed as exemplary forms for implementing at least some of the claims.

[0105] Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed as implying that these operations are necessarily order-dependent. Benefiting from this description, alternative orderings will be appreciated. In addition, it should be understood that not all operations must appear in every embodiment provided herein. Moreover, it should be understood that in some embodiments, not all operations are required.

[0106] It should be understood that in some embodiments, for purposes of simplicity and ease of understanding, the layers, components, elements, etc. depicted herein are shown as having specific dimensions relative to one another (e.g., structural dimensions or orientations), and their actual dimensions are quite different from those shown herein. In addition, there are various techniques for forming the layers, regions, components, elements, etc. mentioned herein, such as at least one of etching techniques, planarization techniques, implantation techniques, doping techniques, spin coating techniques, sputtering techniques, growth techniques, or deposition techniques such as chemical vapor deposition (CVD).

[0107] In addition, "exemplary" is used herein to mean serving as an example, instance, illustration, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, "a" and "an" as used in this application and the appended claims generally should be construed to mean "one or more" unless otherwise stated or clearly indicated from the context to be in the singular form. Moreover, at least one of A and B, etc. generally means A or B or A and B. In addition, to the extent that the terms "includes", "having", "has", "with" or variations thereof are used, such terms are intended to be inclusive in a manner similar to the term "comprising". Moreover, unless otherwise stated, "first", "second", etc. are not intended to imply a temporal aspect, a spatial aspect, an order, etc. Rather, such terms are merely used as identifiers, names, etc. for components, elements, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical or the same elements.

[0108] Moreover, although the invention has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to others of ordinary skill in the art based on a reading and understanding of this specification and the drawings. The invention includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions implemented by the components described above (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe such components are intended to correspond to any component that implements the specified function of the described component (e.g., functional equivalent), even if not structurally equivalent to the disclosed structure. Additionally, although a particular feature of the invention may have been disclosed only with respect to one of several embodiments, such a feature may be combined with one or more other features of the other embodiments, which may be desirable and advantageous for any given or particular application.

Claims

1. A semiconductor device, comprising: The first deep trench isolation (DTI) structure is located within a substrate and a first dielectric layer, wherein: The first deep trench isolation structure includes a barrier structure, a dielectric structure, and a copper structure; The dielectric structure is located between the barrier structure and the copper structure; and The barrier structure is located between the substrate and the dielectric structure, wherein the copper structure completely fills from a first sidewall of the dielectric structure to a second sidewall of the dielectric structure such that there are no voids in the copper structure.

2. The semiconductor device according to claim 1, wherein: The coefficient of thermal expansion of the dielectric structure is between 2.5 and 16.

3. The semiconductor device according to claim 1, wherein: The dielectric structure includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, or silicon fluoride glass.

4. The semiconductor device according to claim 1, wherein: The barrier structure includes at least one of aluminum oxide, hafnium oxide, or tantalum nitride.

5. The semiconductor device according to claim 1, wherein: The first dielectric layer is located on the substrate, wherein a first portion of the first dielectric layer has a first sidewall aligned with a first portion of a first sidewall of the barrier structure.

6. The semiconductor device according to claim 5, wherein: A second portion of the first dielectric layer has a tapered sidewall aligned with a tapered sidewall of a first portion of the substrate.

7. The semiconductor device according to claim 1, comprising: A photodiode is located within the substrate, wherein the first deep trench isolation structure is laterally offset from the photodiode.

8. The semiconductor device according to claim 7, comprising: A second deep trench isolation structure is located within the substrate and is laterally offset from the photodiode, wherein: The photodiode is located between the first deep trench isolation structure and the second deep trench isolation structure.

9. The semiconductor device according to claim 8, wherein: The second deep trench isolation structure includes a second barrier structure, a second dielectric structure, and a second copper structure; The second dielectric structure is located between the second barrier structure and the second copper structure; and The second barrier structure is located between the substrate and the second dielectric structure.

10. A semiconductor device, comprising: A photodiode is located within the substrate; A first dielectric layer is located on the substrate, wherein: A first portion of the first dielectric layer is located on the photodiode; The first portion of the first dielectric layer has a tapered sidewall; and A first portion of the substrate separates the first portion of the first dielectric layer from the photodiode; and A first deep trench isolation (DTI) structure, wherein: The first deep trench isolation structure includes a barrier structure, a dielectric structure, and a copper structure; An interface is defined at the contact of the barrier structure with the first dielectric layer; The dielectric structure is located between the barrier structure and the copper structure; and The barrier structure is located between the substrate and the dielectric structure, wherein the copper structure completely fills from a first sidewall of the dielectric structure to a second sidewall of the dielectric structure such that there are no voids in the copper structure.

11. The semiconductor device according to claim 10, wherein, The first portion of the substrate has a first tapered sidewall aligned with the tapered sidewall of the first portion of the first dielectric layer.

12. The semiconductor device according to claim 11, wherein: A second portion of the first dielectric layer is located on the photodiode; The second portion of the first dielectric layer has a tapered sidewall; and The first portion of the substrate has a second tapered sidewall aligned with the tapered sidewall of the second portion of the first dielectric layer.

13. The semiconductor device according to claim 12, wherein: The first tapered sidewall of the first portion of the substrate has a first slope; The second tapered sidewall of the first portion of the substrate has a second slope; and The second slope is opposite in polarity to the first slope.

14. The semiconductor device according to claim 10, wherein: The first deep trench isolation structure is laterally offset from the photodiode.

15. The semiconductor device according to claim 14, wherein: A second portion of the substrate separates the first deep trench isolation structure from the photodiode.

16. The semiconductor device according to claim 14, comprising: A second deep trench isolation structure, laterally offset from the photodiode, wherein: The photodiode is located between the first deep trench isolation structure and the second deep trench isolation structure; The second deep trench isolation structure includes a second barrier structure, a second dielectric structure, and a second copper structure; The second dielectric structure is located between the second barrier structure and the second copper structure; and The second barrier structure is located between the substrate and the second dielectric structure.

17. The semiconductor device according to claim 10, comprising: A lens array, wherein a first lens of the lens array is located above the first portion of the first dielectric layer.

18. A method for forming a semiconductor device, comprising: Form a first dielectric layer over the substrate; Form a first trench extending through the first dielectric layer and into the substrate; Form a first barrier layer over the first dielectric layer and in the first trench; Form a second dielectric layer over the first barrier layer and in the first trench; And Form a first copper layer over the second dielectric layer and in the first trench, wherein the first copper layer completely fills from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer such that there are no voids in the first copper layer.

19. The method according to claim 18, wherein: Forming the first copper layer includes performing a plating process with a current density of at least 5 milliamperes per square centimeter.

20. The method according to claim 18, comprising: Form a first groove in the substrate, wherein: Forming the first dielectric layer includes forming a first portion of the first dielectric layer in the first groove; and The first portion of the first dielectric layer is located above a photodiode within the substrate.

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