A quadruple frequency circuit

Abstract

The present application discloses a quadruple frequency circuit, comprising the following parts. A clock source, used to provide a first clock signal CK1. A duty cycle correction module, used to correct the duty cycle of the first clock signal, and output a second clock signal with an accurate duty cycle of 50%. A double frequency multiplier 1, used to generate a double frequency intermediate signal according to the second clock signal; the double frequency multiplier 1 includes a phase-locked circuit 1, used to generate a fourth clock signal with a phase shift of 90 degrees relative to the second clock signal and a seventh clock signal with a phase shift of 180 degrees relative to the second clock signal; the fourth clock signal is used to generate a double frequency intermediate signal with a duty cycle of 50%; the seventh clock signal is used to provide to the duty cycle correction module to correct the duty cycle of the second clock signal. A double frequency multiplier 2, used to generate a quadruple frequency output signal according to the double frequency intermediate signal. The quadruple frequency signal output by the present application has the characteristics of low spurious and low noise.

Description

Technical Field

[0001] The present application relates to a quadruple frequency circuit, that is, the frequency of an output signal is four times the frequency of an input signal. Background Art

[0002] PLL (phase-locked-loop) is the most commonly used clock signal source for various digital circuits and communication systems. It uses a low-noise crystal oscillator as the input reference clock and outputs a high-frequency clock that is much higher than the crystal oscillation frequency. One of the most critical technical indicators of PLL is phase noise, which directly affects the maximum operating frequency of digital circuits and the data transmission efficiency of communication systems. With the development of communication systems, data rates continue to increase, and the system's requirements for phase noise are becoming more stringent. Phase noise mainly comes from the phase noise of the reference clock, the noise of the PFD (phase frequency detector) and CP (charge pump), the noise of the divider, and the noise of the VCO (voltage-controlled oscillator). Among the many technologies for optimizing PLL phase noise, increasing the input reference clock frequency is a very effective way. First, when the VCO frequency is fixed, increasing the reference clock frequency can reduce the impact of the PFD and / or CP noise on the PLL output phase noise. Second, increasing the reference clock frequency can effectively improve the output quantization noise of the fractional PLL. Third, increasing the reference clock frequency can make the PLL bandwidth higher, thereby suppressing the impact of VCO noise on the PLL output phase noise. However, the processing cost of high-frequency crystals is expensive, and the cost of directly using high-frequency crystal oscillators as PLL reference clocks is very high.

[0003] Therefore, if Figure 1 As shown, the scheme of using a low-frequency crystal oscillator as the original input clock signal and utilizing frequency multiplication technology to generate a clock as the PLL reference clock signal becomes very attractive. Figure 1 In the figure, xtal represents a low-frequency crystal oscillator (crystal), xN represents an N-frequency multiplication circuit, and the output of the N-frequency multiplication circuit is used as the reference clock signal of the PLL circuit in the dotted box. LPF represents a low-pass filter, DSM represents a delta-sigma modulation module, and DN.a represents a decimal, with the integer part being N and the decimal part being a. This can achieve the purpose of improving the noise performance of the PLL at a low cost. The N-frequency multiplication circuit usually adopts a double-frequency and a quadruple-frequency scheme considering the noise performance and implementation advantages.

[0004] Typical N-frequency multiplication circuit based on XOR gate is as follows: Figures 2 to 5 shown. Figure 2 It is a frequency doubling circuit based on XOR gate, mainly composed of delay module and XOR gate. The delay parameter τ in the delay module is T / 4, and T represents the clock period of input signal A with a duty cycle of 50%. Figure 2 The working waveforms of each point in the circuit shown are as follows Figure 3 As shown, it can be found that the frequency of the output signal C is twice that of the input signal A. Figure 4 It is a quadruple frequency circuit based on XOR gate, mainly composed of two Figure 2 The double frequency circuit shown is cascaded, the delay parameter in the first delay module is T / 4, the delay parameter τ in the second delay module is T / 8, and T represents the clock period of the input signal A with a duty cycle of 50%. Figure 4 The working waveforms of each point in the circuit shown are as follows Figure 5 As shown, it can be found that the frequency of the output signal E is four times that of the input signal A. This frequency multiplication circuit based on the XOR gate has a simple structure, and the implementation cost and power consumption are relatively low.

[0005] However, a prominent drawback of the XOR gate-based frequency multiplication circuit is that the quality of its output signal is very sensitive to the duty cycle deviation of the input signal. Figures 6 to 9 In the figure, the ordinate dimension is voltage, and the unit is dBv; the duty cycles of the input signals are 50%, 49%, 51%, and 52% respectively. It can be found that when the input signal has a duty cycle other than 50%, the output signal of the double frequency circuit has spurious components at the frequency positions of the first and third frequencies, which seriously affects the system performance and even violates the wireless spectrum specification. Therefore, synthesizing a low-spurious double frequency clock signal strictly requires that the input clock signal has a duty cycle of 50%.

[0006] In addition, in the frequency multiplication circuit based on XOR gate, the input clock signal will introduce additional noise after passing through the delay module, which will lead to the deterioration of the phase noise of the output clock signal. Figure 3 As shown in the figure, at time t1, the rising edge of the output signal C is the rising edge of the input signal A, which is output after passing through a single-stage XOR gate, and its phase noise is almost not deteriorated. At time t2, the falling edge of the output signal C is the rising edge of the input signal A, which is output after passing through a delay module and an XOR gate, and its phase noise will be affected by the delay module. The influence of the above two factors is more obvious in the quadruple frequency circuit, so the traditional quadruple frequency circuit based on the XOR gate can hardly be used to generate the reference clock signal of the high-performance PLL. Summary of the invention

[0007] The technical problem to be solved by the present application is to provide a quadruple frequency circuit which has a relatively low cost and can be used as a reference clock signal to realize a high-performance PLL.

[0008] In order to solve the above technical problems, the present application proposes a quadruple frequency circuit, including the following parts. A clock source, used to provide a first clock signal CK1. A duty cycle correction module, used to correct the duty cycle of the first clock signal, and output a second clock signal with an accurate duty cycle of 50%. A double frequency multiplier 1, used to generate a double frequency intermediate signal according to the second clock signal; the double frequency multiplier 1 includes a phase-locked circuit 1, used to generate a fourth clock signal with a phase shift of 90 degrees relative to the second clock signal and a seventh clock signal with a phase shift of 180 degrees relative to the second clock signal; the fourth clock signal is used to generate a double frequency intermediate signal with a duty cycle of 50%; the seventh clock signal is used to provide to the duty cycle correction module to correct the duty cycle of the second clock signal. A double frequency multiplier 2, used to generate a quadruple frequency output signal according to the double frequency intermediate signal. The above circuit is embodiment 2 of the present application.

[0009] Furthermore, the quadruple frequency circuit also includes a double frequency multiplier three and a double frequency multiplier four. The double frequency multiplier two is changed to generate a ninth clock signal of quadruple frequency according to the double frequency intermediate signal. The double frequency multiplier three includes a phase-locked circuit two, which is used to generate a tenth clock signal with a phase shift of 90 degrees relative to the second clock signal according to the ninth clock signal; the double frequency multiplier three generates a double frequency eleventh clock signal according to the tenth clock signal and the second clock signal. The double frequency multiplier four is used to generate a quadruple frequency output signal according to the double frequency eleventh clock signal. The above circuit is embodiment 1 of the present application.

[0010] Furthermore, the frequency doubler 1 includes a delay module 1, a delay module 2 and an XOR gate 1; after the duty cycle correction module is started, the second clock signal is delayed by a quarter of a cycle through the delay module 2 to obtain a third clock signal; the third clock signal and the fourth clock signal are connected to a two-to-one multiplexing circuit to obtain a fifth clock signal; the second clock signal and the fifth clock signal are connected to the XOR gate 1 to obtain a double-frequency intermediate signal; the double-frequency intermediate signal is connected to the delay module 1 for a delay of one-half cycle, and the delay module 1 is also used as a phase-locked circuit 1 to lock After doubling the phase of the intermediate signal, four clock signals CK90a, CK180a, CK270a and CK360a with phases of 90 degrees, 180 degrees, 270 degrees and 360 degrees are output; the frequency of the CK360a signal is divided by 2 to become the seventh clock signal; the seventh clock signal is fed back to the duty cycle correction module to correct the duty cycle of the second clock signal to be precisely 50%; the frequency of the CK180a signal is divided by 2 to obtain a fourth clock signal with a duty cycle of 50% and a phase shift of 90 degrees relative to the second clock signal.

[0011] Furthermore, the frequency doubler 2 includes a delay module 4 and an XOR gate 2; the frequency doubled intermediate signal is connected to the delay module 4 and delayed by one eighth of a cycle to obtain an eighth clock signal; the second clock signal and the eighth clock signal are connected to the XOR gate 2 to obtain a quadruple frequency output signal. This is an exemplary description of the frequency doubler 2 in the second embodiment.

[0012] Furthermore, the frequency doubler 2 includes a delay module 4 and an XOR gate 2; the frequency doubled intermediate signal is connected to the delay module 4 and delayed by one eighth of a cycle to obtain an eighth clock signal; the second clock signal and the eighth clock signal are connected to the XOR gate 2 to obtain a ninth clock signal. This is an exemplary description of the frequency doubler 2 in the first embodiment.

[0013] Furthermore, the frequency doubler three includes the frequency doubler two, and also includes a delay module three, an XOR gate one and an XOR gate three; the ninth clock signal is connected to the delay module three for a delay of one quarter cycle, and the delay module three also acts as a phase-locked circuit two to lock the phase of the ninth clock signal, and then outputs four clock signals CK90b, CK180b, CK270b and CK360b with phases of 90 degrees, 180 degrees, 270 degrees and 360 degrees; the frequency of the CK360b signal is divided by 4 to obtain a tenth clock signal with a duty cycle of 50% and a phase shift of 90 degrees relative to the second clock signal; the second clock signal and the tenth clock signal are connected to the XOR gate three to obtain a twice-frequency eleventh clock signal.

[0014] Furthermore, the double frequency multiplier four includes a delay module five and an XOR gate four; the doubled frequency eleventh clock signal is connected to the delay module five and delayed by one eighth of a cycle to obtain a twelfth clock signal; the eleventh clock signal and the twelfth clock signal are connected to the XOR gate four to obtain a four-fold frequency output signal.

[0015] Further, the duty cycle correction module includes a charge pump, a phase frequency detector, and a capacitor 2 between the output end of the charge pump and the ground; the phase frequency detector compares the phase of the rising edge of the seventh clock signal and the falling edge of the second clock signal. If the falling edge of the second clock signal is ahead of the rising edge of the seventh clock signal, it means that the duty cycle of the second clock signal is less than 50%. The phase frequency detector and the charge pump discharge the capacitor 2 to increase the duty cycle of the second clock signal; conversely, if the falling edge of the second clock signal lags behind the rising edge of the seventh clock signal, it means that the duty cycle of the second clock signal is greater than 50%. The phase frequency detector and the charge pump charge the capacitor 2 to reduce the duty cycle of the second clock signal.

[0016] Furthermore, the phase-locked circuit one and / or the phase-locked circuit two adopts a delayed phase-locked loop, including a frequency detector, a charge pump and a voltage-controlled delay chain connected in sequence, and capacitor three is between the output end of the charge pump and the ground; the frequency detector detects the phase difference between the input clock signal and the output signal of the voltage-controlled delay chain, and according to the leading and lagging relationship of the phase difference, the charge pump sends out a current signal to charge or discharge capacitor three, thereby adjusting the delay of the voltage-controlled delay chain, and finally realizing that the output signal of the voltage-controlled delay chain is accurately delayed by one cycle relative to the input clock signal, and the voltage-controlled delay chain also has other N-1 output signals.

[0017] Furthermore, the phase-locked circuit 1 and / or the phase-locked circuit 2 adopts a phase-locked loop, including a frequency detector, a charge pump, a voltage-controlled oscillator, and a frequency divider connected in sequence, and the capacitor 5 is between the output end of the charge pump and the ground; the frequency detector detects the phase difference between the input clock signal and the signal output by the voltage-controlled oscillator, and according to the leading and lagging relationship of the phase difference, the charge pump sends out a current signal to charge or discharge the capacitor 5, thereby adjusting the oscillation frequency of the voltage-controlled oscillator, and the voltage-controlled oscillator outputs a clock signal that is divided by the frequency divider to obtain N-1 output signals.

[0018] The technical effect achieved by the present application is: providing a high-performance frequency-multiplied clock generation technology: using a phase-locked circuit to generate a clock signal with a duty cycle of 50% and twice the input frequency, and using a phase-locked circuit to generate a clock signal with a frequency four times the input frequency based on the twice-frequency signal. The low-frequency phase noise introduced in the present application is extremely low. When a crystal oscillator is used as the input clock source, the output quadruple-frequency clock has a low-frequency phase noise equivalent to that of a crystal oscillator of the same frequency. In addition, the output quadruple-frequency clock has very low spurious energy at one-time and two-time frequencies. The present application is suitable for circuit modules that require low-noise clocks, such as reference clocks for PLLs or sampling clocks for ADCs (analog-to-digital converters). BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The schematic diagram is a structural diagram of a fractional frequency PLL circuit that uses a frequency-multiplied clock as a PLL reference clock source signal.

[0020] Figure 2 It is a schematic diagram of the structure of a frequency doubling circuit based on an XOR gate.

[0021] Figure 3 yes Figure 2 Schematic diagram of the working waveform of the circuit shown.

[0022] Figure 4 It is a structural diagram of a quadruple frequency circuit based on an XOR gate.

[0023] Figure 5 yes Figure 4 Schematic diagram of the working waveform of the circuit shown.

[0024] Figure 6 yes Figure 2 The schematic diagram of the frequency spectrum of the output signal when the circuit shown uses a 100MHz, 50% duty cycle input signal.

[0025] Figure 7 yes Figure 2 The circuit shown here shows the frequency spectrum of the output signal when an input signal of 100MHz and a duty cycle of 49% is used.

[0026] Figure 8 yes Figure 2 The schematic diagram of the frequency spectrum of the output signal when the circuit shown uses a 100MHz, 51% duty cycle input signal.

[0027] Fig. 9 yes Figure 2 The schematic diagram of the frequency spectrum of the output signal when the circuit shown uses a 100MHz input signal with a duty cycle of 52%.

[0028] Fig.10 It is a structural schematic diagram of the first embodiment of the low-noise and low-spurious quadruple frequency circuit proposed in the present application.

[0029] Fig.11 It is a structural schematic diagram of the second embodiment of the low-noise and low-spurious quadruple frequency circuit proposed in the present application.

[0030] Fig.12 yes Fig.10 Schematic diagram of the working waveform of the circuit shown.

[0031] Fig.13 It is a schematic diagram of the phase noise curve of the output clock of the doubler when a common inverter chain and a delay locked loop are used as the delay module.

[0032] Fig.14 This is the principle diagram of duty cycle correction. Figure 1 , at this time the duty cycle is equal to 50%.

[0033] Fig.15 This is the principle diagram of duty cycle correction. Figure 2 , at this time the duty cycle is less than 50%.

[0034] Fig.16 This is the principle diagram of duty cycle correction. Figure 3 , at this time the duty cycle is greater than 50%.

[0035] Fig.17 is a circuit diagram of an embodiment of a duty cycle correction module.

[0036] Fig.181 is a circuit diagram of a first embodiment of a phase-locked circuit.

[0037] Fig.19 It is a circuit diagram of a second embodiment of a phase-locked circuit. DETAILED DESCRIPTION

[0038] See also Fig.10 This is the first embodiment of the low-noise and low-spurious quadruple frequency circuit proposed in the present application, which includes the following parts.

[0039] The clock source (XCLK) is used to provide a first clock signal CK1. The first clock signal CK1 is, for example, a square wave signal with a period of T and a frequency of 1 / T.

[0040] The duty cycle correction module (DCC) is used to correct the duty cycle of the first clock signal CK1, and the output second clock signal CK2 has an accurate duty cycle of 50%. The second clock signal CK2 is also a square wave signal with a period of T and a frequency of 1 / T.

[0041] The doubler (DOUBLER) 1 is used to generate a doubled frequency intermediate signal X2 according to the second clock signal CK2. The frequency of the doubled frequency intermediate signal X2 is 2 / T.

[0042] The second frequency doubler is used to generate a fourth-frequency ninth clock signal CK9 according to the second-frequency intermediate signal X2. The frequency of the fourth-frequency ninth clock signal CK9 is 4 / T.

[0043] The frequency doubler 3 is used to generate a tenth clock signal CK10 with a phase shift of 90 degrees relative to the second clock signal CK2 according to the ninth clock signal CK9, and the frequency of the tenth clock signal CK10 is 1 / T; and to generate a doubled frequency eleventh clock signal CK11 according to the tenth clock signal CK10 and the second clock signal CK2. The frequency of the doubled frequency eleventh clock signal CK11 is 2 / T.

[0044] The basic structure of the double frequency multiplier in this application is a clock signal input, one way without any delay, the other way after T / 4 delay, and finally the two ways of signal input to the XOR gate to obtain a double frequency signal. Double frequency multiplier 2 is a necessary component of the delay circuit in double frequency multiplier 3, so double frequency multiplier 3 completely includes double frequency multiplier 2.

[0045] The frequency doubler 4 is used to generate a quadruple frequency output signal X4 according to the doubled frequency eleventh clock signal CK11. The frequency of the quadruple frequency output signal X4 is 4 / T.

[0046] The main innovation of the first embodiment is that the duty cycle correction module is used to effectively reduce the spurious spectrum components of the output signal, and at the same time, a low-noise clock rising / falling edge is generated through a phase-locked loop for the input of the multiplier, thereby effectively improving the noise performance and spectrum purity of the output signal.

[0047] As an example, the double frequency multiplier 1 includes a delay module 1, a delay module 2 and an XOR gate 1 (XNOR1). In the reset stage of the duty cycle correction module, the LOCK signal is set to 0, and the duty cycle correction module is set to bypass mode. The LOCK signal is generated by the delay module 1, and the LOCK signal is used to control the "two-to-one multiplexing circuit". The bypass mode means that the duty cycle correction module does not correct the duty cycle of the first clock signal CK1, and the duty cycle of the output second clock signal CK2 is approximately equal to the duty cycle of the input first clock signal CK1. After the duty cycle correction module is started, the second clock signal CK2 passes through the delay module 2 and the XOR gate 1 to generate a double frequency intermediate signal X2. The delay module 2 delays the second clock signal CK2 by τ2 time, τ2=T / 4, to obtain the third clock signal CK3. The third clock signal CK3 and the fourth clock signal CK4 are connected to the "two-to-one multiplexing circuit" to obtain the fifth clock signal CK5. The second clock signal CK2 and the fifth clock signal CK5 are connected to the XOR gate 1 to obtain the double frequency intermediate signal X2. The twice-frequency intermediate signal X2 is connected to the delay module 1 for a delay of T / 2. The delay module 1 also serves as a phase-locked circuit 1. After the phase-locked circuit 1 locks the phase of the twice-frequency intermediate signal X2, it outputs four clock signals CK90a, CK180a, CK270a and CK360a with phases of 90 degrees, 180 degrees, 270 degrees and 360 degrees, and the frequencies are all 2 / T. At the same time, the LOCK signal becomes 1, and the frequency of the CK360a signal is divided by 2 to become the seventh clock signal CK7. The seventh clock signal CK7 is fed back to the duty cycle correction module to correct the duty cycle of the second clock signal CK2 to an accurate 50%. The frequency of the CK180a signal is divided by 2 to obtain the fourth clock signal CK4 with a frequency of 1 / T, a duty cycle of 50% and a phase shift of 90 degrees relative to the second clock signal CK2.

[0048] As an example, the frequency doubler 2 includes a delay module 4 and an XNOR gate 2 (XNOR2). The double frequency intermediate signal X2 is connected to the delay module 4, and the delay module 4 delays the double frequency intermediate signal X2 by τ4 time, τ4=T / 8, to obtain the eighth clock signal CK8. The second clock signal CK2 and the eighth clock signal CK8 are connected to the XNOR gate 2 to obtain the ninth clock signal CK9.

[0049] As an example, the double frequency multiplier 3 completely includes the double frequency multiplier 2, and also includes a delay module 3, an XOR gate 1 and an XOR gate 3 (XNOR3). The ninth clock signal CK9 is connected to the delay module 3 for a delay of T / 4. The delay module 3 also serves as the phase-locked circuit 2. After the phase-locked circuit 2 locks the phase of the ninth clock signal CK9, it outputs four clock signals CK90b, CK180b, CK270b and CK360b with phases of 90 degrees, 180 degrees, 270 degrees and 360 degrees, and the frequencies are all 4 / T. The frequency of the CK360b signal is divided by 4 to obtain the tenth clock signal CK10 with a frequency of 1 / T, a duty cycle of 50% and a phase shift of 90 degrees relative to the second clock signal CK2. The second clock signal CK2 and the tenth clock signal CK10 are connected to the XOR gate 3 to obtain the eleventh clock signal CK11 with a double frequency.

[0050] XOR gate 1 is in both frequency multiplier 1 and frequency multiplier 3. The second clock signal CK2 is passed through frequency multiplier 1, frequency multiplier 2 and delay module 3 to obtain a quadruple frequency signal CK360b, which is divided by 4 to obtain a tenth clock signal CK10 with a frequency multiplication as one of the inputs of XOR gate 3. Another input of XOR gate 3 is also a frequency multiplication signal - the second clock signal CK2. The purpose of this is to generate a T / 4 delay signal with lower phase noise, and ultimately improve the noise performance of the quadruple frequency output signal. It should be noted that the fourth clock signal CK4 is actually also a signal with an accurate T / 4 delay, but its phase noise is relatively poor, which will affect the noise performance of the output quadruple frequency signal X4. In short, one goal achieved by the three modules of frequency multiplier 2, phase-locked circuit 2 and division by four unit is to generate a T / 4 delay signal with a much better phase noise than the fourth clock signal CK4.

[0051] As an example, the double frequency multiplier 4 includes a delay module 5 and an XNOR gate 4 (XNOR4). The double frequency eleventh clock signal CK11 is connected to the delay module 5, and the delay module 5 delays the eleventh clock signal CK11 by τ5 time, τ5=T / 8, to obtain the twelfth clock signal CK12. The eleventh clock signal CK11 and the twelfth clock signal CK12 are connected to the XOR gate 4 to obtain the quadruple frequency output signal X4.

[0052] See also Fig.11 This is the second embodiment of the low-noise and low-spurious quadruple frequency circuit proposed in the present application, which includes the following parts.

[0053] The clock source (XCLK) is used to provide a first clock signal CK1. The first clock signal CK1 is, for example, a square wave signal with a period of T and a frequency of 1 / T.

[0054] The duty cycle correction module (DCC) is used to correct the duty cycle of the first clock signal CK1, and the output second clock signal CK2 has an accurate duty cycle of 50%. The second clock signal CK2 is also a square wave signal with a period of T and a frequency of 1 / T.

[0055] The frequency doubler 1 is used to generate a frequency-doubled intermediate signal X2 according to the second clock signal CK2. The frequency of the frequency-doubled intermediate signal X2 is 2 / T.

[0056] The second frequency doubler is used to generate a quadruple frequency output signal X4 according to the double frequency intermediate signal X2. The frequency of the quadruple frequency output signal X4 is 4 / T.

[0057] By comparing the above two embodiments, it can be found that the second embodiment is a simplified version of the first embodiment, omitting the double frequency multiplier three and the double frequency multiplier four in the first embodiment, which can further reduce the overall power consumption and implementation cost. In the second embodiment, since the falling edge noise of the double frequency intermediate signal X2 is greatly affected by the delay module, the quadruple frequency output signal X4 (i.e., the ninth clock signal CK9 in the first embodiment) will have half of the rising edge phase noise poor.

[0058] See also Fig.12 ,This is Fig.10 The working waveform of the first embodiment of the quadruple frequency circuit is shown. Fig.12 The starting signal edge of each arrow in the figure determines the phase noise of the ending signal edge of the arrow, that is, this figure mainly explains which signal edges the phase noise of each edge of the quadruple frequency output signal X4 is related to, and further explains that the phase noise of each signal edge at t1, t2, t3 and t4 is different. Embodiment 1 of the present application can greatly reduce the phase noise of the signal edge of the quadruple frequency output signal X4 at t2 and t4.

[0059] The principle that the embodiment 1 of the present application can achieve low spurious output is as follows: the duty cycle of the second clock signal CK2 output by the duty cycle correction module is 50%. As can be seen from the foregoing, the spurious energy of the doubled frequency intermediate signal X2 output by the double frequency multiplier 1 is extremely low at the one-fold frequency. The tenth clock signal CK10 generated by the CK360b signal output by the phase-locked circuit 2 through the division 4 unit is accurately phase-shifted by 90 degrees relative to the second clock signal CK2, and the duty cycle is 50%. Therefore, the duty cycle of the eleventh clock signal CK11 output by the double frequency multiplier 3 is 50% and the spurious energy at the one-fold frequency is extremely low. The spurious energy of the quadruple frequency output signal X4 output by the double frequency multiplier 4 with the eleventh clock signal CK11 as input is also very low at the two-fold frequency.

[0060] As mentioned above, the noise level of the delay module determines the phase noise performance of the doubled frequency clock. Therefore, the key to realizing a low-noise quadruple frequency circuit is to reduce the noise level of the delay module. This application uses a phase-locked circuit to implement some delay modules (delay module one, delay module three) mainly for two reasons: first, the phase-locked circuit can achieve precise delay, thereby achieving a 50% duty cycle clock; second, the low-frequency noise introduced by the phase-locked circuit can be reduced to a very low level, thereby outputting a low-noise doubled frequency clock. Since delay modules two, four, and five do not require precise delays, they can be implemented using an ordinary inverter chain, and of course, they can also be implemented using a phase-locked circuit. Please refer to Fig.13 This is the phase noise curve of the output clock of the doubler when using a common inverter chain and a delay phase-locked loop (i.e., phase-locked circuit) as the delay module. It can be found that the noise performance of the doubler based on the delay phase-locked loop is significantly better than that of the doubler based on the common inverter chain.

[0061] It should be pointed out that: first, usually, only the noise of the rising edge or falling edge of the clock signal in the PLL or ADC circuit will significantly affect the circuit performance. Therefore, this application only discusses the rising edge noise of the quadruple frequency clock. If the phase-locked loop pays more attention to the falling edge of the clock signal, it can be obtained through a first-level inverter. Second, the delay phase-locked loop compares the rising edge of the reference clock with the rising edge of the 360-degree phase-shifted clock in each cycle, and outputs their phase difference as a feedback signal to adjust the phase of the 360-degree phase-shifted clock, that is, the 360-degree phase-shifted clock can track the phase change of the reference signal well. Therefore, the low-frequency phase noise of the 360-degree phase-shifted clock will be suppressed by the loop, and the 360-degree phase-shifted clock has lower low-frequency phase noise than the 90-degree, 180-degree and 270-degree phase-shifted clocks. Therefore, the double frequency multiplier based on the delay phase-locked loop uses the 360-degree phase-shifted clock to generate a double frequency signal as much as possible.

[0062] See also Fig.12The principle of low noise achieved by the first embodiment of the present application is as follows: at time t1, the rising edge of the quadruple frequency output signal X4 is output by the rising edge of the second clock signal CK2 through two XOR gates (XOR gate 3 and XOR gate 4), and its phase noise is very low. At time t2, the rising edge of the quadruple frequency output signal X4 clock is output by the falling edge of the eleventh clock signal CK11 through XOR gate 4, the falling edge of the eleventh clock signal CK11 is output by the rising edge of the tenth clock signal CK10 through XOR gate 3, and the rising edge of the tenth clock signal CK10 is generated by the CK360b signal output by the phase-locked circuit 2 through the division 4 unit. As can be seen from the foregoing, the CK360b signal has very low low-frequency noise, so the low-frequency phase noise of the rising edge of the quadruple frequency output signal X4 at time t2 is also very low. At time t3, the rising edge of the quadruple frequency output signal X4 is output by the falling edge of the second clock signal CK2 through two XOR gates (XOR gate 3 and XOR gate 4), and its phase noise is very low. At time t4, the rising edge of the quadruple frequency output signal X4 is output by the falling edge of the eleventh clock signal CK11 via the XOR gate four, the falling edge of the eleventh clock signal CK11 is output by the falling edge of the tenth clock signal CK10 via the XOR gate three, and the falling edge of the tenth clock signal CK10 is generated by the CK360b signal output by the phase-locked circuit two through the division-by-4 unit. As can be seen from the foregoing, the CK360b signal has very low low-frequency noise, so the low-frequency phase noise of the rising edge of the quadruple frequency output signal X4 at time t4 is also very low.

[0063] See also Figures 14 to 16 The working principle of the duty cycle correction module is as follows. Fig.14 As shown in FIG. 1 , when the duty cycle of the second clock signal CK2 is 50%, the rising edge of the CK360a signal output by the phase-locked circuit 1 is precisely delayed by T / 2 relative to the rising edge of the twice-frequency intermediate signal X2, the falling edge of the second clock signal CK2 is aligned with the rising edge of the seventh clock signal CK7, and the feedback loop of the duty cycle correction module maintains the duty cycle of the second clock signal CK2 unchanged. Fig.15 As shown, when the duty cycle of the second clock signal CK2 is less than 50%, the rising edge of the CK360a signal output by the phase-locked circuit 1 is delayed by about T / 2 relative to the rising edge of the double frequency intermediate signal X2, the falling edge of the second clock signal CK2 is ahead of the rising edge of the seventh clock signal CK7, and the feedback loop of the duty cycle correction module increases the duty cycle of the second clock signal CK2. Fig.16 As shown, when the duty cycle of the second clock signal CK2 is greater than 50%, the rising edge of the CK360a signal output by the phase-locked circuit 1 is delayed by approximately T / 2 relative to the rising edge of the twice-frequency intermediate signal X2, the falling edge of the second clock signal CK2 phase lags behind the rising edge of the seventh clock signal CK7, and the feedback loop of the duty cycle correction module reduces the duty cycle of the second clock signal CK2.

[0064] See also Fig.17 This is an exemplary circuit structure of the duty cycle correction module, including a charge pump (CP), a phase frequency detector (PFD), a plurality of transistors M1 to M6, a plurality of capacitors C1 to C2, and a resistor R1. The rising edge of the seventh clock signal CK7 has an accurate T / 4 phase delay relative to the rising edge of the second clock signal CK2. The phase frequency detector compares the phase of the rising edge of the seventh clock signal CK7 with the falling edge of the second clock signal CK2. If the falling edge of the second clock signal CK2 is ahead in phase, it means that the duty cycle of the second clock signal CK2 is less than 50%. The phase frequency detector and the charge pump discharge the capacitor C2, so that the voltage value VB becomes smaller, thereby increasing the duty cycle of the second clock signal CK2; on the contrary, if the falling edge of the second clock signal CK2 lags behind the rising edge of the seventh clock signal CK7, it means that the duty cycle of the second clock signal CK2 is greater than 50%. The phase frequency detector and the charge pump charge the capacitor C2 to reduce the duty cycle of the second clock signal CK2. For more working principles of the duty cycle correction module, please refer to the Chinese invention patent "A circuit for accurately correcting the duty cycle of a clock signal" with authorization announcement number CN110957998B and authorization announcement date of August 11, 2020.

[0065] See also Fig.18 This is the first embodiment of the phase-locked circuit, which adopts a DLL (delay phase-locked loop). The phase-locked circuit includes a phase frequency detector (PFD), a charge pump (CP), a voltage controlled delay line (VCDL) and a capacitor C3. Fig.18 It is a typical delay chain phase-locked loop, which can generate accurate T / N delay, T is the period of the input clock signal CLKIN, and N is an integer. Its working principle is: the frequency detector detects the phase difference between the input clock signal CLKIN and the output signal CLKFB of the voltage-controlled delay chain. According to the lead and lag relationship of the phase difference, the charge pump sends out a current signal to charge or discharge the capacitor C3, and then adjusts the delay of the voltage-controlled delay chain, and finally realizes that the output signal CLKFB of the voltage-controlled delay chain is accurately delayed by one cycle relative to the input clock signal CLKIN. The other N-1 output signals CLKOUT[N-1:1] of the voltage-controlled delay chain are delayed by T / N, 2T / N, 3T / N, ..., (N-1)T / N relative to the input clock signal CLKIN.

[0066] See also Fig.19 This is the second embodiment of the phase-locked circuit, which uses a PLL (phase-locked loop). The phase-locked circuit includes a phase frequency detector (PFD), a charge pump (CP), a voltage-controlled oscillator (VCO), a divider (Divider), a plurality of capacitors C4 to C5, and a resistor R2. Fig.19It is a typical phase-locked loop circuit, which is used to generate accurate T / N delay, where T is the period of the input clock signal CLKIN and N is an integer. Its working principle is: the phase frequency detector detects the phase difference between the input clock signal CLKIN and the CLKFB1 signal output by the voltage-controlled oscillator. According to the lead and lag relationship of the phase difference, the charge pump sends out a current signal to charge or discharge the capacitor C5, thereby adjusting the oscillation frequency of the voltage-controlled oscillator. The voltage-controlled oscillator output clock signal CLKFB1 is divided by the frequency divider to obtain N-1 output signals CLKOUT[N-1:1]. When finally locked, the N-1 output signals CLKOUT[N-1:1] are delayed by T / N, 2T / N, 3T / N, ..., (N-1)T / N relative to the input clock signal CLKIN.

[0067] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should all be included in the protection scope of the present application.

Claims

1. A quadruple frequency circuit, characterized in that: It includes the following parts: A clock source, used to provide a first clock signal CK1; A duty cycle correction module, used to correct the duty cycle of the first clock signal and output a second clock signal with an accurate duty cycle of 50%; A frequency doubler 1, comprising a delay module 1, a delay module 2 and an XOR gate 1; the delay module 1 also serves as a phase-locked circuit 1; the phase-locked circuit 1 is used to generate a fourth clock signal with a phase shift of 90 degrees relative to the second clock signal and a seventh clock signal with a phase shift of 180 degrees relative to the second clock signal according to a doubled frequency intermediate signal; the delay module 2 is used to delay the second clock signal by a quarter cycle to obtain a third clock signal; the third clock signal and the fourth clock signal are connected to a two-to-one multiplexing circuit to obtain a fifth clock signal; the second clock signal and the fifth clock signal are generated into a doubled frequency intermediate signal through an XOR gate 1; the seventh clock signal is used to provide a duty cycle correction module to correct the duty cycle of the second clock signal; The frequency doubler 2 includes a delay module 3 and an XOR gate 2; the frequency doubled intermediate signal is connected to the delay module 3 to delay by one eighth of a cycle to obtain an eighth clock signal; the second clock signal and the eighth clock signal are connected to the XOR gate 2 to obtain a quadruple frequency output signal.

2. The quadruple frequency circuit according to claim 1, characterized in that: In the described double frequency multiplier 1, after the duty cycle correction module is started, the second clock signal is delayed by a quarter of a cycle through the delay module 2 to obtain the third clock signal; the third clock signal and the fourth clock signal are connected to the two-to-one multiplexing circuit to obtain the fifth clock signal; the second clock signal and the fifth clock signal are connected to the XOR gate 1 to obtain the double frequency intermediate signal; the double frequency intermediate signal is connected to the delay module 1 for a delay of half a cycle, and the delay module 1 also acts as a phase-locked circuit 1 to lock the phase of the double frequency intermediate signal, and outputs four clock signals CK90a, CK180a, CK270a and CK360a with phases of 90 degrees, 180 degrees, 270 degrees and 360 degrees; the frequency of the CK360a signal is divided by 2 to become the seventh clock signal; the seventh clock signal is fed back to the duty cycle correction module to correct the duty cycle of the second clock signal to be exactly 50%; the frequency of the CK180a signal is divided by 2 to obtain a fourth clock signal with a duty cycle of 50% and a phase shift of 90 degrees relative to the second clock signal.

3. The quadruple frequency circuit according to claim 1, characterized in that: The duty cycle correction module includes a charge pump, a phase frequency detector, and a capacitor 2 between the output end of the charge pump and the ground; the phase frequency detector compares the phase of the rising edge of the seventh clock signal and the falling edge of the second clock signal. If the falling edge of the second clock signal is ahead of the rising edge of the seventh clock signal, it means that the duty cycle of the second clock signal is less than 50%. The phase frequency detector and the charge pump discharge the capacitor 2 to increase the duty cycle of the second clock signal; conversely, if the falling edge of the second clock signal lags behind the rising edge of the seventh clock signal, it means that the duty cycle of the second clock signal is greater than 50%. The phase frequency detector and the charge pump charge the capacitor 2 to reduce the duty cycle of the second clock signal.

4. The quadruple frequency circuit according to claim 1, characterized in that: The phase-locked circuit 1 adopts a delayed phase-locked loop, including a frequency detector, a charge pump and a voltage-controlled delay chain connected in sequence, and capacitor 3 is between the output end of the charge pump and the ground; the frequency detector detects the phase difference between the input clock signal and the output signal of the voltage-controlled delay chain, and according to the leading and lagging relationship of the phase difference, the charge pump sends out a current signal to charge or discharge capacitor 3, thereby adjusting the delay of the voltage-controlled delay chain, and finally realizing that the output signal of the voltage-controlled delay chain is accurately delayed by one cycle relative to the input clock signal, and the voltage-controlled delay chain also has other N-1 output signals.

5. The quadruple frequency circuit according to claim 1, characterized in that: The phase-locked circuit 1 adopts a phase-locked loop, including a frequency detector, a charge pump, a voltage-controlled oscillator, and a frequency divider connected in sequence, and the capacitor 5 is between the output end of the charge pump and the ground; the frequency detector detects the phase difference between the input clock signal and the signal output by the voltage-controlled oscillator, and according to the leading and lagging relationship of the phase difference, the charge pump sends out a current signal to charge or discharge the capacitor 5, thereby adjusting the oscillation frequency of the voltage-controlled oscillator, and the voltage-controlled oscillator outputs a clock signal that is divided by the frequency divider to obtain N-1 output signals.

6. A frequency quadrupling circuit, characterized in that: It includes the following parts: A clock source, used to provide a first clock signal CK1; A duty cycle correction module, used to correct the duty cycle of the first clock signal and output a second clock signal with an accurate duty cycle of 50%; A frequency doubler 1, comprising a delay module 1, a delay module 2 and an XOR gate 1; the delay module 1 also serves as a phase-locked circuit 1; the phase-locked circuit 1 is used to generate a fourth clock signal with a phase shift of 90 degrees relative to the second clock signal and a seventh clock signal with a phase shift of 180 degrees relative to the second clock signal according to a doubled frequency intermediate signal; the delay module 2 is used to delay the second clock signal by a quarter cycle to obtain a third clock signal; the third clock signal and the fourth clock signal are connected to a two-to-one multiplexing circuit to obtain a fifth clock signal; the second clock signal and the fifth clock signal are generated into a doubled frequency intermediate signal through an XOR gate 1; the seventh clock signal is used to provide a duty cycle correction module to correct the duty cycle of the second clock signal; The frequency doubler 2 includes a delay module 4 and an XOR gate 2; the doubled frequency intermediate signal is connected to the delay module 4 to delay by one eighth of a cycle to obtain an eighth clock signal; the second clock signal and the eighth clock signal are connected to the XOR gate 2 to obtain a quadrupled frequency ninth clock signal; a frequency doubler 3, comprising a phase-locked circuit 2, for generating a tenth clock signal which is phase-shifted by 90 degrees relative to the second clock signal according to the ninth clock signal; generating an eleventh clock signal having a doubled frequency according to the tenth clock signal and the second clock signal; The frequency doubler four includes a delay module five and an XOR gate four; the eleventh clock signal with double frequency is connected to the delay module five to delay one eighth of a cycle to obtain the twelfth clock signal; the eleventh clock signal and the twelfth clock signal are connected to the XOR gate four to obtain a four-fold frequency output signal.

7. The quadruple frequency circuit according to claim 6, characterized in that: In the described double frequency multiplier 1, after the duty cycle correction module is started, the second clock signal is delayed by a quarter of a cycle through the delay module 2 to obtain the third clock signal; the third clock signal and the fourth clock signal are connected to the two-to-one multiplexing circuit to obtain the fifth clock signal; the second clock signal and the fifth clock signal are connected to the XOR gate 1 to obtain the double frequency intermediate signal; the double frequency intermediate signal is connected to the delay module 1 for a delay of half a cycle, and the delay module 1 also acts as a phase-locked circuit 1 to lock the phase of the double frequency intermediate signal, and outputs four clock signals CK90a, CK180a, CK270a and CK360a with phases of 90 degrees, 180 degrees, 270 degrees and 360 degrees; the frequency of the CK360a signal is divided by 2 to become the seventh clock signal; the seventh clock signal is fed back to the duty cycle correction module to correct the duty cycle of the second clock signal to be exactly 50%; the frequency of the CK180a signal is divided by 2 to obtain a fourth clock signal with a duty cycle of 50% and a phase shift of 90 degrees relative to the second clock signal.

8. The quadruple frequency circuit according to claim 6, characterized in that: The frequency doubler 2 includes a delay module 4 and an XOR gate 2; the frequency doubled intermediate signal is connected to the delay module 4 to delay by one eighth of a cycle to obtain an eighth clock signal; the second clock signal and the eighth clock signal are connected to the XOR gate 2 to obtain a ninth clock signal.

9. The quadruple frequency circuit according to claim 6, characterized in that: The frequency doubler three includes the frequency doubler two, and also includes a delay module three, an XOR gate one and an XOR gate three; the ninth clock signal is connected to the delay module three for a delay of one quarter of a cycle, and the delay module three also acts as a phase-locked circuit two to lock the phase of the ninth clock signal, and then outputs four clock signals CK90b, CK180b, CK270b and CK360b with phases of 90 degrees, 180 degrees, 270 degrees and 360 degrees; the frequency of the CK360b signal is divided by 4 to obtain a tenth clock signal with a duty cycle of 50% and a phase shift of 90 degrees relative to the second clock signal; the second clock signal and the tenth clock signal are connected to the XOR gate three to obtain a twice-frequency eleventh clock signal.

10. The quadruple frequency circuit according to claim 6, characterized in that: The duty cycle correction module includes a charge pump, a phase frequency detector, and a capacitor 2 between the output end of the charge pump and the ground; the phase frequency detector compares the phase of the rising edge of the seventh clock signal and the falling edge of the second clock signal. If the falling edge of the second clock signal is ahead of the rising edge of the seventh clock signal, it means that the duty cycle of the second clock signal is less than 50%. The phase frequency detector and the charge pump discharge the capacitor 2 to increase the duty cycle of the second clock signal; conversely, if the falling edge of the second clock signal lags behind the rising edge of the seventh clock signal, it means that the duty cycle of the second clock signal is greater than 50%. The phase frequency detector and the charge pump charge the capacitor 2 to reduce the duty cycle of the second clock signal.

11. The quadruple frequency circuit according to claim 6, characterized in that: The phase-locked circuit 1 and / or the phase-locked circuit 2 adopts a delayed phase-locked loop, including a frequency detector, a charge pump and a voltage-controlled delay chain connected in sequence, and capacitor 3 is between the output end of the charge pump and the ground; the frequency detector detects the phase difference between the input clock signal and the output signal of the voltage-controlled delay chain, and according to the leading and lagging relationship of the phase difference, the charge pump sends out a current signal to charge or discharge capacitor 3, thereby adjusting the delay of the voltage-controlled delay chain, and finally realizing that the output signal of the voltage-controlled delay chain is accurately delayed by one cycle relative to the input clock signal, and the voltage-controlled delay chain also has other N-1 output signals.

12. The quadruple frequency circuit according to claim 6, characterized in that: The phase-locked circuit 1 and / or the phase-locked circuit 2 adopts a phase-locked loop, including a phase frequency detector, a charge pump, a voltage-controlled oscillator, and a frequency divider connected in sequence, and the capacitor 5 is between the output end of the charge pump and the ground; the phase frequency detector detects the phase difference between the input clock signal and the signal output by the voltage-controlled oscillator, and according to the leading and lagging relationship of the phase difference, the charge pump sends out a current signal to charge or discharge the capacitor 5, thereby adjusting the oscillation frequency of the voltage-controlled oscillator, and the voltage-controlled oscillator outputs a clock signal that is divided by the frequency divider to obtain N-1 output signals.

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