Correlated double sampling circuit and image sensor including the same

Abstract

A flicker detection circuit is provided. The flicker detection circuit may include a flicker detection correlated double sampling (FD CDS) circuit, the FD CDS circuit including first to sixth switches and first to fourth capacitors that are turned on or off based on a control signal, the FD CDS circuit being configured to receive a flicker pixel signal output from at least one pixel, sum with an output offset signal, and amplify the sum based on a gain to form a flicker detection signal; and an analog-to-digital converter (ADC) configured to quantize the flicker detection signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2020-0028652 filed on March 6, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a correlated double sampling (CDS) circuit, and more particularly, to a CDS circuit for adjusting gain and output offset and an image sensor including the CDS circuit. Background Art

[0004] An image sensor may convert an optical signal including image information about an object into an electrical signal. The image sensor may include a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor. Recently, with the development of the computer industry and the communication industry, the demand for image sensors with enhanced performance is increasing in various electronic devices such as digital cameras, camcorders, personal communication systems (PCS), game consoles, security cameras, medical miniature cameras, and portable phones.

[0005] The correlated double sampling (CDS) circuit is an element that can be applied to the field of CMOS image sensors and can subtract the analog value that is input when there is light or when there is no light, thereby removing the common noise component. The CDS circuit can be used to improve the detection sensitivity in low-light environments. Summary of the invention

[0006] The image sensor of the exemplary embodiment can convert an optical signal including image information about an object into an electrical signal. Such an image sensor can include, for example, a charge coupled device (CCD) image sensor and / or a complementary metal oxide semiconductor (CMOS) image sensor, and can be used in various electronic devices such as digital cameras, video cameras, personal communication systems (PCS), game consoles, security cameras, medical miniature cameras, and portable phones.

[0007] Exemplary embodiment correlated double sampling (CDS) circuits may be used as elements of a CMOS image sensor and may subtract analog values, which are input in the presence or absence of light, thereby removing common noise components to increase detection sensitivity in a low illumination environment.

[0008] According to an exemplary embodiment of the present invention, a flicker detection (FD) circuit is provided, including a flicker detection correlated double sampling (FD CDS) circuit, the FD CDS circuit having first to sixth switches and first to fourth capacitors that are turned on or off based on a control signal, the FD CDS circuit being configured to receive a flicker pixel signal output from at least one pixel, sum it with an output offset signal, and amplify the sum based on a gain to form a flicker detection signal; and an analog-to-digital converter (ADC) configured to quantize the flicker detection signal.

[0009] According to an exemplary embodiment of the present invention, there is provided an image sensor, comprising: a pixel array having a plurality of pixels configured to convert an optical signal into an electrical signal; a correlated double sampling (CDS) circuit configured to perform CDS on an image pixel signal and a reset signal output from each of the pixels arranged in a first area of ​​the pixel array; and a flicker detection circuit configured to perform flicker detection based on a flicker pixel signal and a reset signal output from each of the pixels arranged in a second area of ​​the pixel array.

[0010] According to an exemplary embodiment, an image sensor includes: a pixel array having a first plurality of pixels and a second plurality of pixels, the first plurality of pixels having a first plurality of outputs for a first plurality of electronic image signals, the second plurality of pixels having at least one second output for at least one electronic flicker signal; a first correlated double sampling (CDS) circuit connected to the first plurality of outputs; a first analog-to-digital converter (ADC) connected to the first CDS circuit; and a flicker detection circuit connected to at least one second output and having a second CDS circuit and a second ADC connected to the second CDS circuit. The image sensor may include a CDS circuit responsive to a first plurality of reset signals output from the first plurality of pixels. The image sensor may include a flicker detection circuit responsive to at least one reset signal output from the second plurality of pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Exemplary embodiments of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram of an image sensor according to an embodiment;

[0013] Figure 2 is a block diagram of a pixel array according to an embodiment;

[0014] Figure 3Ais a circuit diagram showing a flicker detection (FD) correlated double sampling (CDS) (FD CDS) circuit and a FD analog-to-digital converter (FD ADC) according to an embodiment;

[0015] Figure 3B is a circuit diagram showing an FD CDS circuit and an FD ADC according to an embodiment;

[0016] Figure 4A is a timing chart showing the operation of the FD CDS circuit according to the embodiment;

[0017] Figure 4B is a conceptual diagram showing changes in an output signal of an FD CDS circuit according to an embodiment;

[0018] Figure 5A is a block diagram of a pixel array according to an embodiment;

[0019] Figure 5B is a block diagram of a pixel array according to an embodiment;

[0020] Figure 6 is a flowchart showing the operation sequence of the flicker detection system according to the embodiment; and

[0021] Figure 7 is a block diagram illustrating a computing system including an image sensor according to an embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, exemplary embodiments may be described in detail with reference to the accompanying drawings.

[0023] Figure 1 An image sensor 10 according to an embodiment is shown.

[0024] refer to Figure 1 , the image sensor 10 may include a pixel array 100, a flicker detection (FD) circuit 110, a correlated double sampling (CDS) circuit 120, an analog-to-digital converter (ADC) 130, a buffer 140, a row driver 150, a timing generator 160, a control register 170, and a ramp signal generator 180. The flicker detection (FD) circuit 110 may include a flicker detection correlated double sampling (FDCDS) circuit 190, a flicker detection analog-to-digital converter (FD ADC) 200, a fast Fourier transform (FFT) circuit 210, and a frequency analyzer 220.

[0025] The pixel array 100 may include a plurality of pixels connected to a plurality of row lines and a plurality of column lines and arranged in a matrix form. Each of the plurality of pixels may include a plurality of transistors and a photoelectric conversion element. The photoelectric conversion element may sense light to generate an image signal. For example, the photoelectric conversion element may generate electrons from the light received therefrom, and may generate an electrical signal based on the number of generated electrons. According to an exemplary embodiment, the photoelectric conversion element may include at least one of a photodiode, a photogate, and a pinned photodiode.

[0026] The timing generator 160 may generate one or more control signals for controlling the operation of each of the row driver 150 , the CDS circuit 120 , the ADC 130 , and the ramp signal generator 180 .

[0027] The control register 170 may generate one or more control signals for controlling the operation of each of the ramp signal generator 180 , the timing generator 160 , and the buffer 140 .

[0028] The row driver 150 may drive the pixel array 100 in row line units. For example, the row driver 150 may generate a selection signal for selecting one row line from among a plurality of row lines. Each of the plurality of pixels may sense incident light to output an image reset signal and an image signal to the CDS circuit 120 through a column line. When receiving the image reset signal and the image signal, the CDS circuit 120 may perform correlated double sampling on each of the image reset signal and the image signal.

[0029] The ADC 130 may compare the ramp signal output from the ramp signal generator 180 with the sampling signal output from the CDS circuit 120 to output a comparison signal. The ADC 130 may count the level transition time of the comparison signal based on the clock signal provided from the timing generator 160 to output the count value to the buffer 140. The ramp signal generator 180 may operate based on the control of the timing generator 160.

[0030] The buffer 140 may store each of the plurality of digital signals output from the ADC 130, and may sense, amplify, and output each stored digital signal. Therefore, the buffer 140 may include, for example, a memory and a sense amplifier. The memory may store a count value, and the count value may represent a count value associated with a signal output from each of the plurality of pixels. The sense amplifier may sense and amplify each count value output from the memory.

[0031] The FD CDS circuit 190 may receive a flashing pixel signal V from the pixel array 100. FLICKER , for the flashing pixel signal V received FLICKERThe stored reset signal is subtracted to generate a signal, the generated signal is amplified by a gain, and an output offset is added to the amplified signal to output an analog signal. The flashing pixel signal V FLICKER The gain may represent the signal received from each pixel in the pixel array 100 except the active pixel array. The gain may represent the flickering pixel signal V FLICKER The value of the amplified level and may be changed by adjusting the capacitance of at least one capacitor included in the FD CDS circuit 190. The output offset may be a value that allows the range of the amplified flickering pixel signal to match the input range of the FD ADC 200. The gain and output offset will be described in detail below.

[0032] The FD ADC 200 may convert the analog signal output from the FD CDS circuit 190 into a digital signal. The conversion of the analog signal into the digital signal may be substantially the same as the operation of the ADC 130 , and thus, repeated descriptions may be omitted. The FD ADC 200 may transmit the digital signal to the FFT circuit 210 .

[0033] The FFT circuit 210 may perform FFT on the output signal of the FD ADC 200. The FFT circuit 210 may convert the output time domain signal of the FD ADC 200 into a frequency domain signal to obtain the relationship between the intensity and frequency of the light. The frequency analyzer 220 may determine whether flicker is detected based on the FFT result of the FFT circuit 210. For example, flicker may be generated based on the periodic fluctuation of the intensity of the light generated by the fluorescence. For example, the frequency analyzer 220 may compare the FFT conversion value of the fluorescence with a threshold value to determine whether flicker is detected. Figure 6 and 7 The operation of detecting flicker is described in more detail.

[0034] Figure 2 A pixel array 100 according to an embodiment is shown.

[0035] refer to Figure 2 , the pixel array 100 may be divided into a first region 210 and a second region 220. The first region 210 may be referred to as an active pixel array. The first region 210 may include a plurality of pixels that output information about an image based on received light. That is, for example, a signal V generated by a pixel included in the first region 210 PIXEL Can be output along the column line to Figure 1 CDS circuit 120.

[0036] The second region 220 may represent a region other than the first region 210 in the pixel array 100. That is, the second region 220 may include a plurality of pixels disposed outside the pixel array 100. The second region 220 may be referred to as a flashing pixel array. The pixels of the second region 220 may output a flashing pixel signal V to the FD CDS circuit 190. FLICKER .

[0037] refer to Figure 2 , flashing pixel signal V FLICKER It can be the sum of the signals of the pixels included in the second area 220, without limitation. That is, the active pixel array of the first area 210 can output the pixel signal V on each column line respectively. PIXEL The scintillation pixel array of the second area 220 can output a scintillation pixel signal V obtained by combining the pixel signals of the scintillation pixels included in the second area 220 to the FD CDS circuit 190. FLICKER .

[0038] In the above embodiment, the flashing pixel signal V FLICKER It has been described as the sum of the signals of the pixels included in the second area 220, but is not limited thereto. According to an alternative embodiment, the flashing pixel signal V FLICKER It can be output in units of multiple column lines. In an alternative embodiment, the flashing pixel signal V FLICKER It may be a maximum value or a minimum value of signals of pixels included in the plurality of column lines and / or the second region 220 .

[0039] Figure 3A An FD CDS circuit 190 and an FD ADC 200 according to an embodiment are shown.

[0040] refer to Figure 3A , the FD CDS circuit 190 may include a plurality of capacitors (such as, for example, first to fourth capacitors C 1 To C 4 ), a plurality of switches (such as, for example, first to sixth switches SW 1 To SW 6 ), and amplifier 310.

[0041] A first capacitor C among the plurality of capacitors 1 and the second capacitor C 2 can be respectively connected to the input node of the amplifier 310. That is, the first capacitor C 1 A node receiving a signal output from the flashing pixel array of the second area 220 of the pixel array 100 and an input node ND 1 (such as, for example, the negative (-) input node of the amplifier 310). The second capacitor C2 The ground node GND and another input node ND can be set 2 (such as, for example, the positive (+) input node of amplifier 310).

[0042] According to an exemplary embodiment, the first switch SW 1 and the fourth switch SW 4 The first switch SW may be respectively arranged between the input node and the output node of the amplifier 310. 1 The negative input node ND of the amplifier 310 may be set 1 and the positive output node ND of the amplifier 310 3 When the first switch SW 1 When activated, the flashing pixel signal V FLICKER can be stored in the first capacitor C 1 As another example, the fourth switch SW 4 The positive input node ND of the amplifier 310 can be set 2 and the negative output node ND of the amplifier 310 4 When the fourth switch SW 4 When activated, the ground value can be stored in the second capacitor C 2 According to an exemplary embodiment, the ground node GND may be replaced with a voltage node having a specific voltage level.

[0043] The second switch SW 2 , the third switch SW 3 , the third capacitor C 3 and the fourth capacitor C 4 The output offset can be adjusted. That is, the second switch SW 2 and the third switch SW 3 Can be connected to the fifth and sixth nodes (eg, voltage nodes) ND 5 and ND 6 and can be respectively connected to the third capacitor C 3 and the fourth capacitor C 4 For example, the second switch SW 2 Can be set at the fifth node ND 5 and the negative reference voltage node V REFN When the second switch SW 2 is activated, the negative reference voltage node V REFN can be electrically connected to a third capacitor C 3 , and the charge can be based on the negative reference voltage node V REFN The level is charged into the third capacitor C 3 As another example, the third switch SW 3Can be set at the sixth node ND 6 and the positive reference voltage node V REFP When the third switch SW 3 is activated, the positive reference voltage node V REFP can be electrically connected to a fourth capacitor C 4 , and the charge can be based on the positive reference voltage node V REFP The level is charged into the fourth capacitor C 4 . Positive reference voltage node V REFP and the negative reference voltage node V REFN The difference between can correspond to the output offset value.

[0044] Fifth switch SW 5 and the sixth switch SW 6 The output node ND of the amplifier 310 can be 3 and ND 4 are electrically connected to the fifth and sixth nodes ND 5 and ND 6 For example, the fifth switch SW 5 The positive output node ND of the amplifier 310 can be set 3 and the fifth node ND 5 When the fifth switch SW 5 When activated, the positive output node ND of the amplifier 310 3 May be electrically connected to the fifth node ND 5 , and the third capacitor C 3 The fifth node ND of the amplifier 310 may be connected 5 and the negative input node ND 1 Therefore, the flashing pixel signal can pass through the first capacitor C 1 and the third capacitor C 3 transferred to the positive output node ND of the amplifier 310 3 In this case, the first capacitor C 1 and the third capacitor C 3 According to an exemplary embodiment, the third capacitor C 3 can be implemented as a variable capacitor for variably adjusting the third capacitor C 3 According to an exemplary embodiment, the third capacitor C 3 and the fourth capacitor C 4 The capacitance value of the first capacitor C may be changed, but the present invention is not limited thereto. 1 and the second capacitor C 2 The capacitance value of the first to fourth capacitors C can be adjusted independently 1 To C4 Capacitance value.

[0045] As another example, the sixth switch SW 6 The negative output node ND of the amplifier 310 may be set 4 and the sixth node ND 6 When the sixth switch SW 6 When activated, the negative output node ND of the amplifier 310 4 May be electrically connected to the sixth node ND 6 , and the fourth capacitor C 4 The sixth node ND of the amplifier 310 may be connected 6 and positive input node ND 2 Therefore, the ground value can be connected through the second capacitor C 2 and the fourth capacitor C 4 transferred to the negative output node ND of the amplifier 310 4 In this case, the second capacitor C 2 and the fourth capacitor C 4 According to an exemplary embodiment, any voltage node other than the ground node GND may be connected, and in this case, the ground value may be amplified based on the capacitance ratio of the second capacitor C 2 and the fourth capacitor C 4 The capacitance ratio amplifies any voltage node value. Like the third capacitor C 3 Similarly, the fourth capacitor C 4 It can be implemented as a variable capacitor for variably adjusting the amplification gain.

[0046] According to an exemplary embodiment, the first to fourth switches SW 1 To SW 4 and the fifth and sixth switches SW 5 and SW 6 That is, when the first to fourth switches SW 1 To SW 4 When the fifth and sixth switches SW remain activated, 5 and SW 6 As described above, the first to sixth switches SW 1 To SW 6 can be activated or deactivated alternately, so that double sampling can be performed. This will be referred to below Figure 4A-4B According to an exemplary embodiment, the first to sixth switches SW 1 To SW 6Each of the transistors may be implemented as one of an N-channel metal-oxide-semiconductor (NMOS) transistor, a P-channel metal-oxide-semiconductor (PMOS) transistor, and a complementary metal-oxide-semiconductor (CMOS) transistor.

[0047] According to an exemplary embodiment, the FD ADC 200 may have a ratio Figure 1 The ADC 200 may have a higher resolution than the ADC 130. For example, the ADC 200 may include at least a cyclic ADC, a sigma-delta ADC, and / or a successive approximation register (SAR) ADC.

[0048] refer to Figure 3B , the first switch SW 1 and the fourth switch SW 4 can be referred to as arbitrary voltage nodes and common level voltage nodes V CML That is, combined Figure 3A refer to Figure 3B , the first switch SW 1 and the fourth switch SW 4 can each be connected to a common voltage node V CML , rather than the output node of amplifier 310.

[0049] According to an exemplary embodiment, when the first switch SW 1 and the fourth switch SW 4 Each of them is connected to a common level voltage node V CML When the input node ND of the amplifier 310 is 1 and ND 2 Can be directly connected to the common level voltage node V CML .

[0050] Figure 4A The timing of the operation of the FD CDS circuit according to the embodiment is shown.

[0051] refer to Figure 4A , the period from T1 to T2 may be referred to as a sampling period, and the period starting from T3 may be referred to as a holding period.

[0052] During the period from T1 to T2, the first to fourth switches SW 1 To SW 4can be activated. In addition, during the period from T1 to T2, the fifth and sixth switches SW 5 and SW 6 Can be disabled. Figure 3A and Figure 3B During the period from T1 to T2, the FD CDS circuit 190 may receive an input signal V IN . Input signal V IN can correspond to the output signal of the flashing pixel array, such as V FLICKER The output signal of the flashing pixel array can be charged into the first capacitor C 1 Because the second switch SW 2 is activated, so the third capacitor C 3 can be electrically connected to the negative reference voltage node V REFN , and the third capacitor C 3 The negative reference voltage node V REFN Because the third switch SW 3 is activated, so the fourth capacitor C 4 Based on the positive reference voltage node V REFP Before time T2, the negative reference voltage node V REFN and the positive reference voltage node V REFP Complete the third capacitor C 3 and the fourth capacitor C 4 charging.

[0053] During the period from T2 to T3, the first to sixth switches SW 1 To SW 6 During the period from T2 to T3, the first capacitor C 1 Based on the input signal V IN are charged, and the third and fourth capacitors C 3 and C4 may correspond to a state of being charged based on a reference voltage value.

[0054] During the period T3 to T4, the first to fourth switches SW 1 To SW 4 The deactivated state may be maintained, and the fifth and sixth switches SW 5 and SW 6 can be activated. About the input signal V IN , can be formed including a first capacitor C 1 , the negative input node ND of the amplifier 310 1 , the third capacitor C 3 , the fifth switch SW 5 and the positive output node ND of the amplifier 310 3 As described above, the first capacitor C1 and the third capacitor C 3 capacitor ratio to perform amplification, but because the input signal V IN The value of is constant, so the output of the FD CDS circuit 190 can have an output offset value V OFFSET That is, the output offset value V in the period from T3 to T4 can be obtained. OFFSET To correct the output value of the FD CDS circuit 190. Output offset value V OFFSET can correspond to the negative reference voltage node V REFN and the positive reference voltage node V REFP The difference between .

[0055] At time T4, the input signal V IN The amplitude of the input signal V IN Therefore, in the holding period, the output value of the FD CDS circuit 190 may be as described in the following Equation 1.

[0056] [Equation 1]

[0057] G 1 x(V RST -V SIG )-V OFFSET

[0058] Here, G 1 may represent a gain value, such as an amplification ratio, and may correspond to the first capacitor C 1 and the third capacitor C 3 ratio, or corresponds to the second capacitor C 2 and the fourth capacitor C 4 The ratio of G 1 Can satisfy C 1 / C 3 (i.e., G 1 =C 1 / C 3 ), and / or G 1 Can be used with G 2 Same, G 2 is the second capacitor C 2 and the fourth capacitor C 4 The ratio of G 2 May satisfy C 2 / C 4 (i.e. G 2 =C 2 / C 4 ). In addition, when no light is incident on the image sensor 10, V RST Can correspond to the input signal V INWhen light is incident on the image sensor 10, V SIG Can correspond to the input signal V IN The amplitude.

[0059] refer to Figure 4B , the receivable input range of the ADC receiving the output of the amplifier 310 may correspond to the amplitude a. Considering the characteristics of the image sensor 10 that amplifies the pixel signal to perform signal processing, the pixel signal may have a monotonically increasing characteristic, in which the pixel signal continuously increases when light is applied in a state where there is no light. Therefore, in a case where the output of the FD CDS circuit 190 is greater than half of the input range of the FD ADC 200, when the output offset is not adjusted, the output value of the FD CDS circuit 190 may be used as the input of the ADC. On the other hand, according to an exemplary embodiment, when the output offset is applied to the output signal of the FD CDS circuit 190, an output signal of the FD CDS circuit 190 optimized for the input range of the FD ADC 200 may be generated. Reference Figure 4B , when the output offset value V OFFSET Without being summed and without being amplified by the magnitude of the gain, the magnitude of the output signal of the FD CDS circuit 190 may correspond to b. The output signal of the FD CDS circuit 190 may be amplified by the gain, and the magnitude of the gain may correspond to d. According to an exemplary embodiment, the gain value may correspond to the input signal V IN The ratio of the amplitude of the input signal V to the amplitude of the input range of the FD ADC 200. For example, when the input signal V IN When the amplitude b of the input signal V is 1 / 3 of the amplitude of the input range of the FD ADC 200, the gain value may correspond to 3, for example. IN The ratio of the amplitude b to the amplitude of the input range of the FD ADC 200 is changed, so that an input signal V matching the total input range of the FD ADC 200 can be generated. IN .

[0060] FD CDS circuit 190 can sum the output offset to make the amplified output signal match the input range of FD ADC 200. That is, the output offset value V OFFSET The size of V may not be based on the change of the gain value, but may be adjusted independently. According to an exemplary embodiment, the output offset value V OFFSET The amplitude may correspond to half of the amplified input signal.

[0061] Figure 5A A pixel array 100 according to an embodiment is shown.

[0062] Combination Figure 1 refer to Figure 5A, the image sensor 10 may include a plurality of FD CDS circuits 190 and a plurality of FD ADCs 200. Figure 1 and Figure 2 , a signal is output from the second region 220 of the pixel array 100 , such as from a flashing pixel array in addition to the active pixel array, but the inventive concept is not limited thereto.

[0063] According to an exemplary embodiment, the image sensor 10 may include a plurality of FD CDS circuits 190 and a plurality of FD ADCs 200, and each of the FD CDS circuits 190 and the FD ADCs 200 may correspond to a column line, respectively. FLICKER Each of the plurality of FD CDS circuits 190 and the plurality of FD ADCs 200 may perform flicker detection in parallel. The image sensor 10 may further include an FFT circuit 210 and a frequency analyzer 220 that are additionally connected to each of the plurality of FD CDS circuits 190 and the plurality of FD ADCs 200.

[0064] According to an exemplary embodiment, a flicker detection result may be determined based on flicker detection performed on each of the pixels included in the flicker pixel array. For example, as a result of flicker detection performed on 100 flicker pixels, it may be determined that flicker is detected from 60 pixels, but it may be determined that flicker is not detected from 40 pixels. Because the number of pixels where flicker is detected is greater than the number of pixels where flicker is not detected, the image sensor 10 may determine that flicker is detected. As another example, the image sensor 10 may compare a predetermined threshold with the number of pixels where flicker is determined to be detected. When it is determined that the number of pixels where flicker is detected is greater than the threshold, the image sensor 10 may determine that flicker is detected, and when it is determined that the number of pixels where flicker is detected is not greater than the threshold, the image sensor 10 may determine that flicker is not detected, without limitation.

[0065] Figure 5B A pixel array according to an embodiment is shown.

[0066] refer to Figure 5B , one output obtained by merging nodes of all pixels included in the second region 220 may be applied to the FD CDS circuit 190 .

[0067] According to an exemplary embodiment, a combined output corresponding to a sum of scintillation pixel signals output from the scintillation pixels of the second area 220 may be transmitted to the FD CDS circuit 190. The FD CDS circuit 190 may amplify the sum of the scintillation pixel signals by a gain, sum an output offset value, and transmit the summed output offset value to the FD ADC 200. The FD ADC 200 may convert an analog signal transmitted from the FD CDS 190 into a digital value. In the image sensor 10, one summed output is transmitted to the FD CDS circuit 190, and an input range of the FD ADC 200 may be greater than an input range of the FD ADC 200 included in the image sensor 10, by Figure 5A The plurality of column lines receive the flashing pixel signal.

[0068] Similar to Figure 1 As shown in , FD ADC 200 can transmit digital values ​​to FFT circuit 210 and frequency analyzer 220, thereby allowing the detection or non-detection of flicker to be determined. That is, Figure 5B The image sensor 10 may determine detection or non-detection of flicker based on the magnitude of the sum of flicker pixel signals.

[0069] According to an exemplary embodiment, an image sensor may include: a pixel array having a first subset of pixels and a second subset of pixels, the first subset of pixels having a first output subset for a first subset of electronic image signals, the second subset of pixels having at least one second output for at least one electronic flicker signal; a first correlated double sampling circuit (CDS) connected to the first output subset; a first analog-to-digital converter (ADC) connected to the first CDS circuit; and a flicker detection circuit connected to at least one second output and having a second CDS circuit and a second ADC connected to the second CDS circuit. The image sensor may include a first subset of CDS circuits responsive to a reset signal output from the first subset of pixels. The image sensor may include a flicker detection circuit responsive to at least one reset signal output from the second subset of pixels.

[0070] Figure 6 An operational sequence of a flicker detection system according to an embodiment is shown.

[0071] refer to Figure 6 In operation S110, the FD CDS circuit 190 may receive a pixel signal from each of the pixels other than the active pixel array. The FD CDS circuit 190 may receive a scintillation pixel signal from each of the pixels of the scintillation pixel array of the second area 200 in the pixel array 100. Figure 5A and Figure 5BThe scintillation pixel signal may be one signal obtained by combining the outputs of the pixels of the scintillation pixel array, or may be the output of each of the pixels of the scintillation pixel array, but is not limited thereto.

[0072] In operation S120, the FD CDS circuit 190 may adjust the amplification and output offset of the flashing pixel signal and may perform ADC conversion. The FD CDS circuit 190 may receive the flashing pixel signal and may amplify the flashing pixel signal based on the gain value. As described above, the gain value may have, for example, a value based on the first capacitor C 1 and the third capacitor C 3 The FD CDS 190 may add the output offset value to the amplified flickering pixel signal and may output the added signal to the FDADC 200. The FD ADC 200 may perform ADC conversion on the output signal to convert the analog signal into a digital signal.

[0073] In operation S130, the FFT circuit 210 may perform FFT on the pixel signal converted by the ADC. The received signal may include information about the frequency and amplitude of the output value of the scintillation pixel array relative to time, and thus, the FFT circuit 210 may perform FFT to convert the received signal into information about the amplitude of the output value of the scintillation pixel array relative to frequency.

[0074] In operation S140, the frequency analyzer 220 may determine whether the FFT conversion value corresponding to the flicker frequency is greater than a threshold value. f It can correspond to the frequency of the fluorescence cycle. When it corresponds to the flashing frequency F f When the FFT value of is greater than the threshold, the frequency analyzer 220 may determine (operation S150) that flicker is detected.

[0075] Figure 7 A computing system 700 including an image sensor 740 according to an embodiment is shown. The image sensor 740 may be similar to the image sensor 10, and thus repeated descriptions may be omitted.

[0076] refer to Figure 7 , the computing system 700 may include an image processor 710, a memory device 720, a storage device 730, an image sensor 740, an input / output (I / O) device 750, and a power supply 760. According to an embodiment, the image sensor 740 may include a pixel array such as, but not limited to, Figure 1The computing system 700 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc., or for communicating with other electronic devices.

[0077] The image processor 710 may perform certain calculations or tasks. For example, the image processor 710 may be a microprocessor or a central processing unit (CPU). The image processor 710 may communicate with the memory device 720, the storage device 730, and the I / O device 750 through an address bus, a control bus, and a data bus. For example, the image processor 710 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. When the image processor 710 receives a digital zoom command from a host or the like, the image processor 710 may output zoom information to the image sensor 740 based on the command.

[0078] The memory device 720 can store data required for the operation of the computing system 700. For example, the memory device 720 can be configured with a dynamic random access memory (DRAM), a mobile DRAM, a static random access memory (SRAM), or a non-volatile memory device. The memory chip can be installed by using various types of packages. For example, the chip can be packaged as a package, such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in a waffle package, a die in a wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), or a plastic metric quad flat package (MQFP).

[0079] The storage device 730 may include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The I / O device 750 may include an input device such as a keyboard, a keypad, a mouse device, and an output unit such as a printer and a display. The power supply 760 may provide an operating voltage required for the operation of the computing system 700.

[0080] The image sensor 740 may be connected to the image processor 710 through a bus or another communication link, and communication may be performed. The image sensor 740 and the image processor 710 may be integrated into one chip, or may be integrated into different chips, respectively. The computing system 700 may be interpreted as all computing systems using the image sensor 740. For example, the computing system 700 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, a tablet personal computer (PC), etc.

[0081] While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the relevant art that various changes in form and details may be made without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. A flicker detection circuit, comprising: a flicker detection correlated double sampling FD CDS circuit, comprising first to sixth switches and first to fourth capacitors that are turned on or off based on a control signal, the FD CDS circuit being configured to receive a flicker pixel signal output from at least one pixel, sum it with an output offset signal, and amplify the sum based on a gain to form a flicker detection signal; as well as The analog-to-digital converter ADC is configured to quantize the flicker detection signal.

2. The flicker detection circuit according to claim 1, wherein: The first capacitor and the third capacitor are configured to share a first node corresponding to one input terminal of an amplifier included in the FD CDS circuit, The second capacitor and the fourth capacitor are configured to share a second node corresponding to another input terminal of the amplifier, and The gain corresponds to a ratio of a capacitance value of the third capacitor to a capacitance value of the first capacitor or a ratio of a capacitance value of the second capacitor to a capacitance value of the fourth capacitor.

3. The flicker detection circuit according to claim 2, wherein: The first capacitor is connected between a node receiving the flashing pixel signal and the first node, The second capacitor is connected between the second node and an input voltage node of the amplifier, The input voltage node corresponds to one of a ground node and a node having an arbitrary voltage level, The third capacitor is connected between the first node and the fifth node, The fourth capacitor is connected between the second node and the sixth node, The first switch is connected between the first node and a common level voltage node, The second switch is connected between the fifth node and the first reference voltage node, The third switch is connected between the sixth node and the second reference voltage node, A fourth switch is connected between the second node and the common level voltage node, a fifth switch connected between the third node and the fifth node of the amplifier, and The sixth switch is connected between the fourth node and the sixth node of the amplifier.

4. The flicker detection circuit according to claim 3, wherein: The magnitude of the output offset corresponds to a difference between the first reference voltage node and the second reference voltage node.

5. The flicker detection circuit according to claim 4, wherein: During the sampling period, the first to fourth switches are activated, and the fifth and sixth switches are deactivated, The third capacitor is connected to the first reference voltage node based on activation of the second switch and is charged based on a first reference voltage value, and The fourth capacitor is connected to the second reference voltage node based on activation of the fourth switch, and is charged based on a second reference voltage value.

6. The flicker detection circuit according to claim 5, wherein: During the holding period, the first to fourth switches are deactivated, and the fifth and sixth switches are activated, and When the fifth switch is activated, an electrical path is formed between the first capacitor and the third capacitor, thereby amplifying a change in the flashing pixel signal based on a capacitance ratio.

7. The flicker detection circuit according to claim 1, wherein: Each of the first to sixth switches includes one of an N-channel metal oxide semiconductor (NMOS) transistor, a P-channel metal oxide semiconductor (PMOS) transistor, and a complementary metal oxide semiconductor (CMOS) transistor.

8. The flicker detection circuit according to claim 2, wherein: Each of the third capacitor and the fourth capacitor corresponds to a variable capacitor for variably adjusting a capacitance value.

9. The flicker detection circuit according to claim 1, wherein: The magnitude of the output offset is variably adjusted based on the magnitude of the amplified flickering pixel signal, and the ADC includes at least one of a pipeline ADC, a sigma-delta ADC, and a successive approximation register (SAR) ADC.

10. The flicker detection circuit according to claim 1, further comprising: A fast Fourier transform (FFT) circuit performs an FFT operation on the flicker detection signal to transform it into a frequency domain; as well as Frequency Analyzer, Wherein, the frequency analyzer is configured as: Identify the FFT value corresponding to the flicker frequency, and determining whether the flicker is detected by comparing the identified FFT value with a threshold, and The flickering frequency corresponds to the operating frequency of the fluorescent lamp.

11. An image sensor, comprising: a pixel array including a plurality of pixels configured to convert optical signals into electrical signals; a correlated double sampling (CDS) circuit configured to perform correlated double sampling on an image pixel signal and a reset signal output from each of pixels arranged in a first region of the pixel array; as well as a flicker detection circuit configured to perform flicker detection based on a flicker pixel signal output from each of the pixels arranged in the second area of ​​the pixel array and a reset signal, Wherein, the flicker detection circuit includes a sampling circuit, including first to sixth switches that are turned on or off based on a control signal, first to fourth capacitors, and an amplifier that amplifies a signal in which a flicker pixel signal is added to an output offset signal based on a gain to form a flicker detection signal.

12. The image sensor according to claim 11, wherein: The first area corresponds to the central area of ​​the pixel array, The second area corresponds to a peripheral area of ​​the pixel array except the first area.

13. The image sensor according to claim 11, in, The flicker detection circuit further includes an analog-to-digital converter ADC configured to quantize an analog signal output from the CDS circuit into a digital signal.

14. The image sensor according to claim 13, wherein: The first capacitor is connected between the node receiving the flashing pixel signal and the first node, A second capacitor is connected between the second node of the amplifier and the input voltage node, a third capacitor connected between the first node and the fifth node and sharing the first node with the first capacitor, a fourth capacitor connected between the second node and a sixth node and sharing the second node with the second capacitor, a first switch connected between the first node and a third node corresponding to an output node of the amplifier, The second switch is connected between the fifth node and the first reference voltage node, The third switch is connected between the sixth node and the second reference voltage node, a fourth switch connected between the second node and a fourth node corresponding to another output node of the amplifier, a fifth switch connected between the third node and the fifth node of the amplifier, and A sixth switch is connected between the fourth node and the sixth node of the amplifier.

15. The image sensor according to claim 14, wherein: The magnitude of the output offset corresponds to the difference between the first reference voltage node and the second reference voltage node, and The first gain corresponds to a capacitance ratio between the third capacitor and the first capacitor or between the second capacitor and the fourth capacitor.

16. The image sensor according to claim 15, wherein: During the sampling period, the first to fourth switches are activated, and the fifth and sixth switches are deactivated, The third capacitor is connected to the first reference voltage node based on activation of the second switch and is charged based on a first reference voltage value, and The fourth capacitor is connected to the second reference voltage node based on activation of the fourth switch, and is charged based on a second reference voltage value.

17. The image sensor according to claim 16, wherein: During the holding period, the first to fourth switches are deactivated, and the fifth and sixth switches are activated, and When the fifth switch is activated, an electrical path is formed between the first capacitor and the third capacitor, thereby amplifying a change in the flashing pixel signal based on a capacitance ratio.

18. The image sensor according to claim 14, wherein: Each of the first to sixth switches includes one of an N-channel metal oxide semiconductor (NMOS) transistor, a P-channel metal oxide semiconductor (PMOS) transistor, and a complementary metal oxide semiconductor (CMOS) transistor, and Each of the first to fourth capacitors corresponds to a variable capacitor for variably adjusting a capacitance value.

19. An image sensor, comprising: a pixel array having a first plurality of pixels having a first plurality of outputs for a first plurality of electronic image signals and a second plurality of pixels having at least one second output for at least one electronic scintillation signal; a first correlated double sampling (CDS) circuit connected to the first plurality of outputs; A first analog-to-digital converter ADC, connected to the first CDS circuit; as well as a flicker detection circuit connected to the at least one second output and having a second CDS circuit and a second ADC connected to the second CDS circuit, The flicker detection circuit includes an amplifier that amplifies a signal in which a flicker pixel signal is added to an output offset signal based on a gain to form a flicker detection signal.

20. The image sensor according to claim 19, wherein: the CDS circuit being responsive to a first plurality of reset signals output from the first plurality of pixels, and the flicker detection circuit being responsive to at least one reset signal output from the second plurality of pixels, The flicker detection circuit further includes a sampling circuit, including first to sixth switches and first to fourth capacitors that are turned on or off based on a control signal.

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