Printed Circuit Boards and Modules

By forming conductor patterns and conductive vias around the wiring patterns of the printed circuit board, the problems of EMI and signal loss in high-frequency band RF signal transmission are solved, and the via cracks are prevented when the substrate is bent, achieving more stable signal transmission .

CN113365414BActive Publication Date: 2025-02-18SAMSUNG ELECTRO MECHANICS CO LTD
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Patent Information

Application Number
CN202010589257.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2020-03-02
Filing Date
2020-06-24
Publication Date
2025-02-18
Estimated Expiration
2040-06-24

AI Technical Summary

Technical Problem

Existing printed circuit boards are susceptible to electromagnetic noise during RF signal transmission in high-frequency bands, resulting in electromagnetic interference (EMI) and signal loss, and are prone to via cracks when the substrate is bent.

Method used

A printed circuit board is designed which forms a conductor pattern and conductive vias around the wiring pattern to shield the EMI and is connected to the insulating body through one end of the conductive via to prevent via cracks.

Benefits of technology

It effectively reduces EMI, reduces signal loss, and prevents via cracks when the substrate is bent, improving the stability and signal transmission quality of the printed circuit board.

✦ Generated by Eureka AI based on patent content.

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Abstract

The present disclosure relates to a printed circuit board and a module. The printed circuit board includes an insulating body, a wiring pattern embedded in the insulating body, and a first conductor pattern arranged on the insulating body and overlapping at least a portion of the wiring pattern in a first direction. First conductive vias each penetrate a portion of the insulating body and are respectively arranged on opposite sides of the wiring pattern in a second direction perpendicular to the first direction to surround at least a portion of the wiring pattern. Each first conductive via has a first surface connected to the first conductor pattern and a second surface connected to the insulating body opposite to the first surface.
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Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0025825 filed on March 2, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board and a module including the printed circuit board. Background Art

[0003] The data traffic of mobile communication is growing rapidly every year. Technological development is underway to support the real-time transmission of this rapidly increasing data in wireless networks. For example, data based on the Internet of Things (IoT), augmented reality (AR), virtual reality (VR), live VR / AR combined with SNS, autonomous navigation, applications such as synchronized views (real-time video user transmission using ultra-small cameras), etc. may require wireless communications (e.g., 5G communications, mmWave communications, etc.) that support the transmission and reception of large amounts of data. Therefore, recently, millimeter wave (mmWave) communications including the 5th generation (5G) have been actively studied, and research on the commercialization and standardization of antenna modules has also been actively carried out to smoothly implement antenna modules. At the same time, radio frequency (RF) signals in high frequency bands (e.g., 28GHz, 36GHz, 39GHz, 60GHz, etc.) may be damaged by electromagnetic interference (EMI) due to electromagnetic noise between adjacent circuits during the transmission of RF signals. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board capable of EMI shielding a wiring pattern and a module including the printed circuit board.

[0005] Another aspect of the present disclosure is to provide a printed circuit board that can prevent a via hole crack even when a substrate is bent, and a module including the printed circuit board.

[0006] Another aspect of the present disclosure is to provide a printed circuit board that can reduce signal loss by suppressing generation of static electricity and a module including the printed circuit board.

[0007] An aspect of the present disclosure is to shield EMI of a wiring pattern by forming a conductor pattern and a conductive via around the wiring pattern.

[0008] Another aspect of the present disclosure is that one end of the conductive via is connected to the insulating body to be separated from the conductor pattern.

[0009] According to one aspect of the present disclosure, a printed circuit board includes: an insulating body; a wiring pattern embedded in the insulating body; a first conductor pattern disposed on the insulating body and overlapping at least a portion of the wiring pattern in a first direction. First conductive vias each penetrate a portion of the insulating body and are respectively disposed to surround at least a portion of the wiring pattern in a second direction perpendicular to the first direction. Each first conductive via has a first surface connected to the first conductor pattern and a second surface connected to the insulating body opposite to the first surface.

[0010] According to one aspect of the present disclosure, a module includes: a printed circuit board having a rigid region and a flexible region connected to the rigid region; and an electronic component mounted on the rigid region. The flexible region includes an insulating body, a wiring pattern embedded in the insulating body, a conductor pattern disposed on the insulating body, and a conductive via penetrating a portion of the insulating body, each conductive via having one surface connected to the conductor pattern and another surface connected to the insulating body. The conductor pattern and the conductive via surround at least a portion of the wiring pattern.

[0011] According to another aspect of the present disclosure, a printed circuit board includes: an insulating body; a wiring pattern embedded in the insulating body; a first conductor pattern and a third conductor pattern, respectively disposed on respective surfaces of the insulating body above and below the wiring pattern. A first conductive via extends downward from the first conductor pattern at an opposite side of the wiring pattern, and only a lower end of each first conductive via is embedded in the insulating body to be spaced apart from the wiring pattern and all the conductor patterns and the first conductive vias are spaced apart from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram schematically illustrating an example of an electronic device system;

[0014] Figure 2 is a perspective view schematically showing an example of an electronic device;

[0015] Figure 3 is a perspective view schematically showing an example before a module is bent;

[0016] Figure 4 yes Figure 3 A schematic cross-sectional view of a module;

[0017] Figure 5is a perspective view schematically showing an example after a module is bent;

[0018] Figure 6 yes Figure 5 A schematic cross-sectional view of a module;

[0019] Figure 7 It is schematically shown Figure 6 An enlarged cross-sectional view of a region G;

[0020] Figure 8 is based on Figure 7 A perspective view of an example of area G; and

[0021] Fig. 9 is based on Figure 7 A perspective view of another example of area G of FIG. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described as follows with reference to the accompanying drawings.

[0023] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0024] Reference Figure 1 , the electronic device 1000 may include a main board or motherboard 1010. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically or electrically connected thereto. These components may be connected to other components to be described below to form various signal lines 1090.

[0025] The chip-related components 1020 may include memory chips such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips such as central processing units (e.g., central processing units (CPU)), graphics processors (e.g., graphics processing units (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips such as analog-to-digital converters, application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other.

[0026] The network-related components 1030 may include components compatible with protocols such as Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution Data Only (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Enhanced Data GSM Environment (EDGE), Global System for Mobile Communications (GSM), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, 3G, 4G and 5G protocols, and any other wireless protocols and wired protocols specified after the above protocols. However, the network-related components 1030 are not limited thereto, and may also include components compatible with various other wireless or wired standards or protocols. In addition, the network-related component 1030 may be combined with the above-mentioned chip-related component 1020 together with each other.

[0027] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto, and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 or the network-related components 1030.

[0028] The electronic device 1000 includes other components that may or may not be physically or electrically connected to the main board 1010, depending on the type of the electronic device 1000. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage unit (e.g., a hard disk drive) (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), etc. However, these other components are not limited thereto, but may also include other components for various purposes according to the type of the electronic device 1000, etc.

[0029] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0030] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0031] Referring to the accompanying drawings, the electronic device may be, for example, a smart phone 1100. The mainboard 1110 is housed inside the smart phone 1100. The mainboard 1110 may include a main substrate 1111, a sub-substrate 1112, and a connecting substrate 1113 connecting the main substrate 1111 and the sub-substrate 1112. The mainboard 1110 may be a rigid-flexible printed circuit board (RFPCB). For example, the main substrate 1111 and the sub-substrate 1112 may be rigid substrates, and the connecting substrate 1113 may be a flexible substrate. An antenna module 1120 for 5G communication may be provided at various locations of the mainboard 1110. An additional substrate 1115 may be connected to the mainboard 1110, and various types of antenna modules 1120 may also be provided on the additional substrate 1115. Various electronic components may be provided on the mainboard 1110.

[0032] Figure 3 is a perspective view schematically showing an example before a module is bent.

[0033] Figure 4 yes Figure 3 Schematic cross-sectional view of a module.

[0034] Figure 5 is a perspective view schematically showing an example in which a module is bent.

[0035] Figure 6 yes Figure 5 Schematic cross-sectional view of a module.

[0036] Referring to the accompanying drawings, the module 100 according to the example includes: a printed circuit board S having rigid regions R1 and R2 and a flexible region F; a first antenna region A1, disposed on one side of the first rigid region R1 of the printed circuit board S; a second antenna region A2, disposed on one side of the second rigid region R2 of the printed circuit board S; and an electronic component region C, disposed on the other side of the second rigid region R2 of the printed circuit board S. For example, the module 100 according to the example may be an antenna module in which a configuration (A1, A2) for realizing an antenna function is disposed on a printed circuit board S having a rigid (R1)-flexible (F)-rigid (R2) type and having a configuration containing various types of electronic components. However, the present disclosure is not limited thereto, and only one of the rigid regions R1 and R2 may exist. In addition, the antenna regions A1 and A2 may be omitted, and other configurations may be further provided as needed, so that other types of modules may be used. Meanwhile, rigidity means relatively better rigidity compared to flexibility. In addition, flexibility refers to flexibility having better bending properties relative to rigidity.

[0037] The cross-sectional structure of the RFPCB applicable to the printed circuit board S is not particularly limited, and may be a known core-type RFPCB having a relatively thick core layer therein, or may be formed by a coreless process, or may be a known coreless RFPCB from which the core layer is omitted because it is formed by a coreless process. That is, the internal cross-sectional structure is not particularly limited. The printed circuit board S may include a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers in the rigid regions R1 and R2 and the flexible region F. The flexible region F may include an insulating body, a wiring pattern, a conductor pattern (e.g., a first conductor pattern, a second conductor pattern, a third conductor pattern described below), and a conductive via (e.g., a first conductive via, a second conductive via described below), etc. The flexible region F may connect a plurality of rigid regions (e.g., rigid regions R1 and R2).

[0038] Insulating material can be used as the material of the insulating layer, and in this case, the insulating material can be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide) or a material including a reinforcing material (such as glass fiber (or glass cloth, glass fabric)) and / or an inorganic filler, for example, a prepreg, an Ajinomoto Build-up Film (ABF), a photoimageable dielectric (PID), etc. can be used. However, the present disclosure is not limited to this, and a glass plate can be used as the material of a specific insulating layer, or a ceramic plate can also be used. If necessary, it may include at least one of a liquid crystal polymer (LCP), a polyimide (PI), a cycloolefin polymer (COP), a polyphenylene ether (PPE), a polyetheretherketone (PEK) and polytetrafluoroethylene (PTFE) with low dielectric loss, or a derivative thereof. When a plurality of insulating layers are used, the materials of the insulating layers may be the same or different. When a plurality of insulating layers are used, an adhesive layer may be provided between each insulating layer. The adhesive layer may include, for example, at least one of an epoxy resin, PPE and COP with low dielectric loss, or a derivative thereof.

[0039] Metal materials may be used as materials for the wiring layer, and the metal materials may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof. The wiring layer may perform various functions according to the design of the corresponding layer. For example, the wiring layer may include a ground pattern, a power pattern, a signal pattern, etc. Here, the signal pattern includes various signals other than the signals of the ground pattern, the power pattern, etc., such as an antenna signal and a data signal. These patterns may include line patterns, plane patterns and / or pad patterns.

[0040] Metal materials may also be used as materials for the via layer, and the metal materials may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys. The connection vias of the via layer may be completely filled with metal materials, or the metal material may be formed along the wall surface of the via. In addition, all known shapes such as cones, hourglasses, cylinders, etc. may be applied. The via layer may also perform various functions according to the design of the corresponding layer. For example, connection vias for signal connection, connection vias for ground connection, connection vias for power connection, etc. may be included.

[0041] The antenna areas A1 and A2 may be integrated into the rigid areas R1 and R2 to form a part of the printed circuit board S. For example, the rigid areas R1 and R2 may include a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers that respectively constitute the antenna areas A1 and A2. In this case, at least one of the plurality of wiring layers may include antenna patterns a1 and a2, respectively. The antenna patterns a1 and a2 may be patch antennas. Alternatively, it may be a combination of a patch antenna and a dipole antenna to increase signal transmission power. However, the present disclosure is not limited thereto, and the antenna areas A1 and A2 may be separate antenna components separated from the rigid areas R1 and R2. The antenna component may include a chip-type antenna, a package-type antenna, and the like. The antenna component may be provided on the printed circuit board S in a surface-mounted form by solder or the like.

[0042] The electronic component area C may include various electronic components. For example, the electronic component area C may include semiconductor chips, passive components, etc., and the semiconductor chips or passive components may be provided on the printed circuit board S in a surface mounting form by solder or the like. Optionally, the electronic component area C may include a chip package, the chip package includes a semiconductor chip and / or a passive component, and the chip package may also be provided on the printed circuit board S in a surface mounting form by solder or the like. The semiconductor chip may include a radio frequency integrated circuit (RFIC), but is not limited thereto, and may be another type of IC, such as a memory-related IC or a processor-related IC. The passive component may be a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a LTCC, an EMI filter, an MLCC, etc., but is not limited thereto.

[0043] In addition, for EMI shielding, which has become important recently, it is considered to surround a wiring pattern formed for high-frequency signal transmission with a conductor pattern and a conductive via as described below. In this case, before the module 100 is bent, there is no particular problem with the flexible region F of the printed circuit board S, but after the module 100 is bent, a via crack may occur at a contact point between the conductor pattern and the conductive via in a partially bent region G of the flexible region F. From the perspective of the electronic device, the occurrence of the via crack may increase resistance, causing heat generation, and as a result, battery consumption may increase. A structure for preventing this will be described later.

[0044] Figure 7 It is schematically shown Figure 6 An enlarged cross-sectional view of region G.

[0045] Figure 8 is based on Figure 7 A perspective view of an example of area G.

[0046] Fig. 9 is based on Figure 7 A perspective view of another example of area G of FIG.

[0047] Referring to the drawings, the printed circuit board S includes: an insulating body 110; a wiring pattern 120 embedded in the insulating body 110; a first conductor pattern 131 disposed on the insulating body 110 and extending in a plane (eg, a first direction (eg, Figure 7 The first conductive via 141 covers at least a portion of the wiring pattern 120 or overlaps at least a portion of the wiring pattern 120; and the first conductive via 141 penetrates a portion of the insulating body 110 and is arranged in a plane (e.g., a second direction perpendicular to the first direction (e.g., Figure 7 The first conductive vias 141 are provided at opposite sides of the wiring pattern 120 in a second direction perpendicular to the first direction to surround at least a portion of the wiring pattern 120. For example, the first conductive vias 141 may extend downward from the first conductor pattern 131 at opposite sides of the wiring pattern 120. Only the lower end of the first conductive via 141 may be embedded in the insulating body 110 to be spaced apart from the wiring pattern 120 and all the conductor patterns (e.g., the first conductor pattern 131, the second conductor pattern 132, and the third conductor pattern 133), and the first conductive vias may be spaced apart from each other. The wiring pattern 120 may have a linear pattern. The first conductor pattern 131 may have a planar pattern. At least a portion of the wiring pattern 120 may be surrounded by the first conductor pattern 131 and the first conductive via 141, so that it may have an EMI shielding effect. The first conductive via 141 has an upper surface connected to the first conductor pattern 131 and a lower surface connected to the insulating body 110. The first conductive via 141 may have a lower surface in contact with the insulating body 110. Therefore, the printed circuit board S may not have via cracks during bending.

[0048] The printed circuit board S may further include a second conductor pattern 132, which is embedded in the insulating body 110 and arranged side by side with the wiring pattern 120. For example, the second conductor pattern 132 is arranged on the opposite side of the wiring pattern 120 in the second direction. The second conductor pattern 132 may be a pad-shaped pattern. At least a portion of the wiring pattern 120 may be surrounded by the first conductor pattern 131, the first conductive via 141, and the second conductor pattern 132, and thus, a better EMI shielding effect may be achieved. The second conductor pattern 132 may be arranged to be separated from the first conductive via 141. For example, the central axis of each of the first conductive via 141 and the second conductor pattern 132 (e.g., the central axis extending in the first direction) may be arranged to be staggered from each other (e.g., deviated from each other in the second direction). In addition, the central axis of each of the first conductive via 141 and the second conductive via 142 described later (e.g., the central axis extending in the first direction) may also be arranged to be staggered from each other (e.g., deviated from each other in the second direction). In addition, the lower surface of the first conductive via 141 may be disposed between the side surface of the wiring pattern 120 and the side surface of the second conductor pattern 132. For example, the lower surface of the first conductive via 141 may be disposed between the side surface of the wiring pattern 120 closest to the first conductive via 141 and the side surface of the second conductor pattern 132 corresponding to the first conductive via 141. With this arrangement, the printed circuit board S can be more immune to possible via cracks when bent.

[0049] The printed circuit board S may further include a third conductor pattern 133 and a second conductive via 142, the third conductor pattern 133 being disposed on an opposite side of the insulating body 110 opposite to a side on which the first conductor pattern 131 of the insulating body 110 is disposed, and covering at least a portion of the wiring pattern 120 on a plane (e.g., a first direction) or overlapping at least a portion of the wiring pattern 120, and the second conductive via 142 penetrating another portion of the insulating body 110 and disposed to surround at least a portion of the wiring pattern 120 on a plane (e.g., a second direction). For example, the second conductive vias 142 may be disposed on opposite sides of the wiring pattern 120 in the second direction, respectively, to surround at least a portion of the wiring pattern 120. The second conductive via 142 may extend downward from the corresponding second conductor pattern 132 to the third conductor pattern 133. The second conductive via 142 may connect the corresponding second conductor pattern 132 and the third conductor pattern 133. The third conductor pattern 133 may be a planar pattern. The first conductor pattern 131, the second conductor pattern 132, and the third conductor pattern 133 and the first and second conductive vias 141 and 142 may form a shielding structure surrounding at least a portion of the wiring pattern 120. Since the shielding structure may substantially surround four directions of a signal transmission path of the wiring pattern 120, it may have a better EMI shielding effect.

[0050] The wiring pattern 120 may include a radio frequency signal pattern. The first conductor pattern 131, the second conductor pattern 132, and the third conductor pattern 133 may each include a ground pattern. The first conductive via 141 and the second conductive via 142 may each include a ground via. Because the first conductor pattern 131 is separated from the second conductor pattern 132 and the third conductor pattern 133 in the bending region G, upper and lower ground connections may be avoided. In this case, in terms of signal transmission, static electricity generation may be suppressed, and the stability of signal transmission may be improved by reducing noise.

[0051] The wiring pattern 120 and the first conductor pattern 131, the second conductor pattern 132 and the third conductor pattern 133 and the first conductive via 141 and the second conductive via 142 may include a seed layer s1 and a plating layer p, respectively. The seed layer s1 may have a very thin thickness compared to the plating layer p. The seed layer s1 may include copper (Cu) and / or titanium (Ti). The seed layer s1 may be formed by electroless plating. The plating layer p may include copper (Cu). The plating layer p may be formed by electroplating.

[0052] like Figure 8 As shown, each of the first conductive via 141 and the second conductive via 142 may have a line via shape. Fig. 9 As shown, each of the first conductive via 141 and the second conductive via 142 may have a form of a plurality of hole vias arranged adjacent to each other. As described above, the first conductive via 141 and the second conductive via 142 may have a form capable of surrounding most of the wiring pattern 120, and are not limited to the structures shown in the drawings, and may also have other possible shapes to achieve this purpose.

[0053] The insulating body 110 may include a first resin layer 111 including a thermosetting resin and a second resin layer 112 disposed on the first resin layer 111 and including a thermoplastic resin. The wiring pattern 120 may be embedded in the first resin layer 111. The first conductor pattern 131 may be disposed on the second resin layer 112. The first conductive via 141 may penetrate the second resin layer 112 and may further penetrate a portion of the first resin layer 111. By providing the multiple layers of resin layers 111 and 112, an insulating body 110 that is flexible and conducive to high-frequency signal transmission and has excellent adhesion may be provided.

[0054] The insulating body 110 may include a third resin layer 113, which is disposed on a side of the first resin layer 111 opposite to a side on which the second resin layer 112 is disposed, and the third resin layer 113 may include a thermoplastic resin. The second conductor pattern 132 may be embedded in the first resin layer 111. The third conductor pattern 133 may be disposed on the third resin layer 113. The second conductive via 142 may penetrate the third resin layer 113. In this way, the insulating body 110 that is more flexible and conducive to higher frequency signal transmission and has better adhesion can be provided.

[0055] As the thermosetting resin layer 111, for example, in terms of high-frequency signal transmission, polyphenylene ether (PPE), modified polyimide (PI), modified epoxy resin, etc. can be used. The dielectric loss factor can be adjusted according to the type of resin of the thermosetting resin layer 111, the type of filler contained in the resin, the content of the filler, etc. Here, the dielectric loss factor is the value of the dielectric loss, and the dielectric loss refers to the loss power generated when an alternating electric field is formed in the resin layer (dielectric). The dielectric loss factor is proportional to the dielectric loss, and the smaller the dielectric loss factor, the smaller the dielectric loss. The thermosetting resin layer 111 with low dielectric loss characteristics is advantageous in reducing losses in high-frequency signal transmission. The dielectric loss factor of the thermosetting resin layer 111 may be 0.003 or less, for example, 0.002 or less. In addition, the dielectric constant of the thermosetting resin layer 111 may be 3.5 or less.

[0056] As the thermoplastic resin layers 112 and 113, for example, in terms of high-frequency signal transmission, liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), polyphenylene sulfide (PPS), polyphenylene ether (PPE), polyimide (PI), etc. can be used. The dielectric loss factor (Df) can be adjusted according to the type of resin of the thermoplastic resin layers 112 and 113, the type of filler contained in the resin, the content of the filler, etc. Here, the dielectric loss factor is the value of the dielectric loss, and the dielectric loss refers to the loss power generated when an alternating electric field is formed in the resin layer (dielectric). The dielectric loss factor is proportional to the dielectric loss, and the smaller the dielectric loss factor, the smaller the dielectric loss. The thermoplastic resin layers 112 and 113 with low dielectric loss characteristics are advantageous in terms of loss reduction in high-frequency signal transmission. The dielectric loss factor of the thermoplastic resin layers 112 and 113 may be 0.003 or less, for example, 0.002 or less. In addition, the dielectric constant (Dk) of the thermoplastic resin layers 112 and 113 may be 3.5 or less.

[0057] The thickness of each of the thermoplastic resin layers 112 and 113 may be thicker than the thickness of the thermosetting resin layer 111. In terms of high-frequency signal transmission, it may be more desirable to have such a thickness relationship. The interface between the vertically adjacent thermoplastic resin layers 112 and 113 and the thermosetting resin layer 111 may include a rough surface. The rough surface refers to a surface that has been roughened and has a roughness. According to the rough surface, the vertically adjacent thermoplastic resin layers 112 and 113 and the thermosetting resin layer 111 can ensure adhesion to each other. For example, the surface of the thermoplastic resin layers 112 and 113 that contacts the thermosetting resin layer 111 may have a higher roughness than the surface of the thermoplastic resin layers 112 and 113 that does not contact the thermosetting resin layer 111.

[0058] The insulating body 110 may further include a first passivation layer 151 disposed on the second resin layer 112 and covering at least a portion of the first conductor pattern 131. In addition, the insulating body 110 may further include a second passivation layer 152 disposed on the third resin layer 113 and covering at least a portion of the third conductor pattern 133. The first passivation layer 151 and the second passivation layer 152 may be used as protective layers, respectively. The first passivation layer 151 and the second passivation layer 152 may be ABF. However, the present disclosure is not limited thereto, and the passivation layers 151 and 152 may be known photosensitive insulating layers, for example, solder resist (SR) layers.

[0059] As described above, according to the present disclosure, a printed circuit board capable of EMI shielding a wiring pattern and a module including the printed circuit board can be provided.

[0060] As another one of various effects of the present disclosure, a printed circuit board which can prevent a via hole from being broken even when a substrate is bent, and a module including the printed circuit board can be provided.

[0061] As another one of various effects of the present disclosure, a printed circuit board that can reduce signal loss by suppressing generation of static electricity and a module including the same may be provided.

[0062] Throughout the specification, it will be understood that when an element such as a layer, region, or wafer (substrate) is referred to as being "on", "connected to," or "bonded to" another element, it may be directly "on," "connected to," or "bonded to" another element, or there may be other elements between them. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly bonded to" another element, there may be no elements or layers between them. Throughout the text, the same reference numerals represent the same elements. As used herein, the term "and / or" includes any one of the relevant listed items and all combinations of any two or more items.

[0063] It will be apparent that, although the terms first, second, third, etc., may be used herein to describe various members, components, regions, layers, and / or parts, these members, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one member, component, region, layer, or part from another member, component, region, layer, or part. Therefore, without departing from the teachings of the exemplary embodiments, the first member, first component, first region, first layer, or first part discussed below may be referred to as the second member, second component, second region, second layer, or second part.

[0064] For ease of description, spatially relative terms such as "above", "above", "below", and "below" may be used herein to describe the positional relationship of one element relative to other elements in the orientation schematically shown in the drawings. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation other than the orientation depicted in the drawings. For example, if the device in the drawings is turned over, the elements described as being "above" or "above" relative to other elements or features will instead be oriented to be "below" or "below" relative to other elements or features. Therefore, depending on the particular orientation of the drawings and the device, the term "above" may cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0065] The terms used herein describe only specific embodiments, and the present disclosure is not limited thereto. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of stated features, values, steps, operations, components, elements and / or groups thereof, but do not exclude the presence or addition of one or more other features, values, steps, operations, components, elements and / or groups thereof.

[0066] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Insulation body; a wiring pattern embedded in the insulating body; a first conductor pattern disposed on the insulating body and overlapping at least a portion of the wiring pattern in a first direction; first conductive vias, each penetrating a portion of the insulating body and respectively arranged to surround at least a portion of the wiring pattern in a second direction perpendicular to the first direction; a second conductor pattern embedded in the insulating body and disposed on an opposite side of the wiring pattern in the second direction, wherein each first conductive via extends from the first conductor pattern toward the wiring pattern along the first direction and has a first surface connected to the first conductor pattern and a second surface connected to the insulating body opposite to the first surface in the first direction, wherein the first conductive via and the second conductor pattern are arranged to be separated from each other, and Wherein, relative to the first direction, the second conductor pattern is arranged at a height where the wiring pattern is arranged.

2. The printed circuit board according to claim 1, wherein: Central axes of each of the first conductive via and the second conductor pattern extending in the first direction are disposed to be offset from each other in the second direction.

3. The printed circuit board according to claim 2, wherein: The second surface of each first conductive via is disposed between a side surface of the wiring pattern closest to each first conductive via and a side surface of the second conductor pattern corresponding to each first conductive via.

4. The printed circuit board according to claim 1, further comprising: a third conductor pattern disposed on an opposite side of the insulating body to a side of the insulating body having the first conductor pattern, and overlapping at least a portion of the wiring pattern in the first direction; as well as second conductive vias, each penetrating another portion of the insulating body and respectively arranged to surround at least a portion of the wiring pattern in the second direction, Each second conductive via connects the corresponding second conductor pattern and the third conductor pattern.

5. The printed circuit board according to claim 4, wherein: Central axes of each of the first conductive via and the second conductive via extending in the first direction are disposed offset from each other in the second direction.

6. The printed circuit board according to claim 4, wherein: The first conductor pattern, the second conductor pattern, and the third conductor pattern and the first conductive via and the second conductive via form a shielding structure surrounding at least a portion of the wiring pattern, The wiring pattern includes a radio frequency signal pattern, The first conductor pattern, the second conductor pattern, and the third conductor pattern each include a ground pattern, and The first conductive via and the second conductive via each include a ground via.

7. The printed circuit board according to claim 1, wherein: The insulating body includes a first resin layer and a second resin layer, the first resin layer includes a thermosetting resin, the second resin layer is disposed on the first resin layer and includes a thermoplastic resin, The wiring pattern is embedded in the first resin layer, The first conductor pattern is provided on the second resin layer, and Each first conductive via penetrates a portion of the first resin layer and the second resin layer.

8. The printed circuit board according to claim 7, wherein: The first resin layer includes polyphenylene ether, and The second resin layer includes a liquid crystal polymer.

9. The printed circuit board according to claim 7, wherein: The insulating body also includes: a third resin layer disposed on an opposite side of the first resin layer to the side having the second resin layer thereon, and comprising a thermoplastic resin; a second conductor pattern embedded in the first resin layer; a third conductor pattern, disposed on the third resin layer; a second conductive via, penetrating the third resin layer, The first conductive via and the second conductor pattern are separated from each other, and The second conductive vias are connected to the corresponding second conductor pattern and the third conductor pattern.

10. The printed circuit board according to claim 9, wherein: The first resin layer includes polyphenylene ether, and The second resin layer and the third resin layer each include a liquid crystal polymer.

11. The printed circuit board according to claim 9, further comprising: a first passivation layer disposed on the second resin layer and covering at least a portion of the first conductor pattern; as well as The second passivation layer is disposed on the third resin layer and covers at least a portion of the third conductor pattern.

12. The printed circuit board according to claim 1, wherein: The printed circuit board has a flexible region, and The flexible region includes the insulating body, the wiring pattern, the first conductor pattern, and the first conductive via.

13. The printed circuit board according to claim 12, wherein: The printed circuit board also has a plurality of rigid regions, and The flexible region connects the plurality of rigid regions.

14. A module comprising: A printed circuit board having a rigid region and a flexible region connected to the rigid region, wherein the flexible region includes an insulating body, a wiring pattern embedded in the insulating body, a conductor pattern disposed on the insulating body, and a conductive via penetrating a portion of the insulating body, wherein each conductive via extends from the conductor pattern toward the wiring pattern along an extension direction of each conductive via and has a first surface connected to the conductor pattern and a second surface opposite to the first surface in the extension direction and connected to the insulating body, the conductor pattern and the conductive via surround at least a portion of the wiring pattern, the second surface of each conductive via is disposed at a height between a top surface and a bottom surface of the wiring pattern opposite to each other in the extension direction, and the second surface of each conductive via contacts the insulating body; and An electronic component is mounted on the rigid area.

15. The module according to claim 14, further comprising an antenna area, the antenna area being disposed on a side of the rigid area opposite to a side on which the electronic component is mounted on the rigid area, in, The electronic component includes a radio frequency integrated circuit.

16. A printed circuit board, comprising: Insulation body; a wiring pattern embedded in the insulating body; A first conductor pattern and a third conductor pattern are respectively disposed on respective surfaces of the insulating body above and below the wiring pattern; as well as a first conductive via extending downward from the first conductor pattern on an opposite side of the wiring pattern, wherein only the lower end of each first conductive via is embedded in the insulating body to be spaced apart from the wiring pattern and all the conductor patterns and the first conductive vias are spaced apart from each other, and Wherein, the printed circuit board further comprises: a second conductor pattern embedded in the insulating body on an opposite side of the wiring pattern; and The second conductive vias each extend downward from the corresponding second conductor pattern to the third conductor pattern, wherein the printed circuit board has a cross section extending through each of the second conductor pattern, the first conductive via, and the wiring pattern, wherein each of the second conductor pattern, the first conductive via, and the wiring pattern are separated from each other by a portion of the insulating body.

17. The printed circuit board according to claim 16, wherein: The printed circuit board includes a flexible region and a rigid region, the rigid region having a higher rigidity than the flexible region, and The wiring pattern, the first and third conductor patterns, and the first conductive via are disposed in the flexible region.

18. The printed circuit board according to claim 16, wherein The first conductive vias are disposed on opposite sides of the wiring pattern in a first direction, The wiring pattern extends linearly in a second direction perpendicular to the first direction, and The first conductive vias include: a first plurality of first conductive vias linearly arranged along the second direction at a first side of the wiring pattern; and a second plurality of first conductive vias linearly arranged along the second direction at a second side of the wiring pattern.

19. The printed circuit board according to claim 16, wherein: The second conductive via is arranged on the opposite side of the wiring pattern in the first direction, and the second conductive via includes: a first group of multiple second conductive vias, which are linearly arranged along a second direction perpendicular to the first direction on the first side of the wiring pattern; and a second group of multiple second conductive vias, which are linearly arranged along the second direction on the second side of the wiring pattern.

Citation Information

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