Computing system and method of operating the same

Abstract

The present application discloses an electronic device, a computing system, a host, and a method for operating the host. A computing system includes a host and a storage device. The host generates a host authentication code. The storage device receives a first request from the host among a series of first to third requests for security writing and write data, generates a device authentication code based on the write data, receives a second request and the host authentication code from the host, and performs a programming operation on the write data based on a comparison result of the host authentication code and the device authentication code.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0029238, filed on Mar. 9, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to a computing system and an operating method thereof. Background Art

[0004] The storage device may store data in response to the control of a host device such as a computer or a smart phone. The storage device may include a memory device that stores data and a memory controller that controls the memory device. Generally, there are two types of memory devices: volatile memory devices and non-volatile memory devices.

[0005] A volatile memory device may store data only when power is supplied, and may lose the stored data when power is not supplied. Examples of volatile memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Nonvolatile memory devices can retain stored data even when power supply is interrupted or blocked. Examples of nonvolatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the invention

[0007] Various embodiments of the present disclosure are directed to a computing system with improved write performance and a method of operating the computing system.

[0008] According to an embodiment, a computing system may include a host and a storage device. The host may generate a host authentication code. The storage device may receive a first request and write data from the host among a series of requests including a first request and a second request regarding security write, generate a device authentication code based on the write data, receive a second request and the host authentication code from the host, and perform a programming operation on the write data based on a comparison result of the host authentication code and the device authentication code.

[0009] According to an embodiment, a host may include a host memory and a host processor. The host memory may store write data. The host processor may provide a first request and the write data among a series of requests including at least a first request and a second request for security write to a storage device, provide the write data and generate a host authentication code in parallel, and provide the second request and the host authentication code to the storage device.

[0010] According to an embodiment, a method of operating a host to control security writing of a storage device may include: providing a first request and write data from a series of requests regarding security writing, including at least a first request and a second request, to the storage device, and generating a host authentication code in parallel; receiving a first response from the storage device indicating whether the first request has been received; and providing a second request and the host authentication code to the storage device.

[0011] According to an embodiment, a computing system may include a host and a storage device. The storage device may include a memory device including a write protection area. The host may perform the following operations in parallel: an operation of providing a first request for security write and write data to the device storage, and an operation of generating a host authentication code based on the write data and a key shared with the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a computing system according to an embodiment of the present disclosure.

[0013] Figure 2 is a diagram illustrating security writing according to an embodiment.

[0014] Figure 3 is a diagram illustrating security writing according to an embodiment.

[0015] Figure 4 is a diagram showing a method such as Figure 1 Schematic diagram of the configuration and operation of the computing system shown in .

[0016] Figure 5 It shows that Figure 4 An illustration of the data validation component shown in .

[0017] Figure 6 is a diagram illustrating another embodiment of a memory controller.

[0018] Figure 7 is a block diagram illustrating a memory card system to which a memory device according to an embodiment of the present disclosure is applied.

[0019] Figure 8 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0020] Fig. 9 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0021] Specific structural and functional descriptions are provided herein to describe only embodiments of the present invention. However, as will be appreciated by those skilled in the art from this disclosure, the present invention may be configured and / or implemented in various other ways. Therefore, the present invention is not limited to any one of the disclosed embodiments, nor to any specific details described in the present application document. Moreover, throughout the specification, references to "embodiment", "another embodiment", etc. are not necessarily directed only to one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. When the term "embodiment" is used herein, it is not necessarily directed to all embodiments.

[0022] Figure 1 is a diagram illustrating a computing system 400 according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the computing system 400 may include a storage device 50 and a host 300 .

[0024] The storage device 50 may include a memory device 100 and a memory controller 200 that controls the operation of the memory device 100. The storage device 50 may store data in response to the control of the host 300. Examples of the storage device 50 include cellular phones, smart phones, MP3 players, laptop computers, desktop computers, game consoles, televisions, tablet PCs, and in-vehicle infotainment systems.

[0025] The storage device 50 may be configured as any one of various types of storage devices according to a host interface as a communication method with the host 300. For example, the storage device 50 may be configured as a solid state drive (SSD), a multimedia card (MMC), a multimedia card in the form of eMMC, RS-MMC, and micro-MMC, a secure digital card in the form of SD, mini SD, and micro SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a high-speed PCI (PCI-e or PCIe) card type storage device, a compact flash (CF) card, a smart media card, or a memory stick.

[0026] The memory device 50 may be manufactured as any of various types of packages. For example, the memory device 50 may be manufactured as a package on package (POP), a system in package (SIP), a system on chip (SOC), a multi-chip package (MCP), a chip on board (COB), a wafer-level manufacturing package (WFP), or a wafer-level stacked package (WSP).

[0027] The memory device 100 may store data. The memory device 100 may operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data.

[0028] Each of the memory cells may be a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data.

[0029] The memory cell array may include a plurality of memory blocks, each of which may include a plurality of memory cells. Each memory block may include a plurality of pages. According to an embodiment, a page may be a unit for storing data in the memory device 100, or a unit for reading data stored in the memory device 100.

[0030] A memory block may be a unit of erasing data. According to an embodiment, the memory device 110 may be: a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphic double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM). By way of example, it is assumed that in the context of the following description, the memory device 110 is a NAND flash memory.

[0031] The memory device 100 can receive commands and addresses from the memory controller 200, and access the area selected by the address in the memory cell array. That is, the memory device 100 can perform the operation indicated by the command on the area selected by the address. For example, the memory device 100 can perform a write operation (or a programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 can program data to the area selected by the address. During the read operation, the memory device 100 can read data from the area selected by the address. During the erase operation, the memory device 100 can erase the data stored in the area selected by the address.

[0032] According to an embodiment, the memory device 100 may include a write protection area. Write data with verified integrity may be stored in the write protection area. Integrity may refer to a state in which the write data received from the host 300 is not distorted or modulated.

[0033] The memory controller 200 may control general operations of the memory device 50 .

[0034] When power is supplied to the memory device 50, the memory controller 200 may run firmware (FW). When the memory device 100 is a flash memory device, the memory controller 200 may run firmware such as a flash translation layer (FTL) to control communication between the host 300 and the memory device 100.

[0035] According to an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300 and convert the LBA into a physical block address (PBA) indicating an address of a memory cell in the memory device 100 where data is to be stored.

[0036] For example, the memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation in response to a request from the host 300. During a program operation, the memory controller 200 may provide a write command, a PBA, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0037] According to an embodiment, the memory controller 200 may generate and transmit commands, addresses, and data to the memory device 100 regardless of a request from the host 300. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0038] According to an embodiment, the memory controller 200 may control at least two memory devices 100. The memory controller 200 may control the memory devices 100 according to an interleaving scheme, thereby improving operation performance. In the interleaving scheme, operation periods of two or more memory devices 100 may at least partially overlap.

[0039] According to an embodiment, the memory controller 200 may generate a device authentication code using write data received from the host 300 and a key shared with the host 300. The memory controller 200 may verify the integrity of the write data based on a result of comparing the device authentication code with the host authentication code received from the host 300. The memory controller 200 may control the memory device 100 in response to a request from the host 300 to store the write data with verified integrity in the write protection area. The memory controller 200 may provide the result of the programming operation on the write data to the host 300 in response to a request from the host 300. The result of the programming operation may include information about whether the write data has integrity and information about whether the programming operation has passed or failed.

[0040] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as: Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM) and / or Load Reduced DIMM (LRDIMM).

[0041] Then refer to Figure 2 and Figure 3 Communication regarding security write between the host 300 and the storage device 50 is described.

[0042] Figure 2 is a diagram illustrating security writing according to an embodiment.

[0043] Reference Figure 2 In step S201, the host 300 may generate a host authentication code based on a key shared with the storage device 50 and the write data. The host 300 may generate the host authentication code by using a message authentication code (MAC) algorithm. The host authentication code may be used to verify the integrity of the write data. In other words, the host authentication code may be used to verify whether the write data is distorted or modulated during transmission of the write data from the host 300 to the storage device 50.

[0044] The host 300 may provide a series of requests, for example, first to third requests, to the storage device 50 for security writing.

[0045] In step S203, the host 300 may provide a first request to the storage device 50. The first request may be used to program write data into a write protection area of ​​the storage device 50. The host 300 may provide the first request, the write data, and a host authentication code to the storage device 50.

[0046] In step S205 , the storage device 50 may provide a first response indicating whether the first request has been received to the host 300 .

[0047] In step S207, the host 300 may provide a second request to the storage device 50 in response to the first response. The second request may be used to check whether the result of the program operation on the write data is available, ie, ready to be collected.

[0048] In step S209 , the storage device 50 may provide a second response indicating whether the second request has been received to the host 300 .

[0049] In step S211, the host 300 may provide a third request to the memory device 50 in response to the second response. The third request may be a result of a program operation for write data.

[0050] In step S213, the storage device 50 may provide a third response including a result of the program operation on the write data to the host 300 in response to the third request. The result of the program operation may include information indicating whether the program operation has passed or failed, and may also include information indicating whether the write data has integrity.

[0051] In step S215 , the storage device 50 may receive the write data, the host authentication code, and the first request together from the host 300 .

[0052] In step S217, the storage device 50 may generate a device authentication code based on the key shared with the host 300 and the received write data. The storage device 50 may generate the device authentication code by using a message authentication code (MAC) algorithm.

[0053] In step S219, the storage device 50 may verify whether the written data has integrity. According to the verification result, when it is determined that the written data has integrity, the processing flow may proceed to step S221. Alternatively, when it is determined that the written data does not have integrity, the processing flow may proceed to step S213.

[0054] In step S221, the storage device 50 may perform a programming operation to store write data in the write protection area. After performing the programming operation, the storage device 50 may generate information indicating whether the programming operation has passed or failed. After performing step S221, the process flow may proceed to step S213.

[0055] Figure 3 is a diagram illustrating security writing according to an embodiment.

[0056] Reference Figure 3 , the host 300 may provide a series of first to third requests for security writing to the storage device 50 .

[0057] In step S301, the host 300 may provide a first request to the storage device 50. The first request may be used to program write data into a write protection area of ​​the storage device 50. The host 300 may provide the first request and the write data to the storage device 50.

[0058] In step S303, the host 300 may generate a host authentication code after providing the first request to the storage device 50. The host 300 may generate the host authentication code based on the key shared with the storage device 50 and the write data. The host 300 may generate the host authentication code by using a message authentication code (MAC) algorithm. The host 300 may provide the write data to the storage device 50 in parallel with the generation of the host authentication code. In other words, the host 300 may start the generation of the host authentication code when transferring the write data to the storage device 50.

[0059] According to various embodiments, when the host 300 generates the host authentication code in step S303, the storage device 50 may generate the device authentication code in step S317. In other words, the generation of the host authentication code may be performed in parallel with the generation of the device authentication code.

[0060] In step S305 , the storage device 50 may provide a first response indicating whether the first request has been received to the host 300 .

[0061] In step S307, when the generation of the host authentication code is completed, the host 300 may provide a second request to the storage device 50 in response to the first response. The second request may be used to check whether the result of the program operation of writing data is ready to be collected. The host 300 may provide the second request and the host authentication code to the storage device 50.

[0062] In step S309 , the storage device 50 may provide a second response indicating whether the second request has been received to the host 300 .

[0063] In step S311, the host 300 may provide a third request to the memory device 50 in response to the second response. The third request may be a result of a program operation for write data.

[0064] At step S313, the memory device 50 may provide a third response including a result of the program operation on the write data to the host 300. The result of the program operation may include information indicating whether the program operation has passed or failed, and may also include information indicating whether the write data has integrity.

[0065] In step S315 , the storage device 50 may receive the write data together with the first request from the host 300 .

[0066] In step S317, the storage device 50 may generate a device authentication code based on the key shared with the host 300 and the received write data. The storage device 50 may generate the device authentication code by using a message authentication code (MAC) algorithm.

[0067] In step S319, the storage device 50 may determine whether the host authentication code has been received from the host 300. When it is determined that the host authentication code has been received, the process flow may proceed to step S321. Alternatively, when it is determined that the host authentication code has not been received, the process flow may proceed to step S325.

[0068] In step S321, the storage device 50 may verify whether the written data has integrity. According to the verification result, when it is determined that the written data has integrity, the processing flow may proceed to step S323. Alternatively, when it is determined that the written data does not have integrity, the processing flow may proceed to step S313.

[0069] In step S323, the storage device 50 may perform a programming operation to store the write data in the write protection area. After performing the programming operation, the storage device 50 may generate information indicating whether the programming operation has passed or failed. After performing step S323, the process flow may proceed to step S313.

[0070] In step S325, the storage device 50 may wait until the host authentication code is received together with the second request from the host 300. After executing step S325, the process flow may proceed to step S319.

[0071] exist Figure 3 In the embodiment shown in , generation of the host authentication code can be performed in parallel with transferring write data from the host 300 to the storage device 50. Therefore, the time required to perform a security write operation can be reduced by the time during which generation of the host authentication code overlaps with transferring write data.

[0072] According to another embodiment, generation of the host authentication code may be performed in parallel with generation of the device authentication code of the storage device 50. Therefore, the time required to perform the security write operation may be reduced by the time during which generation of the host authentication code overlaps with generation of the device authentication code.

[0073] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 1 4 is a diagram of the configuration and operation of a computing system 400 shown in FIG.

[0074] Reference Figure 4 , the computing system 400 may include a storage device 50 and a host 300 .

[0075] According to an embodiment, the memory device 100 may include a write protection area 110 .

[0076] The write protection area 110 may be an area storing write data W_DATA having verified integrity. The integrity may refer to a state in which the write data W_DATA received from the host 300 is not distorted or modulated.

[0077] The memory device 100 may perform a program operation of storing write data W_DATA having verified integrity in the write protection area 110 in response to a program command received from the memory controller 200. In response to a status read command received from the memory controller 200, the memory device 100 may provide a status read response STA_RES to the memory controller 200, the status read response STA_RES including information indicating whether the program operation has passed or failed.

[0078] According to an embodiment, the memory controller 200 may include an authenticating write controller 210 and a data verification component 220 .

[0079] The authentication write controller 210 may provide a response RES to a series of requests REQ regarding security write received from the host 300 to the host 300. The series of requests REQ regarding security write may include reference Figure 2 and Figure 3 Described first request to third request.

[0080] For example, the authentication write controller 210 may receive a first request and write data W_DATA from the host 300. The authentication write controller 210 may provide a first response indicating whether the first request has been received to the host 300 in response to the first request received from the host 300. The first request may be used to program the write data W_DATA into the write protection area 110 of the memory device 100.

[0081] The authentication write controller 210 may receive the second request and the host authentication code HA_CODE from the host 300. The authentication write controller 210 may provide a second response indicating whether the second request has been received to the host 300 in response to the second request received from the host 300. The second request may be used to check whether the result of the program operation on the write data W_DATA is ready to be collected.

[0082] Authentication write controller 210 may receive a third request from host 300 to request a result of the program operation on write data W_DATA. Authentication write controller 210 may provide a third response including a result of the program operation on write data to host 300 in response to the third request received from host 300.

[0083] The authenticated write controller 210 may control the memory device 100 to store the write data W_DATA in the write protection area 110. For example, the authenticated write controller 210 may determine whether the write data W_DATA has integrity based on the authentication information AUT_INF received from the data verification component 220. The authenticated write controller 210 may provide a program command with respect to the write data W_DATA having verified integrity to the memory device 100.

[0084] After providing the program command to the memory device 100, the authentication write controller 210 may provide a status read command to the memory device 100 to receive the result of the program operation. The authentication write controller 210 may receive a status read response STA_RES indicating the result of the program operation from the memory device 100. The status read response STA_RES may include information indicating whether the program operation has passed or failed.

[0085] Authentication write controller 210 may provide a response including a result of the program operation storing write data W_DATA in write protection area 110 to host 300. The result of the program operation may include information on whether write data W_DATA has integrity and information on whether the program operation has passed or failed.

[0086] The data verification component 220 may generate authentication information AUT_INF indicating integrity of the write data W_DATA received from the host 300. The data verification component 220 may provide the authentication information AUT_INF to the authentication write controller 210.

[0087] More specifically, the data verification component 220 may generate a device authentication code by using the write data W_DATA received from the host 300 and a key shared with the host 300. The data verification component 220 may generate authentication information AUT_INF indicating the integrity of the write data W_DATA based on a result of comparing the host authentication code HA_CODE received from the host 300 with the device authentication code. When the authentication write controller 210 receives the second request from the host 300, the host authentication code HA_CODE may be received.

[0088] According to an embodiment, the host 300 may include a host processor 310 and a host memory 320 .

[0089] The host processor 310 may provide a series of requests REQ regarding security write to the memory controller 200. The series of requests REQ may include reference Figure 2 and Figure 3 Described first request to third request.

[0090] The host processor 310 may provide the write data W_DATA stored in the host memory 320 and the first request to the memory controller 200 .

[0091] After providing the first request to the memory controller 200 , the host processor 310 may generate a host authentication code HA_CODE based on the key shared with the memory device 50 and the write data W_DATA.

[0092] The host processor 310 may provide the write data W_DATA to the memory controller 200 in parallel with the generation of the host authentication code HA_CODE. In other words, the generation of the host authentication code HA_CODE may be performed in parallel with the transmission of the write data W_DATA.

[0093] When the generation of the host authentication code HA_CODE is completed, the host processor 310 may provide the second request and the host authentication code HA_CODE to the memory controller 200 in response to the first response received from the memory controller 200 .

[0094] In response to the second response received from the memory controller 200 , the host processor 310 may provide a third request regarding a result of the program operation on the write data W_DATA to the memory controller 200 .

[0095] The host memory 320 may store write data W_DATA to be provided to the memory controller 200 .

[0096] According to reference Figure 4In the described embodiment, the generation of the host authentication code HA_CODE by the host processor 310 can be performed in parallel with the transmission of the write data W_DATA to the storage device 50. Therefore, the time required to perform the security write operation can be reduced by the time when the generation of the host authentication code HA_CODE overlaps with the transmission of the write data W_DATA.

[0097] According to reference Figure 4 In the described embodiment, the generation of the host authentication code HA_CODE by the host processor 310 can be performed in parallel with the generation of the device authentication code by the data verification component 220. Therefore, the time required to perform the security write operation can be reduced by the following time: the time during which the generation of the host authentication code HA_CODE overlaps with the generation of the device authentication code.

[0098] Figure 5 It is shown Figure 4 Schematic diagram of the data validation component 220 shown in .

[0099] Reference Figure 5 The data verification component 220 may include an authentication code generator 221 and an authentication code comparator 222. The data verification component 220 may further include an encryption key storage device 223.

[0100] The authentication code generator 221 may generate a device authentication code DA_CODE based on the write data W_DATA received from the host and the shared key KEY received from the encryption key storage device 223. The authentication code generator 221 may generate the device authentication code DA_CODE by using a message authentication code (MAC) algorithm. The authentication code generator 221 may provide the device authentication code DA_CODE to the authentication code comparator 222.

[0101] The authentication code comparator 222 may generate authentication information AUT_INF indicating integrity of the write data W_DATA based on comparison between the host authentication code HA_CODE and the device authentication code DA_CODE received from the host 300. The authentication code comparator 222 may determine whether the write data W_DATA has integrity according to whether the host authentication code HA_CODE is identical to the device authentication code DA_CODE.

[0102] The encryption key storage device 223 can store a shared key KEY between the host and the storage device. The shared key KEY can be used to generate an authentication code. The shared key KEY can be pre-stored in the encryption key storage device 223. The shared key KEY can be changed in response to a request from the host.

[0103] Figure 6 It is shown Figure 100147] Figure 2 is a diagram of another embodiment of a memory controller shown in FIG.

[0104] Reference Figure 6 , the memory controller 1000 may be connected to the host and the memory device. The memory controller 1000 may access the memory device in response to a request from the host. For example, the memory controller 1000 may control the write operation, read operation, erase operation, and background operation of the memory device. The memory controller 1000 may provide an interface between the memory device and the host. The memory controller 1000 may be configured to drive firmware for controlling the memory device.

[0105] The memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) block 1030 , a host interface 1040 , a buffer controller 1050 , a memory interface 1060 , and a bus 1070 .

[0106] The bus 1070 may provide a channel between the components of the memory controller 1000 .

[0107] The processor 1010 may control the overall operation of the memory controller 1000 and may perform a logic operation. The processor 1010 may communicate with an external host through a host interface 1040 and communicate with a memory device through a memory interface 1060. Further, the processor 1010 may communicate with a memory buffer 1020 through a buffer controller 1050. The processor 1010 may control the operation of a memory device by using the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory.

[0108] Processor 1010 can perform the function of flash translation layer (FTL). Processor 1010 can convert the logical block address (LBA) provided by the host into a physical block address (PBA) through FTL. FTL can receive LBA and convert LBA into PBA by using a mapping table. According to the mapping unit, there can be various address mapping methods for FTL. Typical address mapping methods can include page mapping method, block mapping method and hybrid mapping method.

[0109] The processor 1010 may be configured to randomize data received from the host. For example, the processor 1010 may use a randomization seed to randomize data received from the host. The randomized data may be provided to the memory device as data to be stored and may be programmed into the memory cell array.

[0110] The processor 1010 may be configured to de-randomize data received from the memory device during a read operation. For example, the processor 1010 may use a de-randomization seed to de-randomize data received from the memory device. The de-randomized data may be output to the host.

[0111] According to an embodiment, the processor 1010 may execute software or firmware to perform randomization and de-randomization operations.

[0112] The memory buffer 1020 may be used as an operation memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may store data processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0113] The ECC block 1030 may perform error correction. The ECC block 1030 may perform ECC encoding based on data to be written to the memory device through the memory interface 1060. The ECC-encoded data may be transmitted to the memory device through the memory interface 1060. The ECC block 1030 may perform ECC decoding on data received from the memory device through the memory interface 1060. For example, the ECC block 1030 may be included as a component of the memory interface 1060 and may be provided in the memory interface 1060.

[0114] The host interface 1040 may be configured to communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual Inline Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0115] The buffer controller 1050 may be configured to control the memory buffer 1020 under the control of the processor 1010 .

[0116] The memory interface 1060 may be configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 may exchange commands, addresses, and data with the memory device through a channel.

[0117] In an embodiment, the memory controller 1000 does not include the memory buffer 1020 and the buffer controller 1050. Instead, one or both of these components may be provided separately, and / or the functions of one or both of these components may be distributed within the memory controller 1000.

[0118] For example, the processor 1010 may use the code to control the operation of the memory controller 1000. The processor 1010 may load the code from a nonvolatile memory device (eg, a read only memory (ROM)) provided in the memory controller 1000. In another example, the processor 1010 may load the code from the memory device through the memory interface 1060.

[0119] For example, the bus 1070 of the memory controller 1000 may be divided into a control bus and a data bus. The data bus may be configured to transmit data in the memory controller 1000, and the control bus may be configured to transmit control information such as commands and addresses in the memory controller 1000. The data bus and the control bus may be isolated from each other so as not to interfere or affect each other. The data bus may be connected to the host interface 1040, the buffer controller 1050, the ECC block 1030, and the memory interface 1060. The control bus may be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0120] According to an embodiment, the authentication write controller 210 and the data verification component 220 may be included in the processor 1010 .

[0121] Figure 7 is a block diagram illustrating a memory card system 2000 to which a memory device according to an embodiment of the present disclosure is applied.

[0122] Reference Figure 7 , the memory card system 2000 may include a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0123] The memory controller 2100 may be connected to the memory device 2200. The memory controller 2100 may access the memory device 2200. For example, the memory controller 2100 may be configured to control a read operation, a write operation, an erase operation, and a background operation of the memory device 2200. The memory controller 2100 may be configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 may be configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may be configured to be similar to the above referenced Figure 1 The memory controller 200 is configured in the same manner as described.

[0124] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC block.

[0125] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a specific communication protocol. For example, the memory controller 2100 may communicate with an external device through at least one of various communication protocols such as: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-e or PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and / or High-Speed ​​Non-Volatile Memory (NVMe). For example, the connector 2300 may be defined by at least one of the various communication protocols described above.

[0126] For example, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and / or spin transfer torque magnetic RAM (STT-MRAM).

[0127] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device and form a memory card such as a Personal Computer Memory Card International Association (PCMCIA), a Compact Flash card (CF), a Smart Media Card (e.g., SM or SMC), a Memory Stick, a Multimedia Card (e.g., MMC, RS-MMC, Micro MMC, or eMMC), a Secure Digital (SD) card (e.g., SD, Mini SD, Micro SD, or SDHC), and a Universal Flash Storage (UFS).

[0128] Figure 8 is a block diagram illustrating a solid state drive (SSD) system 3000 to which a storage device according to an embodiment of the present disclosure is applied.

[0129] Reference Figure 8, the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange signals with the host 3100 through a signal connector 3001, and may receive power through a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0130] According to an embodiment, the SSD controller 3210 may perform the above-mentioned Figure 1 The functionality of memory controller 200 is described.

[0131] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100. For example, the signal may be based on an interface of the host 3100 and the SSD 3200. For example, the signal may be defined by at least one of various interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-e or PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash memory (UFS), WiFi, Bluetooth, and / or non-volatile memory Express (NVMe).

[0132] The auxiliary power supply 3230 may be coupled to the host 3100 through the power connector 3002. The auxiliary power supply 3230 may be charged with power supplied from the host 3100. When power is not stably supplied from the host 3100, the auxiliary power supply 3230 may supply power of the SSD 3200. For example, the auxiliary power supply 3230 may be provided inside or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided in a mainboard, and may supply auxiliary power to the SSD 3200.

[0133] The buffer memory 3240 may be used as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, or PRAM.

[0134] According to an embodiment, the host 3100 may be connected to the reference Figure 4 The host 300 operates in the same manner as described.

[0135] Fig. 9 is a block diagram illustrating a user system 4000 to which a storage device according to an embodiment of the present disclosure is applied.

[0136] Reference Fig. 9 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0137] The application processor 4100 may operate components, an operating system (OS), or a user program included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0138] The memory module 4200 may be used as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a nonvolatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP), and then may be provided as a single semiconductor package.

[0139] The network module 4300 can communicate with an external device. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, or WiFi. For example, the network module 4300 may be included in the application processor 4100.

[0140] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may transmit the data stored in the storage module 4400 to the application processor 4100. According to an embodiment, the storage module 4400 may be implemented as a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure. For example, the storage module 4400 may be set as a removable storage medium (i.e., a removable drive) of the user system 4000, such as a memory card or an external drive.

[0141] According to an embodiment, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be used in the same manner as described above with reference to Figure 1 The storage module 4400 can be operated in the same manner as the memory device described above. Figure 1 The storage device 50 operates in the same manner as described.

[0142] The user interface 4500 may include an interface for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, or a piezoelectric device. The user interface 4500 may further include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, or a monitor.

[0143] According to an embodiment of the present disclosure, a computing system with improved write performance and an operating method of the computing system are provided.

[0144] Although the present invention has been shown and described in conjunction with various embodiments, it will be understood by those skilled in the art from this disclosure that various changes in form and operation may be made without departing from the scope and spirit of the present invention. The present invention encompasses all such changes that fall within the scope of the claims.

Claims

1. A computing system comprising: Host, generate host authentication code; as well as a storage device that receives a first request among a series of requests for security writing and write data from the host while generating the host authentication code; generating a device authentication code based on the write data in response to the first request; receiving, from the host, the host authentication code and a second request in the series of requests; and performing a programming operation on the write data based on a comparison result of the host authentication code and the device authentication code in response to the second request, The storage device starts generating the device authentication code regardless of whether the host authentication code is received. 2 . The computing system of claim 1 , wherein the host generates the host authentication code while providing the write data to the storage device. 3 . The computing system of claim 1 , wherein the host authentication code is generated and the device authentication code is generated by the storage device in parallel.

4. The computing system of claim 1 , wherein the storage device comprises: a memory device including a write protected area; as well as A memory controller controls the security writing.

5. The computing system of claim 4, wherein the memory controller comprises: a data verification component that generates authentication information indicating the integrity of the written data based on a comparison result of the host authentication code and the device authentication code; as well as The authentication write controller controls the programming operation based on the authentication information in response to the second request.

6. The computing system of claim 5, wherein the authentication write controller provides a first response to the host indicating whether the first request has been received in response to the first request, and provides a second response to the host indicating whether the second request has been received in response to the second request. 7 . The computing system of claim 5 , wherein the verifying write controller provides a third response including a result of the programming operation to the host in response to a third request among the series of requests received from the host. 8 . The computing system of claim 7 , wherein the result of the program operation includes information indicating whether the write data has integrity and information indicating whether the program operation has passed or has failed.

9. The computing system of claim 5, wherein the authenticate write controller controls the memory device to store the write data in the write protection area during the programming operation.

10. The computing system of claim 5, wherein the data validation component comprises: an authentication code generator, generating the device authentication code based on a key shared between the host and the storage device and the received write data; as well as An authentication code comparator generates the authentication information based on whether the host authentication code is the same as the device authentication code.

11. The computing system of claim 1, wherein the device authentication code and the host authentication code are generated based on a message authentication code algorithm (MAC algorithm).

12. A host, comprising: Host memory, storing write data; as well as a host processor providing a first request among a series of requests for security writes and the write data to a storage device; generating a host authentication code while providing the write data to the storage device; and providing a second request among the series of requests having the host authentication code to the storage device, The host processor transmits the host authentication code to the storage device upon completion of generating the host authentication code, regardless of whether reception of the write data is completed at the storage device.

13. The host of claim 12, wherein the host processor provides a third request in the series of requests, and The third request requests the memory device for a result of a program operation on the write data.

14. The host according to claim 13, wherein the result of the program operation includes information indicating whether the program operation has passed or has failed and authentication information indicating integrity of the write data, and The authentication information is generated based on a comparison result between a device authentication code and the host authentication code, and the storage device generates the device authentication code based on the write data. 15 . The host of claim 12 , wherein the host processor generates the host authentication code based on a key shared between the storage device and the host and the write data.

16. The host of claim 12, wherein the host processor receives a first response from the storage device indicating whether the first request has been received; and provides the second request to the storage device in response to the first response; receiving a second response from the storage device indicating whether the second request has been received; and providing a third request from the series of requests to the storage device in response to the second response.

17. A method for operating a host, the method comprising: providing a first request of a series of requests for security writes and write data to a storage device, generating a host authentication code after providing the first request to the storage device; providing a second request among the series of requests and the host authentication code to the storage device after generating the host authentication code, wherein the host authentication code is generated while providing the write data to the storage device, and The host authentication code is transmitted to the storage device when generation of the host authentication code is completed, regardless of whether reception of the write data is completed at the storage device.

18. The method according to claim 17, further comprising: receiving a first response from the storage device, the first response indicating whether the first request has been received; receiving a second response from the storage device indicating whether the second request has been received; providing a third request to the storage device; and A third response including a result of the programming operation on the write data is received from the memory device.

19. The method of claim 18, wherein the host authentication code is generated based on a key shared between the storage device and the host and the write data.

20. The method according to claim 18, wherein the result of the program operation includes information indicating whether the program operation has passed or has failed and authentication information indicating integrity of the written data, and The authentication information is generated based on a comparison result between a device authentication code and the host authentication code, and the storage device generates the device authentication code based on the write data.

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