Method for finding optimal read voltage, flash memory system

Abstract

The application relates to the storage technical field and discloses a method for searching for an optimal reading voltage and a flash memory system. The method comprises the following steps: acquiring the difference value of the first state bit count at a first position and a second position in a threshold voltage range, the difference value of the first state bit count and the second state bit count at the first position, the difference value of the first state bit count at the second position and a third position, and the difference value of the first state bit count and the second state bit count at the second position; determining the direction for searching for the optimal reading voltage based on the difference values and determining the offset for searching for the optimal reading voltage according to the corresponding relationship between the difference value of the bit count and the offset; applying the offset to a current reference voltage for reading; and if the reading fails, acquiring new first and second positions according to the direction and the offset until the reading succeeds.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to methods for finding the optimal read voltage and flash memory systems. Background Technology

[0002] Non-volatile memory systems have become an important way to store data because the data stored in them is not lost when power is off. Among these non-volatile memory systems, NAND flash memory is popular due to its advantages of low power consumption and high efficiency.

[0003] When a flash memory is programmed, each storage cell has specific state information. This state information can represent any bit or data and forms a threshold voltage distribution corresponding to each state information. After programming, a read operation is performed to identify the storage cell with the specific state information. As described in patent document [US8953373B1], the charge stored in the battery can be detected in the form of cell voltage. To read an SLC (Single-level-cell) flash memory cell, the flash memory controller provides one or more reference voltages (also called read voltages). If the cell voltage is greater than the reference voltage, the detection circuitry in the flash memory represents the bit as "0"; if the cell voltage is less than the reference voltage, the bit is represented as "1". Therefore, SLC flash memory requires a single reference voltage. In contrast, MLC (Multi-level-cell) flash memory requires three such reference voltages, and TLC (Triple-level-cell) flash memory requires seven. Therefore, reading data from an MLC or TLC flash memory device requires the controller to provide multiple reference voltages with optimal values ​​to allow the storage device to correctly detect the stored data value.

[0004] However, as flash memory integration density increases, the reduction in flash cell size and the increase in noise between adjacent cells alter the target conductivity of the cells. Conventional methods using reference voltage to assist in detecting stored data values ​​typically rely on the assumption that the reference voltage window has a Gaussian distribution. Changes in the flash memory's operating environment can cause variations in the threshold voltage distribution, leading to errors that differ from the original programmed state information. For example, read errors may occur due to temperature variations and increased P / E cycles (program / erase cycles). This phenomenon is exacerbated by increasing flash memory density and the size of the programmed state information per cell. For instance, TLCs are less tolerant of variations than MLCs.

[0005] Furthermore, the conventional read retry method, which blindly searches for the reference voltage for successful page reads, can be slow, thus negatively impacting memory throughput. This method severely affects memory throughput in systems with TLC flash memory because previous page reads use four reference voltages, leading to an exponential increase in read retry time. The goal is to enable the flash controller to determine the optimal reference voltage by performing the fewest possible read retries. The prior art selects a reference voltage that operates at a high frequency from a preset pool of candidates. In other words, it determines the optimal Vref based on historical learning. It fails when there is no accumulated history or no candidates to correct errors.

[0006] Another existing technique for determining the optimal reference voltage [US8811076B2] is to apply an error count of adding / subtracting delta (or offset) to the reference voltage Vref to find the direction of the optimal Vref. When the current Vref differs too much from the optimal Vref, an error count cannot be obtained because the ECC engine has limitations in finding error counts. Therefore, it cannot be applied when the distribution varies greatly. Another problem is that it uses a linear search concept, by keeping the reference voltage added / subtracted by delta and reading it again, although this can make the reference voltage delta smaller each time. Summary of the Invention

[0007] The purpose of this application is to provide a method for finding the optimal read voltage in a flash memory system, which determines the optimal read voltage based on a single threshold voltage distribution, thereby improving the success probability of soft decision.

[0008] One embodiment of this application discloses a method for finding an optimal reference voltage, comprising:

[0009] The first difference between the first state bit count at the first position and the first state bit count at the second position within the threshold voltage range is obtained; the second difference between the first state bit count at the first position and the second state bit count at the second position is obtained; the third difference between the first state bit count at the second position and the first state bit count at the third position is obtained; and the fourth difference between the first state bit count at the second position and the second state bit count at the second position is obtained.

[0010] Based on the aforementioned differences, the direction for finding the optimal read voltage is determined, and the offset for finding the optimal read voltage is determined according to the correspondence between the bit count differences and the offset.

[0011] The determined offset is applied to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal reading voltage. If the reading fails, a new first position and a second position are obtained according to the determined direction and offset until the reading is successful.

[0012] In a preferred embodiment, the step of determining the direction for finding the optimal read voltage based on the various differences and determining the offset for finding the optimal read voltage according to the correspondence between the bit count differences and the offset further includes:

[0013] If the first difference is greater than the third difference and the second difference is greater than the fourth difference, the direction of the optimal reading voltage is determined to be the positive direction starting from the first position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference;

[0014] If the first difference is less than the third difference and the second difference is greater than the fourth difference, the direction of the optimal reading voltage is determined to be the positive direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the third difference;

[0015] If the first difference is less than the third difference and the second difference is less than the fourth difference, the direction of the optimal reading voltage is determined to be a negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference.

[0016] If the first difference is greater than the third difference and the second difference is less than the fourth difference, the direction of the optimal reading voltage is determined to be a negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference.

[0017] If the first difference is equal to the third difference, the bit counts of the first position, the second position, and the third position are retrieved again.

[0018] In a preferred embodiment, the correspondence between the bit count difference and the offset is expressed as follows: Where K is the predetermined offset of each group, W is the voltage width of each group, R1 is the first state bit count of the first position, R2 is the first state bit count of the second position, and Δ is the difference between the first state bit count of the first position and the first state bit count of the second position.

[0019] In a preferred embodiment, the correspondence between the bit count difference and the offset is represented as a lookup table comprising multiple bit count difference groups.

[0020] One embodiment of this application discloses a method for finding an optimal reference voltage, comprising:

[0021] Obtain the first difference between the first state bit count at the first position and the first state bit count at the second position within the threshold voltage range, the second difference between the first state bit count and the second state bit count at the first position, and the third difference between the first state bit count and the second state bit count at the second position;

[0022] Based on the various differences and a predetermined peak threshold, the direction for finding the optimal read voltage is determined. If the first difference is less than the predetermined peak threshold, the offset for finding the optimal read voltage is determined according to the correspondence between the first difference and the offset. If the first difference is greater than or equal to the predetermined peak threshold, a third position is calculated according to the relationship between the first difference, the second difference, and the third difference. The first state bit count at the third position is read, and a fourth difference between the first state bit count at the second position and the first state bit count at the third position is obtained, or a fifth difference between the first state bit count at the third position and the first state bit count at the first position is obtained. Furthermore, the offset for finding the optimal read voltage is determined according to the correspondence between the bit count difference and the offset.

[0023] The determined offset is applied to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal reading voltage. If the reading fails, a new first position and a second position are obtained according to the determined direction and offset until the reading is successful.

[0024] In a preferred embodiment, if the first difference is less than the predetermined peak threshold, the step of determining the offset for finding the optimal read voltage based on the correspondence between the first difference and the offset further includes:

[0025] If the second difference is greater than the third difference, the direction of the optimal reading voltage is determined to be the positive direction starting from the first position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference;

[0026] If the second difference is less than the third difference, the direction of the optimal reading voltage is determined to be a negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference.

[0027] In a preferred embodiment, if the first difference is greater than or equal to the predetermined peak threshold, then a third position is calculated based on the relationship between the first difference, the second difference, and the third difference; a first state bit count is read from the third position; and a fourth difference is obtained between the first state bit count at the second position and the first state bit count at the third position, or a fifth difference is obtained between the first state bit count at the third position and the first state bit count at the first position. Furthermore, the step of determining the offset for finding the optimal reading voltage based on the correspondence between the bit count differences and the offset further includes:

[0028] If the second difference is greater than the third difference, the third position is located to the right of the second position. The first state bit count of the third position and the fourth difference between the first state bit count of the second position and the first state bit count of the third position are obtained. The direction of the optimal reading voltage is determined to be the positive direction starting from the second position. The offset of the optimal reading voltage is determined to be the offset corresponding to the fourth difference.

[0029] If the second difference is less than the third difference, the third position is located to the left of the first position. The first state bit count of the third position and the fifth difference between the first state bit count of the first position and the first state bit count of the third position are obtained. The direction of the optimal reading voltage is determined to be a negative direction starting from the first position. The offset of the optimal reading voltage is determined to be the offset corresponding to the fifth difference.

[0030] In a preferred embodiment, if the second difference equals the third difference, the bit counts of the first and second positions are retrieved again.

[0031] In a preferred embodiment, the correspondence between the bit count difference and the offset is expressed as follows: Where K is the predetermined offset of each group, W is the voltage width of each group, R1 is the first state bit count of the first position, R2 is the first state bit count of the second position, and Δ is the difference between the first state bit count of the first position and the first state bit count of the second position.

[0032] In a preferred embodiment, the correspondence between the bit count difference and the offset is represented as a lookup table comprising multiple bit count difference groups.

[0033] One embodiment of this application discloses a flash memory system, including:

[0034] The counter is configured to acquire a first difference between a first state bit count at a first position and a first state bit count at a second position within a threshold voltage range, a second difference between the first state bit count at the first position and the second state bit count, a third difference between the first state bit count at the second position and the first state bit count at a third position, and a fourth difference between the first state bit count at the second position and the second state bit count.

[0035] The control logic is configured as follows:

[0036] Based on the aforementioned differences, the direction for finding the optimal read voltage is determined, and the offset for finding the optimal read voltage is determined according to the correspondence between the bit count differences and the offset.

[0037] The determined offset is applied to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal reading voltage. If the reading fails, a new first position and a second position are obtained according to the determined direction and offset until the reading is successful.

[0038] In this embodiment, the optimal reading voltage is determined based on a single threshold voltage distribution, thereby improving the success probability of soft decision.

[0039] Compared to existing technologies, this application employs a bit count with no limit on the degree of error. It achieves a unified state point for the page, program, and read cells. To reduce physical interference between adjacent cells, this application employs randomization of the data used for programming, which results in an almost equal distribution of all states (eight for TLC type pages) across all cells of the page, with each state decoded as a bit. The bit count difference between two adjacent states is minimized when the read voltage Vref is at its optimal level. Our scheme searches for smaller offsets in the bit count. This scheme does not work if data is not written in a uniform distribution across all states. However, data randomization during writes is a standard applied to all current NAND flash memory.

[0040] Another major improvement in this application is the speed increase achieved by inferring the optimal read voltage Vref based on the bit count difference between two Vrefs. The target NAND chip distribution is pre-characterized as a bit count distribution by different Vrefs, using a lookup table for bit count differences and distances to the optimal Vref. Referencing the current bit count difference at the two Vrefs to the lookup table allows for on-the-fly inference of the optimal Vref without requiring continuous reads as each Vref changes.

[0041] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating a method for finding the optimal reading voltage according to one embodiment of this application.

[0043] Figure 2A and Figure 2B This is a schematic diagram of the process of adjusting the reference voltage in one embodiment of this application.

[0044] Figure 3 This is a schematic diagram of grouping threshold voltage ranges according to one embodiment of this application.

[0045] Figure 4 This is a flowchart illustrating a method for finding the optimal reading voltage according to one embodiment of this application.

[0046] Figure 5A and Figure 5B This is a schematic diagram of the process of adjusting the reference voltage in one embodiment of this application.

[0047] Figure 6 This is a schematic diagram of the structure of a flash memory system according to one embodiment of this application. Detailed Implementation

[0048] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0050] like Figure 1 As shown, in one embodiment of this application, the method for finding the optimal reading voltage includes the following steps:

[0051] Step 102: Obtain the first difference R12 between the first state bit count R1 at the first position and the first state bit count R2 at the second position within the threshold voltage range; the second difference R1Δ(0-1) between the first state bit count and the second state bit count at the first position; the third difference R23 between the first state bit count R2 at the second position and the first state bit count R3 at the third position; and the fourth difference R2Δ(0-1) between the first state bit count and the second state bit count at the second position. In this embodiment, the first state is logic "1" and the second state is logic "0". It should be noted that each difference R12, R1Δ(0-1), R23, and R2Δ(0-1) is taken as an absolute value.

[0052] Step 104: Determine the direction for finding the optimal read voltage based on the various differences, and determine the offset for finding the optimal read voltage according to the correspondence between the bit count differences and the offset. (Reference) Figure 2A and 2B As shown, in one embodiment, this step further includes the following:

[0053] If the first difference R12 is greater than the third difference R23 and the second difference R1Δ(0-1) is greater than the fourth difference R2Δ(0-1), the direction of the optimal reading voltage is determined to be the positive direction starting from the first position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference R12. Figure 2A As shown by the middle arrow 202, the reference voltage determined in this case is R1 + offset(R12), where offset(R12) is the offset corresponding to the difference R12.

[0054] If the first difference R12 is less than the third difference R23 and the second difference R1Δ(0-1) is greater than the fourth difference R2Δ(0-1), the direction of the optimal reading voltage is determined to be the positive direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the third difference R23. Figure 2B As indicated by arrow 206, the threshold voltage peak crosses to the left at this point. The reference voltage determined in this case is R2 + offset(R23), where offset(R23) is the offset corresponding to the difference R23.

[0055] If the first difference R12 is less than the third difference R23 and the second difference R1Δ(0-1) is less than the fourth difference R2Δ(0-1), the direction of the optimal reading voltage is determined to be a negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference R12. Figure 2A As shown by the middle arrow 204, the reference voltage determined in this case is R2-offset(R12), where offset(R12) is the offset corresponding to the difference R12.

[0056] If the first difference R12 is greater than the third difference R23 and the second difference R1Δ(0-1) is less than the fourth difference R2Δ(0-1), the direction of the optimal reading voltage is determined to be a negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference R12. Figure 2B As indicated by arrow 208, the threshold voltage peak crosses to the right at this point. The reference voltage determined in this case is R2 - offset(R12), where offset(R12) is the offset corresponding to the difference R12.

[0057] Furthermore, if the first difference R12 is equal to the third difference R23, the bit counts R1, R2, and R3 of the first, second, and third positions are reacquired.

[0058] In one embodiment, the correspondence between the bit count difference and the offset can be expressed as follows: Where K is the predetermined offset of each group, W is the voltage width of each group, R1 is the first state bit count of the first position, R2 is the first state bit count of the second position, and Δ is the difference between the first state bit count of the first position and the first state bit count of the second position.

[0059] In one embodiment, the correspondence between the bit count difference and the offset can be represented as a lookup table including multiple bit count difference groups. Specifically: assuming two adjacent threshold voltage states are symmetrically distributed, the threshold voltage states are grouped according to the bit count range, and the linear gradient of each region (group) is approximately the same. Figure 3As shown, the threshold voltage ranges on both sides of the center of symmetry are symmetrically divided into four groups. The four groups on the left represent increasing the offset, and the four groups on the right represent subtracting the offset. The adjustment offset from each region to the optimal read voltage (the voltage value at the center of symmetry of two adjacent threshold voltage state distributions) can be predetermined and provided as a defined lookup table. The offset lookup table corresponding to the first difference R12 is shown in Table 1 below. Here, K1, K2, K3, and K4 represent the predetermined offsets for groups 1 to 4, respectively, and W1, W2, W3, and W4 represent the voltage widths for groups 1 to 4, respectively.

[0060] Table 1: Offset Lookup Table Corresponding to the First Difference R12

[0061] R12 Location offset >3000 Peak value (Summit) invalid 1500-3000 High2 (Group 1) ±K1±W1×(Δ-R2) / R12 500-1500 High1 (Group 2) ±K2±W2×(Δ-R2) / R12 200-500 Mid (Group 3) ±K3±W3×(Δ-R2) / R12 0-200 Low (Group 4) ±K4±W4×(Δ-R2) / R12

[0062] In one embodiment, K1 can be 30, K2 can be 20, K3 can be 10, K4 can be 0, and W1, W2, W3 and W4 can all be 10.

[0063] In a typical correction process, a soft decision is usually used to attempt to correct the error. However, when the reference voltage deviates too far from the median (optimal) value, the correction time taken by the soft decision becomes very long, and its correction capability decreases accordingly, eventually failing to correct the error. If an offset lookup table search algorithm is used, low-density parity-check codes (LDPC) can still correct the error even if the reference voltage deviates from the median value, thus significantly improving the overall correction capability and shortening the correction time considerably.

[0064] Step 106: Apply the determined offset to the current reference voltage for reading. If the reading is successful, the current reference voltage plus the offset is the optimal reading voltage. If the reading fails, obtain a new first position and a second position according to the determined direction and offset until the reading is successful.

[0065] like Figure 4 As shown, in another embodiment of this application, the method for finding the optimal reading voltage includes the following steps:

[0066] Step 402: Obtain the first difference R12 between the first state bit count R1 at the first position and the first state bit count R2 at the second position within the threshold voltage range, the second difference R1Δ(0-1) between the first state bit count and the second state bit count at the first position, and the third difference R2Δ(0-1) between the first state bit count and the second state bit count at the second position.

[0067] Step 404: Determine the direction for finding the optimal read voltage based on the various differences and the predetermined peak threshold (ST). If the first difference R12 is less than the predetermined peak threshold ST, determine the offset for finding the optimal read voltage according to the correspondence between the first difference R12 and the offset. Figure 5A As shown, in one embodiment, this step further includes the following:

[0068] If the second difference R1Δ(0-1) is greater than the third difference R2Δ(0-1), the direction of the optimal reading voltage is determined to be the positive direction starting from the first position. Figure 5A As indicated by arrow 502, the offset of the optimal read voltage is determined to be the offset corresponding to the first difference R12. In this case, the determined reference voltage is R1 + offset(R12), where offset(R12) is the offset corresponding to the difference R12.

[0069] If the second difference R1Δ(0-1) is less than the third difference R2Δ(0-1), the direction of the optimal reading voltage is determined to be the negative direction starting from the second position. Figure 5A As indicated by arrow 504, the offset of the optimal read voltage is determined to be the offset corresponding to the first difference R12. In this case, the determined reference voltage is R2 - offset(R12), where offset(R12) is the offset corresponding to the difference R12.

[0070] In other embodiments, if the first difference R12 is greater than or equal to the predetermined peak threshold ST, then the third position is calculated based on the relationship between the first difference R12, the second difference R1Δ(0-1), and the third difference R2Δ(0-1), with reference to... Figure 5B As shown, in one embodiment, this step further includes the following:

[0071] If the second difference R1Δ(0-1) is greater than the third difference R2Δ(0-1), and the third position is located to the right of the second position, obtain the first state bit count R3 of the third position and the fourth difference R23 between the first state bit count R2 of the second position and the first state bit count R3 of the third position, and determine the direction of the optimal reading voltage as the positive direction starting from the second position. Figure 5B As indicated by arrow 506. Furthermore, the offset of the optimal read voltage is determined to be the offset corresponding to the fourth difference. At this time, the threshold voltage peak crosses to the left. The reference voltage determined in this case is R2 + offset(R23), where offset(R23) is the offset corresponding to the difference R23.

[0072] If the second difference R1Δ(0-1) is less than the third difference R2Δ(0-1), the third position is located to the left of the first position. The fifth difference R13 between the first state bit count R3 of the third position and the first state bit count R1 of the first position and the first state bit count R3 of the third position is obtained. Furthermore, the direction of the optimal read voltage is determined to be a negative direction starting from the first position. Figure 5B As indicated by arrow 508. Furthermore, the offset of the optimal read voltage is determined to be the offset corresponding to the fifth difference. At this point, the threshold voltage peak crosses to the right. The reference voltage determined in this case is R1-offset(R13), where offset(R13) is the offset corresponding to the difference R13.

[0073] Furthermore, if the second difference R1Δ(0-1) is equal to the third difference R2Δ(0-1), the bit counts R1 and R2 of the first and second positions are reacquired.

[0074] Step 406: Apply the determined offset to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal reading voltage. If the reading fails, obtain a new first position and a second position according to the determined direction and offset until the reading is successful.

[0075] Compared to method 100, which seeks the optimal reading voltage, method 400 only needs to acquire the first and second positions initially, and only needs to acquire the third position when a peak value is crossed. Method 400 can further shorten the time required to find the optimal reading voltage.

[0076] One embodiment of this application discloses a flash memory system. Figure 6 This is a block diagram of a flash memory system 600 according to an embodiment of this application. The flash memory system 600 may include a memory controller 602 and a flash memory 608. According to this embodiment, the flash memory 608 receives control signals from the controller 602 and performs operations corresponding to the control signals. The flash memory 608 sends the execution result of the operation corresponding to the control signals to the memory controller. For example, in response to the control signals, the flash memory 608 may perform a read operation, a program operation, or an erase operation, or it may send the read data, information about whether programming and erasing have been completed, to the memory controller 602. For example, performing the bit counting read operation described above.

[0077] In one embodiment, the storage controller 602 may include a counter 604 and control logic 606. The counter is configured to acquire a first difference between a first state bit count at a first position and a first state bit count at a second position within a threshold voltage range, a second difference between the first state bit count at the first position and the second state bit count, a third difference between the first state bit count at the second position and the first state bit count at a third position, and a fourth difference between the first state bit count at the second position and the second state bit count.

[0078] Control logic 606 is configured to determine the direction for finding the optimal read voltage based on the various differences, determine the offset for finding the optimal read voltage according to the correspondence between the bit count difference and the offset, and apply the determined offset to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal read voltage. If the reading fails, a new first position and a second position are obtained according to the determined direction and offset until the reading is successful.

[0079] It should be noted that in this patent application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0080] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

[0081] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A method for finding an optimal reference voltage, characterized in that, include: Obtain the first difference (R12) between the first state bit count (R1) at the first position and the first state bit count (R2) at the second position within the threshold voltage range, the second difference (R1Δ(0-1)) between the first state bit count and the second state bit count at the first position, the third difference (R23) between the first state bit count (R2) at the second position and the first state bit count (R3) at the third position, and the fourth difference (R2Δ(0-1)) between the first state bit count and the second state bit count at the second position; Based on the first difference (R12), the second difference (R1Δ(0-1)), the third difference (R23) and the fourth difference (R2Δ(0-1)), the direction for finding the optimal read voltage is determined, and the offset for finding the optimal read voltage is determined according to the correspondence between the bit count difference and the offset. The determined offset is applied to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal reading voltage. If the reading fails, a new first position and a second position are obtained according to the determined direction and offset until the reading is successful.

2. The method for finding the optimal reference voltage according to claim 1, characterized in that, The step of determining the direction for finding the optimal read voltage based on the first difference (R12), the second difference (R1Δ(0-1)), the third difference (R23), and the fourth difference (R2Δ(0-1)), and determining the offset for finding the optimal read voltage according to the correspondence between the bit count difference and the offset, further includes: If the first difference (R12) is greater than the third difference (R23) and the second difference (R1Δ(0-1)) is greater than the fourth difference (R2Δ(0-1)), the direction of the optimal reading voltage is determined to be the positive direction starting from the first position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference (R12). If the first difference (R12) is less than the third difference (R23) and the second difference (R1Δ(0-1)) is greater than the fourth difference (R2Δ(0-1)), the direction of the optimal reading voltage is determined to be the positive direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the third difference (R23). If the first difference (R12) is less than the third difference (R23) and the second difference (R1Δ(0-1)) is less than the fourth difference (R2Δ(0-1)), the direction of the optimal reading voltage is determined to be the negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference (R12). If the first difference (R12) is greater than the third difference (R23) and the second difference (R1Δ(0-1)) is less than the fourth difference (R2Δ(0-1)), the direction of the optimal reading voltage is determined to be the negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference (R12). If the first difference (R12) is equal to the third difference (R23), the bit counts of the first, second, and third positions are retrieved again.

3. The method for finding the optimal reference voltage according to claim 2, characterized in that, The correspondence between the difference in bit counts and the offset is expressed as follows: Where K is the predetermined offset of each group, W is the voltage width of each group, R1 is the first state bit count of the first position, R2 is the first state bit count of the second position, and Δ is the difference between the first state bit count of the first position and the first state bit count of the second position.

4. The method for finding the optimal reference voltage according to claim 2, characterized in that, The correspondence between the bit count difference and the offset is represented as a lookup table that includes multiple bit count difference groups.

5. A method for finding an optimal reference voltage, characterized in that, include: Obtain the first difference (R12) between the first state bit count (R1) at the first position and the first state bit count (R2) at the second position within the threshold voltage range, the second difference (R1Δ(0-1)) between the first state bit count and the second state bit count at the first position, and the third difference (R2Δ(0-1)) between the first state bit count and the second state bit count at the second position. Based on the first difference (R12), the second difference (R1Δ(0-1)), and the third difference (R2Δ(0-1)) and a predetermined peak threshold, the direction for finding the optimal read voltage is determined. If the first difference is less than the predetermined peak threshold (ST), the offset for finding the optimal read voltage is determined according to the correspondence between the first difference (R12) and the offset. If the first difference is greater than or equal to the predetermined peak threshold (ST), then the direction for finding the optimal read voltage is determined according to the correspondence between the first difference (R12), the second difference (R1Δ(0-1)), and the predetermined peak threshold (ST). The relationship of the third difference (R2Δ(0-1)) is used to calculate the third position. The first state bit count (R3) of the third position is read and the fourth difference (R23) between the first state bit count (R2) at the second position and the first state bit count (R3) at the third position is obtained, or the fifth difference (R13) between the first state bit count (R3) at the third position and the first state bit count (R1) at the first position is obtained. Furthermore, the offset for finding the optimal reading voltage is determined based on the correspondence between the bit count difference and the offset. The determined offset is applied to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal reading voltage. If the reading fails, a new first position and a second position are obtained according to the determined direction and offset until the reading is successful.

6. The method for finding the optimal reference voltage according to claim 5, characterized in that, If the first difference (R12) is less than the predetermined peak threshold (ST), the step of determining the offset for finding the optimal read voltage based on the correspondence between the first difference (R12) and the offset further includes: If the second difference (R1Δ(0-1)) is greater than the third difference (R2Δ(0-1)), the direction of the optimal reading voltage is determined to be the positive direction starting from the first position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference (R12). If the second difference (R1Δ(0-1)) is less than the third difference (R2Δ(0-1)), the direction of the optimal reading voltage is determined to be the negative direction starting from the second position, and the offset of the optimal reading voltage is determined to be the offset corresponding to the first difference (R12).

7. The method for finding the optimal reference voltage according to claim 5, characterized in that, If the first difference (R12) is greater than or equal to the predetermined peak threshold (ST), then a third position is calculated based on the relationship between the first difference (R12), the second difference (R1Δ(0-1)), and the third difference (R2Δ(0-1)). The first state bit count (R3) at the third position is read, and a fourth difference (R23) is obtained between the first state bit count (R2) at the second position and the first state bit count at the third position, or a fifth difference (R13) is obtained between the first state bit count (R3) at the third position and the first state bit count (R1) at the first position. Furthermore, the step of determining the offset for finding the optimal reading voltage based on the correspondence between the bit count differences and the offset further includes: If the second difference (R1Δ(0-1)) is greater than the third difference (R2Δ(0-1)), the third position is located to the right of the second position. The first state bit count (R3) of the third position and the fourth difference (R23) between the first state bit count (R2) of the second position and the first state bit count of the third position are obtained. The direction of the optimal reading voltage is determined to be the positive direction starting from the second position. The offset of the optimal reading voltage is determined to be the offset corresponding to the fourth difference (R23). If the second difference (R1Δ(0-1)) is less than the third difference (R2Δ(0-1)), the third position is located to the left of the first position. The first state bit count (R3) of the third position and the fifth difference (R13) between the first state bit count (R1) of the first position and the first state bit count of the third position are obtained. The direction of the optimal reading voltage is determined to be a negative direction starting from the first position. The offset of the optimal reading voltage is determined to be the offset corresponding to the fifth difference (R13).

8. The method for finding the optimal reference voltage according to claim 6 or 7, characterized in that, If the second difference (R1Δ(0-1)) is equal to the third difference (R2Δ(0-1)), the bit counts of the first and second positions are retrieved again.

9. The method for finding the optimal reference voltage according to claim 6 or 7, characterized in that, The correspondence between the difference in bit counts and the offset is expressed as follows: Where K is the predetermined offset of each group, W is the voltage width of each group, R1 is the first state bit count of the first position, R2 is the first state bit count of the second position, and Δ is the difference between the first state bit count of the first position and the first state bit count of the second position.

10. The method for finding the optimal reference voltage according to claim 6 or 7, characterized in that, The correspondence between the bit count difference and the offset is represented as a lookup table that includes multiple bit count difference groups.

11. A flash memory system, characterized in that, include: The counter is configured to acquire a first difference (R12) between a first state bit count (R1) at a first position and a first state bit count (R2) at a second position within a threshold voltage range, a second difference (R1Δ(0-1)) between the first state bit count and the second state bit count at the first position, a third difference (R23) between the first state bit count (R2) at the second position and the first state bit count (R3) at the third position, and a fourth difference (R2Δ(0-1)) between the first state bit count and the second state bit count at the second position. The control logic is configured as follows: Based on the first difference (R12), the second difference (R1Δ(0-1)), the third difference (R23) and the fourth difference (R2Δ(0-1)), the direction for finding the optimal read voltage is determined, and the offset for finding the optimal read voltage is determined according to the correspondence between the bit count difference and the offset. The determined offset is applied to the current reference voltage for reading. If the reading is successful, the voltage obtained by adding the offset to the current reference voltage is the optimal reading voltage. If the reading fails, a new first position and a second position are obtained according to the determined direction and offset until the reading is successful.

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