semiconductor packaging devices

Abstract

The present disclosure provides a semiconductor packaging device, in which a through hole is opened in a protrusion by mechanical drilling to obtain a uniform hole diameter. The outer wall of the through hole is spaced apart from the interior of the accommodating cavity to prevent the through hole from passing through the interface between the adhesive layer and the first dielectric layer, thereby avoiding the problem of necking or voids generated at the interface between the adhesive layer and the first dielectric layer by mechanical drilling, thereby improving product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging device. Background Art

[0002] Flip Chip Ball Grid Array (FCBGA) substrates are increasingly in demand for fifth-generation (5G) mobile communications. FCBGA substrates have many layers, so improving their yield is a major challenge from a manufacturing perspective. To increase substrate yield, the fabricated substrates are typically bonded together with an adhesive layer before drilling holes to facilitate electrical connections in subsequent steps.

[0003] In actual production, if laser drilling is used, due to the characteristics of laser, the top diameter of the drilled hole will be larger than the bottom diameter, with a large diameter difference, occupying a large top surface space, thereby limiting the circuit design of the substrate. If mechanical drilling is used, since the hardness of the adhesive layer is lower than that of the dielectric layer, necking or voids will occur at the interface between the adhesive layer and the dielectric layer, which will lead to failure of the hole electroplating in the subsequent process. Figure 1A As shown, the hardness of the adhesive layer 12 is less than that of the first dielectric layer 11 and the third dielectric layer 18. When mechanical drilling is performed from top to bottom, a crack as shown in FIG. Figure 1B The necking 31 shown in a in FIG. 1 produces a shape similar to that in FIG. 1 at the interface between the adhesive layer 12 and the third dielectric layer 18. Figure 1B The void 32 shown in b. Neck shrinkage, voids or cracks will affect subsequent processes, such as causing failure of through-hole electroplating. This problem needs to be solved urgently. Summary of the Invention

[0004] The present disclosure provides a semiconductor packaging device and a method for manufacturing the same.

[0005] In a first aspect, a semiconductor packaging device includes:

[0006] A first circuit layer, comprising a first dielectric layer, wherein the first dielectric layer is provided with a receiving cavity penetrating the first dielectric layer, and the first dielectric layer has a first surface;

[0007] an adhesive layer, disposed on the first surface and provided with a convex portion matching the accommodating cavity, wherein the hardness of the adhesive layer is lower than that of the first dielectric layer;

[0008] A through hole is provided in the convex portion, and a distance is provided between an outer wall of the through hole and an inner wall of the accommodating cavity.

[0009] In some optional embodiments, a through-hole conductive layer is provided in the through-hole, and the through-hole conductive layer is electrically connected to the first circuit layer.

[0010] In some optional embodiments, the first dielectric layer further includes a second surface opposite to the first surface;

[0011] The first circuit layer further includes:

[0012] a second dielectric layer disposed on the second surface, wherein a metal layer covering the accommodating cavity is disposed between the second dielectric layer and the first dielectric layer;

[0013] The through hole passes through the metal layer and is at least partially disposed in the second dielectric layer.

[0014] In some optional embodiments, the first circuit layer is a substrate or a redistribution layer including at least one layer of circuits.

[0015] In some optional embodiments, a via hole is provided on the first surface, and an inner wall of the via hole contacts the adhesive layer.

[0016] In some optional embodiments, the semiconductor packaging device further includes: a second circuit layer, disposed on a surface of the adhesive layer away from the first circuit layer, the second circuit layer being a substrate or a redistribution layer including at least one layer of circuits.

[0017] In some optional embodiments, the semiconductor packaging device further includes: an electrical connector, disposed on the first surface and electrically connected to the first circuit layer.

[0018] In some optional embodiments, the semiconductor packaging device further includes:

[0019] The chip is arranged with its passive surface facing the second circuit layer and its active surface facing the adhesive layer, and the adhesive layer covers the chip, and the chip is electrically connected to the electrical connector.

[0020] In some optional embodiments, the semiconductor packaging device further includes: a heat dissipation circuit, which is disposed in the second circuit layer and contacts the passive surface of the chip.

[0021] In some optional embodiments, the semiconductor packaging device further includes: a passive electronic component disposed on the adhesive layer.

[0022] In some optional embodiments, the passive electronic component is electrically connected to the first circuit layer.

[0023] In some optional embodiments, the passive electronic component is electrically connected to the second circuit layer.

[0024] In some optional embodiments, a via hole is provided on the connection surface of the second circuit layer and the adhesive layer, and an inner wall of the via hole contacts the adhesive layer.

[0025] In some optional embodiments, the diameter of the through hole is 50 to 80 microns.

[0026] In some optional embodiments, the minimum diameter of the horizontal cross-section of the accommodating cavity is greater than the diameter of the through hole and does not exceed 120% of the diameter of the through hole.

[0027] In some optional embodiments, the semiconductor packaging device further includes:

[0028] The bonding line is arranged on the adhesive layer.

[0029] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor package device, comprising:

[0030] Providing a first dielectric layer and an adhesive layer, wherein the first dielectric layer is provided with a receiving cavity penetrating the first dielectric layer, the first dielectric layer has a first surface, the adhesive layer is provided on the first surface and has a protrusion matching the receiving cavity, and the hardness of the adhesive layer is less than that of the first dielectric layer;

[0031] A hole is drilled through the convex portion, and a distance is provided between the outer wall of the hole and the inner wall of the accommodating cavity to obtain the through hole.

[0032] The present disclosure provides a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device is designed to include: a first dielectric layer and an adhesive layer, wherein the first dielectric layer is provided with a receiving cavity penetrating the first dielectric layer, and the first dielectric layer has a first surface; the adhesive layer is provided on the first surface and provided with a convex portion matching the receiving cavity, and the hardness of the adhesive layer is less than that of the first dielectric layer. The convex portion is provided with a through hole, and there is a distance between the outer wall of the through hole and the inner wall of the receiving cavity. That is, by mechanically drilling a through hole in the convex portion to obtain a uniform aperture, there is a distance between the outer wall of the through hole and the interior of the receiving cavity, thereby avoiding the through hole from passing through the interface between the adhesive layer and the first dielectric layer, thereby avoiding the problem of necking or voids at the interface between the adhesive layer and the first dielectric layer caused by mechanical drilling, and improving the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

[0034] Figure 1A is a schematic longitudinal cross-sectional view of an embodiment of a semiconductor packaging device in the prior art;

[0035] Figure 1B yes Figure 1A An enlarged schematic diagram of the longitudinal cross-section local structure corresponding to the rectangular dotted line frame portion in the embodiment shown;

[0036] Figure 2A is a schematic longitudinal cross-sectional view of a semiconductor packaging device 200A according to an embodiment of the present disclosure;

[0037] Figure 2B for Figure 2A A longitudinal cross-sectional diagram of the local structure of the dotted line portion;

[0038] Figure 2C 、 2D 2E and 2F are schematic longitudinal cross-sectional views of semiconductor package devices 200C, 200D, 200E and 200F according to the present disclosure, respectively;

[0039] Figure 3 FIG. 1 is a schematic diagram of a longitudinal cross-sectional partial structure of a semiconductor package device manufactured according to an embodiment of the present disclosure;

[0040] Figures 4A to 4E 1 is a schematic longitudinal cross-sectional view of a semiconductor packaging device manufactured at different stages according to another embodiment of the present disclosure.

[0041] Explanation of symbols:

[0042] 11-first circuit layer; 111-first dielectric layer; 111a-first surface; 111b-second surface; 112-second dielectric layer; 113-accommodating cavity; 12-adhesive layer; 121-convex portion; 13-through hole; 131-through hole conductive layer; 14-second circuit layer; 141-heat dissipation circuit; 15-metal layer; 19-conductive hole; 20-electrical connector; 21-chip; 22-passive electronic component; 23-wire bonding; 31-necking; 32-void; 41-first carrier board; 42-second carrier board. DETAILED DESCRIPTION

[0043] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present invention and the technical effects produced by the present invention through the contents of this specification. It should be understood that the specific embodiments described herein are intended only to illustrate the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0044] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0045] It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0046] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0047] refer to Figure 2A and Figure 2B , Figure 2A FIG. 1 is a schematic longitudinal cross-sectional view of an embodiment 200A of a semiconductor package device according to the present disclosure. Figure 2B for Figure 2A Schematic diagram of the longitudinal section of the local structure of the dotted line part.

[0048] like Figure 2A and 2B As shown, the semiconductor package device 200A includes: a first circuit layer 11 , a second circuit layer 14 , an adhesive layer 12 disposed between the first circuit layer 11 and the second circuit layer 14 , and a through hole 13 .

[0049] in:

[0050] The first circuit layer 11 has a first dielectric layer 111. The first dielectric layer 111 is provided with a receiving cavity 113 penetrating the first dielectric layer 111. The first dielectric layer 111 further has a first surface 111a and a second surface 111b opposite to the first surface 111a.

[0051] The first dielectric layer 111 may include organic and / or inorganic substances, wherein the organic substance may be, for example, polyamide fiber (PA), polyimide (PI), epoxy resin (Epoxy), poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., and the inorganic substance may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0052] The adhesive layer 12 is disposed on the first surface 111 a and has a protrusion 121 matching the accommodating cavity 113 . The hardness of the adhesive layer 12 may be lower than that of the first dielectric layer 11 .

[0053] The adhesive layer 12 may include liquid and / or thin film organic materials, such as non-conductive plastic (NCP), non-conductive film (NCF), anisotropic conductive adhesive film (ACF), anisotropic conductive adhesive plastic (ACP), PI, epoxy, resin, PP, ABF, glue, etc. The materials of the adhesive layer 12 are merely illustrative and not specific. In the technical solution of the present disclosure, the hardness of the adhesive layer 12 can be less than the hardness of the first dielectric layer 11.

[0054] The through hole 13 is formed in the protrusion 121 , and a distance exists between the outer wall of the through hole 13 and the inner wall of the accommodating cavity 121 .

[0055] The through hole 13 can be drilled by mechanical drilling. In practice, the drilling direction of the through hole 13 can also be selected according to actual needs. For example, Figure 2A and Figure 2B As shown, a hole can be drilled from the outer surface of the second circuit layer 14 at the corresponding convex portion 121 toward the first circuit layer 11, and through the second circuit layer 14, the adhesive layer 12 and the convex portion 121. The through hole 13 can also partially or completely pass through the second dielectric layer 112. After drilling, the semiconductor package device can be turned over to obtain Figure 2A and Figure 2BIt should be noted that the through hole 13 can be a hole that passes through the semiconductor package device, or a hole that connects the surface and inner layer of the semiconductor package device without passing through the semiconductor package device.

[0056] It can be understood that the outer wall of the through hole 13 and the inner wall of the accommodating cavity 113 can be at least part of the protrusion 121 of the adhesive layer 12, and the through hole 13 does not contact the interface between the first dielectric layer 11 and the adhesive layer 12, that is, the inner wall of the accommodating cavity 113 during the opening process.

[0057] The present disclosure does not specifically limit the horizontal cross-sectional shape of the accommodating cavity 113 . The horizontal cross-sectional shape of the accommodating cavity 113 may be a regular or irregular shape generated by a drilling process, such as a square, a circle, an irregular polygon, etc.

[0058] The technical effects that can be achieved by the semiconductor packaging device 200A provided by the above-mentioned embodiments provided in the present disclosure include but are not limited to: by opening a through hole 13 in the protrusion 121, there is a distance between the outer wall of the through hole 13 and the interior of the accommodating cavity 113, thereby preventing the through hole 13 from passing through the interface between the adhesive layer 12 and the first dielectric layer 11, thereby avoiding the problem of necking or voids generated at the interface between the adhesive layer 12 and the first dielectric layer 11 by mechanical drilling, thereby improving the product yield of the semiconductor packaging device 200A.

[0059] In some optional embodiments, the second surface 111b is provided with a metal layer 15 covering the accommodating cavity 113. The metal layer 15 is provided on the protrusion 121, and the through hole 13 penetrates the metal layer 15. The dielectric material surface of the protrusion 121 of the adhesive layer 12 is directly attached to the metal layer 15. By penetrating the metal layer 15 to form the through hole 13, it is possible to avoid passing through the interface of two dielectric layers of different hardness when forming the through hole 13, thereby avoiding the problem of necking or voids caused by passing through the interface of two dielectric layers of different hardness during mechanical drilling.

[0060] In some optional embodiments, a through-hole conductive layer 131 is provided in the through-hole 13 , and the through-hole conductive layer 131 is electrically connected to the first circuit layer 11 .

[0061] In some optional embodiments, the first circuit layer 11 further includes a second dielectric layer 112 . The second dielectric layer 112 may be disposed on the second surface 111 b , and a metal layer 15 covering the accommodating cavity 113 is disposed between the second dielectric layer 112 and the first dielectric layer 111 .

[0062] The range of dielectric materials available for the second dielectric layer 112 is the same as that for the first dielectric layer 111 and will not be described in detail herein. In practice, the dielectric material of the second dielectric layer 112 may be the same as or different from that of the first dielectric layer 111 according to actual product or process requirements.

[0063] The through hole 13 may penetrate the metal layer 15 , the through hole 13 may penetrate the second dielectric layer 112 , or the through hole 13 may be at least partially disposed in the second dielectric layer 112 .

[0064] In some optional embodiments, the metal layer 15 and the through-hole conductive layer 131 may include a seed layer and a metal material layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal material layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof. Here, the seed layer can improve the bonding strength between the metal material layer and the dielectric material.

[0065] The first circuit layer 11 and / or the second circuit layer 14 can be a substrate composed of a conductive material and a dielectric material. The dielectric material can include organic and / or inorganic materials. Examples of organic materials include polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (Prepreg, also known as prepreg), and ABF (Ajinomoto Build-up Film). Examples of inorganic materials include silicon (Si), glass, ceramic, silicon oxide, silicon nitride, and tantalum oxide. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or their alloys.

[0066] The first circuit layer 11 and / or the second circuit layer 14 may also be a redistribution layer including at least one circuit layer. It should be noted that the manufacturing process may adopt currently known or future developed redistribution layer formation technology, which is not specifically limited in this application. For example, the redistribution layer may be formed by methods including but not limited to photolithography, electroplating, and electroless plating. Here, the dielectric material may include organic and / or inorganic substances, wherein the organic substances may include, for example, polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while the inorganic substances may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

[0067] In some optional embodiments, such as Figure 2A As shown, the first surface 111a may be provided with a via 19, the inner wall of which may contact the adhesive layer 12. The via 19 may increase the contact area between the first surface 111a and the adhesive layer 12, thereby increasing the bonding strength of the semiconductor package device.

[0068] The dielectric material selection range of the second circuit layer 14 is the same as that of the first circuit layer 11, which will not be repeated here. In practice, the dielectric material of the second circuit layer 14 can be the same as or different from that of the first circuit layer 11 according to actual product or process requirements.

[0069] In some optional embodiments, as shown in FIG. A , the semiconductor package device 200A further includes an electrical connector 20 disposed on the first surface 111 a and electrically connected to the first circuit layer 11 .

[0070] In some optional embodiments, such as Figure 2A As shown, the semiconductor package device 200A may further include:

[0071] The chip 21 is disposed with its passive surface facing the second circuit layer 14 and its active surface facing the adhesive layer 12 . The adhesive layer 12 covers the chip 21 , and the chip 21 is electrically connected to the electrical connector 20 .

[0072] In some optional embodiments, such as Figure 2A As shown, semiconductor package device 200A may further include a heat dissipation circuit 141 disposed on third dielectric layer 18 and contacting the lower surface of chip 21. Heat dissipation circuit 141 can conduct heat to chip 21, dissipating heat generated when chip 21 is powered on, thereby improving the chip heat dissipation performance of the semiconductor package device.

[0073] In some optional embodiments, such as Figure 2A As shown, the semiconductor package device 200A further includes a passive electronic component 22 disposed on the adhesive layer 12. Placing the passive electronic component 22 on the adhesive layer 12 can improve the utilization of the adhesive layer space, help improve the integration of the semiconductor package device, and reduce the volume or thickness of the semiconductor package device.

[0074] Continue to refer Figure 2C , Figure 2C The semiconductor package device 200C shown is similar to Figure 2A The semiconductor package device 200A shown in FIG. 2 is different in that the semiconductor package device 200C further includes bonding wires 23 disposed on the adhesive layer 12 .

[0075] Continue to refer Figure 2D , Figure 2D The semiconductor package device 200D shown is similar to Figure 2A The semiconductor package device 200A shown in FIG. 2 is different in that the passive electronic component 22 in the semiconductor package device 200D is electrically connected to the first circuit layer 11 .

[0076] Continue to refer Figure 2E , Figure 2E The semiconductor package device 200E shown is similar to Figure 2A The semiconductor package device 200A shown in FIG. 2 is different in that the passive electronic component 22 in the semiconductor package device 200E is electrically connected to the second circuit layer 15 .

[0077] The passive electronic components 22 are passive devices, such as capacitors, inductors, resistors, etc.

[0078] Continue to refer Figure 2F , Figure 2F The semiconductor package device 200F shown is similar to Figure 2AThe semiconductor package device 200A shown in FIG2 differs in that, in the semiconductor package device 200F, a via 19 is provided at the connection surface between the second circuit layer 15 and the adhesive layer 12. The inner wall of the via 19 contacts the adhesive layer 12. Thus, the via 19 increases the contact area between the third dielectric layer 18 and the adhesive layer 12, thereby improving the adhesion between the third dielectric layer 18 and the adhesive layer 12, thereby increasing the bonding strength of the semiconductor package device and enhancing the fixation of the semiconductor package device.

[0079] In some optional embodiments, the diameter of the through hole 13 is between 50 and 80 microns. The actual diameter range of the through hole 13 can be determined according to the accuracy of the drilling process. This is just an example. On the basis of improving the accuracy of the drilling process, the diameter of the through hole 13 can be further reduced.

[0080] In some optional embodiments, the minimum horizontal cross-sectional diameter of the accommodating cavity 113 is greater than the diameter of the through-hole 13 and does not exceed 120% of the diameter of the through-hole 13. The horizontal cross-sectional diameter of the accommodating cavity 113 should be spaced apart from the outer wall of the through-hole 13. Therefore, the minimum horizontal cross-sectional diameter of the accommodating cavity 113 should be greater than the diameter of the through-hole 13. To improve the integration density of the semiconductor packaging device and avoid wasted space, the minimum horizontal cross-sectional diameter of the accommodating cavity 113 should also not exceed 120% of the diameter of the through-hole 13. This is set to account for the process precision tolerance of mechanical drilling.

[0081] Reference below Figure 3 , Figure 3 is a schematic diagram of a partial longitudinal cross-section of a semiconductor packaging device 300 at a manufacturing stage according to some embodiments of the present disclosure.

[0082] refer to Figure 3 , providing a first dielectric layer 111 and an adhesive layer 12.

[0083] Here, the first dielectric layer 111 is provided with a receiving cavity 113 extending through the first dielectric layer 111. The first dielectric layer 111 has a first surface 111a and a second surface 111b opposite the first surface. The adhesive layer 12 is provided below the first surface 111a and has a protrusion 121 that matches the receiving cavity 113. The adhesive layer 12 has a lower hardness than the first dielectric layer 111.

[0084] Continue to refer Figure 3 A hole is drilled from the first surface 111 a through the convex portion 121 toward the second surface 111 b , with a distance between the outer wall of the drilled hole and the inner wall of the accommodating cavity 113 to obtain a through hole 13 .

[0085] Then, flip it to get Figure 2B A local structure of a semiconductor packaging device.

[0086] Reference below Figures 4A to 4E , Figures 4A to 4E 1 is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor package device manufactured at various stages according to some embodiments of the present disclosure.

[0087] refer to Figure 4A , providing a fan-out redistribution layer structure (including a first carrier board 41 and a first circuit layer 11), an adhesive layer 12 and a heat dissipation component layer structure (including a second carrier board 42 and a second circuit layer 15).

[0088] like Figure 4A As shown, the fan-out redistribution layer structure includes a first carrier 41 and a first circuit layer 11 disposed on the first carrier 41, which includes a first dielectric layer 111. The first circuit layer 11 is a redistribution layer comprising at least one circuit layer. The first dielectric layer 111 is provided with a receiving cavity 113 extending through the first dielectric layer 111. The first dielectric layer 111 has a first surface 111a and a second surface 111b opposite the first surface 111a. The second surface 111b is provided with a metal layer 15 covering the receiving cavity 113. The first surface 111a is provided with a via 19. The first dielectric layer 111 is electrically connected to a passive electronic component 22. The heat dissipation component layer structure includes a second carrier 42 and a second circuit layer 15 disposed on the second carrier 42. A chip 21 is disposed on the second circuit layer 15, which is electrically connected to an electrical connector 20. A heat dissipation circuit 141 is disposed on the second circuit layer 15 and contacts the passive surface of the chip 21.

[0089] refer to Figure 4B The fan-out redistribution layer structure (including the first carrier 41 and the first circuit layer 11) is bonded to the heat dissipation component layer structure (including the second carrier 42 and the second circuit layer 15) using the adhesive layer 12, and a heating process is performed to solidify the adhesive layer 12 and bond the fan-out redistribution layer structure (including the first carrier 41 and the first dielectric layer 111) to the heat dissipation component layer structure (including the second carrier 42 and the second circuit layer 15).

[0090] The fan-out redistribution layer structure (including the first carrier 41 and the first circuit layer 11), the adhesive layer 12, and the heat dissipation component layer structure (including the second carrier 42 and the second circuit layer 15) are pressed together. The adhesive layer 12 forms a protrusion 121 corresponding to the receiving cavity 113 and contacts the inner wall of the conductive via 19. After bonding, the chip 21 can be electrically connected to the fan-out redistribution layer structure (including the first carrier 41 and the first dielectric layer 111) via the electrical connector 20.

[0091] The bonding process may use, for example, flip chip bonding (FCB), thermal compression bonding (FCB) or similar technologies.

[0092] refer to Figure 4C , remove the first carrier plate 41 and the second carrier plate 42.

[0093] like Figure 4C As shown, for example, after removing the first carrier 41 , the semiconductor package device may be flipped over, and then the second carrier 42 may be removed. In actual manufacturing processes, the package structure may be flipped as needed, which is not specifically limited here.

[0094] refer to Figure 4D , at least one through hole 13 is drilled by mechanical drilling.

[0095] like Figure 4D As shown, the through hole 13 is opened through the protrusion 121 , and there is a distance between the outer wall of the through hole 13 and the inner wall of the accommodating cavity 113 .

[0096] refer to Figure 4E , a through-hole conductive layer 131 is formed on the inner wall and the end of the through-hole 13 .

[0097] The through-hole conductive layer 131 may be formed in the through-hole 13 by electroplating, electroless plating, or similar techniques. For example, a seed layer of the through-hole conductive layer may be formed on the inner wall and the surface of the through-hole 13, and a metal material layer of the through-hole conductive layer may be disposed on the upper surface of the seed layer of the through-hole conductive layer.

[0098] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present disclosure and the actual implementation. There may be other embodiments of the present disclosure that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor packaging device, comprising: A first circuit layer, comprising a first dielectric layer, wherein the first dielectric layer is provided with a receiving cavity penetrating the first dielectric layer, and the first dielectric layer has a first surface; an adhesive layer, disposed on the first surface and provided with a convex portion matching the accommodating cavity, wherein the hardness of the adhesive layer is lower than that of the first dielectric layer; a through hole, formed in the convex portion, with a distance between an outer wall of the through hole and an inner wall of the accommodating cavity; a second circuit layer, disposed on a surface of the adhesive layer away from the first circuit layer; The chip is arranged with its passive surface facing the second circuit layer and its active surface facing the adhesive layer, and the adhesive layer covers the chip.

2. The device according to claim 1, wherein: A through-hole conductive layer is provided in the through-hole, and the through-hole conductive layer is electrically connected to the first circuit layer.

3. The device according to claim 2, wherein The first dielectric layer further includes a second surface opposite to the first surface; The first circuit layer further includes: a second dielectric layer disposed on the second surface, wherein a metal layer covering the accommodating cavity is disposed between the second dielectric layer and the first dielectric layer; The through hole passes through the metal layer and is at least partially disposed in the second dielectric layer.

4. The device according to claim 1, wherein: The first circuit layer is a substrate or a redistribution layer including at least one layer of circuits.

5. The device according to claim 1, wherein The second circuit layer is a substrate or a redistribution layer including at least one layer of circuits.

6. The device according to claim 5, wherein The semiconductor packaging device further includes: An electrical connector is disposed on the first surface and electrically connected to the first circuit layer.

7. The device according to claim 6, wherein The chip is electrically connected to the electrical connection member.

8. The device according to claim 7, wherein The semiconductor packaging device further includes: The heat dissipation circuit is arranged on the second circuit layer and contacts the passive surface of the chip.

9. The apparatus according to claim 5, wherein: A connecting surface between the second circuit layer and the adhesive layer is provided with a via hole, and an inner wall of the via hole contacts the adhesive layer.

10. The device according to claim 1, wherein The minimum diameter of the horizontal cross section of the accommodating cavity is greater than the diameter of the through hole and does not exceed 120% of the diameter of the through hole.

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