Memory devices and methods

Abstract

In an embodiment, a memory device includes a first dielectric layer located over a substrate; a word line located over the first dielectric layer, the word line including a first main layer and a first adhesion layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer located over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage band disposed between the first bit line and the word line, the data storage band extending along a second sidewall of the word line. Embodiments of the invention also relate to methods of forming a memory device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to memory devices and methods. BACKGROUND

[0002] By way of example, semiconductor memory is used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computing devices, among others. Semiconductor memory includes two main categories. One is volatile memory; the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose stored information when not powered.

[0003] Non-volatile memory, on the other hand, can store data on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). Advantages of FeRAM include fast write / read speed and small size. SUMMARY

[0004] According to one aspect of the present invention, a method of forming a memory device is provided, comprising: etching a first trench in a multi-layer stack, the multi-layer stack comprising alternating dielectric layers and sacrificial layers; replacing a first portion of the sacrificial layers exposed by the first trench with a first conductive component; forming a first data storage strap and a first semiconductor strap in the first trench; after forming the first data storage strap and the first semiconductor strap, etching a second trench in the multi-layer stack; replacing a second portion of the sacrificial layers exposed by the second trench with a second conductive component; and forming a second data storage strap and a second semiconductor strap in the second trench.

[0005] According to another aspect of the present invention, a memory device is provided, comprising: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line comprising a first main layer and a first adhesion layer, the first adhesion layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strap disposed between the first bit line and the word line, the data storage strap extending along a second sidewall of the word line.

[0006] According to yet another aspect of the present application, a memory device is provided, comprising: a first dielectric layer over a substrate; a second dielectric layer over the first dielectric layer; a word line between the first dielectric layer and the second dielectric layer, the word line comprising a first main layer, a second main layer, and a first adhesive layer laterally disposed between the first main layer and the second main layer; a first data storage band contacting sidewalls of the first main layer, the first dielectric layer, and the second dielectric layer; and a second data storage band contacting sidewalls of the second main layer, the first dielectric layer, and the second dielectric layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice, the various drawings are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a block diagram of a random access memory according to some embodiments.

[0009] Figure 2A and Figure 2B are various views of a memory array according to some embodiments.

[0010] Figures 3A-14B are various views of an intermediate stage of manufacturing a memory array according to some embodiments.

[0011] Figures 15A-15B are various views of a memory array according to some other embodiments.

[0012] Figure 16A and Figure 16B are various views of a memory array according to some other embodiments.

[0013] Figure 17A and Figure 17B are various views of a memory array according to some other embodiments.

[0014] Figure 18A and Figure 18B are various views of a memory array according to some other embodiments.

[0015] Figures 19A-21B are various views of an intermediate stage of manufacturing a memory array according to some other embodiments.

[0016] Figure 22 is a cross-sectional view of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and the second component are in direct contact forming, and can also include embodiments where additional components can be formed between the first component and the second component such that the first component and the second component can not be in direct contact. Furthermore, the present application can be repeated with variations and / or modifications and with the same or equivalent process functions being combined in other configurations and / or arrangements for each individual embodiment. The same reference numerals in different drawings represent the same or similar elements.

[0018] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] According to various embodiments, word lines of a memory array are formed through a multiple patterning process, where a first portion of the word lines of the memory array and a first subset of transistors are formed in a first patterning process, and where a second portion of the word lines of the memory array and a second subset of transistors are subsequently formed in a second patterning process. Thus, the aspect ratio of the columns of the memory array can be improved while avoiding distortion or collapse of the components during the formation process.

[0020] Figure 1 is a block diagram of a random access memory 50 according to some embodiments. The random access memory 50 includes a memory array 52, a row decoder 54, and a column decoder 56. The memory array 52, the row decoder 54, and the column decoder 56 can each be part of the same semiconductor die, or can be part of different semiconductor dies. For example, the memory array 52 can be part of a first semiconductor die, while the row decoder 54 and the column decoder 56 can be part of a second semiconductor die.

[0021] The memory array 52 includes memory cells 58, word lines 62, and bit lines 64. The memory cells 58 are arranged in rows and columns. The word lines 62 and the bit lines 64 are electrically connected to the memory cells 58. The word lines 62 are conductive lines that extend along the rows of memory cells 58. The bit lines 64 are conductive lines that extend along the columns of memory cells 58.

[0022] Row decoder 54 can be, for example, a static complementary metal-oxide semiconductor (CMOS) decoder, a pseudo-N-type metal-oxide semiconductor (NMOS) decoder, or the like. During operation, row decoder 54 selects a desired memory cell 58 in a row of memory array 52 by activating a word line 62 of the row. Column decoder 56 can be, for example, a static CMOS decoder, a pseudo-NMOS decoder, or the like, and can include write drivers, sense amplifiers, combinations thereof, or the like. During operation, column decoder 56 selects a bit line 64 from a column of memory array 52 for a desired memory cell 58 in the selected row, and reads data from or writes data to the selected memory cell 58 using the bit line 64.

[0023] Figure 2A and Figure 2B are various views of memory array 52 according to some embodiments. Figure 2A is a circuit diagram of memory array 52. Figure 2B is a three-dimensional view of a portion of memory array 52.

[0024] In some embodiments, memory array 52 is a flash memory array, such as a NOR flash memory array. In some embodiments, memory array 52 is another type of non-volatile memory array, such as a magnetoresistive random access memory (MRAM) array, a resistive random access memory (RRAM) array, or the like. Each memory cell 58 is a flash memory cell that includes a thin-film transistor (TFT) 68. A gate of each TFT 68 is electrically connected to a respective word line 62, a first source / drain region of each TFT 68 is electrically connected to a respective bit line 64, and a second source / drain region of TFT 68 is electrically connected to a respective source line 66 (which is electrically grounded). Memory cells 58 in a same row of memory array 52 share a common word line 62, while memory cells in a same column of memory array 52 share a common bit line 64 and a common source line 66.

[0025] Memory array 52 includes a plurality of horizontally arranged conductive lines (e.g., word lines 62), with each of word lines 62 disposed between dielectric layers 72. Word lines 62 extend along a first direction Di that is parallel to a major surface of an underlying substrate (not shown in FIG. 1, but described in detail below in connection with FIG. 2). Word lines 62 can have a stepped arrangement such that lower word lines 62 are longer than upper word lines 62 and extend laterally beyond endpoints of upper word lines 62. For example, in Figure 2B is a three-dimensional view of a portion of memory array 52. Figures 3A-14B is a three-dimensional view of a portion of memory array 52. Figure 2BIn particular, a plurality of, stacked layers of word lines 62 are shown, with the uppermost word line 62A being the shortest line and the lowermost word line 62B being the longest line. The length of the respective word lines 62 increases in a direction extending toward the underlying substrate. In this manner, portions of each word line 62 can be accessed from above the memory array 52, such that conductive contacts can be formed to exposed portions of each word line 62.

[0026] The memory array 52 also includes a plurality of vertically arranged conductive lines (e.g., bit lines 64 and source lines 66). The bit lines 64 and source lines 66 extend in a second direction D2 that is perpendicular to the first direction Dl and a major surface of the underlying substrate. Dielectric layers 74 are disposed between and isolate adjacent bit and source lines. The boundaries of each memory cell 58 are defined by pairs of bit lines 64 and source lines 66 and intersecting word lines 62. Dielectric plugs 76 are disposed between and isolate adjacent pairs of bit and source lines 64, 66. Although Figure 2A and Figure 2B A particular placement of the bit lines 64 relative to the source lines 66 is shown, but it should be appreciated that the placement of the bit lines 64 and source lines 66 can be reversed in other embodiments.

[0027] The memory array 52 also includes ferroelectric strips 84 and semiconductor strips 82. The ferroelectric strips 84 are in contact with the word lines 62. The semiconductor strips 82 are disposed between the ferroelectric strips 84 and the dielectric layers 74.

[0028] The semiconductor strips 82 provide channel regions for the TFTs 68 of the memory cells 58. For example, when an appropriate voltage (e.g., above a respective threshold voltage (V th )) is applied through the respective word line 62, the region of the semiconductor strip 82 intersecting the word line 62 can allow current to flow from the bit line 64 to the source line 66 (e.g., in the Dl direction).

[0029] The ferroelectric strips 84 are data storage layers that can be polarized in one of two different directions by applying an appropriate voltage differential across the ferroelectric strip 84. Depending on the polarization direction of a particular region of the ferroelectric strip 84, the threshold voltage of the respective TFT 68 changes and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the ferroelectric strip 84 has a first polarization direction, the respective TFT 68 can have a relatively low threshold voltage, while when the region of the ferroelectric strip 84 has a second polarization direction, the respective TFT 68 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift can make it easier (e.g., less error prone) to read the digital value stored in the respective memory cell 58. Accordingly, the memory array 52 can also be referred to as a ferroelectric random access memory (FERAM) array.

[0030] To perform a write operation on a particular memory cell 58, a write voltage is applied across a region of the ferroelectric strip 84 corresponding to the memory cell 58. For example, the write voltage can be applied by applying appropriate voltages to the word line 62, the bit line 64, and the source line 66 corresponding to the memory cell 58. By applying the write voltage across the region of the ferroelectric strip 84, the polarization direction of the region of the ferroelectric strip 84 can be changed. Accordingly, the corresponding threshold voltage of the corresponding TFT 68 can be switched from a low threshold voltage to a high threshold voltage (or vice versa), such that a digital value can be stored in the memory cell 58. Because the word line 62 and the bit line 64 intersect in the memory array 52, individual memory cells 58 can be selected and written.

[0031] To perform a read operation on a particular memory cell 58, a read voltage (a voltage between the low and high threshold voltages) is applied to the word line 62 corresponding to the memory cell 58. Depending on the polarization direction of the corresponding region of the ferroelectric strip 84, the TFT 68 of the memory cell 58 can or can not be conductive. Accordingly, the bit line 64 can or can not be discharged (e.g., to ground) through the source line 66, thereby enabling the digital value stored in the memory cell 58 to be determined. Because the word line 62 and the bit line 64 intersect in the memory array 52, individual memory cells 58 can be selected and read from.

[0032] Figures 3A-14B are various views of an intermediate stage of manufacturing the memory array 52 according to some embodiments. Portions of the memory array 52 are shown. For clarity of illustration, some components are not shown, such as the stepped arrangement of word lines (see Figure 2B ). Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A and Figure 14A are three-dimensional views of the memory array 52. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B and Figure 14B are cross-sectional views taken along the reference section B-B in Figure 13A .

[0033] In Figure 3A and Figure 3B substrate 102 can be a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which can be doped (e.g., doped with a dopant of p-type or n-type) or undoped. The substrate 102 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or graded substrates, can also be used. In some embodiments, the semiconductor material of the substrate 102 can include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. The substrate 102 can include a dielectric material. For example, the substrate 102 can be a dielectric substrate, or can include a dielectric layer on a semiconductor substrate. Possible dielectric materials for a dielectric substrate include oxides such as silicon oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or a combination thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, or the like. In some embodiments, the substrate 102 is formed of silicon carbide.

[0034] A multilayer stack 104 is formed over the substrate 102. The multilayer stack 104 includes overlapping first dielectric layers 104A and second dielectric layers 104B. The first dielectric layers 104A are formed of a first dielectric material, while the second dielectric layers 104B are formed of a second dielectric material. The dielectric materials can each be selected from the candidate dielectric materials of the substrate 102. In the illustrated embodiment, the multilayer stack 104 includes five layers of first dielectric layers 104A and four layers of second dielectric layers 104B. It should be noted that the multilayer stack 104 can include any number of first dielectric layers 104A and any number of second dielectric layers 104B.

[0035] The multi-layer stack 104 is to be patterned in subsequent processing. As such, the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B both have a high etch selectivity compared to etching of the substrate 102. The patterned first dielectric layer 104A is to be used to isolate TFTs formed subsequently. The patterned second dielectric layer 104B is a sacrificial layer (or dummy layer) that is to be removed in subsequent processing and replaced by word lines of the TFTs. As such, the second dielectric material of the second dielectric layer 104B also has a high etch selectivity compared to etching of the first dielectric material of the first dielectric layer 104A. In embodiments where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A can be formed of an oxide such as silicon oxide, and the second dielectric layer 104B can be formed of a nitride such as silicon nitride. Other combinations of dielectric materials with workable etch selectivity between each other can also be used.

[0036] Each layer of the multi-layer stack 104 can be formed by a workable deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The thickness of each layer can be in a range from about 15 nm to about 90 nm. In some embodiments, the first dielectric layer 104A is formed to a different thickness than the second dielectric layer 104B. For example, the first dielectric layer 104A can be formed to have a first thickness Tl, and the second dielectric layer 104B can be formed to have a second thickness T2, where the second thickness T2 is greater than or less than the first thickness Tl by a difference in a range from about 0% to about 100%. The multi-layer stack 104 can have a total height Hl in a range from about 1000 nm to about 10000 nm.

[0037] As will be explained in detail below, Figures 4A-11B A process of patterning trenches in the multi-layer stack 104 and forming TFTs in the trenches is shown. Specifically, a multiple patterning process is used to form the TFTs. The multiple patterning process can be a double patterning process, a quadruple patterning process, etc. Figures 4A-11B A double patterning process is shown. In the double patterning process, a first etch process is used to pattern first trenches 106 (see Figure 4A and Figure 4B ) in the multi-layer stack 104, and form elements of a first subset of the TFTs in the first trenches 106. Then, a second etch process is used to pattern second trenches 120 (see Figure 8A and Figure 8B), and a second subset of TFTs is formed in the second trenches 120. Forming the TFTs by a multiple patterning process allows each patterning process to be performed at a low patterning density, which can help reduce defects while still allowing the memory array 52 to have sufficient memory cell density. Forming the TFTs by a multiple patterning process also allows each patterned portion of the multi-layer stack 104 to avoid having an overly large aspect ratio, thereby improving the structural stability of the resulting memory array.

[0038] In Figure 4A and Figure 4B , a first trench 106 is formed in the multi-layer stack 104. In the illustrated embodiment, the first trench 106 extends through the multi-layer stack 104 and exposes the substrate 102. In another embodiment, the first trench 106 extends through some, but not all, of the layers of the multi-layer stack 104. The first trench 106 can be formed using available photolithography and etching techniques, such as with an etching process that is selective to the multi-layer stack 104 (e.g., a process that etches the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B at a faster rate than the material of the substrate 102). The etching can be any available etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or combinations thereof. The etching can be anisotropic. In embodiments where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A is formed of silicon oxide, and the second dielectric layer 104B is formed of silicon nitride, the first trench 106 can be formed by dry etching using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (H2) or oxygen (O2) gas.

[0039] A portion of the multi-layer stack 104 is disposed between each pair of first trenches 106. Each portion of the multi-layer stack 104 can have a width Wl in a range from about 50 nm to about 500 nm, and have a height Hl as described with reference to Figure 3A and Figure 3B Furthermore, each portion of the multi-layer stack 104 is separated by a separation distance S l, which can be in a range from about 50 nm to about 200 nm. The aspect ratio (AR) of each portion of the multi-layer stack 104 is the ratio of the height Hl to the width of the narrowest feature of that portion of the multi-layer stack 104, which is the width Wl at that processing step. According to some embodiments, the aspect ratio of each portion of the multi-layer stack 104 is in a range from about 5 to about 15 when the first trench 106 is formed. Forming each portion of the multi-layer stack 104 with an aspect ratio less than about 5 can not allow the memory array 52 to have sufficient memory cell density. Forming each portion of the multi-layer stack 104 with an aspect ratio greater than about 15 can cause distortion or collapse of the multi-layer stack 104 in subsequent processing.

[0040] In Figure 5A andFigure 5B In particular, portions of the sidewalls of the second dielectric layer 104B exposed by the first trench 106 are recessed from the first sidewall recess 110. Although the sidewalls of the second dielectric layer 104B are shown as being straight, the sidewalls can be concave or convex. The first sidewall recess 110 can be formed by an available etching process, such as an etching process selective to the material of the second dielectric layer 104B (e.g., etching the second dielectric layer 104B at a faster rate than the material of the first dielectric layer 104A and the material of the substrate 102). The etching can be isotropic. In an embodiment where the substrate 102 is formed of silicon carbide, the first dielectric layer 104A is formed of silicon oxide, and the second dielectric layer 104B is formed of silicon nitride, the first trench 106 can be expanded by a wet etching using phosphoric acid (H3PO4). In another embodiment, a dry etching selective to the material of the second dielectric layer 104B can be used.

[0041] After formation, the first sidewall recess 110 has a depth D3 that extends beyond the sidewalls of the first dielectric layer 104A. After the first sidewall recess 110 reaches the desired depth D3, a timed etching process can be used to stop the etching of the first sidewall recess 110. For example, the first sidewall recess 110 can have a depth D3 ranging between about 10 nm to about 60 nm. Forming the first sidewall recess 110 reduces the width of the second dielectric layer 104B. In the above example, after etching, the second dielectric layer 104B can have a width W2 ranging between about 50 nm to about 450 nm. As described above, the aspect ratio (AR) of each portion of the multilayer stack 104 is the ratio of the height Hl to the width of the narrowest part of that portion of the multilayer stack 104, which width is the width W2 at that processing step. Thus, forming the first sidewall recess 110 increases the aspect ratio of each portion of the multilayer stack 104. According to some embodiments, after forming the first sidewall recess 110, the aspect ratio of each portion of the multilayer stack 104 remains within the above-described range, such as between about 5 to about 15. Thus, the advantages of such aspect ratios (as described above) can still be realized.

[0042] In Figure 6A and Figure 6B the first conductive features 112A are formed in the first sidewall recess 110, thus completing the process of replacing the first portions of the second dielectric layer 104B. The first conductive features 112A can each include one or more layers, such as an adhesion layer, a barrier layer, a diffusion layer, and a fill layer, among others. In some embodiments, each first conductive feature 112A includes an adhesion layer 112A G and a main layer 112A M . Each adhesion layer 112A G along the corresponding main layer 112AM three sides (e.g., a top side, a sidewall, and a bottom side) of the first dielectric layer 104A. The adhesion layer 112A G is composed of a first conductive material, such as a metal nitride, e.g., titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, etc. The main layer 112A M may be composed of a second conductive material, such as a metal, e.g., tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, and alloys thereof. The adhesion layer 112A G is a material that has good adhesion to the material of the first dielectric layer 104A, and the main layer 112A M is a material that has good adhesion to the material of the adhesion layer 112A G . In embodiments where the first dielectric layer 104A is formed of an oxide, such as silicon oxide, the adhesion layer 112A G may be formed of titanium nitride, and the main layer 112A M may be formed of tungsten. The adhesion layer 112A G and the main layer 112A M may each be formed by a viable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. An acceptable etching process, such as a dry etching process (e.g., reactive ion etching (RIE), neutral beam etching (NBE), etc.), a wet etching process, or a combination thereof, can be performed to remove excess material from the sidewalls of the first dielectric layer 104A and the top side of the substrate 102. The etching can be anisotropic. Each first conductive feature 112A Figure 3A and Figure 3B may have a similar total thickness T2 as the second dielectric layer 104B (as described above in connection with Figure 5A and Figure 5B ), and can have a similar total width as the depth D3 of the first sidewall recess 110 (as described above in connection with and

[0043] . Each adhesion layer 112A G may have a thickness T3 in a range between about 1 nm and about 10 nm, and each main layer 112A M may have a thickness T4 in a range between about 15 nm and about 35 nm, where the thickness T4 is greater than the thickness T3. Figure 7A Figure 7B In and

[0044] The ferroelectric strip 114A is a data storage strip composed of an acceptable ferroelectric material for storing digital values, where acceptable ferroelectric materials include, for example, hafnium zirconium oxide (HfZrO); zirconium oxide (ZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), etc.; undoped hafnium oxide (HfO); etc. The material of the ferroelectric strip 114A can be formed by an acceptable deposition process, such as ALD, CVD, physical vapor deposition (PVD), etc.

[0045] The semiconductor strip 116A is composed of an acceptable semiconductor material for providing a channel region of a TFT, where acceptable semiconductor materials include, for example, indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), polysilicon, amorphous silicon, etc. The material of the semiconductor strip 116A can be formed by an acceptable deposition process, such as ALD, CVD, PVD, etc.

[0046] The dielectric layer 118A is composed of a dielectric material. Possible dielectric materials include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc. The material of the dielectric layer 118A can be formed by an acceptable deposition process, such as ALD, CVD, flowable CVD (FCVD), etc.

[0047] The ferroelectric strip 114A, the semiconductor strip 116A, and the dielectric layer 118A can be formed by a combination of deposition, etching, and planarization. For example, a ferroelectric layer can be conformally deposited on the multilayer stack 104 and in the first trench 106 (e.g., on the sidewalls of the first conductive feature 112A and on the sidewalls of the first dielectric layer 104A). Then, a semiconductor layer can be conformally deposited on the ferroelectric layer. Then, the semiconductor layer can be anisotropically etched to remove the horizontal portions of the semiconductor layer, thus exposing the ferroelectric layer. Then, a dielectric layer can be conformally deposited on the remaining vertical portions of the semiconductor layer and on the exposed portions of the ferroelectric layer. Then, a planarization process is employed on the layers to remove excess material above the multilayer stack 104. The planarization process can be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The portions of the ferroelectric layer, the semiconductor layer, and the dielectric layer remaining in the first trench 106 form the ferroelectric strip 114A, the semiconductor strip 116A, and the dielectric 118A, respectively. The planarization process exposes the multilayer stack 104 such that the top surfaces of the multilayer stack 104, the ferroelectric strip 114A, the semiconductor strip 116A, and the dielectric layer 118A are coplanar (within process variation) after the planarization process.

[0048] In Figure 8A and Figure 8BIn some embodiments, the second trench 120 is formed in the multilayer stack 104. In the illustrated embodiment, the second trench 120 extends through the multilayer stack 104 and exposes the substrate 102. In another embodiment, the second trench 120 extends through some, but not all, of the layers of the multilayer stack. The second trench 120 can be formed using available photolithography and etching techniques, such as with an etching process selective to the multilayer stack 104 (e.g., a process that etches the dielectric material of the first dielectric layer 104A and the dielectric material of the second dielectric layer 104B at a faster rate than the material of the substrate 102). The etching can be any available etching process, and in some embodiments, can be similar to the etching described with reference to Figure 4A and Figure 4B the formation of the first trench 106.

[0049] A portion of the multilayer stack 104 is disposed between each second trench 120 and each first trench 106. Each portion of the multilayer stack 104 can have a width W3 in a range from about 50 nm to about 500 nm, and a height Hl as described with reference to Figure 3A and Figure 3B the formation of the first trench 106. Also, each portion of the multilayer stack 104 is separated by a separation distance S2, which can be in a range from about 50 nm to about 200 nm. The aspect ratio (AR) of each portion of the multilayer stack 104 is the ratio of the height Hl to the width of the narrowest part of that portion of the multilayer stack 104, which is the width W3 at that processing step. According to some embodiments, the aspect ratio of each portion of the multilayer stack 104 is between about 5 and about 15 when the second trench 120 is formed. Forming each portion of the multilayer stack 104 with an aspect ratio less than about 5 can not allow the memory array 52 to have a sufficient density of memory cells. Forming each portion of the multilayer stack 104 with an aspect ratio greater than about 15 can cause distortion or collapse of the multilayer stack 104 in subsequent processing.

[0050] In Figure 9A and Figure 9B the second trench 120 is extended to form a second sidewall recess 124. Specifically, the remaining portion of the second dielectric layer 104B is removed to form the second sidewall recess 124. Thus, the second sidewall recess 124 exposes a portion of the first conductive feature 112A, such as the adhesion layer 112A G The second sidewall recess 124 can be formed by an available etching process, such as an etching process selective to the material of the second dielectric layer 104B (e.g., a process that selectively etches the material of the second dielectric layer 104B at a faster rate than the material of the first dielectric layer 104A and the material of the substrate 102). The etching can be any available etching process, and in some embodiments, can be similar to the etching described with reference to Figure 5A and Figure 5BThe etch to form the first sidewall recess 110. After formation, the second sidewall recess 124 has a depth D4 that extends beyond the sidewall of the first dielectric layer 104A. In some embodiments, the depth D4 is similar to the depth D3 referenced above Figure 5A and Figure 5B In another embodiment, the depth D4 is different from (e.g., greater than or less than) the depth D3 referenced above Figure 5A and Figure 5B

[0051] In Figure 10A and Figure 10B the first conductive member 112A is formed in the second sidewall recess 124, thus completing the process of replacing the second portion of the second dielectric layer 104B. The second conductive member 112B can be formed of a material selected from the same group of candidate materials as the first conductive member 112A, and can be formed using a method selected from the same group of candidate methods as the method used to form the first conductive member 112A. The first conductive member 112A and the second conductive member 112B can be formed of the same material, or can include different materials. In some embodiments, each second conductive member 112B includes an adhesive layer 112B G and a main layer 112B M The adhesive layer 112B G and the main layer 112B M of the second conductive member 112B can have similar thicknesses to the adhesive layer 112A G and the main layer 112A M of the first conductive member 112A, respectively. In some embodiments, the adhesive layer 112A G and the adhesive layer 112B G are formed of similar materials, in which case the adhesive layer 112A G and the adhesive layer 112B G may fuse during formation such that there is no discernible interface between them. In another embodiment (discussed further below), the adhesive layer 112A G and the adhesive layer 112B G are formed of different materials, in which case the adhesive layer 112A G and the adhesive layer 112B G may not fuse during formation such that there is a discernible interface between them.

[0052] It should be understood that the adhesive layer 112A G , 112B G are optional, and their formation depends on the conductive material of the main layer 112A M , 112B M The main layer 112A M ​, 112B M Some of the conductive materials can have sufficient adhesion such that the adhesive layer 112A G , 112B G .

[0053] The first conductive component 112A and the second conductive component 112B are collectively referred to as word lines 112 of the memory array 52. Adjacent pairs of the first conductive component 112A and the second conductive component 112B are in physical contact with each other and are electrically coupled to each other. Thus, each pair of the first conductive component 112A and the second conductive component 112B functions as a single word line 112.

[0054] In Figure 11A and Figure 11B , a TFT thin film stack is formed in the second trench 120. Specifically, two ferroelectric strips 114B, one semiconductor strip 116B, and one dielectric layer 118B are formed in each second trench 120. In this embodiment, no other layers are formed in the second trench 120. In another embodiment (to be further explained below), additional layers are formed in the second trench 120.

[0055] The ferroelectric strip 114B can be composed of a material selected from the same group of candidate materials for the ferroelectric strip 114A, and can be formed using a method selected from the same group of candidate methods for forming the material of the ferroelectric strip 114A. The ferroelectric strip 114A and the ferroelectric strip 114B can be composed of the same material, or can include different materials. The ferroelectric strip 114A and the ferroelectric strip 114B are collectively referred to as ferroelectric strips 114. The thickness of the ferroelectric strips 114 can range between about 2 nm to about 20 nm.

[0056] The semiconductor strip 116B can be composed of a material selected from the same group of candidate materials for the semiconductor strip 116A, and can be formed using a method selected from the same group of candidate methods for forming the material of the semiconductor strip 116A. The semiconductor strip 116A and the semiconductor strip 116B can be composed of the same material, or can include different materials. The semiconductor strip 116A and the semiconductor strip 116B are collectively referred to as semiconductor strips 116. The thickness of the semiconductor strips 116 can range between about 2 nm to about 20 nm.

[0057] Dielectric layer 118B can be composed of a material selected from the same set of candidate materials as dielectric layer 118A, and can be formed using a method selected from the same set of candidate methods as the materials used to form dielectric layer 118A. Dielectric layer 118A and dielectric layer 118B can be composed of the same material, or can include different materials. Dielectric layer 118A and dielectric layer 118B are collectively referred to as dielectric layer 118. The thickness of dielectric layer 118 can range from about 42 nm to about 192 nm. The desired thickness of dielectric layer 118 depends on the thickness of ferroelectric strap 114 and semiconductor strap 116, as well as the separation distance S2 after formation of second trench 120.

[0058] Ferroelectric strap 114B, semiconductor strap 116B, and dielectric layer 118B can be formed by a combination of deposition, etching, and planarization. For example, ferroelectric strap 114B, semiconductor strap 116B, and dielectric layer 118B can be formed by a combination of steps similar to the steps used to form ferroelectric strap 114A, semiconductor strap 116A, and dielectric layer 118A.

[0059] In Figure 12A and Figure 12B dielectric plug 132 is formed through dielectric layer 118 and semiconductor strap 116. Dielectric plug 132 is an isolation pillar that will be disposed between adjacent TFTs, and will physically and electrically separate the adjacent TFTs. In the illustrated embodiment, dielectric plug 132 does not extend through ferroelectric strap 114. Different regions of ferroelectric strap 114 can be individually polarized, so ferroelectric strap 114 can be used to store a value even if adjacent regions are not physically and electrically separated. In another embodiment, dielectric plug 132 is also formed through ferroelectric strap 114. Dielectric plug 132 also extends through any remaining portions of first dielectric layer 104A and second dielectric layer 104B.

[0060] As one example of forming dielectric plug 132, openings for dielectric plug 132 can be formed through dielectric layer 118 and semiconductor strap 116. These openings can be formed using available photolithography and etching techniques. One or more dielectric materials are then formed in the openings. Available dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. The dielectric material can be formed by an available deposition process such as ALD, CVD, and the like. In some embodiments, silicon oxide or silicon nitride is deposited in the openings. A planarization process is then applied to the layers to remove excess dielectric material above topmost dielectric layer 104A. The planarization process can be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like. The remaining dielectric material forms dielectric plug 132 in the openings.

[0061] In Figure 13A and Figure 13B the bit lines 134 and the source lines 136 are formed through the dielectric layer 118. The bit lines 134 and the source lines 136 also extend through any remaining portions of the first dielectric layer 104A and the second dielectric layer 104B. The bit lines 134 and the source lines 136 serve as source / drain regions for the TFTs. The bit lines 134 and the source lines 136 are conductive columns formed in pairs, with each semiconductor strip 116 contacting a respective bit line 134 and a respective source line 136. Each TFT includes a bit line 134, a source line 136, a word line 112, and a region of the semiconductor strip 116 and the ferroelectric strip 114 that intersects the word line 112. Each dielectric plug 132 is disposed between a bit line 134 of one TFT and a source line 136 of another TFT. In other words, the bit lines 134 and the source lines 136 are disposed at opposite sides of each dielectric plug 132. Thus, each dielectric plug 132 physically and electrically separates adjacent TFTs.

[0062] As one example of forming the bit lines 134 and the source lines 136, openings for the bit lines 134 and the source lines 136 can be formed through the dielectric layer 118. The openings can be formed by using available photolithography and etching techniques. In particular, the openings are formed on opposite sides of the dielectric plugs 132. One or more conductive materials are then formed in the openings. Available conductive materials include metals such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, and the like. The conductive materials can be formed by available deposition processes such as ALD or CVD, available plating processes such as electroplating or electroless plating, and the like. In some embodiments, tungsten is deposited in the openings. A planarization process is then employed on the various layers to remove excess conductive material above the topmost dielectric layer 104A. The planarization process can be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like. The remaining conductive material forms the bit lines 134 and the source lines 136 in the openings. In some embodiments, each bit line 134 and / or source line 136 includes an adhesion layer and a main layer on the adhesion layer. Similar to the word lines 112, the use of an adhesion layer depends on the conductive material of the main layer.

[0063] In Figure 14A and Figure 14B the interconnect structure 140 is formed over the intermediate structure. For clarity of illustration, in Figure 14AOnly some components of the interconnect structure 140 are shown. The interconnect structure 140 can include, for example, a metallization pattern 142 in a dielectric material 144. The dielectric material 144 can include one or more dielectric layers, such as one or more low-k or extremely low-k dielectric materials. The metallization pattern 142 can be metal interconnects (e.g., metal lines and vias) formed in the one or more dielectric layers. The interconnect structure 140 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0064] The metallization pattern 142 of the interconnect structure 140 is electrically coupled to the bit lines 134 and the source lines 136. For example, the metallization pattern 142 includes bit line interconnects 142B (which are electrically coupled to the bit lines 134) and source line interconnects 142S (which are electrically coupled to the source lines 136). Adjacent bit lines 134 are connected to different bit line interconnects 142B, which helps to avoid shorting of adjacent bit lines 134 when a common word line 112 of the adjacent bit lines 134 is activated. Likewise, adjacent source lines 136 are connected to different source line interconnects 142S, which helps to avoid shorting of adjacent source lines 136 when a common word line 112 of the adjacent source lines 136 is activated.

[0065] In this embodiment, the bit lines 134 and the source lines 136 are formed in a staggered layout, in which adjacent bit lines 134 and adjacent source lines 136 are laterally offset from one another along a first direction Dl (see Figure 2B ). Thus, each word line 112 is disposed laterally between a dielectric plug 132 and a bit line 134 or between a dielectric plug 132 and a source line 136. The bit line interconnects 142B and the source line interconnects 142S each extend along a second direction D2 (see Figure 2B ), for example along columns of the memory array 52. The bit line interconnects 142B are connected to overlapping bit lines of the bit lines 134 along columns of the memory array 52. The source line interconnects 142S are connected to overlapping source lines of the source lines 136 along columns of the memory array 52. The laterally offset bit lines 134 and source lines 136 eliminate the need for lateral interconnects along columns of the memory array 52, thus allowing the bit line interconnects 142B and the source line interconnects 142S to be straight conductive segments that can be formed at a lowest level of the interconnect structure 140. In another embodiment (discussed below), the bit lines 134 and the source lines 136 are not formed in a staggered layout, but lateral interconnects are implemented in the interconnect structure 140.

[0066] Figure 15A and Figure 15B are various views of the memory array 52 provided in accordance with some other embodiments. Portions of the memory array 52 are shown. Some components are not shown for clarity, such as a stepped arrangement of word lines (see Figure 2B ). Figure 15Ais a three-dimensional view of the memory array 52, Figure 15B is a cross-sectional view showing a cross-section similar to the reference cross-section B-B in Figure 13A .

[0067] In this embodiment, the ferroelectric band 114 is omitted and replaced with a plurality of dielectric layers 150 as data storage bands. Specifically, a first dielectric layer 150A is formed on the substrate 102 and in contact with the sidewalls of the word lines 112. A second dielectric layer 150B is formed on the first dielectric layer 150A. A third dielectric layer 150C is formed on the second dielectric layer 150B. Each of the first, second, and third dielectric layers 150A, 150B, and 150C is formed of a dielectric material. Possible dielectric materials include oxides such as silicon oxide, nitrides such as silicon nitride, carbides such as silicon carbide, and the like, or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. In some embodiments, the first and third dielectric layers 150A and 150C are formed of a first dielectric material (e.g., an oxide such as silicon oxide), and the second dielectric layer 150B is formed of a second, different dielectric material (e.g., a nitride such as silicon nitride). The dielectric material can be formed by a possible deposition process such as ALD, CVD, and the like. For example, the first, second, and third dielectric layers 150A, 150B, and 150C can be formed by a combination of deposition, etching, and planarization in a manner similar to that described above with reference to the ferroelectric band 114. The dielectric layers 150 can allow the TFT to function as a floating gate transistor, thereby forming a NOR flash memory array.

[0068] Figure 16A and Figure 16B are various views of the memory array 52 according to some other embodiments. Portions of the memory array 52 are shown. For clarity of illustration, some components are not shown, such as the stepped arrangement of word lines (see Figure 2B ). Figure 16A is a three-dimensional view of the memory array 52, Figure 16B is a cross-sectional view showing a cross-section similar to the reference cross-section B-B in Figure 13A .

[0069] In this embodiment, a conductive band 160 is formed between the ferroelectric band 114 and the semiconductor band 116. The formation of the conductive band 160 helps to avoid or reduce the formation of interlayer oxides on the ferroelectric band 114 during the formation of the semiconductor band 116. Avoiding or reducing the formation of interlayer oxides can increase the useful lifetime of the memory array 52.

[0070] The conductive strips 160 can be formed of a metal such as ruthenium, tungsten, titanium nitride, tantalum nitride, molybdenum, etc. The conductive material of the conductive strips 160 can be formed by a viable deposition process such as ALD or CVD, a viable plating process such as electroplating or electroless plating, etc. The thickness of the conductive strips 160 can be in a range from about 1 nm to about 20 nm. The conductive strips 160 can be formed in a similar manner as the semiconductor strips 116 and can be formed during the formation of the semiconductor strips 116. The dielectric plugs 132 can (or can not) be formed through the conductive strips 160.

[0071] Figure 17A and Figure 17B are various views of the memory array 52 according to some other embodiments. Portions of the memory array 52 are shown. Some components are not shown for clarity of illustration, such as the stepped arrangement of word lines (see Figure 2B ). Figure 17A is a three-dimensional view of the memory array 52, Figure 17B is a cross-sectional view showing a cross-section similar to the reference cross-section B-B in Figure 13A .

[0072] In this embodiment, the adhesion layer 112A G and the adhesion layer 112B G are composed of different materials. For example, the adhesion layer 112A G may be formed of a first adhesion material (e.g., titanium nitride) and the adhesion layer 112B G may be formed of a second adhesion material (e.g., tantalum nitride). As such, the adhesion layer 112A G and the adhesion layer 112B G may not fuse during formation such that they are independent and different from one another. In some embodiments, the adhesion layer 112B G may be composed of a material having a lower resistivity than the adhesion layer 112A G , thereby improving the performance of the word line 112.

[0073] Figure 18A and Figure 18B are various views of the memory array 52 according to some other embodiments. Portions of the memory array 52 are shown. Some components are not shown for clarity of illustration, such as the stepped arrangement of word lines (see Figure 2B ). Figure 18A is a three-dimensional view of the memory array 52, Figure 18B is a cross-sectional view shown along the reference cross-section B-B in Figure 18A .

[0074] In this embodiment, the metallization pattern 142 of the interconnect structure 140 includes only source line interconnects 142S. Another interconnect structure 170 is formed on the side of the substrate 102 opposite to the interconnect structure 140. The interconnect structure 170 can be formed in a similar manner to the interconnect structure 140. The interconnect structure 170 may include, for example, a metallization pattern 172 in a dielectric material 174. Conductive vias 180 may be formed through the substrate 102 and the ferroelectric band 114 to electrically couple the metallization pattern 172 to bit lines 134 and / or source lines 136. For example, the metallization pattern 172 includes bit line interconnects 172B (which are electrically coupled to the source line 136 through the conductive via 180).

[0075] Furthermore, in this embodiment, the bit lines 134 and source lines 136 are formed in an interleaved arrangement, so adjacent bit lines 134 and adjacent source lines 136 are arranged along the first direction D1 (see...). Figure 2B The word lines 112 are horizontally aligned with each other. Therefore, each word line 112 is horizontally positioned between a pair of bit lines 134 or a pair of source lines 136. Because the bit lines 134 and source lines 136 are not formed in an interleaved layout, the horizontal interconnections to subsets of source line interconnects 142S are implemented in interconnect structure 140, while the horizontal interconnections to subsets of bit line interconnects 172B are implemented in interconnect structure 170. For example, source line interconnects 142S are straight conductive segments formed at intermediate levels of interconnect structure 140. The horizontal interconnects 146 between the first subset of source line interconnects 142S and the first subset of source lines 136 are formed at lower levels of interconnect structure 140 compared to source line interconnects 142S. The straight interconnects 148 between the second subset of source line interconnects 142S and the second subset of source lines 136 are formed at lower levels of interconnect structure 140 compared to source line interconnects 142S. Similarly, bit line interconnect 172B is a straight conductive segment formed at an intermediate level of interconnect structure 170. Lateral interconnect 176 between a first subset of bit line interconnect 172B and a first subset of bit lines 134 is formed at a lower level of interconnect structure 170 compared to bit line interconnect 172B. Straight interconnect 178 between a second subset of bit line interconnect 172B and a second subset of bit lines 134 is formed at a lower level of interconnect structure 140 compared to bit line interconnect 172B.

[0076] It should be noted that in other embodiments, the layout of interconnect structures 140 and 170 may be flipped. For example, the metallization pattern 142 of interconnect structure 140 may include bit line interconnects, and the metallization pattern 172 of interconnect structure 170 may include source line interconnects.

[0077] Figures 19A-21Bare various views of intermediate stages of manufacturing the memory array 52 according to some other embodiments. Portions of the memory array 52 are shown. For clarity of illustration, some components are not shown, such as the stepped arrangement of word lines (see Figure 2B ). Figure 19A and Figure 20A are three-dimensional views of the memory array 52. Figure 19B and Figure 20B are cross-sectional views shown along the reference section B-B in Figure 20A . Figure 21A and Figure 21B are top views of portions of the memory array 52.

[0078] In Figure 19A and Figure 19B , structures similar to those described above in connection with Figure 11A and Figure 11B are implemented, however, in this processing step, the ferroelectric band 114, the semiconductor band 116, and the dielectric layer 118 are not formed. Instead, the first trench 106 (see Figure 4A and Figure 4B ) and the second trench 120 (see Figure 8A and Figure 8B ) are each filled with a dielectric layer 192. The dielectric layer 192 is formed of a dielectric material. Possible dielectric materials include oxides such as silicon oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like. The dielectric material can be formed by a possible deposition process such as ALD, CVD, and the like. In some embodiments, silicon oxide is deposited in the first trench 106 and the second trench 120. A planarization process can be employed on each layer to remove excess dielectric material above the topmost dielectric layer 104A. The planarization process can be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like. For example, a first planarization process can be performed after filling the first trench 106 to form the dielectric layer 192, and a second planarization process can be performed after filling the second trench 120 to form the dielectric layer 192.

[0079] In Figure 20A and Figure 20B , TFT thin film stacks are formed that extend through the dielectric layer 192. The TFT thin film stacks each include the ferroelectric band 114, the semiconductor band 116, and the dielectric layer 118. Then, the bit lines 134 and the source lines 136 are formed at least through the dielectric layer 118.

[0080] The ferroelectric strips 114, the semiconductor strips 116, and the dielectric layer 118 can be formed by a combination of deposition, etching, and planarization. For example, openings can be formed through the dielectric layer 192. The openings can be formed by using available photolithography and etching techniques. The ferroelectric layer can be deposited conformally in the openings through the dielectric layer 192. Then, the semiconductor layer can be deposited conformally on the ferroelectric layer. Then, the semiconductor layer can be anisotropically etched to remove the horizontal portions of the semiconductor layer, thus exposing the ferroelectric layer. Then, the dielectric layer can be deposited conformally on the remaining vertical portions of the semiconductor layer and on the exposed portions of the ferroelectric layer. Then, a planarization process is applied to the layers to remove excess material above the topmost dielectric layer 104A. The planarization process can be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The portions of the ferroelectric layer, the semiconductor layer, and the dielectric layer remaining in the openings through the dielectric layer 192 form the ferroelectric strips 114, the semiconductor strips 116, and the dielectric layer 118, respectively. The planarization process exposes the topmost dielectric layer 104A such that the top surfaces of the topmost dielectric layer 104A, the ferroelectric strips 114, the semiconductor strips 116, and the dielectric layer 118 are coplanar (within process variations) after the planarization process.

[0081] As an example of forming the bit lines 134 and the source lines 136, openings for the bit lines 134 and openings for the source lines 136 can be formed through the dielectric layer 118, and optionally also through the ferroelectric strips 114 and the semiconductor strips 116. The openings can be formed by using available photolithography and etching techniques. In particular, the openings are formed such that they are opposite to the side surfaces of the remaining portions of the dielectric layer 118. In some embodiments, the openings extend only through the dielectric layer 118, such that the bit lines 134 and the source lines 136 replace only portions of the dielectric layer 118 (as shown in Figure 20A and Figure 21A In some embodiments, the openings also extend through the ferroelectric strips 114 and the semiconductor strips 116, such that the bit lines 134 and the source lines 136 also replace portions of the ferroelectric strips 114 and the semiconductor strips 116 (as shown in Figure 21BThe one or more conductive materials can be formed in the openings by a viable deposition process, such as ALD or CVD, a viable plating process, such as electroplating or electroless plating, etc. In some embodiments, tungsten is deposited in the openings. A planarization process is then employed on the layers to remove excess conductive material above the topmost dielectric layer 104A. The planarization process can be chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The remaining conductive material forms bit lines 134 and source lines 136 in the openings. Interconnects can then be formed above (or below) the bit lines 134 and above (or below) the source lines 136 using similar techniques as described above, such that the bit lines 134 and the source lines 136 can be coupled to bit line interconnects and source line interconnects, respectively.

[0082] In the above-described combination Figures 3A-21B In the above-described combination

[0083] Figure 22 is a cross-sectional view of a semiconductor device 200 provided in some embodiments. Figure 22 is a simplified view and some components are omitted for clarity of illustration. The semiconductor device 200 includes a logic region 200L and a memory region 200M. A memory device (e.g., a flash memory) is formed in the memory region 200M and a logic device (e.g., a logic circuit) is formed in the logic region 200L. For example, a memory array 52 (see Figure 1 ) can be formed in the memory region 200M and row decoders 54 and column decoders 56 (see Figure 1 ) can be formed in the logic region 200L. The memory region 200M can be disposed at an edge of the logic region 200L or the logic region 200L can surround the memory region 200M.

[0084] The logic regions 200L and the memory regions 200M are formed over the same semiconductor substrate 202. The semiconductor substrate 202 can be doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 202 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Additionally, other substrates can be used, such as multilayer or graded substrates.

[0085] The devices 204 are formed at an active surface of the semiconductor substrate 202. The devices 204 can be active or passive devices. For example, the electrical components can be transistors / diodes, capacitors, resistors, etc. formed by any suitable formation method. The devices 204 are interconnected to form memory devices and logic devices of the semiconductor device 200.

[0086] One or more interlayer dielectric (ILD) layers 206 are formed on the semiconductor substrate 202, and conductive components, such as contact plugs 208, are formed that are electrically connected to the devices 204. The ILD layers 206 can be composed of any suitable dielectric material, such as nitride (e.g., silicon nitride); oxide (such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.); etc. The ILD layers can be formed by any acceptable deposition process, such as spin-on, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. or combinations thereof. The conductive components in the ILD layers can be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.) etc. or combinations thereof.

[0087] An interconnect structure 210 is formed over the semiconductor substrate 202. The interconnect structure 210 is interconnected with the devices 204 to form integrated circuits in each of the logic regions 200L and the memory regions 200M. The interconnect structure 210 includes a plurality of metallization layers M1-M5. Although five metallization layers are shown, it should be understood that the interconnect structure can include more or fewer metallization layers. Each of the metallization layers M1-M5 includes a metallization pattern in a dielectric layer. The metallization patterns are electrically coupled to the devices 204 of the semiconductor substrate 202 and include metal lines L1-L5 and metal vias V1-V5 formed in one or more intermetal dielectric (IMD) layers, respectively. The interconnect structure 210 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. In some embodiments, the contact plugs 208 are also part of the metallization patterns, such as part of the bottommost layer of the metal vias V1

[0088] The memory array 52 is formed in the interconnect structure 210. The memory array 52 can be formed in any of the metallization layers M1-M5 and is illustrated as being formed in the middle metallization layer M4, but can also be formed in the bottom metallization layer M1 or the upper metallization layer M5. The memory array 52 is electrically connected to the device 204. For example, a metallization layer (e.g., the metallization layer M5) overlying the memory array 52 can include source line interconnects and bit line interconnects of the TFTs and the device 204 that are electrically connected to the memory array 52.

[0089] In some embodiments, the interconnect structure 210 can be formed by first forming layers (e.g., the metallization layers M1-M3) underlying the memory array 52. Then, the memory array 52 can be formed on the metallization layer M3, the IMD of which serves as the substrate 102 (see FIG. 3). After the memory array 52 is formed, the remaining portion of the metallization layer M4 can be formed by, for example, depositing and planarizing the IMD of the metallization layer M4, and then forming the metal lines M4 and the metal vias M4. Then, layers (e.g., the metallization layer M5) overlying the memory array 52 can be formed.

[0090] Embodiments can achieve advantages. Forming the word lines 112 by a multiple patterning process allows the multi-layer stack 104 to be patterned with different patterns at a low pattern density. Thus, the word lines 112 can be formed in portions (e.g., the first conductive portions 112A and the second conductive portions 112B), and distortion or folding of the multi-layer stack 104 can be avoided during formation of each portion of the word lines 112.

[0091] In an embodiment, a method includes etching a first trench in a multi-layer stack, the multi-layer stack including alternating dielectric layers and sacrificial layers; replacing a first portion of the sacrificial layers exposed by the first trench with a first conductive portion; forming a first data storage strip and a first semiconductor strip in the first trench; after forming the first data storage strip and the first semiconductor strip, etching a second trench in the multi-layer stack; replacing a second portion of the sacrificial layers exposed by the second trench with a second conductive portion; and forming a second data storage strip and a second semiconductor strip in the second trench.

[0092] In an embodiment, the method further includes depositing a first dielectric layer in the first trench, the first semiconductor strip disposed between the first dielectric layer and the first data storage strip; and depositing a second dielectric layer in the second trench, the second semiconductor strip disposed between the second dielectric layer and the second data storage strip. In an embodiment, the method further includes forming a first dielectric plug and a second dielectric plug, the first dielectric plug extending through the first dielectric layer and the first semiconductor strip, the second dielectric plug extending through the second dielectric layer and the second semiconductor strip; forming a first bit line and a second bit line, the first bit line extending through the first dielectric layer, the second bit line extending through the second dielectric layer; and forming a first source line and a second source line, the first source line extending through the first dielectric layer, the second source line extending through the second dielectric layer, the first dielectric plug disposed between the first source line and the first bit line, the second dielectric plug disposed between the second source line and the second bit line. In some embodiments of the method, the first data storage strip contacts each of the first conductive features, the second data storage strip contacts each of the second conductive features. In an embodiment, the method further includes depositing a first conductive strip in the first trench, the first data storage strip disposed between the first conductive strip and each of the first conductive features; and depositing a second conductive strip in the second trench, the second data storage strip disposed between the second conductive strip and each of the second conductive features. In some embodiments of the method, the first data storage strip is a first ferroelectric strip, the second data storage strip is a second ferroelectric strip. In some embodiments of the method, the first data storage strip is a first plurality of dielectric layers, the second data storage strip is a second plurality of dielectric layers. In some embodiments of the method, the first trench is one of a plurality of first trenches etched in a multilayer stack, portions of the multilayer stack between the first trenches have a first aspect ratio, each of the first aspect ratios ranges between 5 to 15. In some embodiments of the method, replacing the first portion of the sacrificial layer with the first conductive features includes removing the first portion of the sacrificial layer to form first sidewall recesses in the first trench; depositing first adhesive layers in the first sidewall recesses; and depositing first main layers in the first sidewall recesses, each of the first adhesive layers extending along three sides of a respective one of the first main layers. In some embodiments of the method, replacing the second portion of the sacrificial layer with the second conductive features includes removing the second portion of the sacrificial layer to form second sidewall recesses in the second trench; depositing second adhesive layers in the second sidewall recesses; and depositing second main layers in the second sidewall recesses, each of the second adhesive layers extending along three sides of a respective one of the second main layers. In some embodiments of the method, the first adhesive layers and the second adhesive layers are formed of the same conductive material, the first adhesive layers bonded together with the second adhesive layers. In some embodiments of the method, the first adhesive and the second adhesive layers are formed of different conductive materials, and the first adhesive layers are separated from the second adhesive layers, both different.

[0093] In an embodiment, a device includes a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first adhesion layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage band disposed between the first bit line and the word line, the data storage band extending along a second sidewall of the word line.

[0094] In some embodiments of the device, the word line further includes a second main layer, the first adhesion layer extending along a bottom surface, a top surface, and a sidewall of the second main layer. In some embodiments of the device, the word line further includes a second main layer and a second adhesion layer extending along a bottom surface, a top surface, and a sidewall of the second main layer, the second adhesion layer and the first adhesion layer using different conductive materials. In some embodiments of the device, the first adhesion layer has a thickness ranging between 1 nm and 10 nm, the first main layer has a thickness ranging between 15 nm and 35 nm, the word line has a total thickness ranging between 15 nm and 70 nm, and the word line has a total width ranging between 10 nm and 60 nm. In some embodiments, the device further includes a dielectric plug extending through the second dielectric layer and the first dielectric layer, the word line disposed between the dielectric plug and the first bit line; and an interconnect structure over the second dielectric layer, the interconnect structure including a bit line interconnect extending over the dielectric plug and the first bit line, the bit line interconnect physically and electrically coupled to the first bit line. In some embodiments, the device further includes a second bit line extending through the second dielectric layer and the first dielectric layer, the word line disposed between the first bit line and the second bit line; and an interconnect structure over the second dielectric layer, the interconnect structure including a first bit line interconnect extending over the first bit line and the second bit line, a straight interconnect connecting the first bit line interconnect to the first bit line, a second bit line interconnect laterally offset from the first bit line and the second bit line, and a lateral interconnect connecting the second bit line interconnect to the second bit line.

[0095] In an embodiment, a device includes a first dielectric layer over a substrate; a second dielectric layer over the first dielectric layer; a word line between the first dielectric layer and the second dielectric layer, the word line including a first main layer, a second main layer, and a first adhesion layer laterally disposed between the first main layer and the second main layer; a first data storage band contacting sidewalls of the first main layer, the first dielectric layer, and the second dielectric layer; and a second data storage band contacting sidewalls of the second main layer, the first dielectric layer, and the second dielectric layer.

[0096] In some embodiments of the device, the word line further includes a second adhesion layer laterally disposed between the first adhesion layer and the second main layer, the second adhesion layer and the first adhesion layer including different conductive materials.

[0097] The foregoing summary of some embodiments has been presented with sufficient particularity by way of exemplification and not limitation, and other embodiments can be realized and achieved by making a few of the appropriate substitutions and modifications to the embodiments described in detail above. It is therefore intended that the scope of the application be determined by the following claims rather than by the embodiments presented above, which should be regarded as merely illustrative in nature.

Claims

1. A method of forming an array of memory devices, comprising: etching a first trench in a multi-layer stack, the multi-layer stack comprising alternating dielectric layers and sacrificial layers; replacing a first portion of the sacrificial layers exposed by the first trench with first conductive components; forming first data storage strips and first semiconductor strips in the first trench; etching a second trench in the multi-layer stack after forming the first data storage strips and the first semiconductor strips; replacing a second portion of the sacrificial layers exposed by the second trench with second conductive components; and forming second data storage strips and second semiconductor strips in the second trench, wherein adjacent ones of the first conductive components and the second conductive components are in physical contact and electrically coupled, and adjacent ones of the first conductive components and the second conductive components form a common word line for storage cells in a same row of the array of memory devices.

2. The method of claim 1, further comprising: depositing a first dielectric layer in the first trench, the first semiconductor strips disposed between the first dielectric layer and the first data storage strips; and depositing a second dielectric layer in the second trench, the second semiconductor strips disposed between the second dielectric layer and the second data storage strips.

3. The method of claim 2, further comprising: forming first and second dielectric plugs, the first dielectric plug extending through the first dielectric layer and the first semiconductor strips, the second dielectric plug extending through the second dielectric layer and the second semiconductor strips; forming first and second bit lines, the first bit line extending through the first dielectric layer, the second bit line extending through the second dielectric layer; and forming first and second source lines, the first source line extending through the first dielectric layer, the second source line extending through the second dielectric layer, the first dielectric plug disposed between the first source line and the first bit line, the second dielectric plug disposed between the second source line and the second bit line. The first data storage strips contact each of the first conductive components, and the second data storage strips contact each of the second conductive components.

5. The method of claim 2, further comprising: depositing first conductive strips in the first trench, the first data storage strips disposed between the first conductive strips and each of the first conductive components; and 4. The method of claim 2, wherein, depositing second conductive strips in the second trench, the second data storage strips disposed between the second conductive strips and each of the second conductive components. The first data storage strips are first ferroelectric strips, and the second data storage strips are second ferroelectric strips. The first data storage strips are a first plurality of dielectric layers, and the second data storage strips are a second plurality of dielectric layers. The first trench is one of a plurality of first trenches etched in the multi-layer stack, portions of the multi-layer stack between the first trenches having a first aspect ratio, each of the first aspect ratios ranging between 5 and 15. Replacing the first portion of the sacrificial layers with the first conductive components comprises:

6. The method of claim 1, wherein, ​ 7. The method of claim 1, wherein, ​ 8. The method of claim 1, wherein, ​ 9. The method of claim 1, wherein, ​ removing the first portion of the sacrificial layer to form a first sidewall recess in the first trench; depositing a first adhesive layer in the first sidewall recess; and depositing a first main layer in the first sidewall recess, each of the first adhesive layers extending along three sides of a respective one of the first main layers.

10. The method of claim 9, wherein, replacing the second portion of the sacrificial layer with the second conductive component includes: removing the second portion of the sacrificial layer to form a second sidewall recess in the second trench; depositing a second adhesive layer in the second sidewall recess; and depositing a second main layer in the second sidewall recess, each of the second adhesive layers extending along three sides of a respective one of the second main layers.

11. The method of claim 10, wherein, the first adhesive layer and the second adhesive layer are formed of the same conductive material, the first adhesive layer being fused together with the second adhesive layer.

12. The method of claim 10, wherein, the first adhesive and the second adhesive layers are formed of different conductive materials, and the first adhesive layer is separate and distinct from the second adhesive.

13. An array of memory devices, comprising: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer, a first adhesive layer, a second adhesive layer, and a second main layer, the first adhesive layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer, the first adhesive layer being between the first main layer and the second main layer; a second dielectric layer over the word line, the second dielectric layer extending continuously from over the first main layer to over the second main layer; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line, a dielectric plug extending through the second dielectric layer and the first dielectric layer, the word line being disposed between the dielectric plug and the first bit line, wherein a first conductive component includes the first main layer and the first adhesive layer, and a second conductive component includes the second main layer and the second adhesive layer, wherein adjacent ones of the first conductive component and the second conductive component are in physical contact and electrically coupled, and adjacent ones of the first conductive component and the second conductive component form a common word line for memory cells in a same row of the array of memory devices. the first adhesive layer extends along a bottom surface, a top surface, and a sidewall of the second main layer.

14. The memory device of claim 13, wherein, the second adhesive layer extends along a bottom surface, a top surface, and a sidewall of the second main layer, the second adhesive layer and the first adhesive layer including different conductive materials.

15. The memory device of claim 13, wherein, a thickness of the first adhesive layer is in a range of 1 nm to 10 nm, a thickness of the first main layer is in a range of 15 nm to 35 nm, a total thickness of the word line is in a range of 15 nm to 70 nm, and a total width of the word line is in a range of 10 nm to 60 nm.

16. The memory device of claim 13, wherein, 17. The memory device of claim 13, further comprising: ​ an interconnect structure over the second dielectric layer, the interconnect structure including a bit line interconnect extending over the dielectric plug and the first bit line, the bit line interconnect electrically coupled to the first bit line.

18. The memory device of claim 13, further comprising: a second bit line extending through the second dielectric layer and the first dielectric layer, the word line disposed between the first bit line and the second bit line; and an interconnect structure over the second dielectric layer, the interconnect structure including: a first bit line interconnect extending over the first bit line and the second bit line; a straight interconnect connecting the first bit line interconnect to the first bit line; a second bit line interconnect laterally offset from the first bit line and the second bit line; and a lateral interconnect connecting the second bit line interconnect to the second bit line.

19. An array of memory devices, comprising: a first dielectric layer over a substrate; a second dielectric layer over the first dielectric layer; a word line between the first dielectric layer and the second dielectric layer, the word line including a first main layer, a second main layer, and a first adhesive layer and a second adhesive layer, the first adhesive layer laterally disposed between the first main layer and the second main layer; a first bit line extending through the second dielectric layer and the first dielectric layer; a first data storage strap contacting sidewalls of the first main layer, the first dielectric layer, and the second dielectric layer; a second data storage strap contacting sidewalls of the second main layer, the first dielectric layer, and the second dielectric layer, wherein a first conductive component includes the first main layer and the first adhesive layer, and a second conductive component includes the second main layer and the second adhesive layer, the first dielectric layer continuously extending from the first data storage strap to the second data storage strap, wherein adjacent ones of the first conductive component and the second conductive component are in physical contact and electrically coupled, and adjacent ones of the first conductive component and the second conductive component form a common word line for memory cells in a same row of the array of memory devices.

20. The memory device of claim 19, wherein, the second adhesive layer laterally disposed between the first adhesive layer and the second main layer, the second adhesive layer and the first adhesive layer including different conductive materials.

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