Memory device and method of forming the same

Abstract

A method of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive bars. The resulting structure includes a two-dimensional array of horizontal conductive bars. Memory cells can be distributed along the length of each bar to provide a 3D array. The conductive bars, together with additional conductive structures that can have a vertical or horizontal orientation, allow individual addressing of the memory cells. Forming the conductive layers of carbon-based material facilitates etching the trenches to a high aspect ratio. Thus, forming the conductive layers of carbon-based material enables the memory array to have more layers or a higher area density. Embodiments of the present invention also disclose memory devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory devices and methods of forming the same. Background Art

[0002] Two-dimensional (2D) memory arrays are common in electronic devices and may include, for example, NOR flash memory arrays, NAND flash memory arrays, dynamic random access memory (DRAM) arrays, etc. However, 2D memory arrays have reached the scaling limit and, thus, the limit of memory density. Three-dimensional (3D) memory arrays are promising candidates for increasing memory density and may include, for example, 3D NAND flash memory arrays, 3D NOR flash memory arrays, etc. Summary of the Invention

[0003] According to one aspect of embodiments of the present invention, there is provided a memory device including: a three-dimensional memory cell array disposed between two adjacent metal interconnect layers in a metal interconnect structure, each of the memory cells including a source side, a drain side, a channel extending between the source side and the drain side, a gate, and a data storage film between the gate and the channel; and an array of stacks, each stack including a plurality of conductive bars and a plurality of dielectric bars, wherein the conductive bars extend horizontally to provide gates for a plurality of the memory cells; wherein the conductive bars include a carbon-based conductive material.

[0004] According to another aspect of embodiments of the present invention, there is provided a memory device including: a plurality of stacks, each stack including two or more vertically stacked gate bars separated by dielectric bars; a source line and a drain line located between the stacks and extending along the stacking direction of the stacks; and memory cells each including a channel extending between one of the source lines and one of the drain lines and a data storage structure located between the channel and one of the two or more vertically stacked gate bars; wherein the gate bars include graphite.

[0005] According to yet another aspect of embodiments of the present invention, there is provided a method of forming a memory device, the method including: forming a first stack including a plurality of conductive layers and a plurality of dielectric layers, wherein the conductive layers include a carbon-based material; etching trenches in the first stack to form a plurality of second stacks; and depositing a data storage film in the trenches. Brief Description of the Drawings

[0006] Aspects of the present invention are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0007] Figure 1AA perspective view of a first 3D memory array, which is a 3D memory array according to some aspects of the present teachings.

[0008] Figure 1B A vertical cross-section of the 3D memory array shown in plane B Figure 1A is shown.

[0009] Figure 1C A horizontal cross-section of the 3D memory array shown in plane C Figure 1A is shown.

[0010] Figure 2 is a top view of an integrated circuit showing a 3D memory array having Figure 1A is shown.

[0011] Figure 3 A cross-section of an integrated circuit showing a 3D memory array including Figure 1A is shown.

[0012] Figure 4 An equivalent circuit diagram of the 3D memory array providing Figure 1A is shown.

[0013] Figures 5A to 5C Vertical and horizontal cross-sections of a second 3D memory array, which is a 3D memory array according to some other aspects of the present teachings, are shown.

[0014] Figures 6A to 6B Vertical and horizontal cross-sections of a third 3D memory array, which is a 3D memory array according to some other aspects of the present teachings, are shown.

[0015] Figures 7A to 7B Vertical and horizontal cross-sections of a fourth 3D memory array, which is a 3D memory array according to some other aspects of the present teachings, are shown.

[0016] Figure 8A And Figures 8B to 14A And Figure 14B Are a series of paired top views and cross-sectional views that illustrate a method of forming a device including a 3D memory array having a first 3D memory array according to the present teachings.

[0017] Figure 15A And Figures 15B to 21A And Figure 21B Are a series of paired top views and cross-sectional views that illustrate a method of forming a device including a 3D memory array having a second 3D memory array according to the present teachings.

[0018] Figures 22 to 29Provide a cross-sectional view showing an alternative method of forming a dielectric / gate stack in accordance with some aspects of the present teachings.

[0019] Figure 30A and Figures 30B to 35A and Figure 35B are a series of paired top plan views and cross-sectional views that illustrate a method of forming a device having a 3D memory array including components having a fourth 3D memory array in accordance with the present teachings.

[0020] Figures 36 to 39 Provide flowcharts that illustrate various methods for forming a 3D memory array in accordance with the present teachings. Detailed Description

[0021] The present invention provides many different embodiments or examples for implementing different components of the present invention. Specific examples of elements and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component is in direct contact with the second component, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for purposes of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Moreover, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used therein may be interpreted accordingly.

[0023] A method of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers separated by dielectric layers. Etching trenches in the stack divide the conductive layers into conductive bars. The resulting structure includes a two-dimensional array of horizontal conductive bars. Memory cells may be distributed along the length of each bar to provide a 3D array. The conductive bars, together with additional conductive structures that may have a vertical or horizontal orientation, allow for individual addressing of the memory cells.

[0024] According to the present teachings, the conductive layer is formed of graphite or a similar carbon-based material. When the conductive layer is graphite, it is easier to etch trenches to a high aspect ratio compared to when the conductive layer is formed of a different conductive material such as a metal. Thus, forming the conductive layer of graphite enables the memory array to have more layers or a higher area density. The resulting 3-D memory array has conductive graphite bars.

[0025] Some aspects of the present teachings relate to a three-dimensional array of a type of memory cell, where each of the memory cells includes a source side, a drain side, a channel extending between the source side and the drain side, a control gate, and a data storage membrane between the control gate and the channel. Within the memory array are arrays of stacks, each stack having conductive bars separated by dielectric bars. The conductive bars extend horizontally for connection to a plurality of the memory cells. According to the present teachings, the conductive bars are formed of a carbon-based material. In some embodiments, the carbon-based material includes graphene. In some embodiments, the graphene is in the form of nanoribbons. In some embodiments, the graphene is boron-doped. In some embodiments, the carbon-based material includes nanocrystalline graphite.

[0026] The memory can have any suitable architecture. The architecture can be vertical, horizontal, crossbar, etc. or any combination thereof. In some embodiments, the conductive bars are horizontal gate bars. In some embodiments, additional conductors extend vertically through the array. These conductors can be formed of a metal.

[0027] In some embodiments, recesses are formed in the sides of the stack adjacent to the conductive bars. The data storage membranes can be disposed in these recesses. Forming the data storage membranes within these recesses helps to make the data storage membranes discontinuous between vertically adjacent memory cells in the array. The etch sensitivity of the carbon-based material facilitates the formation of these recesses.

[0028] Some aspects of the present teachings relate to a memory device having a plurality of stacks, each stack including two or more vertically stacked gate bars separated by dielectric bars. Source lines and drain lines are located between the stacks and extend along the stacking direction of the stacks. Memory cells in the array each have a channel extending between one of the source lines and one of the drain lines and a data storage structure located between the channel and one of the gate bars. The gate bars include graphite. In some embodiments, the graphite is graphene.

[0029] Some aspects of the present teachings relate to a method of forming a memory device. The method includes forming a wide stack including a plurality of conductive layers and a plurality of dielectric layers; etching trenches in the wide stack to form a plurality of narrow stacks; and depositing data storage membranes in the trenches. The conductive layers are a carbon-based material, which aids in the etching process.

[0030] Some aspects of the present teachings relate to a method of forming a memory device. The method includes forming a wide stack including a plurality of dummy layers and a plurality of dielectric layers. A first set of trenches is formed in the stack. A first dummy etch is performed in the first set of trenches. The first dummy etch may remove approximately half of each dummy layer. A first deposition process is performed to replace a portion of the dummy layer removed by the first dummy etch with a carbon-based material. In some embodiments, the carbon-based material includes graphene sheets. A second set of trenches is formed in the stack. A second dummy etch is performed in the second set of trenches. The second dummy etch may remove the remaining portion of the dummy layer. A second deposition process is performed to replace a portion of the dummy layer removed by the second dummy etch with a carbon-based material. By this method, a carbon-based material for conductive bars can be deposited using as few as two deposition steps, regardless of the number of conductive bars in each stack.

[0031] Figure 1A A perspective view of a first 3D memory array 100A of memory cells 101A according to some aspects of the present teachings is shown. Figure 1B Along Figure 1A a cross-section of the first 3D memory array 100A is shown in plane B. Figure 1C A cross-section along Figure 1A is shown in plane C. Figure 1B And Figure 1C at the intersection of planes B and C along line BC in. Plane B is vertical. Plane C is horizontal. [[ID=***]]

[0032] A row of stacks 135A is included within the first 3D memory array 100A. Each stack 135A has a gate bar 123A among a plurality of layers 141A to 141D separated by dielectric bars 131A. This example shows four layers 141A to 141D, but the stack 135A may have a greater or smaller number of layers. Data storage structures 108A and channel layers 107A are formed on a first side 133A and a second side 133B of each stack 135A. The data storage structure 108A includes at least a data storage film 111A. Source / drain connections including a source line 103A and a drain line 119A are vertically oriented and arranged between the stacks 135A.

[0033] Memory cells 101A are arranged horizontally and vertically on each of the first side 133A and the second side 133B of the stack 135A. The horizontal positioning of the memory cells 101A may vary from side to side to provide staggering between the memory cells 101A on the first side 133A and the memory cells 101A on the second side 133B, but the arrangement of the repeating memory cells 101A is from layer to layer.

[0034] Each memory cell 101A includes a control gate 109A, a data storage structure 108A, a channel 113A, a source side 105A, and a drain side 117A. The control gate 109A is provided by a gate bar 123A. A single gate bar 123A can provide the control gate 109A for multiple memory cells 101A, which include memory cells 101A horizontally adjacent along the length of the gate bar 123A and memory cells 101A located on opposite sides 133A-B of the gate bar 123A. The channel 113A, the source side 105A, and the drain side 117A are all provided by a portion of the channel layer 107A. The source side 105A is the portion of the channel layer 107A adjacent to the source line 103A. The drain side 117A is the portion of the channel layer 107A adjacent to the drain line 119A. The channel 113A is the portion of the channel layer 107A located between the source side 105A and the drain side 117A.

[0035] The channel layer 107A extends vertically through layers 141A to 141D to provide the channel 113A, the source side 105A, and the drain side 117A for multiple memory cells 101A. Similarly, the data storage structure 108A can include a data storage film 111A continuous across all memory cells 101A on a first side 133A or a second side 133B of the stack 135A. In some embodiments, the channel layer 107A is continuous in the length and height of the stack 135A. Portions of the channel layer 107A can provide the channel 113A, the source side 105A, and the drain side 117A for all horizontally and vertically distributed memory cells 101A on a first side 133A or a second side 133B of the stack 135A.

[0036] Figure 2 A top view of a first 3D memory array 100A in an integrated circuit 200 is shown. Figure 3 A partial cross-sectional view of the integrated circuit 200 is shown. As shown in these figures, the gate bar 123A can extend beyond one end of the first 3D memory array 100A to gradually change in length, thereby forming a stepped pattern 206 that allows each of the gate bars 123A to be coupled to a different word line 207 in the gate in the overlying metal interconnect layer 301D through a via 209. The source lines 201 and the bit lines 203 can also be formed in the metal interconnect layer 301D. The source line routing 201 and the bit line routing 203 can extend crosswise with respect to the gate bars 123A and the stack 135A. Each source line conductor 201 can be coupled to multiple source lines 103A through a via 205. Each bit line 203 can be coupled to multiple drain lines 119A.

[0037] Figure 4Provide an equivalent circuit diagram 400 for the first 3D memory array 100A. As shown in the equivalent circuit diagram 400, each memory cell 101A can be used as a transistor. M memory cells are arranged along each of the gate bars 123A. There are K stacks 135A each having N layers 141A to 141D, giving a total of K*N gate bars 123A. Each memory cell 101A can be addressed separately by selecting the corresponding word line conductive wire 207, bit line conductive wire 203, and source line conductive wire 201. While maintaining this component, the number of gate bars 123A connected to each word line conductive wire 207, the number of source lines 103A connected to each source line conductive wire 201, and the number of drain lines 119A connected to each bit line conductive wire 203 can be changed.

[0038] A transistor has a threshold gate voltage at which the source-to-drain connection changes from open to closed. In a memory cell, this threshold can be changed through write and erase operations to provide two or more different threshold voltages. For example, a data storage structure can include a data storage film 111A that holds the polarization of electric dipoles. The orientation of these dipoles can be changed to modulate the threshold voltage on the control gate 109A at which the electric field makes the channel 113A conductive. The first direction of these electric dipoles provides a first threshold voltage that can represent a logic "1", while the second direction provides a second threshold voltage that can represent a logic "0".

[0039] In the first 3D memory array 100A, a write operation for one of the memory cells 101A can include: setting the corresponding word line conductive wire 207 to a programming voltage V th , while grounding the corresponding bit line conductive wire 203 and the corresponding source line conductive wire 201. The bit lines 203 and source lines 201 of unselected cells can be floating or set to a voltage such as 1 / 2V dd and so on. V th can be the highest possible threshold voltage of the memory cell 101A. For an erase operation, while grounding the corresponding bit line conductive wire 203 and the corresponding source line conductive wire 201 and holding the other bit line conductive wires 203 and source line conductive wires 201 at -1 / 2V dd or making them floating, the corresponding word line conductive wire 207 can be set to -V th . A read operation can include setting the word line conductive wire 207 to an intermediate voltage between the first threshold voltage and the second threshold voltage, such as 1 / 2V th , setting the source line conductive wire 201 to V dd , setting the bit line conductive wire 203 to ground, and determining whether the resulting current is above or below a threshold.

[0040] Figures 2 to 4Shows one way in which memory cells 101A in a first 3D memory array 100A can be coupled within an integrated circuit 200 to effect read, write, and erase operations. Any other suitable coupling can be used, including alternative couplings that result in variations in the number of source line conductive wires 201, bit line conductive wires 203, and word line conductive wires 207 that are respectively connected to source line 103A, drain line 119A, and gate bar 123A. Figures 2 to 3 Shows all connections made through vias 209 and vias 205 that connect to source line conductive wires 201, bit line conductive wires 203, and word line conductive wires 207 arranged in a metal interconnect layer 301D above the first 3D memory array 100A, but some or all of these connections can be connected to conductive wires in a metal interconnect layer 301C below the first 3D memory array 100A. Making these connections using both metal interconnect layer 301C and metal interconnect layer 301D can achieve a reduction in parasitic resistance and capacitance.

[0041] As Figure 3 As shown, the first 3D memory array 100A can be arranged between a metal interconnect layer 301C and a metal interconnect layer 301D within a metal interconnect structure 315 above a substrate 309. The metal interconnect layer 301C and the metal interconnect layer 301D can be the third and fourth metal interconnect layers, the fourth and fifth metal interconnect layers, or any other pair of adjacent metal interconnect layers in the metal interconnect structure 315. The substrate 309 can be a semiconductor substrate and can support field effect transistors (FETs) 307 and other devices for operating the first 3D memory array 100A. These devices can be connected to the first 3D memory array 100A through conductive wires 303 and vias 305 within the metal interconnect structure 315.

[0042] The substrate 309 can be a die cut from a wafer such as a silicon wafer. The substrate 309 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc. Other substrates can also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 309 is or includes silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, silicon-germanium, aluminum gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, indium gallium phosphide, indium gallium arsenide phosphide, or a combination thereof, etc. The substrate 309 can be or include a dielectric material. For example, the substrate 309 can be a dielectric substrate, or can include a dielectric layer on a semiconductor substrate. The dielectric material can be an oxide, such as silicon oxide; a nitride, such as silicon nitride; a carbide, such as silicon carbide; a combination, such as silicon oxynitride, silicon carbonitride, silicon carbide nitride, etc., or any other suitable dielectric.

[0043] Reference Figure 3, the substrate 309 has a main surface 308. The direction D4 is perpendicular to the main surface 308. The direction D4 is herein referred to as the vertical direction and is also referred to as the stacking direction of the stack 135A. The direction D5 is perpendicular to the direction D4, parallel to the main surface 308, is the direction along which the gate strip 123A extends, and is herein referred to as the horizontal direction.

[0044] In an example of the present invention, the memory cell is of the type having a transistor structure, although the concept of the present invention is useful for 3D memory arrays having any type of memory cell. In some embodiments, the memory cell 101A is a ferroelectric memory cell, and the data storage film 111A is a ferroelectric material or includes a ferroelectric material that contains electric dipoles and maintains the polarization of those dipoles. Examples of ferroelectric materials that may be suitable include hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium gadolinium oxide (HFGdO), etc. In some embodiments, the ferroelectric material is doped hafnium oxide. In some embodiments, the doped hafnium oxide is in an orthorhombic phase. In some embodiments, the dopant is present in an atomic percentage of 50% or less.

[0045] In some embodiments, the thickness of the data storage film 111A ranges from about 5 nanometers to about 20 nanometers. In some embodiments, the thickness is about 5 to about 10 nanometers. In some embodiments, the thickness is about 10 to about 15 nanometers. If the data storage film 111A is a ferroelectric material and the thickness is too small (e.g., less than about 5 nanometers), the polarization may not be well maintained and the reliability may be low. If the thickness is too large (e.g., greater than about 20 nanometers), the programming and erasing voltages may be large, and it may have an adverse effect on power efficiency.

[0046] If the memory cell 101A is a ferroelectric memory cell, the data storage structure 108A may include a continuous data storage film 111A across multiple memory cells 101A. In a ferroelectric memory cell, the data storage film 111A can locally store information without being electrically isolated from the data storage films of adjacent cells. The data storage structure 108A may further include a gate dielectric layer (not shown) between the data storage film 111A and the channel 113A. The gate dielectric layer can be deposited as a separate layer or can be spontaneously formed by a reaction such as a reaction between the data storage film 111A and the channel layer 107A. The gate dielectric layer can be any suitable material. For example, the gate dielectric layer can be or include silicon oxide (e.g., SiO2), aluminum oxide (e.g., Al2O3), silicon oxynitride (e.g., SiON), silicon nitride (e.g., Si3N4), lanthanum oxide (e.g., La2O3), strontium titanate oxide (e.g., SrTiO3), undoped hafnium oxide (e.g., HfO2), combinations thereof, etc. In some embodiments, the gate dielectric layer is or includes a high-k dielectric, and a high-k dielectric is a material having a dielectric constant greater than about 3.9. In various embodiments, the gate dielectric layer has a dielectric constant of about 3.9 to 15, about 3.9 to 10, or about 10 to 15.

[0047] In some embodiments, the thickness of the gate dielectric layer is less than about 2.5 nanometers. In some embodiments, the thickness is about 1.5 to about 2.5 nanometers. In some embodiments, the thickness is about 1.5 to about 1.8 nanometers. In some embodiments, the thickness is about 1.7 to about 2.5 nanometers. If the thickness is too small (e.g., about 1 nanometer or less), data retention may be low. If the thickness is too large (e.g., greater than about 2.5 nanometers), the programming and erasing voltages may be too large, or the memory window (i.e., the difference between the high and low threshold voltages) may be too small. High programming and erasing voltages reduce power efficiency. A smaller memory window reduces reliability.

[0048] The channel layer 107A can be or include a semiconductor. In some embodiments, the channel layer 107A is or includes an oxide semiconductor. Oxide semiconductors suitable for the channel layer 107A include but are not limited to zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, etc. In some embodiments, the channel layer 107A is or includes polysilicon, amorphous silicon, etc. In some embodiments, the channel layer has a thickness of about 2 nm to about 30 nm. In some embodiments, the channel layer has a thickness of about 2 nm to about 10 nm. In some embodiments, the channel layer has a thickness of about 5 nm to about 20 nm.

[0049] In some embodiments, the memory cell 101A is a floating gate memory cell and the data storage structure 108A is a charge storage structure. In these embodiments, programming involves storing or removing charge from the data storage film 111A between two dielectric layers. Each of the two dielectric layers can be an oxide such as silicon oxide; a nitride such as silicon nitride; a carbide such as silicon carbide; a combination such as silicon oxynitride, silicon carbonitride, silicon carbide nitride, etc. The data storage film 111A can also be one of these types or some other type of dielectric. For example, the data storage structure 108A can be an ONO structure where the data storage structure 108A is a nitride layer sandwiched between two oxide layers.

[0050] The gate bar 123A is a conductive structure formed of a carbon-based material. The material can be graphite. Graphene is a form of graphite. In some embodiments, the carbon-based material includes graphene. In some embodiments, the graphene is in the form of nanoribbons. In some embodiments, the graphene is boron-doped. In some embodiments, the carbon-based material includes nanocrystalline graphite.

[0051] In some embodiments, the gate bar 123A includes graphene sheets. In some embodiments, the graphene sheets have a horizontal orientation. In some embodiments, the graphene sheets have a vertical orientation in the central region of the gate bar 123A and transition to a horizontal orientation adjacent to the underlying and overlying gate bars 123A, thus providing an overall C-shaped structure. This structure is due to the formation of the gate bar 123A by the replacement gate process described below.

[0052] The source line 103A and the drain line 119A can be formed of any suitable conductive material. Suitable conductive materials for the source line 103A and the drain line 119A can include doped polysilicon, metals, etc. In some embodiments, the conductive material includes a metal. Forming the source line 103A and the drain line 119A with a metal can provide a compact design with low parasitic resistance. Some examples of metals that can be used are tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), etc. and their alloys. In some embodiments, the source line 103A and the drain line 119A also include a diffusion barrier layer, an adhesive layer, or other such layers. Some examples of materials that can be used for the diffusion barrier layer or the adhesive layer are titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), zirconium nitride (ZrN), hafnium nitride (HfN), etc.

[0053] The intra - cell dielectric 115A provides filling and insulation between the source line 103A and the drain line 119A corresponding to each memory cell 101A. The inter - cell dielectric plug 121A provides filling and insulation between the source line 103A and the drain line 119A of horizontally adjacent memory cells 101A. The intra - cell dielectric 115A, the inter - cell dielectric plug 121A, and the dielectric strip 131A can each be any suitable dielectric. Suitable dielectrics for these structures can be, for example, oxides such as silicon oxide, nitrides such as silicon nitride, carbides such as silicon carbide, and combinations thereof such as silicon oxynitride, silicon carbonitride, silicon oxycarbide, etc. Different dielectrics can be selected for the intra - cell dielectric 115A and the inter - cell dielectric plug 121A to provide etch selectivity that aids in manufacturing.

[0054] In some embodiments, the height H1 of the dielectric strip 131A and the height H2 of the gate strip 123A are each in the range of about 15 nm to about 90 nm. In some embodiments, the height H1 is in the range of about 15 nm to about 45 nm. In some embodiments, the height H1 is in the range of about 45 nm to about 90 nm. In some embodiments, the height H2 is in the range of about 15 nm to about 30 nm. In some embodiments, the height H2 is in the range of about 30 nm to about 60 nm. In some embodiments, the height H1 is greater than the height H2. In some embodiments, the height H2 is greater than the height H1. In some embodiments, the height H1 is within three times the height H2. In some embodiments, the height H1 is within two times the height H2.

[0055] The width W2 of the dielectric strip 131A is also the width of the stack 135A. In some embodiments, the width W2 is in the range of about 20 nm to about 200 nm. In some embodiments, the width W2 is in the range of about 30 nm to about 160 nm. In some embodiments, the distance D2 between adjacent stacks 135A is from about 30 nm to about 200 nm. In some embodiments, the distance D2 is from about 40 nm to about 140 nm.

[0056] The source line 103A and the drain line 119A can have dimensions similar to each other. In some embodiments, the widths W1 and lengths L2 of the source line 103A and the drain line 119A are respectively in the range of about 20 nm to about 100 nm. In some embodiments, the widths W1 and lengths L2 are respectively in the range of about 30 nm to about 80 nm. In some embodiments, the cross - sectional area of the source line 103A and the drain line 119A in the horizontal plane is in the range of about 500 nm 2 to about 10,000 nm 2 In some embodiments, the area is in the range of about 900 nm 2 to about 6,000 nm 2within the range of.

[0057] In some embodiments, the length L1 of the channel 113A is in the range of about 30 nm to about 200 nm. In some embodiments, the length L1 is in the range of about 60 nm to about 150 nm. Due to the protrusion 106A, the distance D1 between the source line 103A and the drain line 119A is less than the channel length L1. The channel length L1 can be the distance from the point where the channel layer 107A abuts the source line 103A to the point where the channel layer 107A abuts the drain line 119A. In some embodiments, the distance D1 is 90% or less of the length L1. In some embodiments, the distance D1 is 80% or less of the length L1. In some embodiments, the distance D1 is 70% or less of the length L1. In some embodiments, the area ratio of the source line 103A to the drain line 119A is not more than 5% greater than the area without the protrusion 106A. In some embodiments, the area ratio of the source line 103A to the drain line 119A is not more than 10% greater than the area without the protrusion 106A. In some embodiments, the area ratio of the source line 103A to the drain line 119A is not more than 20% greater than the area without the protrusion 106A.

[0058] In some embodiments, the pitch S1 between adjacent memory cells 101A within the layers 141A to 114D is in the range of about 30 nm to about 200 nm. In some embodiments, the pitch S1 is in the range of about 30 nm to about 100 nm. In some embodiments, the pitch S1 is in the range of about 60 nm to about 200 nm. In some embodiments, the pitch S1 between horizontally adjacent memory cells 101A in a given layer 141A to 114D is greater than the height H1, where the height H1 is the pitch between vertically adjacent memory cells 101A.

[0059] Figure 5A and Figure 5B shows a cross-section of the second 3D memory array 100B. Figure 5C A perspective view of the second 3D memory array 100B is provided. The second 3D memory array 100B has memory cells 101B and is generally similar to the first 3D memory array 100A and has corresponding components except for the differences noted below. One such difference is that in the second 3D memory array 100B, the data storage film 111B is disposed within the recess 127B in the stack 135B. This structure renders the data storage film 111B discontinuous between the layers 141A to 141D. Another difference is that the dielectric plug 121B extends across the distance D2 between adjacent stacks 135B. The dielectric plug 121B is formed before the recess 127B, whereby the recess 127B does not extend through the dielectric plug 121B. This structure renders the data storage film 111B discontinuous between adjacent cells within each of the layers 141A to 141D.

[0060] Each memory cell 101B has a recess 127B. The data storage film 111B is received within the recess 127B. As a result, the data storage film 111B is discontinuous between horizontally adjacent memory cells 101B, between vertically adjacent memory cells 101B, and between any pair of memory cells in the second 3D memory array 100B. Because the data storage film 111B is discontinuous, there are more choices for the data storage structure 108B compared to the data storage structure 108A. For example, the data storage structure 108B can be a floating gate having a conductive data storage film 111B on which charge can be stored to change the threshold voltage for the control gate 109B. The data storage structure 108B can include an insulating film between the data storage film 111B and each of the channel layer 107B and the control gate 109B.

[0061] The dielectric strip 131B has dielectric sidewalls 129B. The gate strip 123B has gate sidewalls 125B that are recessed relative to the dielectric sidewalls 129B to create the recess 127B in the stack 135B. The recess 127B is a region inward from the dielectric sidewalls 129B in a cross-section extending in the vertical direction, which is the stacking direction of the stack 135B. The gate sidewalls 125B can be concave and recessed relative to the dielectric sidewalls 129B by a distance D1. The source line 103B and the drain line 119B are vertically oriented and disposed between the stacks 135B.

[0062] The data storage film 111B can fill the recess 127B. The data storage film 111B has an upper surface 155B and a lower surface 161B that are horizontally aligned with the upper surface 153B and the lower surface 163B of adjacent gate strips 123B, respectively. Within the layers 141B to 141C, the upper surface 153B and the upper surface 155B are adjacent to the overlying dielectric strip 131B. Within the layers 141B to 141D, the lower surface 161B and the lower surface 163B are adjacent to the underlying dielectric strip 131B. The sidewall 126B of the data storage film 111B can be horizontally aligned with the vertically adjacent dielectric sidewalls 129B.

[0063] The width W3 of the dielectric strip 131B is also the width of the stack 135B. In some embodiments, the width W3 is in the range of about 30 nm to about 200 nm. In some embodiments, the width W3 is in the range of about 40 nm to about 160 nm. The gate strip 123B can be narrower. The width at the narrowest point of the gate strip 123B can be the width W3 minus the thickness of the data storage film 111B. In some embodiments, the distance D1 is in the range of about 2 nm to about 20 nm. In some embodiments, the distance D1 is in the range of about 2 nm to 12 nm. In some embodiments, the distance D1 is in the range of about 2 nm to about 6 nm.

[0064] The channel layer 107B is disposed on the dielectric sidewall 129B and above the data storage structure 108B. In some of the illustrated embodiments, the channel layer extends over the inter-cell dielectric plugs 121B as shown and is disposed between the inter-cell dielectric plugs 121B and the source line 103A and the drain line 119B. In some other embodiments, the channel layer 107B is formed before the inter-cell dielectric plugs 121B and is not disposed on the sides of the inter-cell dielectric plugs 121B.

[0065] In some embodiments, the channel layer 107B is disposed in the recess 127B. The stack 135B can be made wider and the recess 127B can be made deeper to accommodate the channel layer 107B. In some embodiments, a portion of the channel layer 107B is disposed in the recess 127B while a portion is disposed outside the recess 127B. In addition to the data storage film 111B, the data storage structure 108B can also include layers such as dielectric layers. In some embodiments, the data storage structure 108B fills the recess 127B together with all or a portion of the channel layer 107B.

[0066] Figure 6A and Figure 6B A cross-section of a third 3D memory array 100C showing some other aspects in accordance with the present teachings is shown. The third 3D memory array 100C has memory cells 101C and has components corresponding to the first 3D memory array 100A. The third 3D memory array 100C has a dielectric layer 173 disposed between the data storage film 111C and the gate strip 123C and another dielectric layer 171 disposed between the data storage film 111C and the channel layer 107C. The data storage structure 108C can be, for example, an ONO data storage structure. In some embodiments, the dielectric layer 173 is disposed on the dielectric sidewall 129C and above the data storage film 111C.

[0067] Figure 7A and Figure 7B A fourth 3D memory array 100D showing some other aspects in accordance with the present teachings is shown. Figure 7B is a cross-section along the vertical direction. Figure 7A is a cross-sectional top view, where the cross-section is through Figure 7BLine A is intercepted on a horizontal plane. The fourth 3D memory array 100D can use many of the same materials and layer thicknesses as the first 3D memory array 100A, but has a different structure and connectivity. Similar to the first 3D memory array 100A, the fourth 3D memory array 100D includes a row of stackings 135D, each stacking having a plurality of horizontal conductive bars 123D of carbon-based material separated by dielectric bars. The dielectric bars include an inter-cell dielectric bar 131D and an intra-cell dielectric bar 115D, both of which can be an inter-cell dielectric. The conductive bars 123D serve as source lines and drain lines. The vertical conductive members 103D between the stackings 135D can operate as word lines. The vertical conductive members can have any suitable composition. In some embodiments, the vertical conductive members are metal. Forming the horizontal conductors from carbon-based materials facilitates fabrication.

[0068] The fourth 3D memory array 100D includes memory cells 101D. Each memory cell 101D includes a channel 113D, a data storage structure 108D, and a control gate 109D. The channel 113D extends between a source side 105D adjacent to a first conductive bar 123D and a drain side 117D adjacent to a second conductive bar 123D. The channel 113D is provided by a channel layer 107D disposed on the side surfaces of the intra-cell dielectric bar 115D. The control gate 109D is part of the vertical conductive member 103D. The data storage structure 108D includes a vertical film disposed between the channel 113D and the control gate 109D. The data storage structure 108D can include a portion of the data storage film 111D and can include additional layers such as a dielectric layer 171D.

[0069] Figure 8A and Figures 8B to 14A and Figure 14B are a series of paired top views and cross-sectional views that illustrate a method of forming a device such as a 3D memory array including components having a first 3D memory array 100A according to the present teachings. Although described with reference to various embodiments of the method Figure 8A and Figures 8B to 14A and Figure 14B , it should be understood that Figure 8A and Figures 8B to 14A and Figure 14B the structures shown are not limited to the method but can be independent of the method. Although Figure 8A and Figures 8B to 14A and Figure 14B are described as a series of actions, it should be understood that the order of the actions can be changed in other embodiments. Although Figure 8A and Figures 8B to 14A and Figure 14Bis shown and described as a particular set of actions, but in other embodiments some of the actions shown and described may be omitted. Additionally, actions not shown and / or described may be included in other embodiments. Although described in terms of forming a first 3D memory array 100A Figure 8A and Figures 8B to 14A and Figure 14B the method may be used to form other memory arrays.

[0070] As Figure 8A shown in top view 800A and Figure 8B cross-sectional view 800B, the method begins with forming a wide stack 805 of alternating gate layers 801 and dielectric layers 803 over dielectric layer 317. As Figure 3 shown, dielectric layer 317 may be one or more layers formed over metal interconnect layer 301C, but more generally may be the top layer of any suitable substrate. In wide stack 805, the top and bottom layers are gate layers 801, but either one may be a dielectric layer 803.

[0071] Dielectric layer 803 and gate layer 801 may be formed by any suitable process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. In some embodiments, gate layer 801 is a dummy layer that is subsequently replaced with a carbon-based material to provide a gate bar. In other embodiments, gate layer 801 is a carbon-based material.

[0072] Plasma enhanced CVD may be suitable for depositing graphene and nanocrystalline graphite layers. A power level between 10W and 500W may be used to generate the plasma. The temperature may be increased, but is typically kept below 400 °C. The carbon source may be methane (CH4), etc. An inert gas such as argon (Ar) may be included in the feed gas mixture. In some embodiments, each of the gate layers 801 is formed over a period of time in the range of from about 5 minutes to about 10 hours. In some embodiments, each of the gate layers 801 is formed over a period of time in the range of from about 10 minutes to about 60 minutes. In some embodiments, each of the gate layers 801 is formed over a period of time in the range of from about 1 hour to about 10 hours.

[0073] As Figure 9A shown in top view 900A and Figure 9B cross-sectional view 900B, a mask 901 may be formed and used to pattern trenches 903 that divide wide stack 805 into a series of stacks 135A. Mask 901 may be a hard mask of any suitable material. Mask 901 may be formed by a CVD process, a spin coating process, etc. or any other suitable process. Mask 901 may be patterned by etching through a photoresist mask (not shown). Photolithography may be used to pattern the photoresist mask.

[0074] The stack 135A may include a gate bar 123A formed by a gate layer 801 and a dielectric bar 131A formed by a dielectric layer 1203. The ratio of the height H3 to the width D2 is the aspect ratio of the trench 903. In some embodiments, the aspect ratio ranges from about 5 to about 15. Forming a trench 903 with an aspect ratio less than about 5 would impair the cell density of the first 3D memory array 100A. Forming a trench 903 with an aspect ratio greater than about 15 would cause distortion or collapse of the stack 135A during processing.

[0075] Etching can be accomplished by any suitable etching process or combination of etching processes. The etching process can be an anisotropic etching process. In some embodiments, the etching includes plasma etching. In some embodiments, the etching gas includes an oxygen source. Oxygen can assist in etching the carbon-based material forming the gate layer 801. Argon may also be suitable.

[0076] As Figure 10A shown in the top view 1000A and Figure 10B the cross-sectional view 1000B, layers of the data storage structure 108A and the channel layer 107A can be deposited in the trench 903 and then a dielectric such as the intra-cell dielectric 115A is filled. The data storage structure 108A may include a data storage film 111A that forms a continuous layer on each side of each stack 135A. If a data storage structure 108A is desired, additional layers can be deposited before or after the data storage film 111A. The channel layer 107A can be conformally deposited on the data storage structure 108A. In some embodiments, the data storage structure 108A is completed by a dielectric layer formed during the deposition of the channel layer 107A. The deposition process can be CVD, ALD, etc. or any other suitable process or combination of processes. In some embodiments, the data storage film 111A is deposited by ALD, etc. In some embodiments, the channel layer 107A is deposited by ALD, etc. In some embodiments, the intra-cell dielectric 115A is deposited by a flowable CVD process. After depositing the intra-cell dielectric 115A, a planarization process can be used to remove any intra-cell dielectric 115A or other materials above the mask 901.

[0077] As Figure 11A shown in the top view 1100A and Figure 11BAs shown in cross-sectional view 1100B, a mask 1103 can be formed and used to help define a pattern for selectively etching an opening 1101 in the intra-cell dielectric 115A. During this etching process, the stack 135A can be covered by a mask 901. The etching process can be an anisotropic etching, such as plasma etching. The etching can selectively remove the intra-cell dielectric without removing the material of the channel layer 107A or the material of the data storage structure 108A. Optionally, the etching can remove the exposed portion of the channel layer 107A or both the channel layer 107A and the data storage structure 108A.

[0078] As Figure 12A shown in top view 1200A and Figure 12B cross-sectional view 1200B, the opening 1101 can be filled with an inter-cell dielectric to form an inter-cell dielectric plug 121A. The inter-cell dielectric plug 121A is formed between desired positions of the memory cells 101A. The opening 1101 can be filled with the inter-cell dielectric plug 121A through a deposition process such as CVD. In some embodiments, the CVD process is a flowable CVD process. Even if the opening 1101 has a high aspect ratio, the flowable CVD process can provide good gap filling. The mask 1103 can be stripped or removed by a CMP process that also removes excess inter-cell dielectric.

[0079] As Figure 13A shown in top view 1300A and Figure 13B cross-sectional view 1300B, a mask 1301 having an opening 1305 can be formed and used to etch an opening 1303 in the intra-cell dielectric 115A. According to some aspects of the present teachings, the opening 1305 can be elliptical. The opening 1305 is generally centered above the inter-cell dielectric plug 121A. Each opening can have a first end extending over the intra-cell dielectric 115A on one side of the inter-cell dielectric plug 121A and a second end extending on the opposite side of the inter-cell dielectric plug 121A. This method can help make the opening 1303 larger without being too close. The etching process can be anisotropic and selectively remove the exposed intra-cell dielectric 115A with substantially no etching of the inter-cell dielectric plug 121A, the data storage film 111A, or the channel layer 107A. The etching process can be plasma etching or the like or any other suitable process.

[0080] As Figure 14A shown in top view 1400A and Figure 14BAs shown in the cross-sectional view 1400B, the opening 1303 can be filled with a conductive material to form the source line 103A and the drain line 119A. Filling the opening 1303 with a conductive material can include CVD, electroplating, electroless plating, etc. or any other suitable process. Excess conductive material can be removed by a planarization process such as CMP. The CMP process can also remove the mask 1301, the mask 901, or both. The resulting structure can be the same as that Figures 1A to 1C shown.

[0081] Figure 15A and Figures 15B to 21A and Figure 21B Pairs of top views and cross-sectional views are provided that illustrate Figure 8A and Figures 8A to 14A and Figure 14B variations of the method that can be used to form a memory array having the following components: Figures 5A to 5B the second 3D memory array 100B shown or some other 3D memory array. The variation starts from a structure similar to that Figure 9A shown in the top view 900A and Figure 9B the cross-sectional view 900B, except that the stack 135B is wider than the stack 135A and the trench 903 is proportionally narrower. As Figure 15A shown in the top view 1500A and Figure 15B the cross-sectional view 1500B (stack 135B), the variation can start with filling the trench 903 with the inter-cell dielectric 1503.

[0082] As Figure 16A shown in the top view 1600A and Figure 16B the cross-sectional view 1600B, a mask 1601 can be formed and used to etch an opening 1603 in the inter-cell dielectric 1503. The remaining inter-cell dielectric 1503 forms the inter-cell dielectric plug 121B. The opening 1603 corresponds to the desired location of the memory cell 101B.

[0083] As Figure 17A shown in the top view 1700A and Figure 17BAs shown in the cross-sectional view 1700B, etching can be performed within the opening 1603 to form a groove 127B in the gate bar 123B. The groove 127B is defined by the inter-cell dielectric plug 121B, such that a groove 127B is formed for each desired location of the memory cell 101B. The etching recesses the gate sidewall 125B relative to the dielectric sidewall 129B. As shown, the etching can also cause the gate sidewall 125B to become concave. In some embodiments, the etching is isotropic. In some embodiments, the etching is wet etching. In some embodiments, the etching process is atomic layer etching. The reactivity difference between the carbon-based material of the gate bar 123B and the dielectric material of the dielectric bar 131B helps to select an etching chemistry that provides the desired selectivity.

[0084] As Figure 18A shown in the top view 1800A and Figure 18B the cross-sectional view 1800B, the data storage film 111B is deposited within the groove 127B. The data storage film 111B can initially be conformally deposited on the gate sidewall 125B and the dielectric sidewall 129B. The deposition process can be CVD, ALD, etc. or any other suitable process. If a data storage structure 108A is desired, additional layers can be deposited before or after the data storage film 111B. An anisotropic etching process can be used to remove portions of the data storage film 111B deposited between the layers 141A to 141D and other regions outside the groove 127B. The etching process can be plasma etching. The mask 1501 can align the etching to the stack 135B.

[0085] As Figure 19A shown in the top view 1900A and Figure 19B the cross-sectional view 1900B, the channel layer 107B can be deposited on the side of the stack 135B, and then the opening 1603 can be filled with the intra-cell dielectric 115B. The channel layer 107B can be conformally deposited on the data storage film 111B and the dielectric sidewall 129B. The deposition process can be CVD, ALD, etc. or any other suitable process. The channel layer 107B can extend through the height of the stack 135B. If it is necessary to complete the formation of the data storage structure 108B, one or more additional layers can be deposited before the channel layer 107B. In some embodiments, the data storage structure 108B is completed by a dielectric layer formed during the deposition of the channel layer 107B.

[0086] Optionally, all or a portion of the channel layer 107B may be deposited within the recess 127B. In some embodiments, the data storage film 111B does not completely fill the recess 127B. The channel layer 107B may then complete the filling of the recess 127B. In some embodiments, the data storage film 111B is etched back to provide space for the channel layer 107B within the recess 127B. In some embodiments, the etch back includes isotropic etching, such as wet etching. In some embodiments, the etch back includes atomic layer etching. In some embodiments, an anisotropic etching process is used to remove portions of the channel layer 107B deposited outside the recess 127B. In some embodiments, a second channel layer 107B is then deposited to provide a desired channel layer thickness.

[0087] The intra-cell dielectric 115B may be deposited by CVD or the like or any other suitable process. In some embodiments, the deposition includes a flowable CVD process. After depositing the intra-cell dielectric 115B, a planarization process may be used to remove any intra-cell dielectric 115B or other material above the mask 1501.

[0088] As Figure 20A shown in the top view 2000A of Figure 20B and the cross-sectional view 2000B of

[0089] As Figure 21A shown in the top view 2100A of Figure 21B and the cross-sectional view 2100B of Figures 5A to 5C a mask 2001 having an opening 2005 may be formed and used to etch an opening 2003 in the intra-cell dielectric 115B. The etching process may be anisotropic and selectively remove the exposed intra-cell dielectric 115B with substantially no etching of the inter-cell dielectric plug 121B, the data storage film 111B, or the channel layer 107B. The etching process may be plasma etching or the like or any other suitable process.

[0090] Figures 22 to 29 Provided is a cross-sectional view showing a variation of the method of Figure 8A and Figures 8B to 14A and Figure 14B As Figure 9BAs shown in the cross-sectional view 900B, this alternative method can be used to avoid a processing stage where the stack 135A remains independent. When remaining independent, the stack 135A has the potential to twist, collapse, or otherwise shift or deform. This method also provides the opportunity to first form a gate layer with a pseudo-layer and then replace this layer with a carbon-based material. The advantage is that all carbon-based materials can be deposited through two operations regardless of the number of layers in the stack 135A.

[0091] As Figure 22 shown in the cross-sectional view 2200, a mask 2201 is formed and used to etch trenches 2207 that divide the wide stack 2209 into smaller stacks 2205. The wide stack 2209 can be the same as the wide stack 805 Figure 8B or can have a pseudo-gate layer 2203 instead of the gate layer 801. The pseudo-gate layer 2203 can be a dielectric with an etching selectivity different from that of the dielectric layer 803. The pseudo-gate layer 2203 can alternatively be polysilicon, an analogue, or any other suitable material. The trenches 2207 can have the same dimensions as the trenches 903 Figure 9B but have a number density that is half or less.

[0092] As Figure 23 shown in the cross-sectional view 2300, the pseudo-gate layer 2203 can be etched backward from the trenches 2207 to form recesses 2301 in the smaller stacks 2205. The etching process can remove approximately half of the volume of the pseudo-gate layer 2203. The etching process can be isotropic etching. For example, the dielectric layer 803 can be silicon oxide, the pseudo-gate layer 2203 can be silicon nitride, and the recesses 2301 can be formed by wet etching with phosphoric acid (H3PO4).

[0093] As Figure 24 shown in the cross-sectional view 2400, the recesses 2301 can be filled by depositing a carbon-based material layer 2403. The carbon-based material can be deposited by CVD, ALD, or any other suitable process or combination of processes. After depositing the carbon-based material layer 2403 in an amount sufficient to complete the filling of the recesses 2301, the excess material can be removed by an anisotropic etching process.

[0094] The carbon-based material can be deposited layer by layer in the form of graphene sheets. The orientation of these sheets depends on the orientation of the surface on which they are deposited. In the region 2401 adjacent to the dielectric layer 1203, the sheets can have a horizontal orientation. In the region 2405 adjacent to the remaining part of the pseudo-gate layer 2203, the sheets can have a vertical orientation. The combination of horizontal and vertical orientation plates provides a C-shaped plate structure.

[0095] As Figure 25 shown in the cross-section 2500, the trenches 2207 are filled. In this example, by Figure 10A andFigure 10B The process steps shown fill the trench. These process steps form a data storage structure 108A including a data storage film 111A, form a channel layer 107A, and complete the filling of the trench 2207 with an intra-cell dielectric 115A. In some other embodiments, the trench 2207 is filled with an inter-cell dielectric, another dielectric, polysilicon, etc.

[0096] As Figure 26 shown in cross-sectional view 2600 of Figure 27 shown in cross-sectional view 2700 of Figure 28 shown in cross-sectional view 2800 of Figure 10A and Figure 10B shown in Figure 29 shown in cross-sectional view 2900 of Figures 22 to 29 etc., methods with or without replacement gate process steps can be used to form other structures according to other embodiments and examples provided herein to provide the advantage of preventing twisting, collapse, or other deformations that may occur on narrow isolated stacks.

[0097] Figure 30A and Figures 30B to 34A and Figure 34B provide paired top-down and cross-sectional views that illustrate a method of forming a device such as a 3D memory array including a component having a fourth 3D memory array 100D according to the present teachings. The "A" figure is a top-down view of the cross-section, where the cross-section is taken along line "A" indicated in the "B" figure. The "B" figure is a vertical cross-section through line "A". Although described with reference to various embodiments of the method Figure 30A and Figures 30B to 34A and Figure 34B , it should be understood that Figure 30A and Figures 30B to 34A and Figure 34B shown in the structure is not limited to the method, but can be independent of the method. Although Figure 30A and Figures 30B to 34A and Figure 34B are described as a series of actions, it should be understood that the order of actions can be changed in other embodiments. Although Figure 30A and Figures 30B to 34A and Figure 34Bshown and described as a specific set of actions, but in other embodiments some of the actions shown and described may be omitted. Additionally, actions not shown and / or described may be included in other embodiments. Although described in terms of forming a fourth 3D memory array 100D Figure 30A and Figures 30B to 34A and Figure 34B methods, the methods can be used to form other memory arrays.

[0098] As Figure 30A shown in top view 3000A of Figure 30B and cross-sectional view 3000B of

[0099] As Figure 31A shown in cross-sectional top view 3100A of Figure 31B and cross-sectional view 3100B of

[0100] As Figure 32A shown in top cross-sectional view 3200A of Figure 32B and cross-sectional view 3200B of

[0101] As Figure 33A shown in cross-sectional view 3300A of Figure 33BAs shown in the cross-sectional view 3300B, the channel layer 107D is deposited within the recess 3201. The channel layer 107D may initially be conformally deposited on the stack 135D. The deposition process may be CVD, ALD, etc. or any other suitable process. An anisotropic etching process may be used to remove a portion of the channel layer 107D outside the recess 3201. The etching process may be a plasma etch aligned with the stack 135D.

[0102] As shown by Figure 34A the cross-sectional views 3400A and Figure 34B the cross-sectional view 3400B, a layer of the data storage structure 108D including the data storage film 111D may be deposited on the side of the stack 135D and then the trenches 3101 are filled with the inter-cell dielectric plugs 121D. The data storage film 111D may be conformally deposited on the stack 135D. If the data storage structure 108D is desired, additional layers may be deposited before or after the data storage film 111D. In some embodiments, the data storage structure 108D includes a dielectric layer that is formed by reacting with the material of the channel layer 107D during the deposition of the data storage film 111D. The deposition process may be CVD, DLD, etc. or any other suitable process or combination of processes. In some embodiments, the data storage film 111D is deposited by ALD, etc. In some embodiments, the inter-cell dielectric plugs 121D are deposited by a flowable CVD process.

[0103] As Figure 35A shown in the top view 3500A and Figure 35B the cross-sectional view 3500B, an opening 3501 may be etched in the inter-cell dielectric plugs 121D. The etching process may be an anisotropic etch such as a plasma etch. The opening 3501 may then be filled with a conductive material to produce the Figures 7A to 7B structure shown. The filling process may include CVD, electroplating, electroless plating, etc. or any other suitable process.

[0104] Figure 36 A flowchart of a method 3600 that may be used to form a 3D memory array in accordance with the present invention is presented. Method 3600 begins with operation 3601 of forming a wide stack including multiple layers of carbon-based conductive material separated by dielectric layers. Figure 8B The cross-sectional view 800B provides an example.

[0105] Operation 3603 is etching trenches in the wide stack to form a row of narrow stacks composed of alternating gate bars and dielectric bars, as Figure 9B shown in the cross-sectional view 900B.

[0106] Operation 3609 is an optional operation of etching the gate bars to form recesses in the narrow stacks. Figure 7B The cross-sectional view 1700B provides an example.

[0107] Act 3611 is an optional step of forming the top layer of the data storage structure. "Top" is used with reference to the order of the layers seen in the horizontal memory cells. In particular, the top layer is one or more layers formed between the data storage film and the control gate. Figure 6A and Figure 6B The dielectric layer 173 shown is an example.

[0108] Act 3613 is depositing the data storage film. Figure 10B Cross-sectional view 1000B of Figure 18B Cross-sectional view 1800B of provides examples.

[0109] Act 3615 is an optional step of performing an etch to remove the data storage film from the exterior of the recess. This act is used in combination with the optional act 3609 in which the recess is formed. Figure 18B Cross-sectional view 1800B of provides examples. The etch can include directional or anisotropic etching. The etch can also include isotropic etching that recesses the data storage film within the recess.

[0110] Act 3617 is an optional step of forming the bottom layer of the data storage structure. "Bottom" is used with reference to the order of the layers seen in the horizontal memory cells. In particular, the bottom layer is one or more layers formed between the data storage film and the channel. Figure 6A and Figure 6B The dielectric layer 171 shown is an example.

[0111] Act 3619 is depositing the channel layer. Figure 10B Cross-sectional view 1000B of Figure 18B Cross-sectional view 1800B of provides examples.

[0112] Act 3621 is an optional step of performing anisotropic etching to remove a portion of the channel layer outside the recess. This operation can be selected when act 3609 has formed the recess and the data storage structure has not yet filled the recess.

[0113] Act 3623 is an optional step of depositing another layer of channel material. This operation can be used in combination with the optional act 3621, which may have made the channel layer too thin.

[0114] Act 3625 is depositing intra-cell dielectric to fill the trenches between the stacks. Figure 10B Cross-sectional view 1000B of provides examples.

[0115] Act 3627 is performing an etch to form an opening in the intra-cell dielectric for an inter-cell dielectric plug. Figure 11B Cross-sectional view 1100B of provides examples. Act 3629 fills the opening with inter-cell dielectric to form the inter-cell dielectric plug.Figure 12B A cross-sectional view 1200B provides an example. Optionally, the trench may first be filled with an inter-cell dielectric, and the intra-cell dielectric may be deposited into an opening etched into the inter-cell dielectric. The resulting structure may be substantially the same as the structure shown in Figure 12B cross-sectional view 1200B, providing an example.

[0116] Action 3631 is to etch an opening in the intra-cell dielectric, where vertical connectors such as source lines and bit lines are formed. This etching may be aligned in part by the inter-cell dielectric plugs. Figure 13A A top view 1300A provides an example.

[0117] Action 3633 fills the opening to provide vertical conductive structures such as source lines and bit lines. Figure 14A A top view 1400A provides an example.

[0118] Figure 37 A flowchart of a method 3700 according to the present invention is presented. This method is another method that can be used to form a 3D memory array. Method 3700 includes many of the same actions as method 3600. The main difference is that in method 3700, the intra-cell dielectric plugs are formed before the channel layer and the data storage structure. Another option is to form the intra-cell dielectric plugs after depositing the data storage film but before depositing the channel layer.

[0119] Method 3700 begins with action 3601 (forming a wide stack), action 3603 (etching trenches in the wide stack to form a narrow stack), and action 3705 (filling the trenches with an inter-cell dielectric). Figure 15A A top view 1500A and Figure 15B a cross-sectional view 1500B provide examples.

[0120] Action 3607 is a cell region definition etch. Figure 16A A top view 1600A and Figure 16B a cross-sectional view 1600B provide examples of performing this etch at this processing stage.

[0121] The method may continue with optional action 3609 to recess the gate bars. Figure 17A A top view 1700A and Figure 17B a cross-sectional view 1700B provide examples.

[0122] The method may continue with optional action 3611 to form the top layer of the data storage structure.

[0123] Method 3700 continues to action 3613 to form the data storage film. This may be followed by optional action 3615 to perform an etch to confine the data storage film within the recesses. Figure 18A A top view 1800A andFigure 18B Cross-sectional view 1800B provides an example.

[0124] Method 3700 continues with operation 3619 (depositing a channel layer) and operation 3625 (depositing intra-cell dielectric). Figure 19A Top view 1900A and Figure 19B Cross-sectional view 1900B provide an example. As shown in method 3600, if the gate bars are recessed and the data storage structure does not fill the grooves, operation 3621 can be used to remove the channel material outside the grooves, and operation 3623 can be used to deposit an additional channel layer.

[0125] Method 3700 continues with operations 3631 and 3633. Operation 3631 is to etch an opening in the intra-cell dielectric, where vertical connectors such as source lines and bit lines are formed. Figure 20A Top view 2000A provides an example. Operation 3633 fills the opening to provide vertical conductive structures such as source lines and bit lines. Figure 21A Top view 2100A provides an example.

[0126] Figure 38 A flowchart of method 3800 according to the present invention is presented. This method is another method that can be used to form a 3D memory array. Method 3800 includes many of the same operations as method 3600, but uses Figures 22 to 29 the type of processing shown.

[0127] Method 3800 includes operation 3801 of forming a wide stack of alternating gate layers and dielectric layers. This can be the same as operation 3601 except that the gate layer can be a dummy gate layer. Figure 8B Cross-sectional view 800B provides an example.

[0128] Operation 3803 is to form a first set of trenches. Figure 22 Cross-sectional view 2200 provides an example. Compared with the trenches formed by operation 3603, the number of these trenches is half or less, for which Figure 9B Cross-sectional view 900B provides an example.

[0129] Operations 3805 and 3807 are optional steps used when the gate layer is a dummy layer. Operation 3805 is to etch away a first portion of the dummy layer to form a groove. Figure 23 Cross-sectional view 2300 provides an example. Operation 3807 is to fill the groove with a carbon-based conductor. Figure 24 Cross-sectional view 2400 provides an example. Any conductive material deposited outside the groove 2301 can be removed by anisotropic etching.

[0130] Method 3800 proceeds to operations 3611 to 3625, which may be the same as the operations in method 3600, except that they operate only within the first set of trenches. Figure 25 Cross-sectional view 2500 of Figure 25 provides an example.

[0131] Operation 3809 is to form a mask and etch the second trench. Figure 26 Cross-sectional view 2600 of Figure 26 provides an example. If the gate layer is a dummy gate layer, the method may proceed to operations 3805 and 3807 to complete the gate replacement process. Figure 27 Cross-sectional view 2700 of Figure 27 and Figure 28 Cross-sectional view 2800 of Figure 28 provides an example.

[0132] Method 3800 continues with the repetition of operations 3611 to 3625. Figure 29 Cross-sectional view 2900 of Figure 29 provides an example. As described in connection with method 3600, the processing may continue from operations 3627 to 3633.

[0133] Figure 39 A flowchart of method 3900 according to the present invention is presented. This method is another method that can be used to form a 3D memory array. Method 3900 starts with operation 3901 of forming a wide stack. In this example, the wide stack includes a first dielectric layer, a second dielectric layer, and a carbon-based conductor layer. Figure 30B Cross-sectional view 3000B of Figure 30B provides an example. Optionally, the process of method 3800 may be employed, in which case the carbon-based conductor layer may be replaced with a dummy layer.

[0134] Operation 3903 is to etch trenches in the wide stack to form a row of narrow stacks. Figure 31A Cross-sectional top view 3100A of Figure 31A and Figure 31B Cross-sectional view 3100B of Figure 31B provides an example.

[0135] Operation 3905 is to selectively etch one of the dielectrics to form a recess in the narrow stack. Figure 32A Cross-sectional top view 3200A of Figure 32A and Figure 32B Cross-sectional view 3200B of Figure 32B provides an example.

[0136] Operation 3907 is to deposit a channel layer in the trench. The channel layer may fill the recess. Operation 3911 is an anisotropic etch to remove a portion of the channel layer outside the recess. Figure 33A Cross-sectional top view 3300A of Figure 33A and Figure 33B Cross-sectional view 3300B of Figure 33B provides an example.

[0137] Act 3913 is an optional act of depositing a bottom layer of a data storage structure in a trench. Act 3915 is depositing a data storage film in the trench. Act 3917 is an optional act of depositing a top layer of the data storage structure on the data storage film. Act 3919 is filling the trench with an inter-cell dielectric. Figure 34A A cross-sectional top view 3400A of Figure 34B and a cross-sectional view 3400B of

[0138] Act 3921 is etching a vertical opening in the inter-cell dielectric. Figure 35A A cross-sectional top view 3500A of Figure 35B and a cross-sectional view 3500B of Figure 7A and Figure 7B provide an example of the resulting structure. Step 3923 is filling the opening with a conductive material to form a vertical connector that can be used as a word line.

[0139] Although the methods 3600, 3700, 3800, and 3900 Figures 36 to 39 are shown and described herein as a series of acts or events, it should be understood that the order of the illustrated acts or events should not be construed in a limiting sense. For example, certain acts may occur in a different order and / or concurrently with other acts or events in addition to those shown and / or described herein. Further, not all of the illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0140] Some aspects of the present teachings relate to a device having a three-dimensional memory cell array disposed between two adjacent metal interconnect layers in a metal interconnect structure. Each memory cell includes a source side, a drain side, a channel, a control gate, and a data storage film. The channel extends between the source side and the drain side. The data storage film is located between the control gate and the channel. The three-dimensional memory cell array further includes an array of stacks, each stack including a plurality of conductive bars and a plurality of dielectric bars. The conductive bars extend horizontally to connect with a plurality of the memory cells and are formed of a carbon-based conductive material.

[0141] Some aspects of the present teachings relate to a memory device including a plurality of stacks. Each stack has a vertical arrangement of two or more gate bars formed of a conductive carbon-based material such as graphite. The gate bars are separated by dielectric bars. The source lines and the drain lines are located between the stacks and extend in the vertical direction. Each of the memory cells has a channel extending between one of the source lines and one of the drain lines and a data storage structure located between the channel and one of the gate bars.

[0142] Some aspects of the present teachings relate to a method of forming a memory device, the method including forming a wide stack having a plurality of conductive layers and a plurality of dielectric layers. The conductive layers include a carbon-based material. Trenches are etched in the wide stack to form a plurality of narrow stacks. A data storage film is deposited in the trenches.

[0143] Some aspects of the present teachings relate to a memory device including: a three-dimensional memory cell array disposed between two adjacent metal interconnect layers in a metal interconnect structure, each of the memory cells including a source side, a drain side, a channel extending between the source side and the drain side, a gate, and a data storage film between the gate and the channel; and an array of stacks, each stack including a plurality of conductive bars and a plurality of dielectric bars, wherein the conductive bars extend horizontally to provide gates for a plurality of the memory cells; wherein the conductive bars include a carbon-based conductive material.

[0144] In the above memory device, the carbon-based conductive material is graphene.

[0145] In the above memory device, the graphene is in the form of flakes having a C-shaped structure.

[0146] In the above memory device, the carbon-based conductive material is boron-doped graphene nanoribbons.

[0147] In the above memory device, the carbon-based conductive material is nanocrystalline graphite.

[0148] In the above memory device, further included are: second conductive bars, each extending vertically to connect to two or more of the memory cells; wherein the second conductive bars are metal.

[0149] In the above memory device, further included are: drain lines, extending vertically, each of the drain lines connecting to a plurality of the drain sides; and source lines, extending vertically, each of the source lines connecting to a plurality of the source sides.

[0150] In the above memory device, grooves are formed in the sides of the stacks; and the data storage film is disposed in the grooves.

[0151] Some aspects of the present teachings relate to a memory device including: a plurality of stacks, each stack including two or more vertically stacked gate bars separated by dielectric bars; source lines and drain lines located between the stacks and extending along the stacking direction of the stacks; and memory cells, each including a channel extending between one of the source lines and one of the drain lines and a data storage structure located between the channel and one of the two or more vertically stacked gate bars; wherein the gate bars include graphite.

[0152] In the above memory device, the graphite includes graphene sheets.

[0153] In the above memory device, the gate bar includes a first portion and a second portion; in the first portion, the graphene sheet has a first orientation parallel to the stacking direction of the gate bar and the dielectric bar; and in the second portion, the graphene sheet has a second orientation perpendicular to the first orientation.

[0154] In the above memory device, the graphene includes graphene nanoribbons.

[0155] In the above memory device, the source line and the drain line are metals.

[0156] In the above memory device, each gate bar includes a first sidewall; each dielectric bar includes a second sidewall; the first sidewall is recessed inward from the second sidewall to form a groove in the stack; and the data storage structure includes a data storage film disposed in the groove.

[0157] Some aspects of the present teachings relate to a method of forming a memory device, the method including: forming a first stack including a plurality of conductive layers and a plurality of dielectric layers, wherein the conductive layers include a carbon-based material; etching trenches in the first stack to form a plurality of second stacks; and depositing a data storage film in the trenches.

[0158] In the above method, it further includes: before depositing the data storage film, selectively etching to form a groove in the second stack, wherein the groove is formed adjacent to the conductive layer; and after depositing the data storage film, etching to remove portions of the data storage film outside the groove.

[0159] In the above method, it further includes: forming a dielectric plug in the trench before forming the groove.

[0160] In the above method, it further includes: depositing a channel layer above the data storage film; filling the trenches between the stacks with a second dielectric; etching an opening through the second dielectric; and filling the opening with a metal to form the source line and the drain line.

[0161] In the above method, it further includes: etching second trenches in the plurality of second stacks; and depositing a second data storage film in the second trenches.

[0162] In the above method, the carbon-based material is graphene.

[0163] The foregoing has outlined features of several embodiments in order that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they can readily use the present invention as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A memory device, comprising: A three-dimensional memory cell array disposed between two adjacent metal interconnect layers in a metal interconnect structure, each of the memory cells including a source side, a drain side, a channel extending between the source side and the drain side, a gate, and a data storage film between the gate and the channel; And An array of stacks, each stack including a plurality of conductive bars and a plurality of dielectric bars, wherein the conductive bars extend horizontally to provide gates for a plurality of the memory cells; Wherein the conductive bars comprise a carbon-based conductive material.

2. The memory device according to claim 1, wherein, The carbon-based conductive material is graphene.

3. The memory device according to claim 2, wherein, The graphene is in the form of a sheet having a C-shaped structure.

4. The memory device according to claim 1, wherein, The carbon-based conductive material is boron-doped graphene nanoribbon.

5. The memory device according to claim 1, wherein, The carbon-based conductive material is nanocrystalline graphite.

6. The memory device according to claim 1, further comprising: Second conductive bars, each extending vertically to connect to two or more of the memory cells; Wherein the second conductive bars are metals.

7. The memory device according to claim 1, further comprising: Drain lines extending vertically, each of the drain lines connecting to a plurality of the drain sides; And Source lines extending vertically, each of the source lines connecting to a plurality of the source sides.

8. The memory device according to claim 7, wherein: A groove is formed in a side surface of the stack; and The data storage film is disposed in the groove.

9. A memory device, comprising: A plurality of stacks, each stack including two or more vertically stacked gate bars separated by dielectric bars; A source line and a drain line located between the stacks and extending along the stacking direction of the stacks; And Memory cells, each including a channel extending between one of the source lines and one of the drain lines and a data storage structure located between the channel and one of the two or more vertically stacked gate bars; Wherein the gate bars comprise a carbon-based conductive material.

10. The memory device according to claim 9, wherein, The carbon-based conductive material is a graphene sheet.

11. The memory device according to claim 10, wherein: The gate bar includes a first part and a second part; In the first part, the graphene sheet has a first orientation parallel to the stacking direction of the gate bar and the dielectric bar; And In the second part, the graphene sheet has a second orientation perpendicular to the first orientation.

12. The memory device according to claim 9, wherein, The carbon-based conductive material is graphene nanoribbon.

13. The memory device according to claim 9, wherein, The source line and the drain line are metals.

14. The memory device according to claim 9, wherein: Each of the gate bars includes a first sidewall; Each of the dielectric bars includes a second sidewall; The first sidewall is recessed inwardly from the second sidewall to form a groove in the stack; and The data storage structure includes a data storage film disposed in the groove.

15. A method of forming a memory device, the method comprising: Forming a first stack including a plurality of conductive layers and a plurality of dielectric layers, wherein the conductive layers comprise a carbon-based material and wherein the conductive layers serve as gates of the memory device; Etch trenches in the first stack to form a plurality of second stacks; and Deposit a data storage film in the trenches.

16. The method according to claim 15, further comprising: Before depositing the data storage film, selectively etch to form grooves in the second stack, wherein the grooves are formed adjacent to the conductive layer; and After depositing the data storage film, etch to remove portions of the data storage film outside the grooves.

17. The method according to claim 16, further comprising: Form a dielectric plug in the trenches before forming the grooves.

18. The method according to claim 15, further comprising: Deposit a channel layer over the data storage film; Fill the trenches between the stacks with a second dielectric; Etch an opening through the second dielectric; And Fill the opening with metal to form source and drain lines.

19. The method according to claim 15, further comprising: Etch second trenches in the plurality of second stacks; And Deposit a second data storage film in the second trenches.

20. The method according to claim 15, wherein, The carbon-based material is graphene.

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