Semiconductor device and method of forming a semiconductor device

Abstract

The semiconductor device according to the present invention includes: a source component and a drain component; a plurality of semiconductor nanostructures extending between the source component and the drain component; a gate structure wrapping each of the plurality of semiconductor nanostructures; a bottom dielectric layer located above the gate structure and the drain component; a backside power rail disposed above the bottom dielectric layer; and a backside source contact disposed between the source component and the backside power rail. The backside source contact extends through the bottom dielectric layer. Embodiments of the present application also relate to methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology develops to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current and reducing short channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or a portion thereof disposed on more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and are promising candidates for high-performance and low-leakage applications. FinFETs have a rising channel wrapped by a gate on more than one side (e.g., a gate wraps the top and sidewalls of a "fin" of a semiconductor material extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around a channel region to provide access to two or more side channel regions. Because its gate structure surrounds the channel region, MBC transistors can also be referred to as surround gate transistors (SGTs) or full ring gate (GAA) transistors. The channel region of an MBC transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives the MBC transistor alternative names, such as nanosheet transistor or nanowire transistor.

[0004] As the spacing between the gate structure and the source / drain components in multi-gate devices decreases, some electrical routing is moved to the back side. However, when forming backside contact openings, coverage variations may cause device defects. Therefore, while existing backside contact structures are generally adequate for their intended purposes, they are not satisfactory in all aspects. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor device, comprising: a source component and a drain component; a plurality of semiconductor nanostructures extending between the source component and the drain component; a gate structure wrapping each of the plurality of semiconductor nanostructures; a bottom dielectric layer located above the gate structure and the drain component; a back side power rail disposed above the bottom dielectric layer; and a back side source contact disposed between the source component and the back side power rail, wherein the back side source contact extends through the bottom dielectric layer.

[0006] Still other embodiments of the present application provide a semiconductor device, comprising: a source component and a drain component; a plurality of semiconductor nanostructures extending between the source component and the drain component; a gate structure wrapping each of the plurality of semiconductor nanostructures; a bottom dielectric layer located above the gate structure and the drain component; and a backside power rail disposed above the bottom dielectric layer, wherein the backside power rail is isolated from the drain component by the bottom dielectric layer, and wherein the backside power rail is electrically coupled to the source component.

[0007] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: receiving a workpiece, the workpiece comprising: a substrate, a bottom sacrificial layer, disposed above the substrate, a bottom covering layer, disposed above the bottom sacrificial layer, and a stack, located above the bottom covering layer, the stack comprising a plurality of channel layers interlaced by a plurality of sacrificial layers; forming a fin-shaped structure by the substrate, the bottom sacrificial layer, the bottom covering layer, and the stack; forming a dummy gate stack above a channel region of the fin-shaped structure; forming a source groove above a source region of the fin-shaped structure, and forming a drain groove above a drain region of the fin-shaped structure; selectively etching the source region so that the source groove extends through the bottom covering layer and the bottom sacrificial layer , to expose the substrate, thereby forming a source access opening; depositing a first epitaxial layer in the source access opening; after depositing the first epitaxial layer, forming a second epitaxial layer to form a source component in the source groove and a drain component in the drain groove; removing the pseudo gate stack; selectively removing the channel region and multiple sacrificial layers in the bottom sacrificial layer to release the multiple channel layers as multiple channel components; forming a bottom dielectric layer between the substrate and the bottom cap layer; forming a gate structure around each of the multiple channel components; selectively etching the first epitaxial layer in the source access opening to expose the source component in the back source contact opening; and forming a back source contact in the back source contact opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device having a bottom dielectric layer according to one or more aspects of the present invention is shown.

[0010] Figures 2 to 9 , FIG. 10A to FIG. 17A and FIG. 10B to FIG. 17B According to one or more aspects of the present invention, Figure 1 A partial cross-sectional view of a workpiece during a manufacturing process of the method. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] In addition, when "about," "approximately," or the like is used to describe a value or a range of values, the term is intended to encompass values ​​within a reasonable range, taking into account the inherent variations during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having values ​​associated with the values, the value or range of values ​​encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may encompass dimensions ranging from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to those of ordinary skill in the art is + / - 15%. The present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] The present invention relates generally to backside contact structures for multi-gate transistors, and more particularly to self-aligned backside contact structures.

[0014] The multi-gate device includes a transistor whose gate structure is formed on at least two sides of the channel region. Examples of multi-gate devices include a fin field effect transistor (FinFET) with a fin structure and an MBC transistor with multiple channel components. As described above, the MBC transistor may also be referred to as an SGT, a GAA transistor, a nanosheet transistor, or a nanowire transistor. These multi-gate devices may be n-type or p-type. The MBC transistor includes any device having a gate structure or a portion thereof formed on the 4 sides of the channel region (e.g., a portion surrounding the channel region). The MBC device according to the present invention may have a channel region arranged in a nanowire channel component, a strip channel component, a nanosheet channel component, a nanostructure channel component, a bridge channel component, and / or other suitable channel configurations. Backside contact structures (such as backside power rails (BPR)) may be advantageous for MBC transistors because they provide an additional first metal line (M0), allowing a higher gate density and widening the power rail for low resistance. However, due to overlay variations, it can be challenging to form a satisfactory BPR without causing shorts, such as shorts between the backside source contact and the gate structure.

[0015] The present invention provides an embodiment of a semiconductor device including a bottom self-aligned contact (SAC) dielectric layer covering a source component and a back side of a gate structure to allow selective access to the source component. Thus, the formation of a back side source contact opening to the source component is self-aligned and does not require high overlay accuracy.

[0016] Various aspects of the present invention will now be described in more detail with reference to the accompanying drawings. Figure 1 A flow chart of a method 100 for forming a semiconductor device from a workpiece according to an embodiment of the present invention is shown. Method 100 is merely an example and is not intended to limit the present invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For reasons of simplicity, not all steps are described in detail herein. Method 100 is described below in conjunction with partial cross-sectional views of workpieces at different stages of manufacture according to embodiments of method 100. For the avoidance of doubt, throughout all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction.

[0017] refer to Figure 1 and Figure 2, the method 100 includes a frame 102 of providing a workpiece 200. The workpiece 200 includes a substrate 202, a bottom sacrificial layer 203 disposed above the substrate 202, a bottom capping layer 205 disposed above the bottom sacrificial layer 203, and a stack 204 disposed above the bottom capping layer 205. The stack 204 includes a plurality of channel layers 208 and a plurality of sacrificial layers 206. Because the workpiece 200 will be manufactured into a semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 as the context requires. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon substrate. The substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. In the depicted embodiment, the substrate 202 is a silicon substrate.

[0018] In some embodiments, the bottom sacrificial layer 203 may include a semiconductor material, such as silicon germanium (SiGe). In those embodiments, the bottom sacrificial layer 203 may include a first germanium content between about 10% and about 50%. In some implementations, the bottom sacrificial layer 203 is epitaxially deposited on the substrate 202 using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE), an ultra-high vacuum CVD (UHV-CVD), a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some cases, the bottom sacrificial layer 203 is formed to a thickness between about 8 nm and about 15 nm.

[0019] The bottom capping layer 205 includes a semiconductor material different from the semiconductor material forming the bottom sacrificial layer 203. In some embodiments, the bottom capping layer 205 is formed of silicon (Si). In some embodiments, the bottom capping layer 205 is epitaxially deposited on the bottom sacrificial layer 203 using an MBE process, a VPE process, a UHV-CVD process, an MOCVD process, and / or other suitable epitaxial growth processes. As will be described below, the bottom capping layer 205 is used to control the recess of the bottom sacrificial layer 203 and is not intended to become a channel member. For these reasons, the bottom capping layer 205 can have a thickness less than each of the channel layers 208. In some cases, the bottom capping layer 205 has a thickness between about 2nm and about 5nm.

[0020] like Figure 2As shown, the sacrificial layers 206 and the channel layers 208 in the stack 204 are alternately stacked so that the sacrificial layers 206 are interleaved by the channel layers 208, and vice versa. The sacrificial layers 206 and the channel layers 208 are formed of different semiconductor materials configured to allow selective removal of the sacrificial layers 206 without substantially damaging the channel layers 208. In an embodiment, the sacrificial layer 206 includes silicon germanium (SiGe), and the channel layer 208 includes silicon (Si). In this embodiment, the sacrificial layer 206 includes a second germanium content that can be greater than the first germanium content of the bottom sacrificial layer 203. In some cases, the second germanium concentration is between about 10% and about 50%. Because the higher germanium content in silicon germanium (SiGe) produces a faster etching rate, the larger second germanium content of the sacrificial layer 206 (compared to the first germanium content) allows the sacrificial layer 206 to be selectively recessed during the formation of the internal spacer groove (described below). In addition, the different germanium contents can be configured to achieve simultaneous removal of the sacrificial layer 206 and the bottom sacrificial layer 203 in subsequent processes. For example, the sacrificial layer 206 and the channel layer 208 in the stack 204 may be formed by an MBE process, a VPE process, a UHV-CVD process, an MOCVD process, and / or other suitable epitaxial growth processes.

[0021] It should be noted that three (3) layers of sacrificial layers 206 and three (3) layers of channel layers 208 are arranged alternately, as shown in FIG. Figure 2 As shown, this is for illustrative purposes only and is not intended to limit the contents specifically recited in the claims. It should be understood that any number of sacrificial layers and channel layers can be formed in the stack 204. The number of layers depends on the number of channel components required for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. In some embodiments, all sacrificial layers 206 can have a substantially uniform first thickness, and all channel layers 208 can have a substantially uniform second thickness. The first thickness and the second thickness can be the same or different. The channel layer 208 or a portion thereof can be used as a channel component of a subsequently formed multi-gate device, and the thickness of each channel layer 208 is selected based on device performance considerations. The sacrificial layer 206 can be ultimately removed and used to define the vertical distance between adjacent channel regions of the subsequently formed multi-gate device, and the thickness of each sacrificial layer 206 is selected based on device performance considerations. In some embodiments, the first thickness of the sacrificial layer 206 is less than the thickness of the bottom sacrificial layer 203. In some cases, the first thickness of the sacrificial layer 206 can be between about 6nm and about 13nm. In these embodiments, a thicker bottom sacrificial layer 203 will result in a bottom dielectric layer that is thicker than the vertical distance between channel features.

[0022] refer to Figure 1 and Figure 3, the method 100 includes a block 104, in which a fin structure 210 is formed from a stack 204, a bottom capping layer 205, a bottom sacrificial layer 203, and a substrate 202. In block 108, portions of the stack 204, the bottom capping layer 205, the bottom sacrificial layer 203, and the substrate 202 are patterned using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. Figure 3 As shown, a fin top hard mask 212 may be formed over the stack 204 to facilitate the photolithography process. The fin top hard mask 212 may be a single layer or multiple layers. Figure 3 In the illustrated embodiment, the fin top hard mask 212 is multilayer and includes an oxide layer 214 and a nitride layer 216 above the oxide layer. The oxide layer 214 may include silicon oxide or silicon oxycarbide, and the nitride layer 216 may include silicon nitride or silicon carbonitride. The etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods. In some embodiments, a double patterning or multiple patterning process may be used to define a fin structure having, for example, a pitch that is less than that obtainable using a single, direct lithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The patterned material layer is then removed, and the fin structure 210 may then be patterned using the remaining spacers or mandrels by etching the stack 204, the bottom cap layer 205, the bottom sacrificial layer 203, and a portion of the substrate 202.

[0023] refer to Figure 1 and Figure 4, the method 100 includes a frame 106, wherein an isolation feature 218 is located between the fin structures 210. In some embodiments, the isolation feature 218 can be deposited in the trench 211 between adjacent fin structures 210 to isolate them from each other. The isolation feature 218 can also be referred to as a shallow trench isolation (STI) feature 218. For example, in some embodiments, a dielectric material for the isolation feature 218 is first deposited over the substrate 202, filling the trench 211 with the dielectric material. In some embodiments, the dielectric material can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited by a spin coating process, a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form STI features 218. Figure 4 As shown, at least a portion of the fin structure 210 formed by the stack 204 is elevated above the STI feature 218 after recessing.

[0024] refer to Figure 1 , Figure 4 and Figure 5 , the method 100 includes block 108, in which a dummy gate stack 220 is formed over the channel region 210C of the fin structure 210. Figure 5 In some embodiments shown, the dummy gate stack 220 includes a dummy dielectric layer 222 and a dummy electrode layer 224. In those embodiments, a gate top hard mask layer 226 used to pattern the dummy gate stack 220 may remain on top of the dummy electrode layer 224 to protect the dummy electrode layer 224. In the depicted embodiment, the gate top hard mask layer 226 may include a nitride hard mask layer 228 and an oxide hard mask layer 230 located above the nitride hard mask layer 228. In some embodiments, the dummy dielectric layer 222 may include silicon oxide, the dummy electrode layer 224 may include polysilicon, the nitride hard mask layer 228 may include silicon nitride or silicon oxynitride, and the oxide hard mask layer 230 may include silicon oxide. In an exemplary process for forming the dummy gate stack 220, the dummy dielectric layer 222 is first deposited over the fin structure 210 by CVD, ALD, chemical oxidation, or thermal oxidation, as shown. Figure 4Then, a dummy electrode layer 224 and a gate top hard mask layer 226 are deposited on the dummy dielectric layer 222 using a CVD process, an ALD process, or a suitable deposition process. Then, the gate top hard mask layer 226, the dummy electrode layer 224, and the dummy dielectric layer 222 are patterned using a photolithography and etching process to form a dummy gate stack 220, as shown in FIG. Figure 5 Similar to the formation of the fin structure 210 , the dummy gate stack 220 may be patterned using a double patterning or multiple patterning process.

[0025] The dummy gate stack 220 is used as a reserved position to undergo various processes and will be removed and replaced by a functional gate structure in subsequent steps. Figure 5 As shown, the dummy gate stack 220 is disposed over the channel regions 210C of the fin structure 210. Each of the channel regions 210C is disposed between the source region 210S and the drain region 210D along the length direction of the fin structure 210 aligned with the X direction.

[0026] refer to Figure 1 and Figure 5 , the method 100 includes a frame 110, wherein a first gate spacer layer 232 and a second gate spacer layer 234 are deposited over a workpiece 200. The first gate spacer layer 232 and the second gate spacer layer 234 are conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 220 and the top surface of the fin structure 210. For the convenience of describing a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. The first gate spacer layer 232 and the second gate spacer layer 234 may have different dielectric constants and different etching selectivities. In some embodiments, the dielectric constant of the first gate spacer layer 232 is less than the dielectric constant of the second gate spacer layer 234, and the second gate spacer layer 234 is more etch-resistant than the first gate spacer layer 232. In some embodiments, the first gate spacer layer 232 may include silicon oxide, silicon oxycarbide, or a suitable low-k dielectric material. The second gate spacer layer 234 may include silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. The first gate spacer layer 232 and the second gate spacer layer 234 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process.

[0027] refer to Figure 1 and Figure 6, the method 100 includes a block 112, in which a source region 210S and a drain region 210D of the fin structure 210 are recessed. In some embodiments, the source region 210S and the drain region 210D of the fin structure 210 that are not covered by the dummy gate stack 220, the first gate spacer layer 232, and the second gate spacer layer 234 are anisotropically etched by dry etching or a suitable etching process to form a source recess 236S and a drain recess 236D. For example, the dry etching process may be performed with an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , C 4 F 8 , C 4 F 6 , CH 3 F and / or C 2 F 6 ), carbon-containing gases (e.g., CO and / or CH 4 ), chlorine-containing gases (such as Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBr 3 ), iodine-containing gas, other suitable gas and / or plasma and / or their combination. Figure 6 As shown, the sidewalls of the sacrificial layer 206 and the channel layer 208 in the channel region 210C are exposed in the source recess 236S and the drain recess 236D. The recess at box 112 is controlled to terminate on the top surface of the bottom capping layer 205 or around the bottom capping layer 205. In this regard, the bottom capping layer 205 serves as an etch stop layer (ESL) because it is etched at a smaller etching rate than the sacrificial layer 206 directly on the bottom capping layer 205.

[0028] refer to Figure 1 and Figure 7, the method 100 includes a block 114, in which the sacrificial layer 206 in the channel region 210C is selectively and partially etched to form an inner spacer recess 238. In block 114, the sacrificial layer 206 exposed in the source recess 236S and the drain recess 236D is selectively and partially recessed along the X direction to form the inner spacer recess 238, while the second gate spacer layer 234, the first gate spacer layer 232, the gate top hard mask layer 226, the channel layer 208, and the bottom cap layer 205 are not substantially etched. In an embodiment where both the bottom sacrificial layer 203 and the sacrificial layer 206 are formed of silicon germanium, the bottom sacrificial layer 203 can also be recessed, although more modestly due to its lower germanium content. As described above, the lower first germanium content in the bottom sacrificial layer 203 allows it to be etched slower than the sacrificial layer 206 having a higher second germanium content. In embodiments where the channel layer 208 consists essentially of Si and the sacrificial layer 206 consists essentially of SiGe, the selective recessing of the sacrificial layer 206 may include a SiGe oxidation process and subsequent SiGe oxide removal. In those embodiments, the SiGe oxidation process may include the use of ozone. In some optional embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. In some embodiments, the selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. In some embodiments, the selective wet etching process may include hydrogen fluoride (HF) or NH 4 OH etchant.

[0029] refer to Figure 1 and Figure 8 , the method 100 includes a frame 116, wherein an internal spacer component 240 is formed in the internal spacer groove 238. In some embodiments, the operation in frame 116 may include blanket depositing an internal spacer material layer over the workpiece 200 and etching back the internal spacer material layer to form the internal spacer component 240. The internal spacer material layer may be a single layer or multiple layers. In some embodiments, the internal spacer material layer may be deposited using CVD, PECVD, LPCVD, ALD, or other suitable methods. The internal spacer material layer may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides.

[0030] The deposited inner spacer material layer is then etched back to remove the inner spacer material layer from the sidewalls of the channel layer 208 to obtain the inner spacer feature 240 in the inner spacer recess 238. In block 116, the inner spacer material layer may also be removed from the top surfaces of the gate top hard mask layer 226, the first gate spacer layer 232, the second gate spacer layer 234, and the isolation feature 218. In some embodiments, the composition of the inner spacer material layer is selected so that the inner spacer material layer can be selectively removed without substantially etching the second gate spacer layer 234. In some embodiments, the etch-back operation performed in block 116 may include using hydrogen fluoride (HF), fluorine gas (F 2 ), hydrogen (H 2 ), ammonia (NH 3 ), nitrogen trifluoride (NF 3 ) or other fluorine-based etchants. Figure 8 As shown, each of the inner spacer features 240 is in direct contact with the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208 .

[0031] refer to Figure 1 and Fig. 9 The method 100 includes a block 118 in which the source region 210S is selectively recessed to form a source access opening 242. In block 118, a photolithography process and an etching process are used to selectively recess the source recess 236S ( Figure 8 The source access opening 242 is formed by a bottom cover layer 205, a bottom sacrificial layer 203, and a portion of the substrate 202, while masking the drain recess 236D. In an exemplary process for forming the source access opening 242, a hard mask and a photoresist layer are deposited in sequence. The photoresist layer is patterned using a photolithography technique, and the pattern in the photoresist layer is transferred to the hard mask layer by etching. The patterned hard mask layer covers the workpiece except for the source region 210S, and is then applied as an etching mask to form the source access opening 242. The etching process in frame 118 can be a dry etching process, and can be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , C 4 F 8 , C 4 F 6 , CH 3 F and / or C 2 F 6 ), carbon-containing gases (e.g., CO and / or CH 4 ), chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBr 3 ), iodine-containing gases, other suitable gases and / or plasmas and / or combinations thereof.

[0032] refer to Figure 1 , Fig. 10A and Fig. 10B , method 100 includes box 120, in which a source component 246S and a drain component 246D are formed. In some embodiments, each of the source component 246S and the drain component 246D includes a first epitaxial layer 244 and a second epitaxial layer 245. In some embodiments, the first epitaxial layer 244 can be epitaxially and selectively formed from the exposed top surfaces of the substrate 202, the bottom sacrificial layer 203, the bottom capping layer 205, and the channel layer 208. The first epitaxial layer 244 can be epitaxially deposited using an MBE process, a VPE process, a UHV-CVD process, an MOCVD process, and / or other suitable epitaxial growth processes. In these embodiments, the first epitaxial layer 244 is less likely to be attached and deposited on the internal spacer component 240. The first epitaxial layer 244 can be deposited into the source access opening 242. In Fig. 10A In the example shown, the first epitaxial layer 244 can have a substantially flat top surface. Fig. 10B In other examples shown, the first epitaxial layer 244 can have a concave top surface. Fig. 10A and Fig. 10B The common point in the embodiment is that the first epitaxial layer 244 covers the sidewalls of the bottom cap layer 205 and the bottom sacrificial layer 203 as the first epitaxial layer 244 grows epitaxially therefrom. In some embodiments, the first epitaxial layer 244 can be formed of silicon (Si), germanium (Ge), or silicon germanium (SiGe). In some embodiments, the first epitaxial layer 244 is not intentionally doped or has no doping substances. When an n-type device is desired, the first epitaxial layer 244 can be formed of silicon. When a p-type device is desired, the first epitaxial layer 243 can be formed of germanium or silicon germanium.

[0033] After the first epitaxial layer 244 is deposited, a second epitaxial layer 245 is epitaxially deposited over the source region 210S and the drain region 210D. Fig. 10A and Fig. 10BAs shown, in some embodiments, the second epitaxial layer 245 is epitaxially deposited using an MBE process, a VPE process, a UHV-CVD process, an MOCVD process, and / or other suitable epitaxial growth processes. During epitaxial deposition, the second epitaxial layer 245 grows from the first epitaxial layer 244 and is allowed to overgrow and merge over the internal spacer component 240. The second epitaxial component 245 can be in-situ doped during its epitaxial deposition. When an n-type device is desired, the second epitaxial layer 245 includes silicon doped in-situ with an n-type dopant such as arsenic (As) or phosphorus (P). When a p-type device is desired, the second epitaxial layer 245 includes silicon germanium doped in-situ with a p-type dopant such as boron (B). In some embodiments, the deposition of the first epitaxial layer 244 and the second epitaxial layer 245 can be implemented in the same process chamber without breaking the vacuum. In order to activate the dopant in the second epitaxial layer 245, the frame 120 may include an annealing process. In some embodiments, the annealing process may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a rapid annealing process, or a furnace annealing process. In some cases, the annealing process includes a peak annealing temperature between about 900° C. and about 1100° C. Fig. 10A and Fig. 10B As shown, at the end of the operation in box 120, a source component 246S is formed over the source region 210S, and a drain component 246D is formed over the drain region 210D. Each of the source component 246S and the drain component 246D includes a second epitaxial layer 245 as an inner layer and a first epitaxial layer 244 as an outer layer. The outer layer is disposed between the inner layer and the channel layer 208, between the inner layer and the bottom cover layer 205, and between the inner layer and the substrate 202. Because the first epitaxial layer 244 is undoped, it can be used as a diffusion barrier layer to prevent excessive dopant species from diffusing into the channel member 208, the bottom cover layer 205, and the substrate 202. The first epitaxial layer 244 helps maintain a steep dopant concentration profile at the interface between the channel layer 208 and the source component 246S and the interface between the channel layer 208 and the drain component 246D, thereby reducing the short channel effect.

[0034] refer to Figure 1 , Fig.11A and Fig. 11B, the method 100 includes a block 122, in which the dummy gate stack 220 is removed. The operations in block 122 may include forming a contact etch stop layer (CESL) 262, depositing an interlayer dielectric (ILD) layer 264 over the CESL 262, performing a planarization process to expose the dummy electrode layer 224, and removing the dummy gate stack 220. In some examples, the CESL 262 may include silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 262 may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. Then, an ILD layer 264 is deposited over the CESL 262. In some embodiments, the ILD layer 264 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 264 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 264, the workpiece 200 may be annealed to improve the integrity of the ILD layer 264. After depositing the CESL 262 and the ILD layer 264, the workpiece 200 may be planarized by a planarization process to expose the dummy electrode layer 224. For example, the planarization process may include a CMP process. The exposure of the dummy electrode layer 224 allows the removal of the dummy electrode layer 224 and the removal of the dummy dielectric layer 222. In some embodiments, the removal of the dummy electrode layer 224 and the dummy dielectric layer 222 generates a gate trench above the channel region 210C. Removing the dummy electrode layer 224 and the dummy dielectric layer 222 may include one or more etching processes that are selective to the materials in the dummy electrode layer 224 and the dummy dielectric layer 222. For example, selective wet etching, selective dry etching, or a combination thereof that is selective to the dummy electrode layer 224 and the dummy dielectric layer 222 may be used to remove the dummy electrode layer 224 and the dummy dielectric layer 222. After the dummy electrode layer 224 and the dummy dielectric layer 222 are selectively removed, surfaces of the channel layer 208 and the sacrificial layer 206 in the channel region 210C are exposed in the gate trench.

[0035] refer to Figure 1 , Fig.11A and Fig. 11B , method 100 includes block 124, wherein sacrificial layer 206 and bottom sacrificial layer 203 are selectively removed. To better illustrate the structural relationship, Fig.11A A partial cross-sectional view along the length direction (which is along the Y direction) of the dummy gate stack 220 is provided. Fig. 10A and Fig. 10B shown), and Fig. 11BA partial cross-sectional view of line AA′ along the X direction is provided, which is the length direction of the fin structure 210 ( Figure 5 It should be noted that Fig. 11B 250 is shown in the figure. In the depicted embodiment, each of the hybrid fins 250 includes an outer dielectric layer 252, an inner dielectric layer 254, and a capping dielectric layer 256. The outer dielectric layer 252 and the capping dielectric layer 256 may include silicon nitride, metal oxide, silicon carbonitride, or silicon oxycarbide. The inner dielectric layer 254 may include silicon oxide or silicon oxycarbide or other low-k dielectric materials. With the sidewalls of the sacrificial layer 206 and the bottom sacrificial layer 203 exposed, they are selectively removed to release the channel layer 208 as the channel member 208, and release the bottom capping layer 205. The selective removal of the sacrificial layer 206 and the bottom sacrificial layer 203 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching includes APM etching (e.g., a mixture of ammonium hydroxide-hydrogen peroxide-water). In some embodiments, the selective removal includes SiGe oxidation, followed by SiGeOx removal. For example, oxidation can be provided by ozone cleaning, and then by a cleaning agent such as NH 4 OH etchant removes SiGeOx.

[0036] refer to Figure 1 , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A and Fig. 14B , the method 100 includes block 126, wherein a bottom dielectric layer 270 is formed between the bottom cap layer 205 and the substrate 202. To better illustrate the structural relationship, Fig.11A , Fig. 12A , Fig.13A and Fig.14A Each of which provides a gate stack 220 ( Fig. 10A and Fig. 10B ) is a partial cross-sectional view in the length direction (along the Y direction), and Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B Each of the fin structures 210 ( Figure 5 It should be noted that Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B2. A hybrid fin 250 is shown in FIG. 2. In the depicted embodiment, each of the hybrid fins 250 includes an outer dielectric layer 252, an inner dielectric layer 254, and a capping dielectric layer 256. The outer dielectric layer 252 and the capping dielectric layer 256 may include silicon nitride, metal oxide, silicon carbonitride, or silicon oxycarbide. The inner dielectric layer 254 may include silicon oxide or silicon oxycarbide or other low-k dielectric materials.

[0037] First reference Fig.11A and Fig. 11B , depositing a first dielectric filling layer 260 over the workpiece 200, including in the gate trench. The first dielectric filling layer 260 may be deposited using ALD, PEALD, CVD, or PECVD so that it wraps around each of the channel member 2080 and the bottom cap layer 205. Fig.11A and Fig. 11B As shown, the first dielectric filling layer 260 fills the space between two adjacent channel members 2080 and the space between the bottom cover layer 205 and the substrate 202. Fig.11A and Fig. 11B In some embodiments shown, a seam 261 may be formed because the spacing between the bottom cap layer 205 and the substrate 202 is deeper in the gate trench and greater than the spacing between the channel members 2080. In some embodiments, the first dielectric filler layer 260 may be formed of a dielectric material selected from silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, zirconium oxide, or other suitable dielectric materials.

[0038] Then refer to Fig. 12A and Fig. 12B , so that the first dielectric filling layer 260 is recessed. The recessing of the first dielectric filling layer 260 includes an isotropic wet etching process or an isotropic dry etching process that is selective to the first dielectric filling layer. For example, the isotropic dry etching process or the wet etching process may include using a solution of ammonium hydroxide and hydrogen peroxide, such as RCA Standard Clean-1 (SC-1) or other cleaning solutions. Fig. 12A and Fig. 12BAs shown, because the seam 261 provides more access to the first dielectric fill layer 260 in the space between the bottom cover layer 205 and the substrate 202, the first dielectric fill layer 260 in the space between the bottom cover layer 205 and the substrate 202 is etched faster than the first dielectric fill layer 260 between adjacent channel members 2080. The recess here is time controlled to completely remove the first dielectric fill layer 260 in the space between the bottom cover layer 205 and the substrate 202, while the first dielectric fill layer 260 remains disposed between adjacent channel members 2080. It should be noted that the first dielectric fill layer 260 is also removed from the top surface of the topmost channel member 2080. Completely removing the first dielectric fill layer 260 in the space between the bottom cover layer 205 and the substrate 202 leaves a bottom void 266 between the bottom cover layer 205 and the substrate 202. The bottom void 266 can be formed by depositing a dielectric layer 260 in the source access opening 242 ( Fig. 9 The first epitaxial layer 244 is separated from the first epitaxial layer 244 as shown.

[0039] refer to Fig.13A and Fig. 13B , a second dielectric filling layer 269 is deposited over the workpiece 200. The second dielectric filling layer 269 may be deposited using ALD, PEALD, CVD, or PECVD so that it wraps around the channel member 2080, the first dielectric filling layer 260, and the bottom cap layer 205. Fig. 13B As shown, a second dielectric filling layer 269 is deposited above the topmost channel member 2080, in the space between the hybrid fin 250 and the channel member 2080, and in the space between the bottom cap layer 205 and the substrate 202. The first dielectric filling layer 260 between the channel members 2080 is used to prevent the second dielectric filling layer 269 (or too much thereof) from entering between the channel members 2080. The second dielectric filling layer 269 can be formed of a dielectric material selected from silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, zirconium oxide or other suitable dielectric materials. The composition of the second dielectric filling layer 269 is different from that of the first dielectric filling layer 260. In some embodiments, the composition of the first dielectric filling layer 260 and the second dielectric filling layer 269 is selected so that the first dielectric filling layer 260 can be selectively etched or etched faster than the second dielectric filling layer 269. This material selection ensures that the first dielectric fill layer 260 is completely removed, while the second dielectric fill layer 269 remains in the space between the bottom cap layer 205 and the substrate 202. In some embodiments, the etching selectivity of the first dielectric fill layer 260 over the channel member 2080 (formed of silicon in some embodiments) or silicon nitride is greater than 50, and the etching selectivity of the first dielectric fill layer 260 over the second dielectric fill layer 269 is greater than 25.

[0040] refer to Fig.14A and Fig. 14B, etching back the second dielectric filling layer 269 and the first dielectric filling layer 260 in a top-down manner. Etching back the first dielectric filling layer 260 and the second dielectric filling layer 269 includes an isotropic wet etching process or an isotropic dry etching process that is selective to the first dielectric filling layer. For example, the isotropic dry etching process or the wet etching process may include using a solution of dilute hydrofluoric acid (DHF), buffered hydrofluoric acid (BHF) or ammonium hydroxide and hydrogen peroxide (such as RCA Standard Cleaning-1 (SC-1)). As described above, in some embodiments, the etching selectivity of the first dielectric filling layer 260 over the channel member 2080 (formed by silicon in some embodiments) or silicon nitride is greater than 50, and the etching selectivity of the first dielectric filling layer 260 over the second dielectric filling layer 269 is greater than 25. This arrangement allows the isotropic etching process to etch the first dielectric filling layer 260 and the second dielectric filling layer 269 without damaging the channel member 2080. In addition, because the first dielectric filling layer 260 etches faster than the second dielectric filling layer 269, the first dielectric filling layer 260 between the channel members 2080 can be completely removed, while the second dielectric filling layer 269 remains disposed between the bottom capping layer 205 and the substrate 202. The second dielectric filling layer 269 remaining between the bottom capping layer 205 and the substrate 202 can be referred to as a bottom dielectric layer 270. As will be described below, because the bottom dielectric layer 270 enables the backside source contact opening and the backside source contact to be self-aligned, it can also be referred to as a bottom self-aligned contact (SAC) dielectric layer 270. It should be noted that after the bottom dielectric layer 270 is formed, the channel members 2080 remain suspended (i.e., released) and are ready to form a gate structure.

[0041] refer to Figure 1 , Fig.15A and Fig. 15B, method 100 includes box 128, in which a gate structure 276 is formed. The gate structure 276 wraps each of the channel members 2080 formed by the channel layer 208. The gate structure 276 can be a high-K metal gate structure. Here, "high-K" means that the gate dielectric layer in the gate structure 276 has a dielectric constant greater than that of silicon dioxide, which is about 3.9. In various embodiments, the gate structure 276 includes an interface layer 273, a gate dielectric layer 274 formed above the interface layer 273, and / or a gate electrode layer 275 formed above the gate dielectric layer 274. In some embodiments, the interface layer 273 may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer 273 can be formed after the sacrificial layer 206 and the bottom sacrificial layer 203 are selectively removed in box 124. In one exemplary process, the interface layer 273 may be a native oxide formed as a result of a cleaning process using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). In an alternative embodiment, the interface layer 273 may be reformed in block 128. The gate dielectric layer 274 may include a high-K dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer 274 may include other high-K dielectrics, such as TiO 2 、HfZrO、Ta 2 O 3 、HfSiO 4 、ZrO 2 、ZrSiO 2 、LaO、AlO、ZrO、TiO、Ta 2 O 5 , Y 2 O 3 、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO 3 (BST), Al 2 O 3 、Si 3 N 4 , SiON, combinations thereof, or other suitable materials. The gate dielectric layer 274 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0042] The gate electrode layer 275 may include a single layer or an optional multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or a combination of metal silicides. For example, the gate electrode layer 275 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 275 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, after depositing the gate electrode layer 275, a CMP process may be performed to remove excess metal from the workpiece 200, thereby providing a substantially flat top surface of the gate structure 276.

[0043] refer to Figure 1 , Fig.15A , Fig. 15B , Fig.16A and Fig. 16B , the method 100 includes a block 130 in which a backside source contact opening 278 is formed to expose the source feature 246S. The operations in block 130 may be performed after the workpiece 200 is flipped upside down, such as Fig.15A and Fig. 15B , where the Z coordinate is also flipped up and down. In some embodiments, the workpiece 200 is bonded to a carrier substrate (not explicitly shown) and flipped before forming middle-end-of-line (MEOL) structures (such as front-side source / drain contacts and gate contacts). In some other embodiments, the workpiece 200 is bonded to a carrier substrate (not explicitly shown) and flipped after forming MEOL structures and some back-end-of-line (BEOL) structures (such as interconnect structures). In still other embodiments, the workpiece 200 is bonded to a carrier substrate (not explicitly shown) and flipped after forming all MEOL and BEOL structures. Although not explicitly shown, the substrate 202 may be subjected to a grinding process or a planarization process. Due to the grinding process or the planarization process, the top surface of the substrate 202 and the top surface of the isolation feature 218 are coplanar, as shown in FIG. Fig.15A and Fig. 15B As shown. Fig.15A and Fig. 15B In FIG. 2 , the remaining substrate 202 is the portion of the substrate 202 that is formed as the base portion of the fin structure 210 .

[0044] Reference now Fig.16A and Fig. 16B In block 130 , the remaining substrate 202 and the first epitaxial layer 244 are selectively etched to form a backside source contact opening 278 and a backside power rail trench 280 . Fig.15A , Fig. 15B , Fig.16A and Fig. 16B The back side source contact opening 278 corresponds to the first epitaxial layer 244 (eg, Fig. 9 2). In other words, the backside source contact opening 278 corresponds to the source access opening 242. Due to the compositional differences between the first epitaxial layer 244 and the bottom dielectric layer 270 and the compositional differences between the substrate 202 and the isolation feature 218, the backside source contact opening 278 and the backside power rail trench 280 are formed in a self-aligned manner. In embodiments where the first epitaxial layer 244 includes silicon, germanium, or silicon germanium and the substrate 202 includes silicon, the selective etching in block 130 may be performed using a selective dry etching process. An exemplary selective dry etching process may include using hydrogen (H 2 ), fluorine-containing gases (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , C 4 F 8 , C 4 F 6 , CH 3 F. NF 3 and / or C 2 F 6 ) and / or a combination thereof. At the end of the operations in block 130, the source feature 246S is exposed in the backside source contact opening 278. Unlike the source feature 246S, the drain feature 246D in the drain region 210D and the gate structure 276 in the channel region 210C are covered and protected by the bottom cap layer 205 and the bottom dielectric layer 270 (i.e., the bottom SAC dielectric layer 270).

[0045] refer to Figure 1 , Fig.17A and Fig. 17B , method 100 includes box 132, in which a backside source contact 284 and a backside power rail 286 are formed. In some embodiments, to reduce contact resistance, a silicide layer 282 can be formed on the exposed source component 246S by depositing a metal layer over the source component 246S and performing an annealing process to induce silicide between the metal layer and the source component 246S. Suitable metal layers may include titanium (Ti), tantalum (Ta), nickel (Ni), cobalt (Co), or tungsten (W). The silicide layer 282 may include titanium silicide (TiSi), titanium silicon nitride (TiSiN), tantalum silicide (TaSi), tungsten silicide (WSi), cobalt silicide (CoSi), or nickel silicide (NiSi). In some embodiments, ammonia (NH 2+) may be placed on the deposited metal layer to form a silicide layer 282. 3) is formed into a liner 281, and thus, the liner 281 may include titanium nitride (TiN), tantalum nitride (TaN), nickel nitride (NiN), cobalt nitride (CoN), or tungsten nitride (WN). After forming the silicide layer 282, a metal filling layer may be deposited in the backside source contact opening 278 and the backside power rail trench 280 to form a backside source contact 284 and a backside power rail 286, respectively. The metal filling layer may include titanium nitride (TiN), titanium (Ti), ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo), tungsten (W), tantalum (Ta), or tantalum nitride (TaN). This may be followed by a planarization process to provide a flat top surface, thereby setting a platform for subsequent processes.

[0046] refer to Fig.17A At the end of the operations in block 132, the MBC transistor 290 is substantially formed. The MBC transistor 290 may be an n-type MBC transistor or a p-type MBC transistor. The MBC transistor 290 includes a source component 246S, a drain component 246D, a plurality of channel members 2080 extending between the source component 246S and the drain component 246D, and a gate structure 276 wrapping each of the plurality of channel members 2080. The plurality of channel members 2080 are stacked vertically along the Z direction, and each extends longitudinally along the X direction. The channel members 2080 may also be referred to as nanostructures 2080 due to their nanoscale dimensions. Each of the source component 246S and the drain component 246D includes a first epitaxial layer 244 as an outer layer to interface the channel member 208 with a second epitaxial layer 245 spaced apart from the channel member 2080 by the first epitaxial layer 244. The first epitaxial layer 244 is not intentionally doped, while the second epitaxial layer 245 is in-situ doped. like Fig.17A As shown, the drain feature 246D and the gate structure 276 are partially separated and electrically isolated from the backside power rail 286 by the bottom cap layer 205 and the bottom dielectric layer 270. The source feature 246S is electrically coupled to the backside power rail 286 through the backside source contact 284. In the depicted embodiment, the backside power rail 286 and the backside source contact 284 are formed continuously. The silicide layer 282 is disposed at the interface between the backside source contact 284 and the source feature 246S to reduce the contact resistance. In other words, the silicide layer 282 is sandwiched between the backside source contact 284 and the source feature 246S. The backside power rail 286 is configured to carry a positive power supply voltage and is named accordingly.

[0047] Although not intended to be limiting, one or more embodiments of the present invention provide benefits to semiconductor devices and their formation. For example, embodiments of the present invention include a bottom SAC dielectric layer covering a gate structure and a backside source contact extending through the bottom SAC dielectric layer to couple a source component. In an exemplary process, the bottom SAC dielectric layer includes an opening above the source component, and the backside source contact opening can be formed in a self-aligned manner. This self-alignment prevents short circuits without requiring precise coverage. Therefore, the method of the present invention includes a larger process window and improved yield.

[0048] In one exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes: a source component and a drain component; a plurality of semiconductor nanostructures extending between the source component and the drain component; a gate structure wrapping each of the plurality of semiconductor nanostructures; a bottom dielectric layer located above the gate structure and the drain component; a backside power rail disposed above the bottom dielectric layer; and a backside source contact disposed between the source component and the backside power rail. The backside source contact extends through the bottom dielectric layer.

[0049] In some embodiments, the bottom dielectric layer includes silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, or zirconium oxide. In some embodiments, the semiconductor device may further include a silicide layer sandwiched between the back source contact and the source component. The silicide layer includes tungsten silicide, cobalt silicide, nickel silicide, or titanium silicide. In some embodiments, the semiconductor device may further include a bottom capping layer between the bottom dielectric layer and the drain component. In some cases, the bottom capping layer extends between the bottom dielectric layer and the gate structure. In some embodiments, the back source contact extends through the bottom capping layer. In some embodiments, the bottom capping layer includes silicon. In some embodiments, the semiconductor device may further include an epitaxial component between each of the plurality of semiconductor nanostructures and the source component. The composition of the epitaxial component is different from the composition of the source component.

[0050] In another exemplary aspect, the present invention is directed to a semiconductor device. The semiconductor device includes: a source component and a drain component; a plurality of semiconductor nanostructures extending between the source component and the drain component; a gate structure wrapping each of the plurality of semiconductor nanostructures; a bottom dielectric layer located above the gate structure and the drain component; and a backside power rail disposed above the bottom dielectric layer. The backside power rail is isolated from the drain component by the bottom dielectric layer, and the backside power rail is electrically coupled to the source component.

[0051] In some embodiments, the backside power rail is electrically coupled to the source component via a backside source contact extending through the bottom dielectric layer. In some embodiments, the bottom dielectric layer comprises silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, or zirconium oxide. In some embodiments, the semiconductor device may further comprise a bottom capping layer between the bottom dielectric layer and the drain component. In some embodiments, the bottom capping layer extends between the bottom dielectric layer and the gate structure. In some cases, the backside power rail is electrically coupled to the source component via a backside source contact extending through the bottom dielectric layer and the bottom capping layer. In some embodiments, the bottom capping layer comprises silicon.

[0052] In another exemplary aspect, the present invention is directed to a method. The method includes: receiving a workpiece, the workpiece including a substrate, a bottom sacrificial layer disposed above the substrate, a bottom capping layer disposed above the bottom sacrificial layer, and a stack located above the bottom capping layer, the stack including a plurality of channel layers interlaced by a plurality of sacrificial layers; forming a fin structure from the substrate, the bottom sacrificial layer, the bottom capping layer, and the stack; forming a dummy gate stack above a channel region of the fin structure; forming a source recess above a source region of the fin structure, and forming a drain recess above a drain region of the fin structure; selectively etching the source region so that the source recess extends through the bottom capping layer and the bottom sacrificial layer to expose the substrate, thereby forming a source access opening; depositing a first epitaxial layer in the source access opening; after depositing the first epitaxial layer, forming a second epitaxial layer to form a source component in the source groove and a drain component in the drain groove; removing the dummy gate stack; selectively removing a plurality of sacrificial layers in the channel region and the bottom sacrificial layer to release a plurality of channel layers as a plurality of channel components; forming a bottom dielectric layer between the substrate and the bottom cap layer; forming a gate structure around each of the plurality of channel components; selectively etching the first epitaxial layer in the source access opening to expose the source component in the back source contact opening; and forming a back source contact in the back source contact opening.

[0053] In some embodiments, the plurality of channel layers include silicon. The plurality of sacrificial layers and the bottom sacrificial layer include silicon germanium, and the germanium content of the plurality of sacrificial layers is greater than the germanium content of the bottom sacrificial layer. In some embodiments, forming the bottom dielectric layer includes: depositing a first dielectric filling layer on the surface of the plurality of channel members, the substrate, and the bottom cover layer; isotropically etching the first dielectric filling layer to remove the first dielectric filling layer between the bottom cover layer and the substrate, and the first dielectric filling layer is disposed between the plurality of channel members; after the isotropic etching, depositing a second dielectric filling layer between the bottom cover layer and the substrate; and recessing the first dielectric filling layer and the second dielectric filling layer until the plurality of channel members are released again, and a portion of the second dielectric filling layer remains between the bottom cover layer and the substrate. In some embodiments, the bottom dielectric layer includes silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, or zirconium oxide. In some cases, the second epitaxial layer includes a doping substance selected from the group consisting of phosphorus, arsenic, and boron. The first epitaxial layer has no doping substance.

[0054] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand aspects of the present invention. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a source component and a drain component; a plurality of semiconductor nanostructures extending between the source feature and the drain feature; a gate structure encapsulating each of the plurality of semiconductor nanostructures; a bottom dielectric layer over the gate structure and the drain feature; a backside power rail disposed above the bottom dielectric layer; a backside source contact disposed between the source component and the backside power rail; as well as a bottom capping layer disposed between the bottom dielectric layer and the drain feature, Wherein, the back side source contact extends through the bottom dielectric layer.

2. The semiconductor device according to claim 1, wherein The bottom dielectric layer includes silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, or zirconium oxide.

3. The semiconductor device according to claim 1, further comprising: a silicide layer sandwiched between the backside source contact and the source feature, Wherein, the silicide layer includes tungsten silicide, cobalt silicide, nickel silicide or titanium silicide.

4. The semiconductor device according to claim 1, wherein: The bottom capping layer is in direct contact with the bottom dielectric layer and the drain feature.

5. The semiconductor device according to claim 4, wherein: The bottom capping layer extends between the bottom dielectric layer and the gate structure.

6. The semiconductor device according to claim 5, wherein: The backside source contact extends through the bottom capping layer.

7. The semiconductor device according to claim 5, wherein: The bottom capping layer includes silicon.

8. The semiconductor device according to claim 1, further comprising: An epitaxial feature is located between each of the plurality of semiconductor nanostructures and the source feature, wherein a composition of the epitaxial feature is different from a composition of the source feature.

9. A semiconductor device comprising: a source component and a drain component; a plurality of semiconductor nanostructures extending between the source feature and the drain feature; a gate structure encapsulating each of the plurality of semiconductor nanostructures; a bottom dielectric layer over the gate structure and the drain feature; a backside power rail disposed above the bottom dielectric layer; as well as a bottom capping layer disposed between the bottom dielectric layer and the drain feature, wherein the backside power rail is isolated from the drain component by the bottom dielectric layer, Wherein, the backside power rail is electrically coupled to the source component.

10. The semiconductor device according to claim 9, wherein The backside power rail is electrically coupled to the source feature through a backside source contact extending through the bottom dielectric layer.

11. The semiconductor device according to claim 9, wherein: The bottom dielectric layer includes silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, or zirconium oxide.

12. The semiconductor device according to claim 9, wherein: The bottom capping layer is in direct contact with the bottom dielectric layer and the drain feature.

13. The semiconductor device according to claim 12, wherein: The bottom capping layer extends between the bottom dielectric layer and the gate structure.

14. The semiconductor device according to claim 12, wherein: The backside power rail is electrically coupled to the source feature through a backside source contact extending through the bottom dielectric layer and the bottom capping layer.

15. The semiconductor device according to claim 12, wherein: The bottom capping layer includes silicon.

16. A method of forming a semiconductor device, comprising: A workpiece is received, the workpiece comprising: Substrate, a bottom sacrificial layer disposed above the substrate, a bottom cover layer disposed above the bottom sacrificial layer, and a stack located above the bottom cover layer, the stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers; forming a fin structure by the substrate, the bottom sacrificial layer, the bottom capping layer and the stack; forming a dummy gate stack above the channel region of the fin structure; forming a source recess above a source region of the fin-shaped structure, and forming a drain recess above a drain region of the fin-shaped structure; selectively etching the source region so that the source recess extends through the bottom cap layer and the bottom sacrificial layer to expose the substrate, thereby forming a source access opening; depositing a first epitaxial layer in the source access opening; After depositing the first epitaxial layer, forming a second epitaxial layer to form a source feature in the source recess and a drain feature in the drain recess; removing the dummy gate stack; selectively removing a plurality of sacrificial layers in the channel region and the bottom sacrificial layer to release the plurality of channel layers as a plurality of channel components; forming a bottom dielectric layer between the substrate and the bottom capping layer; forming a gate structure around each of the plurality of channel members; selectively etching the first epitaxial layer in the source access opening to expose the source feature in a backside source contact opening; and A backside source contact is formed in the backside source contact opening.

17. The method according to claim 16, in, The plurality of channel layers include silicon, wherein the plurality of sacrificial layers and the bottom sacrificial layer comprise silicon germanium, and The germanium content of the multiple sacrificial layers is greater than the germanium content of the bottom sacrificial layer.

18. The method according to claim 16, wherein: Forming the bottom dielectric layer includes: depositing a first dielectric fill layer on surfaces of the plurality of channel members, the substrate, and the bottom cap layer; isotropically etching the first dielectric filling layer to remove the first dielectric filling layer between the bottom cover layer and the substrate, while the first dielectric filling layer is disposed between the plurality of channel members; After the isotropic etching, depositing a second dielectric fill layer between the bottom cap layer and the substrate; and The first and second dielectric filling layers are recessed until the plurality of channel members are released again and a portion of the second dielectric filling layer remains between the bottom cover layer and the substrate.

19. The method according to claim 16, wherein: The bottom dielectric layer includes silicon nitride, titanium oxide, aluminum oxide, hafnium oxide, or zirconium oxide.

20. The method according to claim 16, in, The second epitaxial layer includes a doping substance selected from the group consisting of phosphorus, arsenic and boron, Wherein, the first epitaxial layer does not have the doping substance.

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