Thinned semiconductor chip with edge support

Abstract

This application relates to a thinned semiconductor chip having an edge support. A semiconductor device is disclosed in which the device resistance is reduced. The semiconductor device includes a semiconductor chip, wherein the chip thickness at the central portion of the chip where circuit elements are disposed is uniform and different from the chip thickness near the chip side away from the circuit elements.

Description

Technical Field

[0001] This application relates to a thinned semiconductor chip with an edge support member. Background Art

[0002] The trend in semiconductor device evolution is towards thinner chips. One reason is the thinning of end products such as mobile phones and flat panel TVs. In addition, thinner chips perform better in at least two aspects: as the chip gets thinner, heat dissipation is better and device resistance decreases, resulting in lower power consumption. Semiconductor materials such as silicon have a finite resistivity. Electricity flowing through the semiconductor material converts electrical power into heat rather than work, which is generally undesirable.

[0003] One way to reduce device resistance is to construct the device using a thinner chip. Integrated circuits (ICs) are fabricated in semiconductor wafers with a specific thickness to physically support the circuit elements in the wafer. After the front-end process is completed, the wafer is moved to the back-end process, which typically includes a backgrinding step to reduce the wafer thickness, and then individual chips are cut from the wafer and packaged. Currently, the state-of-the-art wafer thinning technology is the TAIKO thinning process, which is an improved backgrinding process that grinds the middle part of the wafer and leaves a 3 mm edge around the wafer. In a manufacturing environment, the TAIKO thinning process can thin semiconductor wafers to about 50 μm; experimental reports have reported reaching 40 μm. The disadvantage of TAIKO thinning is the high equipment cost and the difficulty in handling the individual thin and fragile chips after cutting them from the wafer.

[0004] Other proposed methods for reducing chip resistance include creating grooves, vias, dimples, cavities, and a grid pattern of concave and convex parts on the back side of the wafer to be later filled with metal or other conductive materials. It is hoped that by selectively removing semiconductor material from the back side, the wafer mass can be reduced and thus the total resistance can be proportionally reduced. So far, this model has not been realized in real products. Summary of the Invention

[0005] The inventors of the present invention have found from their own experimental work that even when the silicon wafer loses nearly 20% of its back side area by digging down to a depth of 100 μm to form various hole patterns and intersecting trench grids, the device resistance does not decrease significantly. One possible reason is that the model does not adequately consider the complex and uneven chip topography and thus the harmful effects on the current. Turbulence in the current results in higher local current density, higher ohmic heat, and higher power loss. And in high-frequency switching applications, adding a metal layer with a thickness exceeding the skin depth of the signal does not significantly reduce the total resistance.

[0006] The inventors have also found that during normal operation, very little current flows outside the central portion of the chip where the circuit elements are located, and the peripheral region outside the central portion of the chip has little effect on the total device resistance. Therefore, the inventors have sought to produce a chip that is thicker at the periphery of the chip in structure to enhance the mechanical strength of the chip, and thinner and flatter near the circuit elements to allow current to flow relatively unobstructed. When the thin and flat portion exceeds 60% of the chip area, a device resistance reduction of more than 50% has been achieved. Therefore, another aspect of the present invention is to completely achieve chip resistance reduction by providing a wall structure at the periphery of the chip so as not to impede the current flow near the central portion.

[0007] The present invention can be beneficially applied to many groups of semiconductor devices and ICs. Specifically, trench MOSFETs can benefit because in trench MOSFETs the main current flow path passes through the thickness of the chip.

[0008] Another class of devices that can benefit from the present invention includes circuits in which trench MOSFETs are connected and current enters and exits the chip on the same chip surface (e.g., the top surface of the chip). An example is a circuit in which two trench MOSFETs are connected in series. In such devices, the backside metal layer connects the two MOSFETs, so the current passes through the thin chip twice.

[0009] Even in the most conventional ICs where the current flow is typically parallel to the top surface, a thin chip with a flat backside having a backside metal layer will provide a favorable current path (especially through the backside metal layer) to reduce device resistance and power dissipation.

[0010] Another aspect of the present invention is a process of encapsulating a semiconductor chip with a molding compound (such as epoxy resin) to further enhance the device package integrity. After the wafer has completed the front-end process, the encapsulation process begins by grinding the backside of the wafer to a suitable thickness. After grinding, a photoresist pattern depicting the wall structure surrounding the central portion of each die is applied to the backside of the wafer. Then, the semiconductor material in the region within the wall structure is removed, for example, by plasma etching. Currently, the inventors can typically etch a silicon wafer with a central portion of the chip being about 25 μm from the front chip surface, and also cover thinner chips.

[0011] A metal layer is applied to the entire backside of the thinned wafer. The metal layer can be multilayered, for example, titanium or titanium copper is sputtered on the bare silicon surface as a "bonding layer", and then a thick copper layer is plated to carry current. For some applications, this metal layer can be omitted.

[0012] After applying an optional metal layer, the wafer is encapsulated with a molding compound material that flows under the action of heat, pressure, or both heat and pressure to fill the barrel-shaped portion of the back side of the wafer, including the wall structure. The molding process restores the back side of the wafer to the flatness before etching to facilitate subsequent processing, such as dicing, electrical testing, and laser marking. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A perspective view depicting a chip embodying certain aspects of the present invention.

[0014] Figure 2 A cross-sectional view depicting a wafer at the start of a process embodying certain aspects of the present invention.

[0015] Figure 3 Depicting at a later stage after the wafer has been thinned by backside grinding in the process Figure 2 the wafer.

[0016] Figure 4 Depicting at a later stage in the process when a photoresist pattern is applied Figure 3 the wafer.

[0017] Figure 5 Depicting after performing a plasma etching process to form the wall structure Figure 4 the wafer.

[0018] Figure 6 Depicting at a later stage in the process after forming the backside metal layer Figure 5 the wafer.

[0019] Figure 7 Depicting at a later stage in the process after filling the back side of the wafer with a molding compound layer and providing a smooth and flat surface Figure 6 the wafer.

[0020] Figure 8 Depicting after cutting the semiconductor device from the wafer along the middle of the wall structure Figure 7 the semiconductor device.

[0021] Definition

[0022] The terms used in the present invention generally have their ordinary meaning in the context of the present invention in the art. Certain terms are discussed below to provide additional guidance to practitioners regarding the description of the present invention. It will be understood that the same thing can be described in more than one way. Thus, alternative language and synonyms may be used.

[0023] A semiconductor device in this document refers to a device containing semiconductor materials. The materials can be a single element in Group IV of the periodic table, such as silicon, germanium, and carbon; and compounds, such as gallium nitride and silicon carbide. The semiconductor material in a semiconductor device is usually in the form of a chip. The device may contain more than one chip in a multi-chip package. One or more chips are usually encapsulated by a protective material (such as metal, ceramic, or epoxy resin).

[0024] A chip in this document refers to a small piece of semiconductor material in which circuit elements are embedded. A chip is usually square and has two main opposite surfaces of the main crystal plane. In this document, the term chip can be used interchangeably with the term die.

[0025] In this document, terms such as top, bottom, and side (such as the top surface of the device, the top surface of the chip, and the side of the chip) are used with reference to the accompanying drawings and should not be regarded as indicating directional limitations when describing a physical device.

[0026] In this document, the term central portion (e.g., "in the central portion of the chip") means a general area in the chip away from the chip edge. In a conventional chip design layout, circuit elements and the wiring between the elements are arranged in the central portion because mechanical cutting at the end of the assembly process causes the semiconductor crystal structure to break and generate "crystalline defects". The influence of such defects spreads from the edge inward. To ensure that the device operates as designed, the circuit elements are kept away from the peripheral area of the chip.

[0027] In this document, the term "varying" refers to a measured value that changes with the position or time of measurement, as opposed to being constant. The change can be gradual or can be stepwise.

[0028] In this document, terms such as orthogonal, linear, flat, and uniform are regarded as descriptions of an article. In the sense that there are manufacturing and measurement tolerances, the terms are not necessarily mathematical.

[0029] In this document, circuit elements refer to electrical components that can be coupled together to form a circuit, such as p-n junctions, transistors, diodes, rectifiers, resistors, capacitors, and inductors, as well as conductive wiring.

[0030] In this document, the term device resistance refers to the measured resistance of a circuit element when properly biased. For example, when a p-n junction diode is forward-biased, the device resistance is the ratio of the voltage across the diode terminals to the current through the junction.

[0031] In this document, the term "front end" refers to the following part of semiconductor device manufacturing: starting at a new wafer, passing through the fabrication of circuit elements embedded in the wafer, and customarily ending with the application of a passivation layer on the wafer. The term "back end" refers to the following part of semiconductor device manufacturing: starting when the front end process is completed, and customarily including steps such as back grinding, die bonding, wire bonding, molding, cutting, testing, and laser marking. The processes disclosed in this document include front end process steps and back end process steps.

[0032] In this document, the term "wall structure" refers to a structure that is placed on the edge of a chip and is an integral part of the chip to enhance the mechanical strength of the chip. The wall structure has an outer surface that intersects the top surface of the chip and defines the outer edge of the chip. When the wall structure is formed by plasma etching, the intersection of the vertical portion of the wall with the bottom surface of the chip is curved, as depicted in the figure.

[0033] In this document, the term "enclosure" refers to setting a wall structure around the edge of a chip so that it surrounds the central part of the chip. In some embodiments, the wall structure does not completely seal the central part of the chip and allows gaps to exist in the wall segments.

[0034] In this document, the term "near the top surface of the chip" refers to the location where circuit elements are embedded in a semiconductor chip. Customarily, at the front end, circuit elements are installed in the chip by introducing foreign materials (including selected impurity elements) from the top surface of the chip into the interior of the chip and adding thin films on the top surface. Therefore, the circuit elements are generally placed near the top surface of the chip.

[0035] In this document, the term "height" generally refers to the length of a structural element measured from a reference point. For example, in an embodiment of the present invention that includes a wall structure in a chip, the height of the outer surface of the chip is referenced to the top surface of the chip and the height of the inner surface of the chip is referenced to the bottom surface of the chip. Detailed Description

[0036] Figure 1 A perspective view depicting a semiconductor device 900 embodying certain aspects of the present invention is shown. In this embodiment, elements 20 and 25 are silicon, where element 25 is a substrate layer and element 20 is an epitaxial layer grown on top of the substrate layer 25. The resistivity of the epitaxial layer 20 is higher than the resistivity of the substrate 25. Layers 20 and 25 combine to form the semiconductor chip of the device 900. Layer 40 is a metal layer and is referred to as the backside metal layer, which makes an ohmic contact with the backside of the silicon chip. Layer 50 is a non-conductive layer, and in this embodiment, layer 50 includes a molding compound, a mixture of an epoxy resin material with filler particles. Layer 50 has a flat and smooth backside suitable for laser marking.

[0037] In this embodiment, the silicon chip contains a pair of trench MOSFET devices 103a and 103b. The drain nodes of the two MOSFETs are electrically connected at the backside metal layer 40. The source nodes of the two MOSFETs 103a and 103b can be accessed through two sets of metal pads S1s and S2s. The gate nodes can be accessed through metal pads g1 and g2. Other device elements can also be fabricated in the silicon chip to form different integrated circuits.

[0038] In Figure 1 the embodiment depicted, the edges of the silicon chip are exposed. In other embodiments, the edges can be further covered with a protective material (such as an epoxy-like material of layer 50). The process of fabricating the semiconductor device will be described in more detail in the following paragraphs in conjunction with the figures.

[0039] Figure 2 A cross-sectional view of the wafer 200 at a fabrication stage after the previous process is completed is depicted. The section labeled D shows the part of the wafer that will be cut off at the end of the fabrication process to become part of an individual chip. In the middle of chip D is the section labeled C, which is the central part of the chip, and the two sections labeled P are the peripheral parts of the chip. The span of part C depends on the complexity of the circuit and the process technology node and can range from a few millimeters to a few centimeters. At this stage of the process, the circuit elements embedded in the wafer have been fabricated. For illustrative purposes, Figure 2 it includes four circuit elements 101, 102, 103a, and 103b. In other embodiments of the present invention, the chip can have as few as a single circuit element (such as a p-n junction diode) or have over a billion transistors. In this embodiment, all the circuit elements are embedded in an epitaxial layer 20 less than about 10 μm thick. Other embodiments can have thinner or thicker epitaxial layers. In this embodiment, the substrate layer 25, whose thickness varies according to the diameter of the wafer, is about 300 μm thick. The circuit elements 103a and 103b are two trench MOSFETs and are designed to be connected at their drain nodes. The current path in the trench MOSFETs is mainly perpendicular to the thickness of the chip, and the method of fabricating trench MOSFETs in silicon is well-known in the art. The circuit element 102 is a vertical MOSFET, where the source node is connected to the backside of the chip where a metal layer will be placed later. The circuit element 101 is a "surface device" such as a rectifier, and all its terminal nodes can be accessed from the top surface of the device, and the current path in the device is mainly parallel to the chip surface.

[0040] Figure 3 Depicted after thinning using a mechanical grinding step known in the art Figure 2The wafer in it. In this embodiment, the substrate layer 25 is thinned from its original thickness of about 300 μm to about 150 μm. The starting thickness and the final thickness are for illustrative purposes only and the thicknesses may be different in other embodiments.

[0041] Figure 4 Depicts the wafer after the photoresist pattern 410 is applied to the back side of the wafer Figure 3 The wafer in it. The photoresist pattern depicts a wall structure enclosing the central portion C in each chip. In this embodiment, the photoresist pattern includes orthogonal grid lines and linear grid lines that are about 300 μm wide. In other embodiments, the pattern may vary to include structures in the central portion of the chip that increase the mechanical strength of the chip.

[0042] Figure 5 Depicts the wafer after the silicon undergoes a plasma etching process Figure 4 The wafer in it. Through this process, the central portion of the chip is removed to produce a thin and flat central portion enclosed by a wall structure 35 located at the peripheral portion. In this embodiment, the etchant is a chemical in a plasma state that reacts with the wafer in a sealed chamber with controlled pressure and temperature. In this embodiment, the final thickness of the silicon at the flat portion of the chip is about 25 μm, which includes an epitaxial layer 20 that maintains the original thickness and a portion of the substrate layer 35. The process is similar to the through-silicon via etching process known in silicon process technology. After the plasma etching, the photoresist pattern 410 is removed using an oxidizer.

[0043] As Figure 5 Depicted in it, in this embodiment the wall structure has a cylindrical lower portion and an epitaxial portion towards the central portion of the chip, and the epitaxial portion has a varying thickness greater than the chip thickness near the central portion of the chip.

[0044] Figure 6 Depicts the wafer after the metal layer 40 is applied to the structured back side of the silicon chip Figure 5 The wafer in it. The application method is generally known in wafer processing technology. Wafer processing technology may include sputtering and plating. The metal layer 40 may include multiple different metals with different thicknesses for different purposes. For example, a thin sputtered titanium layer is suitable as a "bonding" layer to enhance the adhesion between the silicon chip surface and the metal. Other metals such as aluminum and aluminum doped with copper may be applied on top of the bonding titanium layer. The metal layer 40 covers the flat portion C of the chip and the side surfaces and bottom of the lower edge of the wall structure 35.

[0045] Figure 7 Depicts the wafer after the molding compound 50 is applied to the back side of the wafer Figure 6 The wafer in it. The molding compound is applied in the form of a highly viscous liquid that flows under high temperature and pressure.

[0046] Figure 8 Depicts the semiconductor device 800 after being cut from the wafer by cutting along the middle of the wall structure 35. When cut off, the outer surface of the wall structure is not covered by the metal layer 40. Figure 1 A perspective view of the semiconductor device is depicted. The back surface of the molding compound is flat and smooth, so the surface is suitable for laser marking at a later stage of device manufacturing.

Claims

1. A semiconductor device, comprising: A semiconductor chip having a top surface, a bottom surface, and side surfaces of the chip; A first semiconductor layer having a first resistivity and a substrate located below the first semiconductor layer, the substrate having a second resistivity lower than the first resistivity; A circuit element disposed in the first semiconductor layer in a central portion of the chip near the top surface of the chip; A structure located in the substrate, the structure having a uniform first thickness at the central portion of the chip near the circuit element and a varying second thickness greater than the first thickness near the side surfaces of the chip remote from the circuit element; And A molded compound layer having a flat back surface that covers the structure having the uniform first thickness at the central portion of the chip near the circuit element.

2. The semiconductor device according to claim 1, further comprising: A linear wall structure disposed along the side surfaces of the chip, enclosing the central portion of the chip; The wall structure having an outer surface extending from the top surface of the chip toward the bottom surface of the chip and an extension portion toward the central portion of the chip; And The extension portion having a varying thickness.

3. The semiconductor device according to claim 2, further comprising a metal layer disposed between the molding compound layer and the bottom surface of the chip.

4. The semiconductor device according to claim 3, wherein an outer surface of the wall structure is not covered by the metal layer.

5. The semiconductor device according to claim 1, wherein the circuit element includes a rectifier.

6. The semiconductor device according to claim 5, wherein the rectifier includes two terminals accessible from the top surface of the chip.

7. The semiconductor device according to claim 1, wherein the circuit element includes a MOSFET.

8. The semiconductor device according to claim 7, wherein the MOSFET includes two terminals accessible from the top surface of the chip.

9. The semiconductor device according to claim 1, wherein the circuit element includes two MOSFETs.

10. The semiconductor device according to claim 9, wherein the two MOSFETs include four terminals accessible from the top surface of the chip and two terminals connected by a backside metal layer at the back surface of the chip.

11. The semiconductor device according to claim 2, wherein the wall structure includes a section of the first semiconductor layer and a section of the substrate.

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