Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method for manufacturing the semiconductor memory device, the device comprising: a peripheral logic structure on a substrate; a horizontally conductive substrate on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked in a vertical direction; a board contact plug connected to the horizontally conductive substrate; and a first through electrode connected to a lower interconnect wiring body, wherein an upper surface of the board contact plug and an upper surface of the first through electrode are located in the same plane, the board contact plug includes an upper portion and a lower portion directly connected to each other, the first through electrode includes an upper portion and a lower portion directly connected to each other, the upper surface of the board contact plug and the upper surface of the first through electrode are moved away from the board contact plug, the width of the upper portion increases and the width of the lower portion decreases.

Description

[0001] Cross-references to related applications

[0002] The entire contents of Korean Patent Application No. 10-2020-0031419, entitled "Semiconductor Memory Device and Method of Fabricating the Same", filed on March 13, 2020 with the Korean Intellectual Property Office, are incorporated herein by reference. Technical Field

[0003] The embodiments relate to semiconductor memory devices and methods of manufacturing the same. Background Technology

[0004] To achieve superior performance and low prices for consumers, the integration density of semiconductor devices can be increased. In the case of semiconductor devices, integration density can be a significant factor determining product price; therefore, increasing integration density is particularly desirable. In the case of two-dimensional or planar semiconductor devices, integration density may be primarily determined by the area occupied by a single memory cell, and it can be greatly influenced by the level of fine patterning technology. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor memory device, the semiconductor memory device comprising: a peripheral logic structure including peripheral circuitry and a lower interconnect wiring body, the peripheral logic structure being located on a substrate; a horizontal conductive substrate located on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked vertically on the horizontal conductive substrate; a board contact plug connected to the horizontal conductive substrate and extending along the vertical direction; and a first through electrode connected to the lower interconnect wiring body and extending along the vertical direction, wherein the upper surface of the board contact plug and the upper surface of the first through electrode are located on the same plane, the board contact plug including a lower interconnect wiring body. The first penetrating electrode comprises an upper and a lower portion directly connected to each other. Moving away from the upper surface of the first penetrating electrode along the vertical direction, the width of the upper portion of the first penetrating electrode, measured in a horizontal direction orthogonal to the vertical direction, increases. Moving away from the upper surface of the plate contact plug along the vertical direction, the width of the upper portion of the plate contact plug, measured in the horizontal direction, increases. Moving away from the upper surface of the plate contact plug along the vertical direction, the width of the lower portion of the plate contact plug, measured in the horizontal direction, decreases. Moving away from the upper surface of the first penetrating electrode along the vertical direction, the width of the lower portion of the first penetrating electrode, measured in the horizontal direction, decreases.

[0006] An embodiment can be implemented by providing a semiconductor memory device, the semiconductor memory device comprising: a peripheral logic structure including peripheral circuitry and a lower interconnect wiring body, the peripheral logic structure being located on a substrate; a horizontally conductive substrate located on the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked vertically on the horizontally conductive substrate; a first board contact plug connected to the horizontally conductive substrate and extending along the vertical direction; a first through electrode connected to the lower interconnect wiring body and extending along the vertical direction; and a second through electrode penetrating... The stacked structure is connected to the lower connection wiring body, wherein the first penetrating electrode and the first plate contact plug do not penetrate the stacked structure, the upper surface of the first plate contact plug, the upper surface of the first penetrating electrode and the upper surface of the second penetrating electrode are located on the same plane, the plane at the maximum width of the first penetrating electrode is higher than the plane at the maximum width of the second penetrating electrode relative to the upper surface of the horizontal conductive substrate in the vertical direction, and the plane at the maximum width of the first penetrating electrode and the plane at the maximum width of the first plate contact plug are located at the same vertical height relative to the upper surface of the horizontal conductive substrate in the vertical direction.

[0007] An embodiment can be implemented by providing a semiconductor memory device, the semiconductor memory device comprising: a peripheral logic structure including peripheral circuitry and a lower interconnect wiring body, the peripheral logic structure being located on a substrate; a horizontal conductive substrate extending along the upper surface of the peripheral logic structure; a stacked structure including a plurality of electrode pads stacked vertically on the horizontal conductive substrate; a plurality of vertical structures penetrating the stacked structure and electrically connected to the horizontal conductive substrate; a vertical structure support film located between the stacked structure and the horizontal conductive substrate and in contact with the vertical structures; a plurality of electrode plugs connected to the plurality of electrode pads; and a board contact plug connected to the... The device comprises a horizontal conductive substrate extending along the vertical direction; and a first penetrating electrode connected to the lower interconnect wiring body and extending along the vertical direction, wherein the upper surface of the plate contact plug and the upper surface of the first penetrating electrode are located on the same plane, the height from the plane where the plate contact plug has its maximum width to the upper surface of the plate contact plug in the vertical direction is a first height, the height from the plane where the first penetrating electrode has its maximum width to the upper surface of the first penetrating electrode in the vertical direction is a second height, the height of the first penetrating electrode in the vertical direction is H, both the first height and the second height are greater than 0, and the difference between the first height and the second height is greater than or equal to 0 and less than or equal to 0.0015 × H.

[0008] An embodiment can be implemented by providing a semiconductor memory device, the semiconductor memory device comprising: a peripheral logic structure including peripheral circuitry and a lower interconnect wiring body, the peripheral logic structure being located on a substrate; a horizontal conductive substrate extending along the upper surface of the peripheral logic structure; a metal plate extending along the lower surface of the horizontal conductive substrate, the metal plate being located between the lower interconnect wiring body and the horizontal conductive substrate; a stacked structure including a plurality of electrode pads stacked vertically on the horizontal conductive substrate; a board contact plug connected to the horizontal conductive substrate and extending along the vertical direction; and a through electrode connected to the lower interconnect wiring body and extending along the vertical direction, wherein the upper surface of the board contact plug and the upper surface of the through electrode are located on the same plane.

[0009] An embodiment can be implemented by providing a method for manufacturing a semiconductor memory device, the method comprising: forming a horizontal conductive substrate on a peripheral logic structure including peripheral circuitry and a lower interconnect wiring body; forming a stacked structure including a plurality of stacked electrode pads and an interlayer insulating film covering the stacked structure on the horizontal conductive substrate; forming electrode plug holes in the interlayer insulating film for exposing the plurality of electrode pads; forming an insulating pad film along the upper surface of the interlayer insulating film and the contour of the electrode plug holes; simultaneously forming a board contact hole and a through electrode hole in the insulating pad film and the interlayer insulating film, such that the board contact hole exposes the horizontal conductive substrate and the through electrode hole exposes the lower interconnect wiring body; and forming an electrode plug, a board contact plug and a through electrode filling the electrode plug holes, the board contact holes and the through electrode holes, wherein, relative to the upper surface of the horizontal conductive substrate in the vertical direction, the plane at the maximum width of the through electrode hole is at the same vertical height as the plane at the maximum width of the board contact hole. Attached Figure Description

[0010] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, wherein:

[0011] Figure 1 This is a block diagram of a semiconductor memory device according to some embodiments;

[0012] Figure 2 This is a perspective view of the outline of a semiconductor memory device according to some embodiments;

[0013] Figure 3 This is a circuit diagram of one of a plurality of memory cell blocks included in a semiconductor memory device according to some embodiments;

[0014] Figure 4 It is a layout diagram of a semiconductor memory device according to some embodiments;

[0015] Figure 5 It is along Figure 4 A cross-sectional view taken from line AA;

[0016] Figures 6 to 9 yes Figure 5 Enlarged views of parts P, Q, R, and S;

[0017] Figure 10 This is an enlarged cross-sectional view of a semiconductor memory device according to some embodiments;

[0018] Figure 11 This is a cross-sectional view of a semiconductor memory device according to some embodiments;

[0019] Figure 12This is a cross-sectional view of a semiconductor memory device according to some embodiments;

[0020] Figure 13 This is a cross-sectional view of a semiconductor memory device according to some embodiments;

[0021] Figure 14 and Figure 15 This is a cross-sectional view of a semiconductor memory device according to some embodiments;

[0022] Figures 16 to 19 These are cross-sectional views of various stages in a method for manufacturing a semiconductor memory device according to some embodiments; and

[0023] Figure 20 This is a cross-sectional view of one stage of a method for manufacturing a semiconductor memory device according to some embodiments. Detailed Implementation

[0024] Figure 1 This is a block diagram of a semiconductor memory device according to some embodiments.

[0025] Reference Figure 1 According to some embodiments, the semiconductor memory device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0026] The memory cell array 20 may include multiple memory cell blocks BLK1 to BLKn. Each memory cell block BLK1 to BLKn may include multiple memory cells. Memory cell blocks BLK1 to BLKn may be connected to the peripheral circuitry 30 via bit line BL, word line WL, at least one serial select line SSL, and at least one ground select line GSL.

[0027] In one embodiment, memory blocks BLK1 to BLKn can be connected to the row decoder 33 via word line WL, at least one string select line SSL, and at least one ground select line GSL. Furthermore, memory blocks BLK1 and BLKn can be connected to the page buffer 35 via bit line BL.

[0028] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from the external device of semiconductor memory device 10, and can send data DATA to and receive data DATA from external devices of semiconductor memory device 10. Peripheral circuitry 30 may include control logic 37, a line decoder 33, and a page buffer 35.

[0029] In one embodiment, the peripheral circuit 30 may further include various sub-circuits, such as input / output circuits, voltage generating circuits that generate various voltages for the operation of the semiconductor memory device 10, and error correction circuits for correcting errors in the data DATA read from the memory cell array 20.

[0030] Control logic 37 can be connected to line decoder 33, voltage generator, and input / output circuitry. Control logic 37 can control the overall operation of semiconductor memory device 10. Control logic 37 can generate various internal control signals used in semiconductor memory device 10 in response to control signal CTRL.

[0031] In one implementation, when a memory operation such as a programming operation or an erasure operation is performed, control logic 37 can adjust the voltage levels supplied to the word line WL and the bit line BL.

[0032] The row decoder 33 can select at least one of a plurality of memory cell blocks BLK1 to BLKn in response to address ADDR, and can select at least one word line W, at least one serial select line SSL, and at least one ground select line GSL of the selected memory cell block BLK1 to BLKn. The row decoder 33 can transmit the voltage for performing the memory operation to the word line WL of the selected memory cell block BLK1 to BLKn.

[0033] Page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can be used as a write driver or a sense amplifier. In one embodiment, during a programming operation, page buffer 35 acts as a write driver and can apply a voltage to bit line BL according to the data DATA to be stored in memory cell array 20. In one embodiment, during a read operation, page buffer 35 acts as a sense amplifier and can sense the data DATA stored in memory cell array 20.

[0034] Figure 2 This is a perspective view of the outline of a semiconductor memory device according to some embodiments.

[0035] Reference Figure 2 According to some embodiments, a semiconductor memory device may include a peripheral logic structure PS and a cell array structure CS.

[0036] The cell array structure CS can be stacked on the peripheral logic structure PS. In one embodiment, from a planar perspective, the peripheral logic structure PS and the cell array structure CS can overlap each other. Semiconductor memory devices according to some embodiments can have a COP (Cell Over Periphery) structure.

[0037] In one embodiment, the cell array structure CS may include Figure 1 The storage cell array 20. The peripheral logic structure PS may include Figure 1 30. Peripheral circuit.

[0038] The cell array structure CS may include multiple memory cell blocks BLK1 to BLKn disposed on the peripheral logic structure PS.

[0039] Figure 3 This is a circuit diagram of one of a plurality of memory cell blocks included in a semiconductor memory device according to some embodiments.

[0040] Reference Figure 3 According to some embodiments, a memory cell block may include a common source line CSL, multiple bit lines BL, and multiple cell strings CSTR disposed between the common source line CSL and the bit lines BL.

[0041] Multiple cell strings (CSTRs) can be connected in parallel to each of the bit lines BL0 to BL2. Multiple cell strings (CSTRs) can also be connected to a common source line (CSL). That is, multiple cell strings (CSTRs) can be positioned between multiple bit lines BL0 to BL2 and a single common source line (CSL). Multiple common source lines (CSLs) can be configured in two dimensions. Here, the same voltage can be applied to the common source line (CSL), or each common source line (CSL) can be electrically controlled.

[0042] In one embodiment, each cell string CSTR may include series-connected string select transistors SST1 and SST2, series-connected memory cells MCT, and a ground select transistor GST. In one embodiment, each memory cell MCT includes a data storage element.

[0043] In one embodiment, each cell string CSTR may include a first string select transistor SST1 and a second string select transistor SST2 connected in series, the second string select transistor SST2 may be connected to bit lines BL0 to BL2, and a ground select transistor GST may be connected to the common source line CSL. The memory cell MCT may be connected in series between the first string select transistor SST1 and the ground select transistor GST.

[0044] Additionally, each cell string CSTR may include a dummy cell DMC connected between the first string select transistor SST1 and the memory cell MCT. In one embodiment, the dummy cell DMC may also be connected between the ground select transistor GST and the memory cell MCT. In one embodiment, similar to the first string select transistor SST1 and the second string select transistor SST2, the ground select transistor GST in each cell string CSTR may include a plurality of MOS transistors connected in series. In one embodiment, each cell string CSTR may include a single string select transistor.

[0045] In one implementation, the first string select transistor SST1 can be controlled by a first string select line SSL1, and the second string select transistor SST2 can be controlled by a second string select line SSL2. The memory cell MCT can be controlled by multiple word lines WL0 to WLn, and the dummy cell DMC can be controlled by a dummy word line DWL. Additionally, the ground select transistor GST can be controlled by a ground select line GSL. The common source line CSL can be commonly connected to the source of the ground select transistor GST.

[0046] A single cell string (CSTR) may include multiple memory cells (MCTs) at different distances from the common source line (CSL). Furthermore, multiple word lines (WL0 to WLn) and DWL may be positioned between the common source line (CSL) and bit lines (BL0 to BL2).

[0047] The gate electrode of a memory cell MCT, which is at approximately the same distance from the common source line CSL, is connected to one of the word lines WL0 to WLn and DWL, and can be at the same potential. In contrast, even if the gate electrode of the memory cell MCT is at approximately the same horizontal level as the common source line CSL, gate electrodes located in different rows or columns can be controlled independently.

[0048] Ground select lines GSL0 to GSL2 and series select lines SSL1 and SSL2 may extend, for example, in the same direction as word lines WL0 to WLn and DWL. Ground select lines GSL0 to GSL2 and series select lines SSL1 and SSL2, which are at substantially the same horizontal level as the common source line CSL, may be electrically isolated from each other.

[0049] Figure 4 This is a layout diagram of a semiconductor memory device according to some embodiments. Figure 5 It is along Figure 4 The cross-sectional view taken from line AA. Figures 6 to 9 yes Figure 5 Enlarged views of parts P, Q, R, and S.

[0050] Reference Figure 4According to some embodiments, a semiconductor memory device may include a peripheral logic structure PS, a horizontal conductive substrate USB, and a stacked structure ST.

[0051] The stacked structure ST includes the cell array region CR and the cell extension region CER.

[0052] A storage cell array comprising multiple storage cells (e.g., Figure 1 20) can be formed in the cell array region CR. In one embodiment, the vertical structure VS and bit line BL, which will be described below, can be formed in the cell array region CR.

[0053] The cell extension region CER can be located around the cell array region CR. In one embodiment, the cell array region CR and the cell extension region CER can extend along the direction of the block separator region WLC. In one embodiment, the cell array region CR and the cell extension region CER can extend along a second (e.g., horizontal) direction D2. Multiple electrode pads EP1 to EP8, described below, can be progressively stacked within the cell extension region CER.

[0054] The stacked structure ST may include blocks of storage cells (e.g., BLK1 to BLKn) separated by block separation regions (WLC).

[0055] In one implementation, the cell extension region CER can be located on one side of the cell array region CR, such as... Figure 4 As shown. In one embodiment, the cell extension region CER can be disposed on both sides of the cell array region CR, with the cell array region CR situated between the cell extension regions CER.

[0056] In one implementation, a single stacked structure ST may be located on a peripheral logic structure PS. In one implementation, two or more stacked structures ST may be located on a peripheral logic structure PS.

[0057] The first through-electrode region THV_R1 may be defined by a peripheral logic structure PS that does not overlap with the horizontal conductive substrate USB in a third (e.g., vertical) direction D3. The first through-electrode region THV_R1 may extend along a first (e.g., horizontal) direction D1.

[0058] The second penetrating electrode region THV_R2 can be defined by the stacked structure ST. In one embodiment, the second penetrating electrode region THV_R2 can be defined as a region extending along the second direction D2. In one embodiment, the second penetrating electrode region THV_R2 can be defined only in the cell array region CR, and not in the cell extension region CER. In one embodiment, the second penetrating electrode region THV_R2 can be defined in all memory cell blocks BLK1 to BLKn.

[0059] A board contact plug region PCC_R may be defined on a horizontally conductive substrate USB that does not overlap with the stacked structure ST. The board contact plug region PCC_R may extend along a first direction D1. The board contact plug region PCC_R is defined to be closer to the stacked structure ST than the first through electrode region THV_R1.

[0060] The first penetrating electrode region THV_R1 and the second penetrating electrode region THV_R2 can be provided with penetrating electrodes. Figure 5 The area (THV1 and THV2). The board contact plug area PCC_R can be a region where board contact plugs are provided ( Figure 5 The PCC1 region. Below is... Figure 5 This will be described in more detail in the description.

[0061] Reference Figures 4 to 9 According to some embodiments, the semiconductor memory device 10 may include a peripheral logic structure PS and a cell array structure CS.

[0062] The peripheral logic structure PS may include the peripheral circuit PTR, the lower connection wiring body PW, and the peripheral logic insulating film 110.

[0063] The peripheral circuit PTR can be located on the substrate 100. The peripheral circuit PTR can be included in... Figure 1 The page buffer 35 may be included in or may be included in Figure 1 In the line decoder 33.

[0064] Substrate 100 may be bulk silicon or SOI (silicon-on-insulator). In one embodiment, substrate 100 may be a silicon substrate, or may include other materials, such as silicon germanium, SGOI (silicon germanium-on-insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. As used herein, the term "or" is not an exclusive term; for example, "A or B" would include A, B, or A and B.

[0065] A peripheral logic insulating film 110 may be formed on the substrate 100. The peripheral logic insulating film 110 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. Low dielectric constant materials may include, for example, fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethyl ethyl cyclotetrasiloxane (OMCTS), hexamethyl disiloxane (HMDS), trimethyl silyl borate (TMSB), diacetoxy diterpene butyl siloxane (DADBS), trimethyl silyl phosphate (TMSP), polytetrafluoroethylene (PTFE), and tonofluoropolymer (TOSZ). SilaZen, FSG (fluorosilicate glass), polyimide nanofoam (such as polypropylene oxide), CDO (carbon-doped silicon dioxide), OSG (organosilicon glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica dry gel, mesoporous silica, or combinations thereof.

[0066] The lower connection wiring body PW can be located within the peripheral logic insulating film 110. The lower connection wiring body PW can be connected to the peripheral circuit PTR.

[0067] The cell array structure CS may include a horizontally conductive substrate USB located on the peripheral logic structure PS and a stacked structure ST located on the horizontally conductive substrate USB.

[0068] The horizontally conductive substrate USB can be located on the peripheral logic structure PS. The horizontally conductive substrate USB may include a first opening OP1. The first opening OP1 may expose a portion of the peripheral logic structure PS or be open to a portion of the peripheral logic structure PS.

[0069] The horizontally conductive substrate USB can be a common source plate. In one embodiment, the horizontally conductive substrate USB can be used as... Figure 3 The common source line CSL.

[0070] The horizontally conductive substrate USB can include a conductive semiconductor film, a metal silicide film, or a metal film. If the horizontally conductive substrate USB includes a conductive semiconductor film, it can include, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or combinations thereof. The horizontally conductive substrate USB can have a crystal structure including single-crystal, amorphous, or polycrystalline structures. The horizontally conductive substrate USB can include p-type impurities, n-type impurities, or carbon contained in the semiconductor film.

[0071] In one embodiment, the horizontal conductive substrate USB can be formed as a multilayer or a single layer.

[0072] The insulating filler 148 may be located on the peripheral logic structure PS. The insulating filler 148 may fill the first opening OP1. The insulating filler 148 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, or a low dielectric constant material.

[0073] The stacked structure ST can be located on the horizontally conductive substrate USB. The stacked structure ST can cover a portion of the horizontally conductive substrate USB.

[0074] In one embodiment, the horizontally conductive substrate USB may include a first region overlapping the stacked structure ST on the third-direction D3 and a second region not overlapping the stacked structure ST on the third-direction D3. The second region of the horizontally conductive substrate USB may include... Figure 4 The board contact plug area PCC_R.

[0075] The stacked structure ST may include multiple electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7, and EP8 stacked along a third direction D3. The stacked structure ST may include an inter-electrode insulating film (ILD) located between the multiple electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7, and EP8. In one embodiment, the stacked structure ST may include eight electrode pads, or a different number of electrode pads.

[0076] In one implementation scheme, such as Figure 5As shown, the thickness of the inter-electrode insulating film (ILD) between multiple electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7, and EP8 can be constant. In one embodiment, the thickness of at least one of the inter-electrode insulating films (ILDs) between the multiple electrode pads EP1 to EP8 can be more than twice the thickness of another inter-electrode insulating film (ILD). In one embodiment, the stacked structure ST can be divided into an upper stacked structure and a lower stacked structure based on the thickness of the inter-electrode insulating film (ILD). The vertical structure VS can include a stepped portion at the division into the upper and lower stacked structures.

[0077] Multiple electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7, and EP8 stacked along the third direction D3 may include those included in the above. Figure 3 The gate electrodes in the string select transistors SST1 and SST2 and the ground select transistor GST described herein. Additionally, multiple electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7, and EP8 stacked along the third direction D3 may include word lines of the memory cell MCT.

[0078] In one embodiment, the first stack structure ST1 may include a third electrode pad EP3, a fourth electrode pad EP4, and a fifth electrode pad EP5 that are adjacent to each other on a third-direction D3. The fourth electrode pad EP4 may be located between the third electrode pad EP3 and the fifth electrode pad EP5.

[0079] The fourth electrode pad EP4 may protrude from or beyond the fifth electrode pad EP5 along a first direction D1 by a first width or a first distance. In one embodiment, the third electrode pad EP3 may protrude from the fourth electrode pad EP4 by a second width along the first direction D1. In one embodiment, the sidewalls of the fourth electrode pad EP4 and the fifth electrode pad EP5 may be laterally spaced apart from each other by a first width along the first direction D1. The sidewalls of the third electrode pad EP3 and the fourth electrode pad EP4 may be laterally spaced apart from each other by a second width along the first direction D1.

[0080] In one embodiment, the first width may be greater than the second width. In a semiconductor memory device according to some embodiments, the stacked structure ST may include sub-stacked structures in which the sidewalls of adjacent electrode pads are spaced apart from each other by a second width. Additionally, the sidewalls of the nearest electrode pads in each sub-stacked structure may be spaced apart from each other by a first width.

[0081] In one embodiment, the portion of the fourth electrode pad EP4 protruding a first width from the fifth electrode pad EP5 along the first direction D1 can be defined as a flat pad region. In one embodiment, the cell extension region CER may include a flat pad region. The flat pad region may be in which a third through electrode, as described below, is disposed. Figure 13 The region of THV3.

[0082] In one implementation scheme, with Figure 5 The situation is different; adjacent electrode pads EP1 to EP8 can protrude by the same width along the first direction.

[0083] In one embodiment, electrode pads EP1 to EP8 may each comprise metals such as tungsten (W), cobalt (Co), and nickel (Ni), or semiconductor materials such as silicon. Electrode pads EP1 to EP8 may each be formed by, for example, a replacement process.

[0084] In one implementation scheme, including Figure 3 The gate electrodes of the string select transistors SST1 and SST2 and the ground select transistor GST, as well as the word lines of the memory cell MCT, described herein may comprise the same material.

[0085] In one implementation scheme, including Figure 3 The gate electrodes in the string select transistors SST1 and SST2 described herein may comprise materials different from those in the gate electrode of the ground select transistor GST and the word lines of the memory cell MCT. In one embodiment, the gate electrodes in the string select transistors SST1 and SST2 may comprise a semiconductor material such as silicon. The gate electrodes in the ground select transistor GST and the word lines of the memory cell MCT may comprise metal.

[0086] The stacked structure ST may include an insulating molded portion (IMS). The insulating molded portion (IMS) may overlap with the first opening OP1 of the horizontally conductive substrate USB on the third-direction D3. Figure 4 The second penetrating electrode region THV_R2.

[0087] The insulating molding portion (IMS) may include an inter-electrode insulating film (ILD) and a sacrificial molding insulating film (ILD_SC) having an etch selectivity. The inter-electrode insulating film (ILD) and the sacrificial molding insulating film (ILD_SC) may be stacked alternately. In one embodiment, the inter-electrode insulating film (ILD) may include silicon oxide, while the sacrificial molding insulating film (ILD_SC) may include silicon nitride.

[0088] Block separator regions (WLCs) can be set in the stacked structure ST. The block separator regions (WLCs) can extend along the second direction D2. Each block separator region (WLC) can be spaced apart from each other in the first direction D1. Each block separator region (WLC) can completely cut through the stacked structure ST. The molded structure ST cut by two adjacent block separator regions (WLCs) can form a memory cell block BLK1 to BLKn.

[0089] The block-separated region WLC may include an insulating material. The block-separated region WLC may include, for example, silicon oxide. In one embodiment, the block-separated region WLC may include multiple films and may include a dual-film structure having a silicon nitride film and a silicon oxide film. In one embodiment, the block-separated region WLC may include a pad formed of an insulating material and a conductive material filling trenches defined by the pad.

[0090] Multiple vertical structures (VS) can be located on a horizontally conductive substrate (USB). Multiple vertical structures (VS) can penetrate the stacked structure (ST). Multiple vertical structures (VS) can be electrically connected to the horizontally conductive substrate (USB). Each vertical structure (VS) can include a sidewall portion extending along a third direction (D3) and a bottom portion connecting the sidewall portion of the vertical structure (VS). The sidewall portion of the vertical structure (VS) can have a tubular shape with a hollow interior, for example, cylindrical or macaroni-shaped.

[0091] The vertical structure VS can include, for example, semiconductor materials such as silicon (Si), germanium (Ge), or mixtures thereof. In one embodiment, the vertical structure VS can include semiconductor materials such as metal oxide semiconductor materials, organic semiconductor materials, and carbon nanostructured semiconductor materials.

[0092] In one implementation scheme, such as Figure 5 and Figure 9 As shown, the barrier insulating film (BIL), the charge storage film (CIL), and the tunneling insulating film (TIL) can be sequentially located between the vertical structure (VS) and the stacked structure (ST).

[0093] A vertical insulating film VI may be located on a vertical structure VS. The vertical insulating film VI may fill the space defined by the vertical structure VS. In one embodiment, a horizontal insulating pattern HP may be located between the electrode pad EP1 and the inter-electrode insulating film ILD and between the electrode pad EP1 and the barrier insulating film BIL. The horizontal insulating pattern HP may include, for example, silicon oxide or a high-dielectric-constant insulating film. In one embodiment, the horizontal insulating pattern HP may not be located between the electrode pad EP1 and the inter-electrode insulating film ILD, but may be located between the electrode pad EP1 and the barrier insulating film BIL.

[0094] The barrier insulating film (BIL), charge storage film (CIL), and tunneling insulating film (TIL) may be spaced apart from the lower portion of the vertical structure VS. The separated barrier insulating film BIL, charge storage film CIL, and tunneling insulating film TIL may expose a portion of the sidewall portion of the vertical structure VS. The vertical structure support film (CSB) may be located between the separated barrier insulating film BIL, charge storage film CIL, and tunneling insulating film TIL. The vertical structure support film CSB may electrically connect the horizontal conductive substrate USB and the vertical structure VS. The vertical structure support film CSB may comprise a semiconductor material such as silicon (Si), germanium (Ge), or mixtures thereof.

[0095] In one embodiment, the vertical structure support film CSB may not be located between the horizontal conductive substrate USB and the stacked structure ST. In this case, the sidewall portion of the vertical structure VS may not be exposed, but the bottom of the vertical structure VS may be exposed. The barrier insulating film BIL, charge storage film CIL, and tunneling insulating film TIL between the bottom of the vertical structure VS and the horizontal conductive substrate USB can be removed. The vertical structure VS can be electrically connected to the horizontal conductive substrate USB through the bottom of the vertical structure VS.

[0096] The first interlayer insulating film 142 can be located on the peripheral logic structure PS. The first interlayer insulating film 142 can cover the stacked structure ST1 and the horizontal conductive substrate USB.

[0097] The second interlayer insulating film 144 and the third interlayer insulating film 146 may be sequentially formed on the first interlayer insulating film 142. A portion of the block separator region WLC may extend into the second interlayer insulating film 144.

[0098] The first interlayer insulating film 142, the second interlayer insulating film 144, and the third interlayer insulating film 146 may comprise, for example, silicon oxide, silicon oxynitride, or a low dielectric constant material.

[0099] Bit line BL can be located on the stacked structure ST. Bit line BL can extend along the first direction D1. Bit line BL can be electrically connected to at least one of the multiple vertical structures VS.

[0100] Bit line BL can be located on the third interlayer insulating film 153. Bit line BL can be electrically connected to the vertical structure VS via bit line pad BL_PAD and bit line plug BL_PG. Bit line BL, bit line pad BL_PAD and bit line plug BL_PG all contain conductive material.

[0101] Multiple electrode plugs WL_PG can be located in the first to third interlayer insulating films 142, 144, and 146. Multiple electrode plugs WL_PG can be located in the cell extension region CER.

[0102] Each electrode plug WL_PG can be electrically connected to the corresponding electrode pads EP1 to EP8. The corresponding electrode plug WL_PG can connect the corresponding electrode pads EP1 to EP8 and the word line connection wiring WL_CW.

[0103] In one embodiment, the sidewalls of the electrode plug WL_PG can be linear, such as... Figure 5 and Figure 7 As shown. In one embodiment, at least a portion of the sidewall of the electrode plug WL_PG may have a convex curve shape.

[0104] The first through-electrode THV1 may be located in the first through-electrode region THV_R1. The first through-electrode THV1 may extend along the third direction D3. The first through-electrode THV1 may be located in the first to third interlayer insulating films 142, 144, and 146 and the peripheral logic insulating film 110. The first through-electrode THV1 may not penetrate the stacked structure ST. The first through-electrode THV1 may be connected to the lower connection wiring body PW and the first through-electrode connection wiring THV1_CW.

[0105] The first plate contact plug PCC1 may be located in the plate contact plug region PCC_R. The first plate contact plug PCC1 may extend along the third direction D3. The first plate contact plug PCC1 may be located in the first to third interlayer insulating films 142, 144 and 146. The first plate contact plug PCC1 may not penetrate the stacked structure ST.

[0106] The first board contact plug PCC1 can be connected to the horizontally conductive substrate USB. The first board contact plug PCC1 can be electrically connected to the horizontally conductive substrate USB in a second region of the horizontally conductive substrate USB. The first board contact plug PCC1 can be connected to the first board contact connection wiring PCC1_CW. A portion of the first board contact plug PCC1 can be located within the horizontally conductive substrate USB.

[0107] The second through electrode THV2 can be located in the second through electrode region THV_R2. The second through electrode THB2 can extend along the third direction D3. The second through electrode THV2 can be located in the insulating molding portion IMS, the filling insulating film 148, and the peripheral logic insulating film 110. The second through electrode THV2 can penetrate the stack structure ST, for example, the insulating molding portion IMS. The second through electrode THV2 can be located in the cell array region CR. The second through electrode THV2 can pass through the first opening OP1. The second through electrode THV2 can be connected to the lower connection wiring body PW and the second through electrode connection wiring THV2_CW.

[0108] In one embodiment, the upper surface 201us of the first penetrating electrode THV1 (e.g., the surface facing away from the substrate 100 on the third-direction D3) and the upper surface 211us of the first plate contact plug PCC1 may be located on the same plane (e.g., they may be coplanar). In one embodiment, the upper surface 211us of the first plate contact plug PCC1 may be located on the same plane as the upper surface 203us of the second penetrating electrode THV2. The upper surfaces 215us of the plurality of electrode plugs WL_PG may be located on the same plane as the upper surface 211us of the first plate contact plug PCC1.

[0109] exist Figure 5 and Figure 6 In this design, the first penetrating electrode THV1 may include an upper portion 201 and a lower portion 202 that are directly connected to each other (e.g., forming a continuous or integral structure). The first penetrating electrode THV1 may include a first _1 boundary IFL11 at which the upper portion 201 and the lower portion 202 form a boundary. Moving away from the upper surface 201us of the first penetrating electrode THV1 along a third direction D3 (e.g., toward the substrate 100), the width of the upper portion 201 of the first penetrating electrode (e.g., in the horizontal direction) may increase. Moving away from the upper surface 201us of the first penetrating electrode THV1 along a third direction D3 (e.g., toward the substrate 100), the width of the lower portion 202 of the first penetrating electrode may decrease. In a direction extending away from the upper surface 201us of the first penetrating electrode THV1 along the third direction D3 (e.g., toward the substrate 100), the width of the first penetrating electrode THV1 may increase and then decrease (e.g., on either side of the first _1 boundary IFL11). For example, the first penetrating electrode THV1 can have a gradually narrowing shape, with its width increasing until the first _1 boundary IFL11, and then the width decreasing.

[0110] At the first _1 boundary IFL11, the first penetrating electrode THV1 may have a maximum width (e.g., width in the first direction D1). The height from the point or plane where the first penetrating electrode THV1 has the maximum width (e.g., the first _1 boundary IFL11) to the upper surface of the first penetrating electrode THV1 (e.g., in the third direction D3) may be a first height H21. At least a portion of the sidewall of the first penetrating electrode THV1 may include a convex curved surface. The first _1 boundary IFL11 where the first penetrating electrode THV1 has the maximum width may be located at the portion of the first penetrating electrode THV1 with the convex curved surface.

[0111] In one implementation scheme, such as Figure 5 and Figure 6As shown, the first plate contact plug PCC1 may include an upper portion 211 and a lower portion 212 directly connected to each other. The first plate contact plug PCC1 may include a second _1 boundary IFL21, at which the upper portion 211 and the lower portion 212 of the first plate contact plug form a boundary. Moving along a third direction D3 away from the upper surface 201us of the first penetrating electrode, the width of the upper portion 211 of the first plate contact plug may increase. Moving along a third direction D3 away from the upper surface 201us of the first penetrating electrode, the width of the lower portion 212 of the first plate contact plug may decrease. Moving along a third direction D3 away from the upper surface 211us of the first plate contact plug, the width of the first plate contact plug PCC1 may increase and then decrease (e.g., on the opposite side of the second _1 boundary IFL21).

[0112] The first plate contact plug PCC1 may have its maximum width at the second _1 boundary IFL21 (e.g., width in the first direction D1). The height from a point or plane of the second _1 boundary IFL21 (where the first plate contact plug PCC1 has its maximum width) to the upper surface 211us of the first plate contact plug (in the third direction D3) may be a second height H22. At least a portion of the sidewall of the first plate contact plug PCC1 may include a convex curved surface. The second _1 boundary IFL21 (where the first plate contact plug PCC1 has its maximum width) may be located at the portion of the first plate contact plug PCC1 with the convex curved surface.

[0113] like Figure 5 and Figure 8 As shown, the second penetrating electrode THV2 may include an upper portion 203 and a lower portion 204 directly connected to each other. The second penetrating electrode THV2 may include a first -2 boundary IFL12, at which the upper portion 203 and the lower portion 204 of the second penetrating electrode form a boundary. Moving along a third direction D3 away from the upper surface 203us of the second penetrating electrode, the width of the upper portion 203 of the second penetrating electrode may increase. Moving along a third direction D3 away from the upper surface 203us of the second penetrating electrode, the width of the lower portion 204 of the second penetrating electrode may decrease. Moving along a third direction D3 away from the upper surface 203us of the second penetrating electrode, the width of the second penetrating electrode THV2 may increase and then decrease.

[0114] The second penetrating electrode THV2 may have its maximum width at the first _2 boundary IFL12 (e.g., width in the first direction D1). The height from the point or plane of the first _2 boundary IFL12 where the second penetrating electrode THV2 has its maximum width to the upper surface of the second penetrating electrode 203 μs may be a third height H23. At least a portion of the sidewall of the second penetrating electrode THV2 includes a convex curved surface. The first _2 boundary IFL12 (where the second penetrating electrode THV2 has its maximum width) is located in the portion of the second penetrating electrode THV2 with the convex curved surface.

[0115] In one embodiment, based on or relative to the upper surface 201µs of the first penetrating electrode or the upper surface of the horizontal conductive substrate USB, the first _1 boundary IFL11 of the first penetrating electrode THV1 may be at the same vertical height as the second _1 boundary IFL21 of the first plate contact plug PCC1 (e.g., they may be coplanar). In one embodiment, the plane of the first penetrating electrode THV1 at its maximum width may be at the same vertical height as the plane of the first plate contact plug PCC1 at its maximum width.

[0116] Here, the term "same vertical height" not only refers to the case where the heights at the two locations being compared are exactly the same, but also to minor differences in height that may be caused by factors such as process allowance.

[0117] In one embodiment, when the relationship between the first height H21 in the first penetrating electrode THV1 and the second height H22 in the first plate contact plug PCC1 is as follows, it can be said that they are at "the same vertical height".

[0118] The height of the first penetrating electrode THV1 in the third direction D3 can be a first -1 height H1. The first height H21 at the first penetrating electrode THV1 and the second height H22 at the first plate contact plug PCC1 can both be greater than zero. The difference between the first height H21 and the second height H22 can be greater than or equal to zero. In one embodiment, the difference between the first height H21 and the second height H22 can be less than or equal to 0.15% of the first -1 height H1. In one embodiment, the difference between the first height H21 and the second height H22 can be less than or equal to H1 × 0.0015. In one embodiment, if the height H1 of the first penetrating electrode THV1 is 2,000 nm, and the difference between the first height H21 and the second height H22 is 3 nm, then the plane at the maximum width of the first penetrating electrode THV1 can be at the same vertical height as the plane at the maximum width of the first plate contact plug PCC1.

[0119] In one embodiment, the first -1 boundary IFL11 of the first penetrating electrode THV1 may be higher than the first -2 boundary IFL12 of the second penetrating electrode THV2 relative to the upper surface of the horizontally conductive substrate USB. In one embodiment, the plane at the maximum width of the first penetrating electrode THV1 may be higher than the plane at the maximum width of the second penetrating electrode THV2 (for example, the distance from the plane at the maximum width of the first penetrating electrode THV1 to the upper surface of the horizontally conductive substrate USB in the third direction D3 is greater than the distance from the plane at the maximum width of the second penetrating electrode THV2 to the upper surface of the horizontally conductive substrate USB).

[0120] In one embodiment, the first height H21 at the first penetrating electrode THV1 may be less than the third height H23 at the second penetrating electrode THV2.

[0121] exist Figures 6 to 8 In this design, the electrode plug WL_PG, the first penetrating electrode THV1, the second penetrating electrode THV2, and the first plate contact plug PCC1 may all include a blocking conductive film BML and a filling conductive film FML. The electrode plug WL_PG, the first penetrating electrode THV1, the second penetrating electrode THV2, and the first plate contact plug PCC1 may be formed at the same horizontal height. Here, the term "at the same horizontal height" means that they are formed using the same manufacturing process.

[0122] Electrode plug WL_PG, first penetrating electrode THV1, second penetrating electrode THV2, and first plate contact plug PCC1 may have the same conductive film stack structure. The blocking conductive film BML may include a metal, metal nitride, metal carbonitride, or a two-dimensional (2D) material. In one embodiment, the two-dimensional material may be a metallic material or a semiconductor material. The two-dimensional (2D) material may include a 2D allotrope or a 2D compound. The filling conductive film FML may include a metal, metal nitride, metal carbonitride, or a conductive semiconductor material.

[0123] In one embodiment, the electrode plug WL_PG, the first penetrating electrode THV1, the second penetrating electrode THV2, and the first plate contact plug PCC1 may consist only of a conductive film FML.

[0124] The first through-electrode connection wiring THV1_CW, the second through-electrode connection wiring THV2_CW, the first board contact connection wiring PCC1_CW, and the word line connection wiring WL_CW can all include conductive materials.

[0125] Figure 10 These are illustrations of semiconductor memory devices according to some embodiments. For ease of description, the description will primarily focus on usage. Figures 4 to 9 The differences in the content described. For reference, Figure 10 yes Figure 5 An enlarged view of the Q part.

[0126] Reference Figure 10 In a semiconductor memory device according to some embodiments, the electrode plug WL_PG may also include an insulating plug liner IPGL on the sidewall of the electrode plug WL_PG.

[0127] The insulating plug liner IPGL may extend along the sidewall of the electrode plug WL_PG. The insulating plug liner IPGL may include an insulating material, such as silicon carbide.

[0128] The insulating plug gasket IPGL may not be on the sidewall of the first penetrating electrode THV1, the sidewall of the second penetrating electrode THV2, or the sidewall of the first plate contact plug PCC1.

[0129] Figure 11 These are illustrations of semiconductor memory devices according to some embodiments. Figure 12 These are illustrations of semiconductor memory devices according to some embodiments. For ease of description, the description will primarily focus on usage. Figures 4 to 9 The differences in the content being described.

[0130] Reference Figure 11 and Figure 12 According to some embodiments, the semiconductor memory device may also include a metal plate film SMP located between the lower interconnect wiring body PW and the horizontal conductive substrate USB.

[0131] The metal plate film SMP can extend along the lower surface of the horizontal conductive substrate USB. The metal plate film SMP can include an opening at a location corresponding to the first opening OP1. In one embodiment, the metal plate film SMP can be in contact with the horizontal conductive substrate USB (e.g., direct contact). In one embodiment, the metal plate film SMP can be spaced apart from the horizontal conductive substrate USB on a third direction D3.

[0132] Metal sheet film SMP can include, for example, metal.

[0133] In one embodiment, the sidewalls of the metal plate film SMP can be aligned with the sidewalls of the horizontal conductive substrate USB on the third direction D3.

[0134] exist Figure 11 In this embodiment, a portion of the first plate contact plug PCC1 can be inserted into (e.g., partially through) the horizontally conductive substrate USB. In one embodiment, the first plate contact plug PCC1 may not be in direct contact with the metal plate film SMP.

[0135] exist Figure 12In this configuration, the first plate contact plug PCC1 can penetrate (e.g., completely penetrate) the horizontally conductive substrate USB. The first plate contact plug PCC1 can make direct contact with the metal plate film SMP.

[0136] Figure 13 These are illustrations of semiconductor memory devices according to some embodiments. For ease of description, the description will primarily focus on usage. Figures 4 to 9 The differences in the content being described.

[0137] Reference Figure 4 and Figure 13 According to some embodiments, the semiconductor memory device may also include a third through electrode THV3 located in the cell extension region CER.

[0138] The horizontally conductive substrate USB may include a second opening OP2. The second opening OP2 may be located at a position overlapping with the cell extension region CER.

[0139] The third through electrode THV3 can be located between electrode plugs WL_PG. The third through electrode THV3 can be located in the flat pad area of ​​the cell extension region CER. The electrode plugs WL_PG around the third through electrode THV3 can be, for example, dummy plugs not connected to the word line connection wiring WL_CW.

[0140] The third through electrode THV3 can be located in the first to third interlayer insulating films 142, 144, and 146, the alternately stacked inter-electrode insulating films ILD and sacrificial molded insulating films ILD_SC, the filling insulating film 148, and the peripheral logic insulating film 110. The third through electrode THV3 can penetrate the inter-electrode insulating films ILD and sacrificial molded insulating films ILD_SC of the cell extension region CER of the stacked structure ST. The third through electrode THV3 can pass through the second opening OP2. The third through electrode THV3 can be connected to the lower connection wiring body PW and the third through electrode connection wiring THV3_CW.

[0141] The upper surface 205us of the third penetrating electrode can be on the same plane as the upper surface 201us of the first penetrating electrode.

[0142] The third penetrating electrode THV3 may include an upper portion 205 and a lower portion 206 directly connected to each other. The third penetrating electrode THV3 may include a first _3 boundary IFL13, at which the upper portion 205 and the lower portion 206 of the third penetrating electrode form a boundary. Moving along the third direction D3 away from the upper surface 205us of the third penetrating electrode, the width of the upper portion 205 of the third penetrating electrode may increase. Moving along the third direction D3 away from the upper surface 205us of the third penetrating electrode, the width of the lower portion 206 of the third penetrating electrode may decrease. Moving along the third direction D3 away from the upper surface 205us of the third penetrating electrode, the width of the third penetrating electrode THV3 may increase and then decrease.

[0143] The third penetrating electrode THV3 has its maximum width at the first _3 boundary IFL13 (e.g., width in the first direction D1). The height from the plane of the first _3 boundary IFL13 where the third penetrating electrode THV3 has its maximum width to the upper surface of the third penetrating electrode (205 μs) can be a fourth height H24. At least a portion of the sidewall of the third penetrating electrode THV3 can include a convex curved surface. The first _3 boundary IFL13 where the third penetrating electrode THV3 has its maximum width can be located at the portion of the third penetrating electrode THV3 with the convex curved surface.

[0144] In one embodiment, the first -1 boundary IFL11 of the first penetrating electrode THV1 may be located at the same vertical height as the first -3 boundary IFL13 of the third penetrating electrode THV3, relative to the upper surface 201us of the first penetrating electrode or the upper surface of the horizontal conductive substrate USB.

[0145] The third penetrating electrode THV3 and the first penetrating electrode THV1 can be located at the same horizontal height. The third penetrating electrode THV3 and the first penetrating electrode THV1 can have the same conductive film stack structure.

[0146] Figure 14 and Figure 15 These are illustrations of semiconductor memory devices according to some embodiments. For ease of description, the description will primarily focus on usage. Figures 4 to 9 The differences in the content described. For reference, Figure 14 It is along Figure 13 A cross-sectional view taken from line AA. Figure 15 yes Figure 14 A magnified view of part R.

[0147] Reference Figure 14 and Figure 15 According to some embodiments, the semiconductor memory device may also include a second plate contact plug PCC2.

[0148] The second plate contact plug PCC2 may be located in the second penetrating electrode region THV_R2. The second plate contact plug PCC2 may extend along the third direction D3. The second plate contact plug PCC2 may be located in the insulating molding portion IMS. The second plate contact plug PCC2 may penetrate the stack structure ST, for example, the insulating molding portion IMS.

[0149] The second board contact plug PCC2 can be connected to the horizontally conductive substrate USB. The second board contact plug PCC2 can be electrically connected to the horizontally conductive substrate USB in a second region of the horizontally conductive substrate USB. The second board contact plug PCC2 can be connected to the second board contact connection wiring PCC2_CW.

[0150] In one embodiment, the upper surface 203us of the second penetrating electrode and the upper surface 213us of the second plate contact plug may be located on the same plane.

[0151] The second plate contact plug PCC2 may include an upper portion 213 and a lower portion 214 directly connected to each other. The second plate contact plug PCC2 may include a second _2 boundary IFL 22, at which the upper portion 213 and the lower portion 214 of the second plate contact plug form a boundary. Moving along a third direction D3 away from the upper surface 213us of the second plate contact plug PCC2, the width of the upper portion 213 of the second plate contact plug PCC2 may increase. Moving along a third direction D3 away from the upper surface 213us of the second plate contact plug PCC2, the width of the lower portion 214 of the second plate contact plug PCC2 may decrease. Moving along a third direction D3 away from the upper surface 213us of the second plate contact plug PCC2, the width of the second plate contact plug PCC2 may increase and then decrease.

[0152] The second plate contact plug PCC2 may have its maximum width at the second _2 boundary IFL22 (e.g., width in the first direction D1). The height from the plane of the second _2 boundary IFL22 (where the second plate contact plug PCC2 has its maximum width) to the upper surface 213µs of the second plate contact plug PCC2 may be a fifth height H25. At least a portion of the sidewall of the second plate contact plug PCC2 includes a convex curved surface. The second _2 boundary IFL22 where the second plate contact plug PCC2 has its maximum width may be located at the portion of the second plate contact plug PCC2 with the convex curved surface.

[0153] In one embodiment, the first -2 boundary IFL12 of the second penetration electrode THV2 may be located at the same vertical height as the second -2 boundary IFL22 of the second plate contact plug PCC2, relative to the upper surface 203µs of the second penetration electrode THV2 or the upper surface of the horizontal conductive substrate USB. In one embodiment, the plane of the second penetration electrode THV2 at its maximum width may be located at the same vertical height as the plane of the second plate contact plug PCC2 at its maximum width.

[0154] The second plate contact plug PCC2 can be located at the same horizontal height as the second penetrating electrode THV2. The second plate contact plug PCC2 and the second penetrating electrode THV2 can have the same conductive film stack structure. The second plate contact plug PCC2 may include a blocking conductive film BML and a filling conductive film FML.

[0155] Figures 16 to 19 The various stages of a method for manufacturing a semiconductor memory device according to some embodiments are shown.

[0156] Reference Figure 16 This can form a peripheral logic structure PS that includes the peripheral circuit PTR and the lower connection wiring body PW.

[0157] A horizontally conductive substrate USB can be formed on the peripheral logic structure PS.

[0158] Subsequently, a stacked structure ST comprising multiple electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7, and EP8 can be formed on the horizontal conductive substrate USB. Additionally, first to third interlayer insulating films 142, 144, and 146 can be formed covering the stacked structure ST.

[0159] The stacked structure ST may include an insulating molded portion IMS in which inter-electrode insulating film ILD and sacrificial molded insulating film ILD_SC are stacked alternately.

[0160] Also refer to Figure 17 Electrode plug holes WL_PGH can be formed in the insulating films 142, 144 and 146 between the first to third layers.

[0161] The electrode plug hole WL_PGH can expose some of the electrode pads in multiple electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7 and EP8.

[0162] Reference Figure 18 An insulating liner 141 can be formed along the upper surface of the third interlayer insulating film 146 and the contour of the electrode plug hole WL_PGH.

[0163] The insulating pad film 141 can be formed conformally. The insulating pad film 141 may include, for example, silicon nitride.

[0164] Reference Figure 19 A mask pattern can be formed on the insulating backing film 141.

[0165] The mask pattern MASK can fill a portion of the electrode plug hole WL_PGH.

[0166] The first plate contact hole PCC1_H, the first through electrode hole THV1_H, and the second through electrode hole THV2_H are simultaneously formed using a mask pattern MASK.

[0167] A first plate contact hole PCC1_H can be formed in the first to third interlayer insulating films 142, 144, and 146. The first plate contact hole PCC1_H exposes a portion of the horizontally conductive substrate USB.

[0168] A first through-hole THV1_H can be formed in the first to third interlayer insulating films 142, 144 and 146 and the peripheral logic insulating film 110. The first through-hole THV1_H can expose a portion of the underlying connection wiring body PW.

[0169] A second through-hole THV2_H can be formed in the stacked structure ST. The second through-hole THV2_H can penetrate the insulating molding portion IMS. The second through-hole THV2_H can expose a portion of the underlying connection wiring body PW.

[0170] As the upper surface moves away from the third interlayer insulating film 146, the width of the first plate contact hole PCC1_H, the width of the first penetrating electrode hole THV1_H, and the width of the second penetrating electrode hole THV2_H can increase and then decrease.

[0171] Relative to the upper surface of the horizontal conductive substrate USB, the plane at the maximum width of the first through electrode hole THV1_H can be at the same vertical height as the plane at the maximum width of the first plate contact hole PCC1_H.

[0172] Relative to the upper surface of the horizontal conductive substrate USB, the plane at the maximum width of the first through electrode hole THV1_H can be higher than the plane at the maximum width of the second through electrode hole THV2_H.

[0173] Next, the mask pattern can be removed. Furthermore, at least a portion of the insulating liner film 141 formed along the contour of the electrode plug hole WL_PGH can be removed. In one embodiment, the insulating liner film 141 formed on the bottom surface of the electrode plug hole WL_PGH can be removed.

[0174] Subsequently, referring to Figure 5 It can form a first plate contact plug PCC1, a first penetrating electrode THV1, a second penetrating electrode THV2, and an electrode plug WL_PG that fill the first plate contact hole PCC1_H, the first penetrating electrode hole THV1_H, the second penetrating electrode hole THV2_H, and the electrode plug hole WL_PGH.

[0175] Figure 20 This is a cross-sectional view of one stage of a method for manufacturing a semiconductor memory device according to some embodiments. Figure 20 It can be in Figure 17 The manufacturing process that follows.

[0176] Reference Figure 20 A mask pattern MASK that fills a portion of the electrode plug hole WL_PGH can be formed on the third interlayer insulating film 146.

[0177] Subsequently, the first plate contact hole PCC1_H, the first through electrode hole THV1_H, and the second through electrode hole THV2_H can be formed simultaneously using a mask pattern MASK.

[0178] In summary and review, ultra-expensive equipment can be used for pattern miniaturization, and the integration density of two-dimensional semiconductor devices is improving, but may still be limited. Therefore, three-dimensional semiconductor memory devices (including memory cells arranged in three dimensions) can be considered.

[0179] One or more embodiments may provide a three-dimensional semiconductor memory device that includes a vertical channel structure and has improved reliability and integration.

[0180] One or more embodiments may provide a semiconductor memory device including a vertical channel structure with improved reliability and integration.

[0181] One or more embodiments may provide a method of manufacturing a semiconductor memory device including a vertical channel structure with improved reliability and integration.

[0182] This document has disclosed exemplary embodiments, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device comprising: a peripheral logic structure including a peripheral circuit and a lower connection wiring body, the peripheral logic structure being located on a substrate; a horizontal conductive substrate located on the peripheral logic structure; a stack structure including a plurality of electrode pads stacked in a vertical direction on the horizontal conductive substrate; a board contact plug connected to the horizontal conductive substrate, extending in the vertical direction, and disposed in a first region extending in a first horizontal direction orthogonal to the vertical direction; a first penetrating electrode connected to the lower connection wiring body, extending in the vertical direction, and disposed in a second region extending in the first horizontal direction, wherein the first region is closer to the stack structure than the second region; and a second penetrating electrode penetrating the stack structure, connected to the lower connection wiring body, and disposed in a third region extending in a second horizontal direction perpendicular to the first horizontal direction and the vertical direction, wherein: an upper surface of the board contact plug and an upper surface of the first penetrating electrode are located on a same plane, the board contact plug includes an upper portion and a lower portion directly connected to each other, the first penetrating electrode includes an upper portion and a lower portion directly connected to each other, a width of the upper portion of the first penetrating electrode measured in the second horizontal direction increases as moving away from the upper surface of the first penetrating electrode in the vertical direction, a width of the upper portion of the board contact plug measured in the second horizontal direction increases as moving away from the upper surface of the board contact plug in the vertical direction, a width of the lower portion of the board contact plug measured in the second horizontal direction decreases as moving away from the upper surface of the board contact plug in the vertical direction, and a width of the lower portion of the first penetrating electrode measured in the second horizontal direction decreases as moving away from the upper surface of the first penetrating electrode in the vertical direction.

2. The semiconductor memory device according to claim 1, wherein: the board contact plug has a maximum width at a first boundary between the upper portion of the board contact plug and the lower portion of the board contact plug, the first penetrating electrode has a maximum width at a second boundary between the upper portion of the first penetrating electrode and the lower portion of the first penetrating electrode, and the first boundary and the second boundary are at a same vertical height with respect to the plane on which the upper surface of the first penetrating electrode and the upper surface of the board contact plug are located.

3. The semiconductor memory device according to claim 2, wherein: at least a portion of a sidewall of the board contact plug has a convex curved surface, at least a portion of a sidewall of the first penetrating electrode has a convex curved surface, the first boundary is located at a portion of the board contact plug having a convex curved surface, and the second boundary is located at a portion of the first penetrating electrode having a convex curved surface.

4. The semiconductor memory device according to claim 1, further comprising a plurality of electrode plugs connected to the plurality of electrode pads, wherein, upper surfaces of the plurality of electrode plugs are located on the same plane as the upper surface of the board contact plug.

5. The semiconductor memory device according to claim 4, wherein, The first penetrating electrode, the board contact plug, and the electrode plug have the same conductive film stack structure.

6. The semiconductor memory device according to claim 1, further comprising: a plurality of electrode plugs connected to the plurality of electrode pads; and an insulating plug liner extending along a sidewall of each of the plurality of electrode plugs.

7. The semiconductor memory device according to claim 1, wherein: the horizontal conductive substrate includes: a first substrate region overlapping the stack structure, and a second substrate region not overlapping the stack structure, and the board contact plug is connected to the second substrate region of the horizontal conductive substrate.

8. The semiconductor memory device according to claim 7, wherein, The board contact plug and the first penetrating electrode do not penetrate the stack structure.

9. The semiconductor memory device according to claim 7, wherein, The board contact plug and the first penetrating electrode penetrate the stack structure.

10. The semiconductor memory device according to claim 1, further comprising a metal plate film extending along a lower surface of the horizontal conductive substrate, the metal plate film being located between the lower connection wiring body and the horizontal conductive substrate.

11. The semiconductor memory device according to claim 1, wherein: the horizontal conductive substrate includes a semiconductor material, and the semiconductor material includes an n-type impurity, a p-type impurity, or carbon.

12. The semiconductor memory device according to claim 1, wherein: the second penetrating electrode includes an upper portion and a lower portion directly connected to each other, and moving away from the upper surface of the second penetrating electrode in the vertical direction, a width of the upper portion of the second penetrating electrode measured in the first horizontal direction increases, and a width of the lower portion of the second penetrating electrode measured in the first horizontal direction decreases.

13. The semiconductor memory device according to claim 12, wherein: the first penetrating electrode does not penetrate the stack structure, and with respect to an upper surface of the horizontal conductive substrate in the vertical direction, a plane at a maximum width of the first penetrating electrode is higher than a plane at a maximum width of the second penetrating electrode.

14. A semiconductor memory device comprising: a peripheral logic structure including a peripheral circuit and a lower connection wiring body, the peripheral logic structure being located on a substrate; a horizontal conductive substrate located on the peripheral logic structure; a stack structure including a plurality of electrode pads stacked in a vertical direction on the horizontal conductive substrate; a first board contact plug connected to the horizontal conductive substrate, extending in the vertical direction, and disposed in a first region extending in a first horizontal direction orthogonal to the vertical direction; a first penetrating electrode connected to the lower connection wiring body and extending in the vertical direction, and provided in a second region extending in the first horizontal direction, wherein the first region is closer to the stacked structure than the second region; and a second penetrating electrode penetrating the stacked structure, connected to the lower connection wiring body, and provided in a third region extending in a second horizontal direction perpendicular to the first horizontal direction and the vertical direction, wherein: the first penetrating electrode and the first plate contact plug do not penetrate the stacked structure, upper surfaces of the first plate contact plug, the first penetrating electrode, and the second penetrating electrode are located on the same plane, with respect to an upper surface of the horizontal conductive substrate in the vertical direction, a plane at a maximum width of the first penetrating electrode is higher than a plane at a maximum width of the second penetrating electrode, and with respect to the upper surface of the horizontal conductive substrate in the vertical direction, a plane at a maximum width of the first penetrating electrode is located at the same vertical height as a plane at a maximum width of the first plate contact plug.

15. The semiconductor storage device according to claim 14, wherein: a width of the first penetrating electrode measured in the second horizontal direction increases and then decreases as moving away from the upper surface of the first penetrating electrode in the vertical direction, a width of the second penetrating electrode measured in the first horizontal direction increases and then decreases as moving away from the upper surface of the second penetrating electrode in the vertical direction, and a width of the first plate contact plug measured in the second horizontal direction increases and then decreases as moving away from the upper surface of the first plate contact plug in the vertical direction.

16. The semiconductor storage device according to claim 14, wherein: at least a portion of a side wall of the first penetrating electrode has a convex curved surface, at least a portion of a side wall of the second penetrating electrode has a convex curved surface, and at least a portion of a side wall of the first plate contact plug has a convex curved surface.

17. The semiconductor storage device according to claim 14, further comprising a second plate contact plug penetrating the stacked structure and connected to the horizontal conductive substrate, wherein the upper surface of the second plate contact plug is located on the same plane as the upper surface of the second penetrating electrode.

18. The semiconductor memory device of claim 17, wherein, with respect to the upper surface of the horizontal conductive substrate in the vertical direction, a plane at a maximum width of the second penetrating electrode is located at the same vertical height as a plane at a maximum width of the second plate contact plug.

19. The semiconductor storage device according to claim 14, further comprising a metal plate film in contact with the horizontal conductive substrate, the metal plate film being located between the lower connection wiring body and the horizontal conductive substrate.

20. A semiconductor storage device, comprising: a peripheral logic structure including a peripheral circuit and a lower connection wiring body, the peripheral logic structure being located on a substrate; a horizontally conductive substrate extending along an upper surface of the peripheral logic structure; a stack structure including a plurality of electrode pads stacked in a vertical direction on the horizontally conductive substrate; a plurality of vertical structures penetrating the stack structure and electrically connected to the horizontally conductive substrate; a vertical structure support film located between the stack structure and the horizontally conductive substrate and in contact with the vertical structures; a plurality of electrode plugs connected to the plurality of electrode pads; a board contact plug connected to the horizontally conductive substrate, extending in the vertical direction, and disposed in a first region extending in a first horizontal direction orthogonal to the vertical direction; a first penetrating electrode connected to the lower connection wiring body and extending in the vertical direction, and disposed in a second region extending in the first horizontal direction, wherein the first region is closer to the stack structure than the second region; and a second penetrating electrode penetrating the stack structure, connected to the lower connection wiring body, and disposed in a third region extending in a second horizontal direction perpendicular to the first horizontal direction and the vertical direction, wherein: an upper surface of the board contact plug and an upper surface of the first penetrating electrode are located on the same plane, a height from a plane at which the board contact plug has a maximum width to the upper surface of the board contact plug in the vertical direction is a first height, a height from a plane at which the first penetrating electrode has a maximum width to the upper surface of the first penetrating electrode in the vertical direction is a second height, a height of the first penetrating electrode in the vertical direction is H, both the first height and the second height are greater than 0, and a difference between the first height and the second height is greater than or equal to 0 and less than or equal to 0.0015×H.

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