Display motherboard and manufacturing method thereof, display substrate and display device

Abstract

The present invention provides a display motherboard, a method for manufacturing the same, a display substrate, and a display device. The display motherboard includes multiple display substrate regions and a cutting region located around each of the display substrate regions. The display motherboard includes: a drive structure layer disposed in each display substrate region; and an identification structure layer disposed in each cutting region. The identification structure layer includes a cutting identification layer; and a planarization layer disposed on the drive structure layer and the identification structure layer, the planarization layer covering the identification structure layer. By retaining a complete planarization layer in the cutting region, the embodiments of the present invention effectively improve the overall stiffness of the film layer in the cutting region, reduce deformation caused by roller pressure, and prevent the formation of bubbles in the cutting region, effectively resolving the issue of unrecognizable cutting marks due to bubbles obscuring the cutting marks.

Description

Technical Field

[0001] The embodiments of the present invention relate to, but are not limited to, the field of display technology, and in particular to a display motherboard and a manufacturing method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous development of display technology, OLED technology is increasingly being used in flexible display devices.

[0003] When preparing a flexible OLED display device, a display motherboard is usually prepared first, and then the display motherboard is cut to separate the display motherboard into multiple display substrates. The separated display substrates can be used to form a single OLED display device. Figure 1 FIG. 1 is a schematic diagram showing the arrangement of multiple display substrates on a display motherboard. Figure 1 As shown, multiple display substrate regions 300 on the display motherboard 100 are arranged in a regular, periodic pattern, with a cutting region 400 located around each display substrate region 300. The display substrate region 300 includes at least a display region 301 and a binding region 302. The display region 301 includes multiple pixels arranged in a matrix, and the binding region 302 includes a driving circuit 303. The binding region 302 is located on one side of the display region 301. The cutting region 400 includes a circular cutting line 401 surrounding the display substrate region 300 and multiple cutting marks 402.

[0004] When cutting, the cutting equipment first identifies the cutting mark and then cuts according to the cutting mark. However, there is a problem in production that the cutting mark cannot be identified. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The technical problem to be solved by the embodiments of the present invention is to provide a display motherboard and a preparation method thereof, a display substrate and a display device, so as to solve the problem that cutting marks cannot be identified during production.

[0007] An embodiment of the present invention provides a display motherboard, comprising a plurality of display substrate regions and a cutting region located around each of the display substrate regions; the display motherboard comprises:

[0008] A driving structure layer is provided in each display substrate area, and a marking structure layer is provided in each cutting area; wherein the marking structure layer includes a cutting marking layer;

[0009] A planarization layer is provided on the driving structure layer and the logo structure layer, and the planarization layer covers the logo structure layer.

[0010] In some possible implementations, the driving structure layer includes a first source-drain metal layer, the marking structure layer includes a cutting marking layer, and the cutting marking layer is provided in the same layer as the first source-drain metal layer.

[0011] In some possible implementations, the driving structure layer also includes: a first insulating layer arranged on a substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, a fourth insulating layer covering the second gate metal layer, and the first source-drain metal layer arranged on the fourth insulating layer; the identification structure layer also includes: a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer stacked on the substrate, and the cutting identification layer is arranged on the fourth insulating layer.

[0012] In some possible implementations, a fifth insulating layer is further included; in the display substrate area, the fifth insulating layer is arranged on the driving structure layer, in the cutting area, the fifth insulating layer is arranged on the identification structure layer, and the planarization layer is arranged on the fifth insulating layer.

[0013] In some possible implementations, the planarization layer includes a second planarization layer disposed on the fifth insulating layer and a pixel definition layer disposed on the second planarization layer; and in the display substrate region, an anode is further disposed between the second planarization layer and the pixel definition layer.

[0014] In some possible implementations, the driving structure layer includes a second source-drain metal layer, the marking structure layer includes a cutting marking layer, and the cutting marking layer is provided in the same layer as the second source-drain metal layer.

[0015] In some possible implementations, the driving structure layer also includes: a first insulating layer arranged on a substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, a fourth insulating layer covering the second gate metal layer, a first source-drain metal layer arranged on the fourth insulating layer, a fifth insulating layer and a first planarization layer covering the first source-drain metal layer, and the second source-drain metal layer is arranged on the first planarization layer; the identification structure layer also includes: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a first planarization layer stacked on the substrate, and the cutting identification layer is arranged on the first planarization layer.

[0016] In some possible implementations, the planarization layer includes a second planarization layer covering the driving structure layer and the identification structure layer and a pixel definition layer arranged on the second planarization layer; in the display substrate area, an anode is also arranged between the second planarization layer and the pixel definition layer.

[0017] In some possible implementations, a protective film is further included; in the display substrate area, an encapsulation layer is provided on the planarization layer, and the protective film is provided on the encapsulation layer; in the cutting area, the protective film is provided on the planarization layer.

[0018] In some possible implementations, the cutting mark layer of the cutting area includes a plurality of cutting marks, and the cutting marks include four rectangular patterns arranged in a field shape.

[0019] An embodiment of the present invention further provides a display substrate, which is formed by cutting the aforementioned display motherboard along the cutting area.

[0020] An embodiment of the present invention further provides a display device including the aforementioned display substrate.

[0021] An embodiment of the present invention further provides a method for preparing a display motherboard, wherein the display motherboard includes a plurality of display substrate regions and a cutting region located around each of the display substrate regions. The method includes:

[0022] Forming a driving structure layer and a marking structure layer in the plurality of display substrate regions and the cutting region respectively; the marking structure layer includes a cutting marking layer;

[0023] A planarization layer is formed on the driving structure layer and the logo structure layer, and the planarization layer covers the logo structure layer.

[0024] In some possible implementations, the driving structure layer includes a first source / drain metal layer, the identification structure layer includes a cutting identification layer, and the driving structure layer and the identification structure layer are respectively formed in multiple display substrate regions and cutting regions, including:

[0025] A first insulating layer is formed on a substrate, an active layer is formed on the first insulating layer, a second insulating layer covering the active layer is formed, a first gate metal layer is formed on the second insulating layer, a third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, a fourth insulating layer covering the second gate metal layer is formed, and the first source-drain metal layer and a cutting mark layer are formed on the fourth insulating layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer are arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.

[0026] In some possible implementations, forming a planarization layer on the driving structure layer and the logo structure layer includes:

[0027] forming a fifth insulating layer on the driving structure layer and the logo structure layer;

[0028] A second planarization layer and a pixel definition layer are sequentially formed on the fifth insulating layer. In the display substrate region, an anode is further formed between the second planarization layer and the pixel definition layer.

[0029] In some possible implementations, the driving structure layer includes a second source / drain metal layer, the identification structure layer includes a cutting identification layer, and the driving structure layer and the identification structure layer are respectively formed in multiple display substrate regions and cutting regions, including:

[0030] A first insulating layer is formed on a substrate, an active layer is formed on the first insulating layer, a second insulating layer covering the active layer is formed, a first gate metal layer is formed on the second insulating layer, a third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, a fourth insulating layer covering the second gate metal layer is formed, a first source-drain metal layer is formed on the fourth insulating layer, a fifth insulating layer covering the first source-drain metal layer is formed, a first planarization layer is formed on the fifth insulating layer, and the second source-drain metal layer and a cutting mark layer are formed on the first planarization layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer are arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.

[0031] In some possible implementations, forming a planarization layer on the driving structure layer and the logo structure layer includes:

[0032] A second planarization layer and a pixel definition layer are sequentially formed on the first planarization layer. In the display substrate region, an anode is further formed between the second planarization layer and the pixel definition layer.

[0033] Some possible implementations also include:

[0034] forming an organic light-emitting layer, a cathode and an encapsulation layer in sequence;

[0035] affixing a protective film on the encapsulation layer, wherein the protective film contacts the pixel definition layer in the cutting area;

[0036] Adhere a backing film to the surface of the substrate away from the planarization layer by roller bonding;

[0037] The display motherboard is cut to form a plurality of display substrates.

[0038] In some possible implementations, after cutting the display motherboard, the method further includes:

[0039] removing the protective film;

[0040] A cover plate is formed on the encapsulation layer; or a touch layer and a cover plate are sequentially formed on the encapsulation layer.

[0041] An embodiment of the present invention provides a display motherboard and a preparation method thereof, a display substrate and a display device. By retaining a complete planarization layer in the cutting area, the overall stiffness of the film layer in the cutting area is effectively improved, the deformation caused by roller pressure is reduced, and the generation of bubbles in the cutting area is avoided, effectively solving the problem of the cutting mark being unrecognizable due to bubbles blocking the cutting mark.

[0042] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present invention and do not constitute a limitation of the technical solutions of the present invention. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present invention.

[0044] Figure 1 A schematic diagram of the arrangement of multiple display substrates on a display motherboard;

[0045] Figure 2 This is a schematic structural diagram of a display motherboard according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of a display motherboard structure after forming a driving structure layer and cutting a marking layer pattern according to an embodiment of the present invention;

[0047] Figure 4 This is a schematic diagram of a display motherboard structure after a planarization layer pattern is formed according to an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of a display motherboard structure after an anode pattern is formed according to an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of a display motherboard structure after forming a pixel definition layer pattern according to an embodiment of the present invention;

[0050] Figure 7 A schematic diagram of a display motherboard structure after a protective film is attached according to an embodiment of the present invention;

[0051] Figure 8 This is a schematic structural diagram of a binding area according to an embodiment of the present invention;

[0052] Figure 9 This is a schematic structural diagram of a cutting mark according to an embodiment of the present invention;

[0053] Figure 10 This is a schematic structural diagram of another display motherboard according to an embodiment of the present invention;

[0054] Figure 11 This is a schematic diagram of another display motherboard structure after forming a driving structure layer and cutting a marking layer pattern according to an embodiment of the present invention;

[0055] Figure 12 This is a schematic diagram of another display motherboard structure after a planarization layer pattern is formed according to an embodiment of the present invention;

[0056] Figure 13 This is a schematic structural diagram of another display motherboard according to an embodiment of the present invention;

[0057] Figure 14 This is a structural diagram of another display motherboard according to an embodiment of the present invention.

[0058] Description of the accompanying drawings:

[0059] 1—Glass carrier; 2—Back film; 10—Substrate;

[0060] 11—first insulating layer; 12—active layer; 13—second insulating layer;

[0061] 14—gate electrode; 15—first capacitor electrode; 16—third insulating layer;

[0062] 17—second capacitor electrode; 18—fourth insulating layer; 19A—source electrode;

[0063] 19B—drain electrode; 20—fifth insulating layer; 21—planarization layer;

[0064] 21A—first planarization layer; 22—anode; 23—pixel definition layer;

[0065] 24—organic light-emitting layer; 25—cathode; 26—encapsulation layer;

[0066] 27—protective film; 40—identification block; 100—display motherboard;

[0067] 101—thin film transistor; 102—storage capacitor; 103—connecting electrode;

[0068] 300—display substrate area; 301—display area; 302—binding area;

[0069] 303—driving circuit; 400—cutting area; 401—cutting line;

[0070] 402—Cutting mark. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. Those skilled in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other in any manner.

[0072] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present invention is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0073] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0074] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is solely for the purpose of facilitating the description of this specification and simplifying the description. They are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. The positional relationships of the components may be appropriately modified depending on the direction in which the components are described. Therefore, the present invention is not limited to the words and phrases described in the specification and may be appropriately modified depending on the circumstances.

[0075] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct or indirect connections through intermediaries; and internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0076] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0077] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0078] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0079] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0080] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0081] Research by the inventors of this application has revealed that the problem of unrecognizable cutting marks in the cutting area during production is caused by bubbles forming in the cutting area during the production process, obscuring the cutting marks. When multiple irregularly shaped bubbles are located in the area where the cutting marks are located, the bubble outlines affect the cutting equipment's ability to accurately determine the cutting mark's shape, leading to the cutting equipment being unable to recognize the cutting marks. Further research by the inventors of this application has revealed that the bubbles in the cutting area are primarily generated during the backing film lamination process. The production process for a display motherboard typically involves first preparing a flexible substrate on a rigid substrate, then preparing the corresponding film layer structure on the flexible substrate to form the display motherboard. After all film layers are prepared, the display motherboard is peeled off from the rigid substrate using a lift-off process. A backing film is then applied to the back of the flexible substrate (the surface facing away from the film layer structure) to protect the flexible substrate. When the backing film is applied using a roller, the softer flexible substrate deforms under the roller's pressure, and bubbles form in the areas of greater deformation due to compression.

[0082] In order to solve the problem of unrecognizable cutting marks during production, an embodiment of the present invention provides a display motherboard. On a plane parallel to the display motherboard, the display motherboard includes multiple display substrate areas and a cutting area located around each of the display substrate areas; on a plane perpendicular to the display motherboard, the display motherboard includes:

[0083] A driving structure layer is provided in each display substrate area, and a marking structure layer is provided in each cutting area; the marking structure layer includes a cutting marking layer;

[0084] A planarization layer is provided on the driving structure layer and the logo structure layer, and the planarization layer covers the logo structure layer.

[0085] In an exemplary embodiment, the driving structure layer includes a first source-drain metal layer, and the marking structure layer includes a cutting marking layer, and the cutting marking layer is provided in the same layer as the first source-drain metal layer.

[0086] In which, the driving structure layer also includes: a first insulating layer arranged on the substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, a fourth insulating layer covering the second gate metal layer, and the first source-drain metal layer is arranged on the fourth insulating layer; the identification structure layer also includes: a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer stacked on the substrate, and the cutting identification layer is arranged on the fourth insulating layer.

[0087] Wherein, it also includes a fifth insulating layer; in the display substrate area, the fifth insulating layer is arranged on the driving structure layer; in the cutting area, the fifth insulating layer is arranged on the marking structure layer, and the planarization layer is arranged on the fifth insulating layer.

[0088] The planarization layer includes a second planarization layer disposed on the fifth insulating layer and a pixel definition layer disposed on the second planarization layer; and in the display substrate region, an anode is further disposed between the second planarization layer and the pixel definition layer.

[0089] In an exemplary embodiment, the driving structure layer includes a second source-drain metal layer, and the marking structure layer includes a cutting marking layer, and the cutting marking layer and the second source-drain metal layer are provided in the same layer.

[0090] In which, the driving structure layer also includes: a first insulating layer arranged on the substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, a fourth insulating layer covering the second gate metal layer, a first source-drain metal layer arranged on the fourth insulating layer, a fifth insulating layer and a first planarization layer covering the first source-drain metal layer, and the second source-drain metal layer is arranged on the first planarization layer; the identification structure layer also includes: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a first planarization layer stacked on the substrate, and the cutting identification layer is arranged on the first planarization layer.

[0091] The planarization layer includes a second planarization layer covering the driving structure layer and the logo structure layer and a pixel definition layer arranged on the second planarization layer; in the display substrate area, an anode is further arranged between the second planarization layer and the pixel definition layer.

[0092] In an exemplary embodiment, a protective film is further included; in the display substrate area, an encapsulation layer is provided on the planarization layer, and the protective film is provided on the encapsulation layer; in the cutting area, the protective film is provided on the planarization layer.

[0093] In an exemplary embodiment, the cutting mark layer of the cutting area includes a plurality of cutting marks, and the cutting marks include four rectangular patterns arranged in a grid pattern.

[0094] An embodiment of the present application provides a display motherboard, which effectively improves the overall stiffness of the film layer in the cutting area by retaining a complete planarization layer in the cutting area, reduces the deformation caused by roller pressure, avoids the generation of bubbles in the cutting area, and thus avoids the situation where the cutting mark cannot be recognized due to bubbles blocking the cutting mark.

[0095] Figure 2 This is a schematic diagram of the structure of a display motherboard according to an embodiment of the present invention, illustrating the cross-sectional structure of the display substrate region and the cutting region of a single source / drain metal layer (single SD or 1SD) structure. In the direction parallel to the plane of the display motherboard, the display motherboard according to this embodiment includes a display substrate region 300 and a cutting region 400. The cutting region 400 is the region other than the display substrate region 300 on the display motherboard. Figure 2 As shown, in a direction perpendicular to the plane of the display motherboard, the display substrate area 300 includes a driving structure layer provided on the base 10 and a light emitting structure layer provided on the driving structure layer, and the cutting area 400 includes a composite insulating layer provided on the base 10, a cutting mark layer provided on the composite insulating layer, and an insulating layer covering the cutting mark layer. The driving structure layer of the display substrate area 300 includes multiple thin film transistors and storage capacitors forming a pixel driving circuit. Figure 2 Only a driving thin film transistor 101 and a storage capacitor 102 are used as an example for illustration. The driving structure layer mainly includes a first insulating layer 11 arranged on the substrate 10, a driving thin film transistor 101 and a storage capacitor 102 arranged on the first insulating layer 11, and a fifth insulating layer 20 and a second planarization layer 21 covering the driving thin film transistor 101 and the storage capacitor 102. The light-emitting structure layer mainly includes an anode 22, a pixel definition layer 23, an organic light-emitting layer 24, a cathode 25 and an encapsulation layer 26. The composite insulating layer of the cutting area 400 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 16 and a fourth insulating layer 18 stacked in sequence on the substrate 10, the cutting identification layer includes an identification block 40 arranged on the composite insulating layer, and the insulating layer of the cutting area 400 includes a fifth insulating layer 20 covering the cutting identification layer, a second planarization layer 21 and a pixel definition layer 23 covering the second planarization layer 21. As shown Figure 2As shown, the second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 are completely retained, and the surface away from the substrate 10 is flat, which effectively improves the overall rigidity of the film layer in the cutting area.

[0096] The structure of the display motherboard of this embodiment will be described below through the fabrication process of the display motherboard. The "patterning process" referred to in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spray coating and spin coating; and etching can be performed by any one or more of dry etching and wet etching. A "thin film" refers to a thin layer of a material deposited on a substrate using a deposition or coating process. When the entire fabrication process does not require a patterning process, the "thin film" can also be referred to as a "layer." When the entire fabrication process requires a patterning process, the "thin film" before the patterning process is referred to as a "thin film," and the "layer" after the patterning process is referred to as a "layer." The "layer" after the patterning process contains at least one "pattern." In this embodiment, "A and B are arranged in the same layer" means that A and B are formed simultaneously through the same patterning process.

[0097] (1) A flexible substrate 10 is prepared on a glass carrier 1. In an embodiment of the present invention, the flexible substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier 1. The first and second flexible material layers can be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers can be made of silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer can be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer again, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the flexible substrate.

[0098] (2) A driving structure layer and a cutting mark layer pattern are prepared on the substrate 10. The driving structure layer is provided in the display substrate region 300, and the cutting mark layer is provided in the cutting region 400. The driving structure layer includes a driving thin film transistor 101 and a storage capacitor 102 constituting a pixel driving circuit. In an exemplary embodiment, the preparation process of the driving structure layer and the cutting mark layer may include:

[0099] A first insulating film and an active layer film are sequentially deposited on substrate 10. The active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire substrate 10 and an active layer 12 pattern disposed on the first insulating layer 11. The active layer 12 is formed in display substrate region 300. After this patterning process, the cutting region 400 includes the first insulating layer 11 disposed on substrate 10.

[0100] Subsequently, a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 13 covering the entire substrate 10 and a first gate metal layer pattern disposed on the second insulating layer 13. The first gate metal layer pattern is formed in the display substrate region 300 and includes at least a gate electrode 14, a first capacitor electrode 15, a first gate line (not shown), and a second gate line (not shown). After this patterning process, the cutting region 400 includes the first insulating layer 11 and the second insulating layer 13 stacked on the substrate 10.

[0101] Subsequently, a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer 16 covering the entire substrate 10 and a second gate metal layer pattern disposed on the third insulating layer 16. The second gate metal layer pattern is formed in the display substrate region 300 and includes at least a second capacitor electrode 17. The position of the second capacitor electrode 17 corresponds to the position of the first capacitor electrode 15. After this patterning process, the cutting area 400 includes the first insulating layer 11, the second insulating layer 13, and the third insulating layer 16 stacked on the substrate 10.

[0102] Subsequently, a fourth insulating film is deposited and patterned through a patterning process to form a fourth insulating layer 18 pattern covering the entire substrate 10. Two first via holes are defined in the fourth insulating layer 18. These two first via holes are formed in the display substrate region 300, corresponding to the positions of the two ends of the active layer 12. The fourth insulating layer 18, the third insulating layer 16, and the second insulating layer 13 within the first via holes are etched away, exposing the surface of the active layer 12. After this patterning process, the cutting area 400 includes the first insulating layer 11, the second insulating layer 13, the third insulating layer 16, and the fourth insulating layer 18 stacked on the substrate 10.

[0103] Subsequently, a third metal film is deposited and patterned through a patterning process to form a first source / drain metal layer and a cutting identification layer pattern on the fourth insulating layer 18. The first source / drain metal layer (SD1) is formed in the display substrate region 300 and includes at least a source electrode 19A, a drain electrode 19B, a data line (not shown), and a power line (not shown). The source electrode 19A and the drain electrode 19B are respectively connected to the active layer 12 through first vias. A cutting identification layer is formed in the cutting region 400 and includes at least two spaced-apart identification blocks 40. After this patterning process, the cutting region 400 includes a composite insulating layer disposed on the substrate 10 and a cutting identification layer disposed on the composite insulating layer. The composite insulating layer includes a stacked first insulating layer 11, a second insulating layer 13, a third insulating layer 16, and a fourth insulating layer 18. The cutting identification layer includes the identification block 40.

[0104] Subsequently, a fifth insulating film is deposited to form a pattern of the fifth insulating layer 20 covering the entire substrate 10. After this patterning process, the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting identification layer disposed on the composite insulating layer, and a fifth insulating layer 20 covering the cutting identification layer. The composite insulating layer includes a stacked first insulating layer 11, a second insulating layer 13, a third insulating layer 16, and a fourth insulating layer 18. The cutting identification layer includes identification blocks 40. In one exemplary embodiment, the fifth insulating layer 20 may not be formed, depending on actual needs.

[0105] At this point, the driving structure layer and the cutting mark layer pattern are prepared on the substrate 10, as shown in FIG. Figure 3 The active layer 12, gate electrode 14, source electrode 19A and drain electrode 19B constitute a thin film transistor 101, the first capacitor electrode 15 and the second capacitor electrode 17 constitute a storage capacitor 102, and the first source and drain metal layer and the cutting mark layer are provided on the same layer and formed by the same patterning process.

[0106] In an embodiment of the present invention, the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, and the fifth insulating film may be made of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON), and may be a single-layer structure or a multi-layer composite structure. Typically, the first insulating layer is referred to as a buffer layer, which is used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are referred to as gate insulating (GI) layers. The fourth insulating layer is referred to as an interlayer insulating (ILD) layer. The fifth insulating layer is referred to as a passivation (PVX) layer. The first metal film, the second metal film, and the third metal film may be made of a metal material, such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or may be an alloy material composed of a metal, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The alloy material may be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of a Mo layer, a Cu layer, and a Mo layer. The active layer thin film can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, that is, the embodiment of the present invention is applicable to thin film transistors manufactured based on oxide technology, silicon technology or organic technology.

[0107] (3) A flat film is coated on the substrate formed with the aforementioned pattern, and the fifth insulating layer 20 is patterned by a patterning process to form a second planarization (PLN) layer 21 covering the entire substrate 10. A second via hole is opened on the fifth insulating layer 20 and the second planarization layer 21. The second via hole is formed in the display substrate area 300. The second planarization layer 21 and the fifth insulating layer 20 in the second via hole are removed to expose the surface of the drain electrode 19B, as shown in FIG. Figure 4 As shown. During this process, the second planarization layer 21 in the cutting area 400 corresponding to the cutting mark layer is retained. The second planarization layer 21 in the cutting area 400 has a flat surface, and the thickness of the second planarization layer 21 in the cutting area 400 is the same as that of the second planarization layer 21 in the display substrate area 300. After this patterning process, the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting mark layer disposed on the composite insulating layer, a fifth insulating layer 20 covering the cutting mark layer, and a second planarization layer 21 covering the fifth insulating layer 20.

[0108] (4) Depositing a transparent conductive film on the substrate formed with the aforementioned pattern, patterning the transparent conductive film through a patterning process, forming an anode 22 pattern on the second planarization layer 21, the anode 22 is formed in the display substrate region 300, and the anode 22 is connected to the drain electrode of the thin film transistor 101 through a second via hole, as shown in FIG. Figure 5As shown. The transparent conductive film can be made of indium tin oxide (ITO) or indium zinc oxide (IZO). After this patterning process, the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting mark layer disposed on the composite insulating layer, a fifth insulating layer 20 covering the cutting mark layer, and a second planarization layer 21 covering the fifth insulating layer 20.

[0109] (5) A pixel definition film is coated on the substrate formed with the aforementioned pattern, and a pixel definition (PDL) layer 23 pattern is formed through masking, exposure, and development processes. A pixel opening is opened on the pixel definition layer 23, and the pixel opening is formed in the display substrate area 300. The pixel definition film in the pixel opening is developed away to expose the surface of the anode 22, as shown in FIG. Figure 6 As shown. Among them, the pixel definition layer can be made of polyimide, acrylic or polyethylene terephthalate, etc. In this process, the pixel definition film at the pixel opening position is developed away, and the pixel definition film at the cutting identification layer position corresponding to the cutting area 400 is retained, so that the pixel definition layer 23 in the cutting area 400 has a flat surface, and the thickness of the pixel definition layer 23 in the cutting area 400 is the same as the thickness of the pixel definition layer 23 in the display substrate area 300. After this patterning process, the cutting area 400 includes a composite insulating layer arranged on the substrate 10, a cutting identification layer arranged on the composite insulating layer, a fifth insulating layer 20 covering the cutting identification layer, a second planarization layer 21 covering the fifth insulating layer 20, and a pixel definition layer 23 covering the second planarization layer 21. The second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 constitute the planarization layer covering the identification structure layer of an embodiment of the present invention.

[0110] (6) In the subsequent process, the organic light-emitting layer 24, the cathode 25 and the encapsulation layer 26 are first formed in the display substrate area 300 in sequence, and then the display motherboard is peeled off from the glass carrier 1 by a peeling process, and a back film 2 is attached to the back of the display motherboard (the side of the substrate 10 away from the film layer) by a roller bonding method to complete the preparation of the display motherboard of this embodiment. Figure 2 Finally, the cutting equipment cuts the display motherboard according to the cutting mark to form multiple display substrates.

[0111] The organic light-emitting layer may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The cathode may be made of any metal material such as magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of one or more of the aforementioned metals. The encapsulation layer may have a stacked structure including, for example, an inorganic material layer, an organic material layer, and an inorganic material layer. The encapsulation layer only covers the display substrate area. In one exemplary embodiment, the display substrate area may further include a touch layer or touch panel disposed on the encapsulation layer, and an overcoat (OC) covering the touch layer or touch panel.

[0112] In an exemplary embodiment, the display substrate region may further include a temporary protective film (TPF) 27. After the encapsulation layer 26 is prepared, a layer of the protective film 27 is attached to the display motherboard through an attachment process. In the display substrate region 300, the protective film 27 is attached to the encapsulation layer. In the cutting region 400, the protective film 27 is attached to the pixel definition layer 23. The protective film 27 is in direct contact with the pixel definition layer 23. Figure 7 As shown. Applying a protective film to the display motherboard protects the film structure of the display substrate. After attaching the protective film 27, the display motherboard is peeled from the glass carrier 1 using a peeling process. A backing film 2 is then attached to the back of the display motherboard using a roller lamination method, completing the preparation of the display motherboard of this embodiment. Subsequently, a cutting device cuts the display motherboard according to the cutting marks to form multiple display substrates. After cutting, the protective film is first removed, and then a touch layer and a cover plate are sequentially placed on the encapsulation layer to form a touch display panel; alternatively, a cover plate is directly placed on the encapsulation layer to form a display panel.

[0113] In an embodiment of the present invention, the display substrate area includes a display area and a binding area. The display area includes multiple pixels arranged in a matrix for realizing image display. The binding area includes a driving circuit for receiving a control signal from an external integrated circuit and sending it to the multiple pixels in the display area. Figure 8 This is a structural diagram of a binding area according to an embodiment of the present invention. The binding area is an area protruding from the display area. After the display motherboard is divided into multiple display substrate areas, the binding area will be bent to the back of the display area. In an exemplary embodiment, the binding area is set on one side of the display area, such as Figure 8As shown, the bonding area includes a first sector (fanout A), a bending area, a second sector (fanout B), a cell test area, an integrated circuit (IC) area, an outer lead bonding (OLB) area, and a flexible printed circuit (FPC) area, which are arranged in sequence along the direction away from the display area. Generally, the length L of the bonding area (the length from the first sector to the flexible printed circuit area) is 9 mm to 10 mm, such as 9.601 mm.

[0114] In order to further reduce the interference and influence of bubbles on the recognition of the cutting mark, a cutting mark structure is proposed in this embodiment. Figure 9 This is a schematic structural diagram of a cutting mark according to an embodiment of the present invention. As Figure 9 shown, the cutting mark of this embodiment includes 4 rectangular patterns, and the 4 rectangular patterns are arranged in a cross shape, that is, arranged in a 2*2 matrix manner. Through the 4 rectangular patterns arranged in a cross shape, the influence of the bubble contour or impurity contour on the shape of the cutting mark can be minimized, the accuracy of the cutting device's judgment on the shape of the cutting mark can be improved, and the situation where the cutting device cannot recognize the cutting mark can be avoided.

[0115] As Figures 2 to 7 shown, the display mother board of this embodiment includes:

[0116] a substrate 10;

[0117] a first insulating layer 11 disposed on the substrate 10;

[0118] an active layer 12 disposed on the first insulating layer 11, and the active layer 12 is disposed in the display substrate area 300;

[0119] a second insulating layer 13 covering the active layer 12;

[0120] a first gate metal layer disposed on the second insulating layer 13, the first gate metal layer is disposed in the display substrate area 300, and at least includes a gate electrode 14 and a first capacitor electrode 15;

[0121] a third insulating layer 16 covering the first gate metal layer;

[0122] a second gate metal layer disposed on the third insulating layer 16, the second gate metal layer is disposed in the display substrate area 300, and at least includes a second capacitor electrode 17;

[0123] a fourth insulating layer 18 covering the second gate metal layer, and two first vias exposing the active layer 12 are formed thereon, and the two first vias are disposed in the display substrate area 300;

[0124] A first source / drain metal layer and a cutting mark layer are provided on the fourth insulating layer 18. The first source / drain metal layer is provided in the display substrate region 300 and includes at least a source electrode 19A and a drain electrode 19B. The source electrode 19A and the drain electrode 19B are respectively connected to the active layer 12 through first vias. The cutting mark layer is provided in the cutting region 400 and includes at least two spaced apart mark blocks 40. The first source / drain metal layer and the cutting mark layer are provided on the same layer and are formed by the same patterning process.

[0125] A fifth insulating layer 20 and a second planarization layer 21 covering the first source / drain metal layer are provided with a second via hole exposing the drain electrode 19B. The second via hole is provided in the display substrate region 300. The surface of the second planarization layer 21 in the cutting region 400 away from the substrate 10 is flush.

[0126] An anode 22 is provided on the second planarization layer 21 , and the anode 22 is provided in the display substrate region 300 and is connected to the drain electrode 19B through a second via hole;

[0127] The pixel definition layer 23 covering the anode 22 has a pixel opening exposing the anode 22 formed thereon. The pixel opening is formed in the display substrate region 300. The surface of the pixel definition layer 23 in the cut region away from the substrate 10 is flush.

[0128] An organic light emitting layer 24 is provided in the 300 pixel openings of the display substrate area, and the organic light emitting layer 24 is connected to the anode 22;

[0129] A cathode 25 is provided on the organic light-emitting layer 24 , wherein the cathode 25 is connected to the organic light-emitting layer 24 ;

[0130] An encapsulation layer 26 disposed in the display substrate region 300;

[0131] The protective film 27 covering the aforementioned structure is disposed on the encapsulation layer in the display substrate region 300 , and is disposed on the pixel definition layer 23 in the cutting region 400 , with the protective film 27 being in direct contact with the pixel definition layer 23 .

[0132] It can be seen from the structure and preparation process of the display motherboard of the embodiment of the present invention that the display motherboard provided by the embodiment of the present invention effectively improves the overall stiffness of the film layer in the cutting area by retaining a complete planarization layer and pixel definition layer in the cutting area, and the cutting mark layer in the cutting area is on the same layer as the first source and drain metal layer in the display substrate area, reduces the deformation caused by the roller pressure, avoids the generation of bubbles in the cutting area, and thus avoids the situation where the cutting mark cannot be recognized due to the bubbles blocking the cutting mark.

[0133] In a traditional structure, in order to reduce the cutting thickness and difficulty of the subsequent cutting process, the planarization layer and the pixel definition layer in the cutting area are both provided with grooves that expose the fifth insulating layer. Since there is a large height difference at the location of the groove, the deformation space of the cutting mark layer is large. Therefore, when the roller presses the substrate in the back film bonding process, the cutting mark layer will produce a large deformation, thereby forming more bubbles. In an embodiment of the present invention, by retaining a complete planarization layer and pixel definition layer in the cutting area, the height difference of the area is filled, which not only increases the overall stiffness of the film layer in the cutting area, but also eliminates the deformation space of the cutting mark layer. When the roller presses the substrate in the back film bonding process, the thicker planarization layer and pixel definition layer above the cutting mark layer can support the cutting mark layer to resist the deformation of the substrate, effectively reducing the deformation of the cutting mark layer and avoiding the generation of bubbles, thereby reducing the interference and influence of bubbles on the identification of the cutting mark, and avoiding the situation where the cutting mark in the cutting area cannot be identified.

[0134] In a traditional structure, the cutting mark layer is usually arranged in the same layer as the first gate metal layer in the display substrate area, that is, the cutting mark layer is arranged between the second insulating layer and the third insulating layer. Since the cutting mark layer and the substrate are only separated by the first insulating layer and the second insulating layer, the thickness and rigidity of the two insulating layers are relatively small. When the softer flexible substrate undergoes a large deformation, the cutting mark layer will also undergo a large deformation, thereby forming more bubbles. In an embodiment of the present invention, by changing the cutting mark layer from the first gate metal layer to the first source and drain metal layer, the cutting mark layer is arranged in the same layer as the first source and drain metal layer in the display substrate area, that is, the cutting mark layer is arranged on the fourth insulating layer, and there are four insulating layers between the cutting mark layer and the substrate, namely the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer, thereby increasing the thickness and rigidity of the film layer between the cutting mark layer and the substrate. In this way, even if the flexible substrate undergoes a large deformation, the four insulating layers with large thickness and rigidity can resist partial deformation of the substrate, thereby reducing the deformation of the cutting mark layer to a certain extent and reducing the number of bubbles.

[0135] Furthermore, the manufacturing process of the embodiment of the present invention can be implemented using mature manufacturing equipment, requiring minimal process improvements, offering high compatibility, simple process implementation, ease of implementation, high production efficiency, low production costs, and a high yield rate. In summary, the embodiment of the present invention avoids the situation where the cutting mark in the cutting area cannot be recognized, ensuring the accuracy and reliability of the cutting process, and has good application prospects.

[0136] Figure 10 This is a schematic diagram of another display motherboard structure according to an embodiment of the present invention, illustrating the cross-sectional structure of the display substrate region and the cutting region of a dual source / drain metal layer (dual SD or 2SD) structure. Figure 10As shown, the display motherboard of this embodiment includes a display substrate area 300 and a cutting area 400. The display substrate area 300 includes a driving structure layer provided on a substrate 10 and a light emitting structure layer provided on the driving structure layer. The cutting area 400 includes a composite insulating layer provided on the substrate 10, a cutting mark layer provided on the composite insulating layer, and an insulating layer covering the cutting mark layer. The driving structure layer of the display substrate area 300 includes a plurality of thin film transistors and storage capacitors forming a pixel driving circuit. Figure 8 Only a driving thin film transistor 101 and a storage capacitor 102 are used as an example for illustration. The driving structure layer mainly includes a first insulating layer 11 arranged on a substrate 10, a thin film transistor 101 and a storage capacitor 102 arranged on the first insulating layer 11, a fifth insulating layer 20 and a first planarization layer 21A covering the thin film transistor 101 and the storage capacitor 102, a second metal conductive layer arranged on the first planarization layer 21A, and a second planarization layer 21 covering the second metal conductive layer. The second metal conductive layer includes a connecting electrode 103 connected to the drain electrode of the thin film transistor 101. The light-emitting structure layer mainly includes an anode 22, a pixel definition layer 23, an organic light-emitting layer 24, a cathode 25, and an encapsulation layer 26. The composite insulating layer of the cutting area 400 includes a first insulating layer 11, a second insulating layer 13, a third insulating layer 16, a fourth insulating layer 18, a fifth insulating layer 20 and a first planarization layer 21A stacked in sequence on the substrate 10. The cutting identification layer includes an identification block 40 provided on the composite insulating layer. The insulating layer includes a second planarization layer 21 covering the cutting identification layer and a pixel definition layer 23 covering the second planarization layer 21. The second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 constitute the planarization layer covering the identification structure layer in an embodiment of the present invention. Figure 10 As shown, the second planarization layer 21 and the pixel definition layer 23 of the cutting area 400 are completely retained, and the surface away from the substrate 10 is flat, which effectively improves the overall rigidity of the film layer in the cutting area.

[0137] The preparation process of this embodiment includes:

[0138] (11) A substrate 10 is formed on a glass carrier 1, and the preparation process is the same as process (1) of the aforementioned embodiment.

[0139] (12) Preparing a driving structure layer and a cutting identification layer pattern on the substrate 10, including: sequentially forming a first insulating layer 11, an active layer 12, a second insulating layer 13, a first gate metal layer, a third insulating layer 16, a second gate metal layer, a fourth insulating layer 18 and a first source-drain metal layer on the substrate 10. The processing process is the same as that in the aforementioned embodiment, except that, when patterning the third metal film, the first source-drain metal layer pattern is only formed in the display substrate area 300, and the cutting identification layer is not formed in the cutting area 400.

[0140] Subsequently, a fifth insulating layer 20 and a first planarization layer 21A are formed to cover the first source-drain metal layer. A third via is provided on the fifth insulating layer 20 and the first planarization layer 21A. The third via is formed in the display substrate region 300, exposing the surface of the drain electrode 19B. Subsequently, a fourth metal film is deposited and patterned by a patterning process to form a second metal conductive layer and a cutting identification layer on the first planarization layer 21A. The second metal conductive layer is formed in the display substrate region 300, the cutting identification layer is formed in the cutting region 400, and the cutting identification layer includes at least two spaced-apart identification blocks 40. In this embodiment, the first source-drain metal layer includes at least a source electrode 19A, a drain electrode 19B, and a data line, and the second metal conductive layer includes a connecting electrode 103 connected to the drain electrode 19B through the third via. After this patterning process, the cutting area 400 includes a composite insulating layer disposed on the substrate 10 and a cutting identification layer disposed on the composite insulating layer. The composite insulating layer includes a stacked first insulating layer 11, a second insulating layer 13, a third insulating layer 16, a fourth insulating layer 18, a fifth insulating layer 20, and a first planarization layer 21A. The cutting identification layer includes an identification block 40. In one exemplary embodiment, the second metal conductive layer may further include any one or more of a power supply line (VDD), a low voltage line (VSS), a compensation line, and an auxiliary cathode, as needed.

[0141] At this point, the driving structure layer and the cutting mark layer pattern are prepared on the substrate 10, as shown in FIG. Figure 11 As shown, the active layer 12, gate electrode 14, source electrode 19A, and drain electrode 19B constitute a thin film transistor 101. The first capacitor electrode 15 and the second capacitor electrode 17 constitute a storage capacitor 102. The first source-drain metal layer includes at least the source electrode 19A and the drain electrode 19B. The second metal conductive layer includes at least the connecting electrode 103. The second metal conductive layer and the cutting mark layer are provided on the same layer and are formed through the same patterning process.

[0142] (13) A flat film is coated on the substrate formed with the aforementioned pattern, and a second flattening layer 21 covering the entire substrate 10 is formed through masking, exposure, and development processes. A fourth via hole is opened on the second flattening layer 21, and the fourth via hole is formed in the display substrate area 300. The flat film in the fourth via hole is developed away, exposing the surface of the connecting electrode 103, as shown in FIG. Figure 12As shown. In this process, the flattened film at the fourth via hole location is developed, while the second planarization layer 21 at the location corresponding to the cutting mark layer in the cutting area 400 is retained. As a result, the second planarization layer 21 in the cutting area 400 has a flat surface, and the thickness of the second planarization layer 21 in the cutting area 400 is the same as that of the second planarization layer 21 in the display substrate area. After this patterning process, the cutting area 400 includes a composite insulating layer disposed on the substrate 10, a cutting mark layer disposed on the composite insulating layer, and the second planarization layer 21 covering the cutting mark layer.

[0143] (14) An anode 22, a pixel definition layer 23, an organic light-emitting layer 24, a cathode 25 and an encapsulation layer 26 are sequentially formed on the substrate on which the aforementioned pattern is formed. The preparation process is the same as processes (4) to (6) of the aforementioned embodiment. The subsequent processes of attaching a protective film, peeling from the glass carrier, attaching a back film, and cutting are the same as those of the aforementioned embodiment and will not be repeated here.

[0144] like Figures 10 to 12 As shown, the display motherboard of this embodiment includes:

[0145] Base 10;

[0146] a first insulating layer 11 disposed on the substrate 10;

[0147] An active layer 12 is provided on the first insulating layer 11 , and the active layer 12 is provided in the display substrate region 300 ;

[0148] a second insulating layer 13 covering the active layer 12;

[0149] A first gate metal layer is provided on the second insulating layer 13 , the first gate metal layer is provided in the display substrate region 300 , and includes at least a gate electrode 14 and a first capacitor electrode 15 ;

[0150] a third insulating layer 16 covering the first gate metal layer;

[0151] A second gate metal layer is provided on the third insulating layer 16 , and the second gate metal layer is provided in the display substrate region 300 and includes at least a second capacitor electrode 17 ;

[0152] a fourth insulating layer 18 covering the second gate metal layer, on which two first via holes exposing the active layer 12 are formed, and the two first via holes are arranged in the display substrate region 300;

[0153] a first source-drain metal layer disposed on the fourth insulating layer 18 , the first source-drain metal layer being disposed in the display substrate region 300 and comprising at least a source electrode 19A and a drain electrode 19B, the source electrode 19A and the drain electrode 19B being connected to the active layer 12 through first vias, respectively;

[0154] A fifth insulating layer 20 and a first planarization layer 21A covering the first source / drain metal layer, wherein a third via hole exposing the drain electrode 19B is formed, and the third via hole is provided in the display substrate region 300;

[0155] A second metal conductive layer and a cutting mark layer are provided on the first planarization layer 21A; the second metal conductive layer is provided in the display substrate region 300 and includes at least a connection electrode 103, which is connected to the drain electrode 19B through a third via hole; the cutting mark layer is provided in the cutting region 400 and includes at least two spaced apart mark blocks 40; the second metal conductive layer and the cutting mark layer are provided on the same layer and are formed by the same patterning process;

[0156] The second planarization layer 21 covering the second metal conductive layer is provided with a fourth via hole exposing the connection electrode 103 , and the fourth via hole is provided in the display substrate region 300 ; the surface of the second planarization layer 21 in the cutting region 400 away from the substrate 10 is flush;

[0157] An anode 22 is provided on the second planarization layer 21 , the anode 22 is formed in the display substrate region 300 , and is connected to the connection electrode 103 through a fourth via hole;

[0158] The pixel definition layer 23 covering the anode 22 has a pixel opening exposing the anode 22 formed thereon. The pixel opening is formed in the display substrate region 300. The surface of the pixel definition layer 23 in the cutting region 400 away from the substrate 10 is flush.

[0159] An organic light emitting layer 24 is provided in the 300 pixel openings of the display substrate area, and the organic light emitting layer 24 is connected to the anode 22;

[0160] a cathode 25 disposed on the organic light-emitting layer 24 , the cathode 25 being connected to the organic light-emitting layer 24 ;

[0161] The encapsulation layer 26 is disposed in the display substrate region 300 .

[0162] The display motherboard of this embodiment also achieves the technical effects of the aforementioned embodiments, effectively reducing the deformation of the cutting mark layer caused by the roller pressure, avoiding the generation of bubbles in the cutting area, and eliminating the interference and influence of bubbles on the identification of the cutting mark, thereby avoiding the situation where the cutting mark in the cutting area cannot be identified. In addition, since this embodiment sets the cutting mark layer to be on the same layer as the second metal conductive layer in the display substrate area, that is, the cutting mark layer is set on the first planarization layer, and there are six insulating layers between the cutting mark layer and the substrate, namely the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the first planarization layer, the thickness and rigidity of the film layer between the cutting mark layer and the substrate are further increased, which can further reduce the deformation of the cutting mark layer, further reduce the number of bubbles, and minimize the situation where the cutting mark in the cutting area cannot be identified.

[0163] Figure 13 This is a schematic diagram of the structure of another display motherboard according to an embodiment of the present invention, which is the aforementioned Figure 2 The structure shown is an extension of the above Figure 2 The difference of the display motherboard shown is that after the driving structure layer and the cutting mark layer are formed in the display substrate area 300 and the cutting area 400 respectively, the second planarization layer 21 is formed directly on the driving structure layer and the cutting mark layer, that is, the display motherboard does not have a fifth insulating layer.

[0164] Figure 14 This is a schematic diagram of the structure of another display motherboard according to an embodiment of the present invention, which is the aforementioned Figure 10 The structure shown is an extension of the above Figure 10 The difference between the display motherboard shown is that after the first source-drain metal layer is formed, the first planarization layer 21A covering the first source-drain metal layer is directly formed, that is, the display motherboard is not provided with the fifth insulating layer.

[0165] The structure and preparation process shown in the embodiment of the present invention are merely exemplary. In the exemplary implementation, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs. For example, the OLED can be a top-emitting structure or a bottom-emitting structure. For another example, the driving thin-film transistor can be a top-gate structure or a bottom-gate structure, a single-gate structure or a dual-gate structure. For another example, other electrodes or leads can be provided in the driving structure layer and the light-emitting structure layer, and the embodiment of the present invention does not specifically limit this.

[0166] Based on any of the display motherboards in the aforementioned embodiments, an embodiment of the present invention further provides a method for preparing a display motherboard. The display motherboard includes a plurality of display substrate regions and a cutting region located around each of the display substrate regions. The preparation method includes:

[0167] S1. Forming a driving structure layer and a marking structure layer in a plurality of display substrate regions and a cutting region, respectively; the marking structure layer includes a cutting marking layer;

[0168] S2. Forming a planarization layer on the driving structure layer and the logo structure layer, wherein the planarization layer covers the logo structure layer.

[0169] In an exemplary embodiment, the driving structure layer includes a first source / drain metal layer, the marking structure layer includes a cutting marking layer, and step S1 includes:

[0170] A first insulating layer is formed on a substrate, an active layer is formed on the first insulating layer, a second insulating layer covering the active layer is formed, a first gate metal layer is formed on the second insulating layer, a third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, a fourth insulating layer covering the second gate metal layer is formed, and the first source-drain metal layer and a cutting mark layer are formed on the fourth insulating layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer are arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.

[0171] In an exemplary embodiment, step S2 includes:

[0172] forming a fifth insulating layer on the driving structure layer and the logo structure layer;

[0173] A second planarization layer and a pixel definition layer are sequentially formed on the fifth insulating layer. In the display substrate region, an anode is further formed between the second planarization layer and the pixel definition layer.

[0174] In an exemplary embodiment, the driving structure layer includes a second source / drain metal layer, and the marking structure layer includes a cutting marking layer. Step S1 includes:

[0175] A first insulating layer is formed on a substrate, an active layer is formed on the first insulating layer, a second insulating layer covering the active layer is formed, a first gate metal layer is formed on the second insulating layer, a third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, a fourth insulating layer covering the second gate metal layer is formed, a first source-drain metal layer is formed on the fourth insulating layer, a fifth insulating layer covering the first source-drain metal layer is formed, a first planarization layer is formed on the fifth insulating layer, and the second source-drain metal layer and a cutting mark layer are formed on the first planarization layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer are arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.

[0176] In an exemplary embodiment, step S2 includes:

[0177] A second planarization layer and a pixel definition layer are sequentially formed on the first planarization layer. In the display substrate region, an anode is further formed between the second planarization layer and the pixel definition layer.

[0178] In an exemplary embodiment, after forming a pixel definition layer on the planarization layer, the method further includes:

[0179] forming an organic light-emitting layer, a cathode and an encapsulation layer;

[0180] affixing a protective film on the encapsulation layer, wherein the protective film contacts the pixel definition layer in the cutting area;

[0181] Adhere a backing film to the surface of the substrate away from the planarization layer by roller bonding;

[0182] The display motherboard is cut to form a plurality of display substrates.

[0183] In an exemplary embodiment, after cutting the display mother panel, the method further includes:

[0184] removing the protective film;

[0185] A cover plate is formed on the encapsulation layer; or a touch layer and a cover plate are sequentially formed on the encapsulation layer.

[0186] An embodiment of the present invention provides a method for preparing a display motherboard. By retaining a complete planarization layer and pixel definition layer in the cutting area, and by locating the cutting mark layer in the cutting area on the same layer as the first source / drain metal layer in the display substrate area, the overall stiffness of the film layer in the cutting area is effectively improved, deformation caused by roller pressure is reduced, and the generation of bubbles in the cutting area is avoided, thereby preventing the cutting mark from being obscured by bubbles and thus making it unrecognizable. This ensures the accuracy and reliability of the cutting process. Furthermore, the preparation process of the embodiment of the present invention can be implemented using mature preparation equipment, with minimal process improvements, high compatibility, simple process implementation, ease of implementation, high production efficiency, low production cost, and high yield rate, thus having good application prospects.

[0187] An embodiment of the present invention further provides a display substrate, which is formed by cutting the display motherboard along the cutting area.

[0188] An embodiment of the present invention further provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0189] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A display motherboard, characterized in that: The display motherboard includes a plurality of display substrate areas and a cutting area located around each of the display substrate areas; The display motherboard includes: A driving structure layer is provided in each display substrate area, and a marking structure layer is provided in each cutting area; the marking structure layer includes a cutting marking layer and a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer stacked on the substrate, and the cutting marking layer is provided on a side of the fourth insulating layer away from the substrate; A planarization layer is arranged on the driving structure layer and the identification structure layer, and the planarization layer covers the identification structure layer; the planarization layer includes a second planarization layer covering the driving structure layer and the identification structure layer and a pixel definition layer arranged on the second planarization layer, and the second planarization layer and the pixel definition layer in the cutting area are completely retained, and the surface away from the side of the substrate is flat, so as to improve the overall stiffness of the film layer in the cutting area.

2. The display motherboard according to claim 1, wherein: The driving structure layer includes a first source-drain metal layer, and the marking structure layer includes a cutting marking layer. The cutting marking layer is provided in the same layer as the first source-drain metal layer.

3. The display motherboard according to claim 2, wherein: The driving structure layer also includes: a first insulating layer arranged on the substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, a fourth insulating layer covering the second gate metal layer, the first source and drain metal layer arranged on the fourth insulating layer; and the cutting identification layer is arranged on the fourth insulating layer.

4. The display motherboard according to claim 3, wherein: It also includes a fifth insulating layer; in the display substrate area, the fifth insulating layer is arranged on the driving structure layer; in the cutting area, the fifth insulating layer is arranged on the marking structure layer, and the planarization layer is arranged on the fifth insulating layer.

5. The display motherboard according to claim 4, characterized in that: In the display substrate region, an anode is further provided between the second planarization layer and the pixel definition layer.

6. The display motherboard according to claim 1, wherein: The driving structure layer includes a second source-drain metal layer, and the marking structure layer includes a cutting marking layer. The cutting marking layer and the second source-drain metal layer are provided in the same layer.

7. The display motherboard according to claim 6, wherein: The driving structure layer also includes: a first insulating layer arranged on the substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, a fourth insulating layer covering the second gate metal layer, a first source-drain metal layer arranged on the fourth insulating layer, a fifth insulating layer and a first planarization layer covering the first source-drain metal layer, and the second source-drain metal layer is arranged on the first planarization layer; the identification structure layer also includes: a fifth insulating layer and a first planarization layer stacked on the fourth insulating layer, and the cutting identification layer is arranged on the first planarization layer.

8. The display motherboard according to claim 7, wherein: In the display substrate region, an anode is further provided between the second planarization layer and the pixel definition layer.

9. The display motherboard according to any one of claims 1 to 8, characterized in that: It also includes a protective film; in the display substrate area, an encapsulation layer is provided on the planarization layer, and the protective film is provided on the encapsulation layer; in the cutting area, the protective film is provided on the planarization layer.

10. The display motherboard according to any one of claims 1 to 8, characterized in that: The cutting mark layer of the cutting area includes a plurality of cutting marks, and each of the cutting marks includes four spaced rectangular patterns arranged in a field shape.

11. A display substrate, characterized in that: The display motherboard according to any one of claims 1 to 10 is cut along the cutting area to form the display motherboard.

12. A display device, characterized in that: The display substrate comprises the display substrate as claimed in claim 11.

13. A method for preparing a display motherboard, characterized in that: The display motherboard includes a plurality of display substrate areas and a cutting area located around each of the display substrate areas. The preparation method includes: A driving structure layer and a marking structure layer are formed in the plurality of display substrate regions and the cutting region, respectively; the marking structure layer comprises a cutting marking layer and a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer stacked on the substrate, and the cutting marking layer is arranged on a side of the fourth insulating layer away from the substrate; A planarization layer is formed on the driving structure layer and the identification structure layer, and the planarization layer covers the identification structure layer; the planarization layer includes a second planarization layer covering the driving structure layer and the identification structure layer and a pixel definition layer arranged on the second planarization layer, and the second planarization layer and the pixel definition layer in the cutting area are completely retained, and the surface away from the side of the substrate is flat, so as to improve the overall stiffness of the film layer in the cutting area.

14. The preparation method according to claim 13, characterized in that The driving structure layer includes a first source / drain metal layer, and the identification structure layer includes a cutting identification layer. The driving structure layer and the identification structure layer are formed in a plurality of display substrate regions and cutting regions, respectively, including: A first insulating layer is formed on a substrate, an active layer is formed on the first insulating layer, a second insulating layer covering the active layer is formed, a first gate metal layer is formed on the second insulating layer, a third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, a fourth insulating layer covering the second gate metal layer is formed, and the first source-drain metal layer and a cutting mark layer are formed on the fourth insulating layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer are arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.

15. The preparation method according to claim 14, characterized in that Forming a planarization layer on the driving structure layer and the logo structure layer, comprising: forming a fifth insulating layer on the driving structure layer and the logo structure layer; A second planarization layer and a pixel definition layer are sequentially formed on the fifth insulating layer. In the display substrate region, an anode is further formed between the second planarization layer and the pixel definition layer.

16. The preparation method according to claim 13, characterized in that The driving structure layer includes a second source / drain metal layer, and the identification structure layer includes a cutting identification layer. The driving structure layer and the identification structure layer are formed in a plurality of display substrate regions and cutting regions, respectively, including: A first insulating layer is formed on a substrate, an active layer is formed on the first insulating layer, a second insulating layer covering the active layer is formed, a first gate metal layer is formed on the second insulating layer, a third insulating layer covering the first gate metal layer is formed, a second gate metal layer is formed on the third insulating layer, a fourth insulating layer covering the second gate metal layer is formed, a first source-drain metal layer is formed on the fourth insulating layer, a fifth insulating layer covering the first source-drain metal layer is formed, a first planarization layer is formed on the fifth insulating layer, and the second source-drain metal layer and a cutting mark layer are formed on the first planarization layer through the same patterning process; the active layer, the first gate metal layer, the second gate metal layer, the first source-drain metal layer and the second source-drain metal layer are arranged in the display substrate area, and the cutting mark layer is arranged in the cutting area.

17. The preparation method according to claim 16, characterized in that Forming a planarization layer on the driving structure layer and the logo structure layer, comprising: A second planarization layer and a pixel definition layer are sequentially formed on the first planarization layer. In the display substrate region, an anode is further formed between the second planarization layer and the pixel definition layer.

18. The preparation method according to any one of claims 13 to 17, characterized in that: Also includes: forming an organic light-emitting layer, a cathode and an encapsulation layer in sequence; A protective film is attached to the encapsulation layer, wherein the protective film contacts the pixel definition layer in the cutting area; Adhere a backing film to the surface of the substrate away from the planarization layer by roller bonding; The display motherboard is cut to form a plurality of display substrates.

19. The preparation method according to claim 18, characterized in that After cutting the display motherboard, the method further includes: removing the protective film; A cover plate is formed on the encapsulation layer; or a touch layer and a cover plate are sequentially formed on the encapsulation layer.

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