Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate, the substrate including an inactive region and an active region, a first fin structure being formed on the inactive region and a second fin structure being formed on the active region; forming a first dummy gate structure on the inactive region, spanning the first fin structure, with the first dummy gate structure located on a portion of the top surface and sidewall surfaces of the first fin structure; forming a dielectric layer on the substrate covering the surfaces of the first and second fin structures, with the dielectric layer exposing the top surface of the first dummy gate structure; removing the first dummy gate structure, forming a first opening in the dielectric layer on the inactive region, with the bottom of the first opening exposing a portion of the top surface and sidewall surfaces of the first fin structure; removing the first fin structure exposed at the bottom of the first opening, and forming a second opening in the first fin structure, with the second opening exposing the substrate surface. The semiconductor structure formed by the method has good performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of information technology, the amount of stored information has increased dramatically. This increase in the amount of stored information has promoted the rapid development of memory, but it has also put forward higher requirements for the stability of memory.

[0003] A basic static random access memory (SRAM) relies on six transistors that form two cross-coupled inverters. Each inverter consists of a pull-up transistor, a pull-down transistor, and an access transistor.

[0004] In order to obtain stronger anti-interference ability and higher reading stability, the transistor used to form the memory can be a trench gate surround (Gate-All-Around, referred to as GAA) structure transistor. Among them, for a given channel length and gate oxide thickness, GAA devices can exhibit the best subthreshold characteristics and control of short channel effects. In addition, the trench gate surround structure transistor is used as the volume increase of the channel region, which can further increase the operating current of the trench gate surround structure transistor, so that the application of the trench gate surround structure transistor in the memory can improve the data storage stability and integration of the memory.

[0005] However, the performance of semiconductor devices composed of existing static memories still needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the formed semiconductor structure.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate including an invalid area and an effective area, the invalid area having a first fin structure, and the effective area having a second fin structure; a dielectric layer located on the substrate and covering the first fin structure and the second fin structure, the dielectric layer on the invalid area having a first opening, and the first opening exposing a portion of the top surface and sidewall surface of the first fin structure; a second opening located in the first fin structure, the second opening being located at a portion of the bottom of the first opening, and the bottom of the second opening exposing the substrate surface.

[0008] Optionally, the method further includes: a third opening located in the dielectric layer above the active area, wherein the third opening exposes a portion of the top surface and sidewall surface of the second fin structure.

[0009] Optionally, the second fin structure includes a plurality of channel layers arranged along a normal direction of the substrate surface, and a fourth opening is provided between adjacent channel layers exposed by the third opening.

[0010] Optionally, the method further includes: a first sidewall located on the sidewall surface of the first opening, and the dielectric layer covers the sidewall surface of the first sidewall.

[0011] Optionally, the method further includes: a second sidewall located on the sidewall surface of the third opening, and the dielectric layer covers the sidewall surface of the second sidewall.

[0012] Optionally, it further includes: a first gate structure located in the first opening and the second opening.

[0013] Optionally, the method further includes: a second gate structure located in the third opening and the fourth opening, and the second gate structure surrounds each channel layer.

[0014] Optionally, it further includes: a source-drain doped layer in the second fin structure on both sides of the second gate structure, the source-drain doped layer is located at the bottom of the dielectric layer, and the source-drain doped layer covers the sidewall surface of the second fin structure layer.

[0015] Optionally, the method further includes: a first isolation layer located on the side wall surface of the second opening, wherein the side wall of the first isolation layer is flush with the side wall of the first sidewall on the inactive area.

[0016] Optionally, the method further includes: a second isolation layer located on the side wall surface of the fourth opening, and the side wall of the second isolation layer is flush with the side wall of the second sidewall on the active area.

[0017] Optionally, the method further includes: an isolation structure located on the surface of the substrate, the dielectric layer is located on the surface of the isolation structure, and the top surface of the isolation structure is lower than the top surfaces of the first fin structure and the second fin structure.

[0018] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including an invalid area and an effective area, the invalid area having a first fin structure, and the effective area having a second fin structure; forming a first dummy gate structure across the first fin structure on the invalid area, and the first dummy gate structure is located on part of the top surface and sidewall surface of the first fin structure; forming a dielectric layer covering the surfaces of the first fin structure and the second fin structure on the substrate, and the dielectric layer exposes the top surface of the first dummy gate structure; removing the first dummy gate structure, forming a first opening in the dielectric layer on the invalid area, the bottom of the first opening exposing part of the top surface and sidewall surface of the first fin structure; removing the first fin structure exposed at the bottom of the first opening, forming a second opening in the first fin structure, and the second opening exposing the substrate surface.

[0019] Optionally, the method for forming the first fin structure and the second fin structure includes: forming an initial fin structure on the substrate, the initial fin structure including a plurality of channel layers overlapping along the normal direction of the substrate surface and a sacrificial layer located on the surface of the channel layer; removing the channel layer on the invalid area, forming grooves between adjacent sacrificial layers on the invalid area and between the bottom sacrificial layer and the substrate, the channel layer and the sacrificial layer located on the effective area form the second fin structure; forming a filling layer in the groove, the filling layer and the sacrificial layer located on the invalid area form the first fin structure.

[0020] Optionally, the method for removing the channel layer on the invalid area includes: forming a first mask layer on the initial fin structure, the first mask layer exposing the surface of the initial fin structure on the invalid area; using the first mask layer as a mask, etching the channel layer on the invalid area to form grooves between adjacent sacrificial layers on the invalid area and between the bottom sacrificial layer and the substrate; after forming the grooves, removing the first mask layer.

[0021] Optionally, a second mask layer is formed on the top surface of the initial fin structure.

[0022] Optionally, the method for forming the filling layer includes: forming a filling film in the groove; and etching the filling film using the second mask layer as a mask to form the filling layer.

[0023] Optionally, it also includes: forming a first gate structure in the first opening and the second opening; the method for forming the first gate structure includes: forming a gate dielectric film on the surface of the first opening and the second opening, and on the surface of the dielectric layer; forming a gate electrode film on the surface of the gate dielectric film, and the gate electrode film fills the first opening and the second opening; flattening the gate electrode film and the gate dielectric film until the surface of the dielectric layer is exposed, so that the gate dielectric film forms a gate dielectric layer, and the gate electrode film forms a gate electrode layer, and the first gate structure is formed in the first opening and the second opening.

[0024] Optionally, the method further includes: before forming the dielectric layer, forming a first sidewall spacer on the sidewall surface of the first dummy gate structure.

[0025] Optionally, it also includes: before forming the dielectric layer, forming a second dummy gate structure across the second fin structure on the effective area, and the second dummy gate structure is located on a portion of the top surface and sidewall surface of the second fin structure, and the dielectric layer exposes the top surface of the second dummy gate structure; forming a second sidewall on the sidewall surface of the second dummy gate structure.

[0026] Optionally, it also includes: after forming the dielectric layer and before forming the second opening, removing the second pseudo gate structure, forming a third opening in the dielectric layer on the effective area, and exposing part of the top surface and sidewall surface of the second fin structure.

[0027] Optionally, the method further includes: after forming the third opening, removing the sacrificial layer exposed by the third opening, and forming a fourth opening between adjacent channel layers.

[0028] Optionally, the method further includes: forming a second gate structure in the third opening and the fourth opening, wherein the second gate structure surrounds each of the channel layers.

[0029] Optionally, it also includes: after forming the second pseudo gate structure and before forming the dielectric layer, removing the second fin structure on both sides of the second pseudo gate structure, forming source and drain openings in the second fin structure on both sides of the second pseudo gate structure; forming a source and drain doping layer in the source and drain openings; after forming the source and drain doping layer, forming the dielectric layer on the substrate, and the dielectric layer is located on the surface of the source and drain doping layer.

[0030] Optionally, after forming the source / drain openings and before forming the source / drain doping layers, a portion of the sacrificial layer exposed on the sidewalls of the source / drain openings is removed to form a second fin groove between adjacent channel layers; and a second isolation layer is formed in the second fin groove.

[0031] Optionally, the method for forming the source and drain openings also includes: removing the first fin structure on both sides of the first pseudo gate structure, and the source and drain openings are also located in the first fin structure on both sides of the first pseudo gate structure; the method for forming the semiconductor structure also includes: removing the portion of the first fin structure exposed by the sidewalls of the source and drain openings, forming a first fin groove at the bottom of the first pseudo gate structure; and forming a first isolation layer in the first fin groove.

[0032] Optionally, the first isolation layer and the second isolation layer are formed in the same process.

[0033] Optionally, the method for forming the first isolation layer and the second isolation layer includes: forming an isolation material film on the substrate surface, the first fin groove, the top surface and sidewall surface of the first pseudo gate structure, the second fin groove, and the top surface and sidewall surface of the second pseudo gate structure; etching back the isolation material film until the substrate surface and the channel layer sidewall surface are exposed to form the first isolation layer and the second isolation layer, the first isolation layer is located in the first fin groove at the bottom of the first pseudo gate structure, and the second isolation layer is located in the second fin groove.

[0034] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0035] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a first opening is formed in the dielectric layer on the invalid area by removing the first dummy gate structure, and the bottom of the first opening exposes part of the top surface of the first fin structure; the first fin structure exposed at the bottom of the first opening is removed, and a second opening is formed in the first fin structure, and the second opening is located at the bottom of the first opening, and the second opening exposes the substrate surface, so that the first gate structure subsequently formed in the first opening and the second opening is located on the substrate surface, and therefore, the device formed on the invalid area is an invalid device. At the same time, before removing the first fin structure exposed at the bottom of the first opening, the first fin structure is conducive to maintaining morphological consistency with the second fin structure on the effective area, so that the first fin structure can reduce process deviations, which is conducive to forming devices with better morphology on the substrate in the first and second areas in subsequent process steps. In summary, the method is conducive to improving the performance of the formed semiconductor structure.

[0036] Furthermore, a second gate structure is formed on the active area, and the second gate structure surrounds each channel layer. Furthermore, the second fin structures on both sides of the second gate structure have source and drain doped layers, and the source and drain doped layers are connected to the channel layers, so that the channel layers can be used to provide channels. Thus, an active device is formed on the active area.

[0037] Furthermore, since the second isolation layer is located within the second fin recess, which is formed by etching a portion of the sacrificial layer at the bottom of the second dummy gate structure, and a portion of the second gate structure is located within the fourth opening, which is formed by removing the sacrificial layer in the second fin structure at the bottom of the second dummy gate structure, the second gate structure is located on the sidewall surface of the second isolation layer. Furthermore, the source-drain doped layer is located on the sidewall surface of the second isolation layer, and therefore, the second isolation layer is located between the source-drain doped layer and the second gate structure. The second isolation layer is beneficial for increasing the isolation performance between the subsequently formed source-drain doped layer and the second gate structure, and is beneficial for reducing the parasitic capacitance between the second gate structure and the source-drain doping, thereby improving the performance of the formed semiconductor structure.

[0038] Furthermore, since the first isolation layer is located within the first fin recess, which is formed by etching a portion of the first fin structure at the bottom of the first dummy gate structure, and a portion of the first gate structure is located within the second opening, which is formed by removing the first fin structure at the bottom of the first dummy gate structure, the first gate structure is located on the sidewall surface of the first isolation layer. Furthermore, the source-drain doped layer is located on the sidewall surface of the first isolation layer, and thus, the first isolation layer is located between the source-drain doped layer and the first gate structure. The first isolation layer is beneficial for increasing the isolation performance between the subsequently formed source-drain doped layer and the first gate structure, and is beneficial for reducing the parasitic capacitance between the first gate structure and the source-drain doping, thereby improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figures 1 to 3 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0040] Figures 4 to 21 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] As described in the background art, the performance of existing semiconductor structures is poor.

[0042] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 3 The present invention is a structural schematic diagram of each step of a semiconductor structure forming method.

[0043] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes adjacent inactive regions I and active regions II, and an initial fin structure 110 is formed on the inactive regions I and active regions II.

[0044] Please refer to Figure 2, the initial fin structure 110 on the inactive area I is removed, and a fin structure 111 is formed on the active area I.

[0045] Please refer to Figure 3 A first gate structure 120 is formed on the inactive region I, and a second gate structure 130 is formed on the active region II across the fin structure 111 , wherein the second gate structure 130 covers a portion of the top surface and sidewall surface of the fin structure 111 .

[0046] In the above method, the first gate structure 120 is used to form a first pull-up transistor, and the second gate structure 130 is used to form a second pull-up transistor. By removing the initial fin structure 110 on the inactive region I, there is no electrical connection between the first gate structure 120 and the second gate structure 130, thereby meeting process requirements.

[0047] However, since it is necessary to remove the initial fin structure 110 on the invalid area I and retain the initial fin structure on the effective area II to form the fin structure 111, the absence of the initial fin structure 110 on the invalid area I reduces the uniformity of the device density on the substrate 100, causing subsequent process steps to easily produce deviations on the invalid area I and the effective area II. For example, the device morphology formed on the invalid area I and the effective area II is inconsistent, resulting in poor performance of the formed semiconductor structure.

[0048] To address the aforementioned technical issues, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: removing the first dummy gate structure, forming a first opening in the dielectric layer above the inactive region, wherein the bottom of the first opening exposes a portion of the top surface of the first fin structure and the substrate surface; removing the first fin structure exposed at the bottom of the first opening, and forming a second opening in the first fin structure, wherein the second opening exposes the substrate surface. This method is advantageous for improving the performance of the resulting semiconductor structure.

[0049] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] Figures 4 to 21 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure in an embodiment of the present invention.

[0051] A substrate is provided. The substrate includes an inactive region and an active region. A first fin structure is formed on the inactive region, and a second fin structure is formed on the active region.

[0052] In this embodiment, the substrate surface has an isolation structure, the isolation structure covers part of the sidewall surface of the first fin structure and part of the sidewall surface of the second fin structure, and the top surface of the isolation structure is lower than the top surface of the first fin structure and the second fin structure. For the specific process of forming the first fin structure and the second fin structure, please refer to Figures 4 to 7 .

[0053] Please refer to Figure 4 and Figure 5 , Figure 5 for Figure 4 A schematic cross-sectional view along the A-A1 cutting line and the A2-A3 cutting line shows a substrate 200 , which includes an inactive region I and an active region II.

[0054] The material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0055] Please continue to refer to Figure 4 and Figure 5 An initial fin structure 210 is formed on the substrate 200. The initial fin structure 210 includes a plurality of channel layers 211 overlapping along the normal direction of the substrate surface and a sacrificial layer 212 located on the surface of the channel layer 211. The channel layer 211 and the sacrificial layer 212 are made of different materials.

[0056] The material of the channel layer 211 includes: single crystal silicon or single crystal silicon germanium. In this embodiment, the material of the channel layer 211 is silicon.

[0057] The material of the sacrificial layer 212 includes: single crystal silicon or single crystal silicon germanium. In this embodiment, the material of the sacrificial layer 212 is silicon germanium.

[0058] In this embodiment, the top surface of the initial fin structure 210 further has a second mask layer 213 .

[0059] The second mask layer 213 has the following functions: on the one hand, to protect the surface of the initial fin structure 210 from being affected by subsequent processes; on the other hand, to serve as a mask layer for subsequent etching filling film to form a filling layer in the groove.

[0060] The material of the second mask layer 213 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride.

[0061] In this embodiment, the material of the second mask layer 213 is silicon nitride.

[0062] The method for forming the initial fin structure 210 includes: forming a fin material film (not shown in the figure) on the substrate 200, the fin material film including a plurality of channel material films (not shown in the figure) overlapping along the normal direction of the surface of the substrate 200, and a sacrificial material film (not shown in the figure) located on the surface of the channel material film; forming a second mask material film (not shown in the figure) on the surface of the fin material film; forming a patterned layer on the surface of the second mask material film; using the patterned layer as a mask, etching the fin material film to form an initial fin structure, and forming the channel material film into a channel layer 211, the sacrificial material film into a sacrificial layer 212, and the second mask material film into a second mask layer 213.

[0063] Please refer to Figure 6 and Figure 7 , Figure 6 For Figure 4 Based on the schematic diagram, Figure 7 For Figure 5 Based on the schematic diagram, the channel layer 211 on the invalid area I is removed, and grooves 205 are formed between adjacent sacrificial layers 212 on the invalid area I, and between the bottom sacrificial layer 211 and the substrate 200. The channel layer 211 and the sacrificial layer 212 located on the effective area II form the second fin structure 222.

[0064] The groove 205 is used to be subsequently filled with a material to form a filling layer. The filling layer and the sacrificial layer 212 together form a first fin structure.

[0065] The method for removing the channel layer 211 on the invalid area I includes: forming a first mask layer 225 on the initial fin structure 210, the first mask layer 225 exposing the surface of the initial fin structure 210 on the invalid area I; using the first mask layer 225 as a mask, etching the channel layer 211 on the invalid area I, and forming a groove 205 between adjacent sacrificial layers 211 on the invalid area I, and between the bottommost sacrificial layer 211 and the substrate 200; after forming the groove 205, removing the first mask layer 225.

[0066] Specifically, in this embodiment, the first mask layer 225 is located on the surface of the second mask layer 213 .

[0067] Specifically, the first mask layer 225 covers the top surface and sidewall surfaces of the initial fin structure 210 on the active region II.

[0068] The process of etching the channel layer 211 on the ineffective area I includes: a dry etching process and a wet etching process, or a combination of the two.

[0069] In this embodiment, the process for etching the channel layer 211 on the inactive region I is a wet etching process. The process parameters of the wet etching include: the etching solution used is a tetramethylammonium hydroxide solution, and the concentration of the tetramethylammonium hydroxide solution is 3% to 20%. The wet etching process is easy to etch the channel layer 211.

[0070] Please refer to Figure 8 and Figure 9 , Figure 8 For Figure 6 Based on the schematic diagram, Figure 9 For Figure 7 Based on the schematic diagram, a filling layer 215 is formed in the groove 205 , and the filling layer 215 and the sacrificial layer 212 located on the ineffective area I form the first fin structure 221 .

[0071] The method for forming the filling layer 215 includes: forming a filling film (not shown in the figure) in the groove 205 ; and etching the filling film using the second mask layer 213 as a mask to form the filling layer 215 .

[0072] The material of the filling film is different from that of the channel layer 211 .

[0073] In this embodiment, the material of the filling film is the same as that of the sacrificial layer 212, namely silicon germanium. In other embodiments, the material of the filling film may be different from that of the sacrificial layer. Accordingly, in this embodiment, the material of the filling layer 215 is silicon germanium.

[0074] The filling film is formed by a chemical vapor deposition process or an epitaxial growth process. In this embodiment, the filling film is formed by an epitaxial growth process.

[0075] At this point, the first fin structure 221 on the invalid area I and the second fin structure 222 on the effective area II are formed. The first fin structure 221 includes several filling layers 215 overlapping along the normal direction of the surface of the substrate 200 and a sacrificial layer 212 located on the surface of the filling layer 215. The second fin structure 222 includes several channel layers 211 overlapping along the normal direction of the surface of the substrate 200 and a sacrificial layer 212 located on the surface of the channel layer 211.

[0076] The second fin structure 222 is used to form a pull-up transistor on the active region II.

[0077] It should be noted that, in this embodiment, the first fin structure 221 and the second fin structure 222 are adjacent to and connected.

[0078] In this embodiment, the method for forming the semiconductor structure further includes: forming an isolation structure (not shown in the figure) on the substrate 200 to cover a portion of the sidewalls of the first fin structure 221 and the second fin structure 222 .

[0079] A top surface of the isolation structure is lower than top surfaces of the first fin structure 221 and the second fin structure 222 .

[0080] The isolation structure is used to achieve electrical isolation between different devices.

[0081] Please refer to Figure 10 and Figure 11 , Figure 10 For Figure 8 Based on the schematic diagram, Figure 11 For Figure 9 Based on the schematic diagram, a first dummy gate structure 231 is formed on the ineffective region I across the first fin structure 221, and the first dummy gate structure 231 is located on a portion of the top surface and sidewall surface of the first fin structure 221.

[0082] In this embodiment, the method for forming the semiconductor structure further includes: forming a second dummy gate structure 232 across the second fin structure 222 on the active region II, and the second dummy gate structure 232 is located on a portion of the top surface and sidewall surface of the second fin structure 222.

[0083] In this embodiment, the first dummy gate structure 231 and the second dummy gate structure 232 are formed in the same process. In other embodiments, the first dummy gate structure and the second dummy gate structure are formed sequentially.

[0084] The method for forming the first dummy gate structure 231 and the second dummy gate structure 232 includes: forming a dummy gate dielectric material film (not shown in the figure) covering the surface of the first fin structure 221 and the second fin structure 222 on the substrate 200; forming a dummy gate electrode material film (not shown in the figure) on the dummy gate dielectric material film; etching the dummy gate dielectric material film and the dummy gate electrode material film until the surface of the substrate 200 is exposed, forming a first dummy gate structure 231 on the first fin structure 221, and forming a second dummy gate structure 232 on the second fin structure 222.

[0085] In this embodiment, the method for forming the semiconductor structure further includes: forming a first sidewall spacer (not labeled) on the sidewall surface of the first dummy gate structure 231; and forming a second sidewall spacer (not labeled) on the sidewall surface of the second dummy gate structure 232.

[0086] The first sidewall spacer and the second sidewall spacer are used to protect the sidewall surface of the first dummy gate structure 231 and the sidewall surface of the second dummy gate structure 232, so as to avoid morphological defects in the subsequently formed first gate structure and second gate structure, thereby affecting the electrical performance of the semiconductor structure.

[0087] In this embodiment, the method for forming the semiconductor structure further includes: forming a first protective layer (not shown in the figure) on the top surface of the first dummy gate structure 231; and forming a second protective layer (not shown in the figure) on the top surface of the second dummy gate structure 232.

[0088] The first protective layer and the second protective layer are used to protect the top surface of the first dummy gate structure 231 and the top surface of the second dummy gate structure 232 when the source and drain doping layers are subsequently formed, so as to avoid affecting the height of the gate structure when the first dummy gate structure 231 is subsequently removed to form the first gate structure and the second dummy gate structure 232 is removed to form the second gate structure.

[0089] Please refer to Figure 12 , Figure 12 For Figure 10 Based on the schematic diagram, the second fin structures 222 on both sides of the second dummy gate structure 232 are removed, and source and drain openings 240 are formed in the second fin structures 222 on both sides of the second dummy gate structure 232 .

[0090] The source / drain openings 240 are used for subsequent formation of source / drain doping layers.

[0091] In this embodiment, the method for forming the source / drain openings 240 further includes: removing the first fin structures 221 on both sides of the first dummy gate structure 231 , so that the formed source / drain openings 240 are also located in the first fin structures 221 on both sides of the first dummy gate structure 231 .

[0092] In this embodiment, specifically, the first fin structure 221 and the second fin structure 222 are etched using the first dummy gate structure 231 and the second dummy gate structure 232 as masks, respectively.

[0093] The process of etching the first fin structure 221 and the second fin structure 222 includes: a dry etching process and a wet etching process, or a combination of the two.

[0094] In this embodiment, the process of etching the first fin structure 221 and the second fin structure 222 is a dry etching process.

[0095] Please refer to Figure 13 , removing the portion of the sacrificial layer 211 exposed on the sidewalls of the source / drain openings 240 , and forming a second fin recess 252 between adjacent channel layers 212 .

[0096] The second fin groove 252 is used to provide space for the subsequent formation of a second isolation layer.

[0097] Specifically, the second fin groove 252 is recessed relative to the sidewall of the second sidewall.

[0098] The sidewalls of the source / drain opening 240 on the active region II expose the sidewall surfaces of the second fin groove 252 . Meanwhile, a source / drain doping layer will be formed in the source / drain opening 240 , so that the second isolation layer formed in the second fin groove 240 is located on the sidewall surfaces of the source / drain doping layer.

[0099] In this embodiment, the further step includes removing a portion of the first fin structure 221 exposed by the sidewalls of the source / drain opening 240 , and forming a first fin recess 251 at the bottom of the first dummy gate structure 231 .

[0100] Specifically, portions of the sacrificial layer 212 and the filling layer 215 exposed on the sidewalls of the source / drain opening 240 are removed, and the sidewalls of the first fin recess 251 are recessed relative to the sidewalls of the first spacer.

[0101] The first fin groove 251 is used to provide space for the subsequent formation of a first isolation layer.

[0102] In this embodiment, the process of removing the portion of the sacrificial layer 211 exposed by the sidewalls of the source / drain opening 240 and the process of removing the portion of the sacrificial layer 212 and the filling layer 215 exposed by the sidewalls of the source / drain opening 240 are formed in the same process, and a wet etching process is used to form the first fin groove 251 and the second fin groove 252.

[0103] The sidewalls of the source / drain opening 240 on the inactive region I expose the sidewall surface of the first fin groove 251. At the same time, a source / drain doping layer will be formed in the source / drain opening 240, so that the first isolation layer formed in the first fin groove 251 is located on the sidewall surface of the source / drain doping layer.

[0104] Please refer to Figure 14 and Figure 15 , Figure 14 and Figure 13 The viewing direction is the same as Figure 15 and Figure 11 In the same viewing direction as FIG, a second isolation layer 262 is formed in the second fin groove 252.

[0105] In this embodiment, the method further includes forming a first isolation layer 261 in the first fin groove 251 .

[0106] In this embodiment, the first isolation layer 261 and the second isolation layer 262 are formed in the same process.

[0107] The method for forming the first isolation layer 261 and the second isolation layer 262 includes: forming an isolation material film (not shown in the figure) on the surface of the substrate 00, in the first fin groove 251, on the top surface and sidewall surface of the first pseudo gate structure 231, the second fin groove 252, and the top surface and sidewall surface of the second pseudo gate structure 232; etching back the isolation material film until the surface of the substrate 200 and the sidewall surface of the channel layer 211 are exposed to form the first isolation layer 261 and the second isolation layer 262, the first isolation layer 2621 is located in the first fin groove 251 at the bottom of the first pseudo gate structure 231, and the second isolation layer 262 is located in the second fin groove 252 at the bottom.

[0108] Please continue to refer to Figure 14 and Figure 15 After forming the first isolation layer 261 and the second isolation layer 262 , a source-drain doping layer 270 is formed in the source-drain opening 240 .

[0109] The process of forming the source / drain doping layer 270 includes an in-situ epitaxial growth process.

[0110] The source-drain doping layer 270 is also doped with source-drain ions, which include P-type ions, such as boron ions or BF 2+ , or N-type ions, including phosphorus ions, arsenic ions or antimony ions. The process of doping source and drain ions in the source and drain doping layer 270 includes: ion implantation process or in-situ doping process.

[0111] Please refer to Figure 16 and Figure 17 , Figure 16 For Figure 14 Based on the schematic diagram, Figure 17 For Figure 15 Based on the schematic diagram, after the source-drain doping layer 270 is formed, a dielectric layer 280 covering the surface of the first fin structure 221 and the second fin structure 222 is formed on the substrate 200, and the dielectric layer 280 exposes the top surface of the first pseudo gate structure 231.

[0112] In this embodiment, the dielectric layer 280 also exposes the top surface of the second dummy gate structure 232 .

[0113] The dielectric layer 280 provides support for the subsequent removal of the first dummy gate structure 231 to form a first opening, and the removal of the second dummy gate structure 232 to form a third opening.

[0114] The dielectric layer 280 covers the sidewall surfaces of the first dummy gate structure 231 and the second dummy gate structure 232 .

[0115] The material of the dielectric layer 280 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbon nitride oxide, or silicon oxynitride. In this embodiment, the material of the dielectric layer 280 is silicon oxide.

[0116] Please refer to Figure 18 and Figure 19 , Figure 18 For Figure 16 Based on the schematic diagram, Figure 19 For Figure 17 Based on the schematic diagram, the first pseudo gate structure 231 is removed, and a first opening 291 is formed in the dielectric layer 280 on the invalid area I, and the bottom of the first opening 291 exposes part of the top surface and sidewall surface of the first fin structure 221.

[0117] In this embodiment, the method for forming the semiconductor structure further includes: removing the second dummy gate structure 232 , forming a third opening 293 in the dielectric layer 280 on the active region II, and exposing part of the top surface and sidewall surface of the second fin structure 232 .

[0118] The process of removing the first dummy gate structure 231 and the second dummy gate structure 232 includes: a dry etching process and a wet etching process, or a combination of the two.

[0119] In this embodiment, the process of removing the first dummy gate structure 231 and the second dummy gate structure 232 is a combination of a wet etching process and a dry etching process.

[0120] Please continue to refer to Figure 18 and Figure 19 , the first fin structure 221 exposed at the bottom of the first opening 291 is removed, and a second opening 292 is formed in the first fin structure 221 , and the second opening 292 exposes the surface of the substrate 200 .

[0121] In this embodiment, the method for forming the semiconductor structure further includes: removing the sacrificial layer 211 exposed by the third opening 293 , and forming a fourth opening 294 between adjacent channel layers 212 .

[0122] Specifically, the first fin structure 221 includes a plurality of overlapping sacrificial layers 212 and filling layers 215, and the second fin structure 222 includes a plurality of overlapping channel layers 211 and sacrificial layers 212.

[0123] In this embodiment, the sacrificial layer 212 is made of silicon germanium, the filling layer 215 is made of silicon germanium, and the channel layer 211 is made of silicon.

[0124] In this embodiment, the sacrificial layer 212 and the filling layer 215 are made of the same material and are etched using a wet etching process. The process parameters for the wet etching include: the etching solution is dilute hydrofluoric acid, and the concentration of the dilute hydrofluoric acid is 3% to 20%. The wet etching process removes the sacrificial layer 212 and the filling layer 215 in the first fin structure 221 exposed by the first opening 291, forming a second opening 292 in the first fin structure 221, and exposing the surface of the substrate 200. Simultaneously, the wet etching process also removes the sacrificial layer 212 in the second fin structure 222 exposed by the third opening, forming a fourth opening 294 between adjacent channel layers 211.

[0125] Please refer to Figure 20 and Figure 21 , Figure 20 For Figure 18 Based on the schematic diagram, Figure 21 For Figure 19 As shown in the schematic diagram above, a first gate structure 295 is formed in the first opening 291 and the second opening 292 .

[0126] In this embodiment, the method further includes forming a second gate structure 296 in the third opening 293 and the fourth opening 294 .

[0127] The method for forming the first gate structure 295 includes: forming a gate dielectric film (not shown in the figure) on the surface of the first opening 291 and the second opening 292, and the surface of the dielectric layer 180; forming a gate electrode film (not shown in the figure) on the surface of the gate dielectric film, and the gate electrode film fills the first opening 291 and the second opening 292; flattening the gate electrode film and the gate dielectric film until the surface of the dielectric layer 280 is exposed, so that the gate dielectric film forms a gate dielectric layer, and the gate electrode film forms a gate electrode layer, and the first gate structure 295 is formed in the first opening 291 and the second opening 292.

[0128] Since the second isolation layer 262 is located within the second fin recess 252, which is formed by etching a portion of the sacrificial layer 212 at the bottom of the second dummy gate structure 232, and a portion of the second gate structure 296 is located within the fourth opening 294, which is formed by removing the sacrificial layer 212 in the second fin structure 222 at the bottom of the second dummy gate structure 232, the second gate structure 296 is located on the sidewall surface of the second isolation layer 262. Furthermore, the source-drain doped layer 270 is located on the sidewall surface of the second isolation layer 262. Therefore, the second isolation layer 262 is located between the source-drain doped layer 270 and the second gate structure 296. The second isolation layer 262 is conducive to increasing the isolation performance between the subsequently formed source-drain doped layer 270 and the second gate structure 296, and is conducive to reducing the parasitic capacitance between the second gate structure 296 and the source-drain doped layer 270, thereby improving the performance of the formed semiconductor structure.

[0129] Since the first isolation layer 261 is located within the first fin recess 251, which is formed by etching a portion of the first fin structure 221 at the bottom of the first dummy gate structure 231, and a portion of the first gate structure 295 is located in the second opening 292, which is formed by removing the first fin structure 221 at the bottom of the first dummy gate structure 231, the first gate structure 295 is located on the sidewall surface of the first isolation layer 261. Furthermore, the source-drain doped layer 270 is located on the sidewall surface of the first isolation layer 261. Therefore, the first isolation layer 261 is located between the source-drain doped layer 270 and the first gate structure 295. The first isolation layer 261 is conducive to increasing the isolation performance between the formed source-drain doped layer 270 and the first gate structure 295, and is conducive to reducing the parasitic capacitance between the first gate structure 295 and the source-drain doped layer 270, thereby improving the performance of the formed semiconductor structure.

[0130] In this embodiment, the gate dielectric film is also located on the surface of the third opening 293 and the fourth opening 294 to form the gate dielectric film; the gate electrode film also fills the third opening 293 and the fourth opening 294; the gate dielectric film and the gate electrode film are planarized to form a gate dielectric layer and a gate electrode layer, and the gate dielectric layer and the gate electrode layer located in the third opening 293 and the fourth opening 294 form a second gate structure 296, and the second gate structure 296 surrounds each of the channel layers 211.

[0131] A second gate structure 296 is formed on the active region II, and the second gate structure 296 surrounds each channel layer 211. Furthermore, source-drain doped layers 270 are provided in the second fin structures 222 on both sides of the second gate structure 296, and the source-drain doped layers 270 are connected to the channel layers 211, so that the channel layers 211 can be used to provide channels. Thus, an active device is formed on the active region II.

[0132] In this embodiment, the second gate structure 296 on the active region I is used to form a channel gate-around structure transistor.

[0133] By removing the first dummy gate structure 231, a first opening 291 is formed in the dielectric layer 280 on the inactive region I. The bottom of the first opening 291 exposes a portion of the top surface of the first fin structure 221. The first fin structure 221 exposed at the bottom of the first opening 291 is removed, and a second opening 292 is formed in the first fin structure 221. The second opening 292 is located at the bottom of the first opening 291 and exposes the bottom surface of the substrate 200. This allows the first gate structure 295 formed in the first and second openings 291 and 292 to be located on the surface of the substrate 200. Therefore, the device formed on the inactive region I is an inactive device. At the same time, before removing the first fin structure 221 exposed at the bottom of the first opening 291, the first fin structure 221 is conducive to maintaining morphological consistency with the second fin structure 222 on the active region II. This allows the first fin structure 221 to reduce process deviations, which is conducive to forming devices with better morphology on the substrate 200 in the inactive region I and the active region II in subsequent process steps. In summary, the method is beneficial to improving the performance of the formed semiconductor structure.

[0134] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please refer to Figure 18 , including: a substrate 200, the substrate 200 including an inactive area I and an active area II, the inactive area I having a first fin structure 221, the active area II having a second fin structure 222; a dielectric layer 280 located on the substrate 200 and covering the first fin structure 221 and the second fin structure 222, the dielectric layer 280 on the inactive area I having a first opening 291, and the first opening 291 exposing a portion of the top surface and sidewall surface of the first fin structure 221; a second opening 292 located in the first fin structure 221, the second opening 292 being located at a portion of the bottom of the first opening 291, and the bottom of the second opening 292 exposing the surface of the substrate 200.

[0135] The following is a detailed description with reference to the accompanying drawings.

[0136] The semiconductor structure further includes a third opening 293 located in the dielectric layer 280 on the active region II, and the third opening 293 exposes a portion of the top surface and sidewall surfaces of the second fin structure 222 .

[0137] The second fin structure 222 includes a plurality of channel layers 211 arranged along a normal direction of the surface of the substrate 200 , and a fourth opening 294 is defined between adjacent channel layers 211 exposed by the third opening 293 .

[0138] The semiconductor structure further includes a first spacer (not labeled) located on a sidewall surface of the first opening 291 , and the dielectric layer 280 covers the sidewall surface of the first spacer.

[0139] The semiconductor structure further includes a second sidewall spacer (not labeled) located on a sidewall surface of the third opening 293 , and the dielectric layer 280 covers the sidewall surface of the second sidewall spacer.

[0140] In this embodiment, the semiconductor structure further includes a first gate structure 295 located in the first opening 291 and the second opening 292 .

[0141] The semiconductor structure further includes a second gate structure 296 located in the third opening 293 and the fourth opening 294 , and the second gate structure 296 surrounds each channel layer 211 .

[0142] The semiconductor structure further includes: a source-drain doped layer 270 located in the second fin structure 222 on both sides of the second gate structure 296 , and the source-drain doped layer 270 is located at the bottom of the dielectric layer 280 and covers the sidewall surface of the second fin structure layer 222 .

[0143] In this embodiment, the source-drain doped layer 270 is also located in the first fin structure 221 on both sides of the first gate structure 295 , and the source-drain doped layer 270 also covers the sidewall surface of the first fin structure 221 .

[0144] The semiconductor structure further includes a first isolation layer 261 located on the sidewall surface of the second opening 292 , and the sidewall of the first isolation layer 261 is flush with the sidewall of the first spacer on the inactive region I.

[0145] The source-drain doped layer 270 further includes a second isolation layer 262 located on the sidewall surface of the fourth opening 294 , and the sidewall of the second isolation layer 262 is flush with the sidewall of the second spacer on the active region II.

[0146] In this embodiment, the semiconductor structure further includes: an isolation structure located on the surface of the substrate 200 , the dielectric layer 280 is located on the surface of the isolation structure, and the top surface of the isolation structure is lower than the top surfaces of the first fin structure 221 and the second fin structure 222 .

[0147] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising an inactive region and an active region, wherein the inactive region has a first fin structure, and the active region has a second fin structure; a dielectric layer located on the substrate and covering the first fin structure and the second fin structure, wherein the dielectric layer on the inactive area has a first opening therein, and the first opening exposes a portion of a top surface and a sidewall surface of the first fin structure; a second opening located in the first fin structure, the second opening being formed by removing the first fin structure exposed by a bottom portion of the first opening, the second opening being located at a portion of the bottom portion of the first opening, and the bottom portion of the second opening exposing the substrate surface; a third opening located in the dielectric layer above the active area, wherein the third opening exposes a portion of a top surface and a sidewall surface of the second fin structure; The second fin structure includes a plurality of channel layers arranged along a normal direction of a substrate surface, and a fourth opening is provided between adjacent channel layers exposed by the third opening; a second gate structure located within the third opening and the fourth opening, wherein the second gate structure surrounds each channel layer; The device formed on the invalid area is an invalid device; wherein, The method for forming the first fin structure and the second fin structure includes: forming an initial fin structure on the substrate, the initial fin structure including a plurality of channel layers overlapping along a normal direction of the substrate surface and a sacrificial layer located on the surface of the channel layer; removing the channel layer on the inactive area, forming grooves between adjacent sacrificial layers on the inactive area and between the bottommost sacrificial layer and the substrate, the channel layer and the sacrificial layer located on the active area forming the second fin structure; forming a filling layer in the groove, the filling layer and the sacrificial layer located on the inactive area forming the first fin structure; The material of the filling layer is different from the material of the channel layer; The material of the filling layer is the same as or different from the material of the sacrificial layer.

2. The semiconductor structure according to claim 1, wherein Also includes: A first sidewall is located on a sidewall surface of the first opening, and the dielectric layer covers the sidewall surface of the first sidewall.

3. The semiconductor structure according to claim 1, wherein: Also includes: A second sidewall is located on a sidewall surface of the third opening, and the dielectric layer covers the sidewall surface of the second sidewall.

4. The semiconductor structure according to claim 1, wherein: Also includes: A first gate structure is located within the first opening and the second opening.

5. The semiconductor structure according to claim 1, wherein Also includes: The source-drain doped layers are located in the second fin structure on both sides of the second gate structure. The source-drain doped layers are located at the bottom of the dielectric layer and cover the sidewall surfaces of the second fin structure layer.

6. The semiconductor structure according to claim 2, wherein: Also includes: A first isolation layer is located on the sidewall surface of the second opening, and the sidewall of the first isolation layer is flush with the sidewall of the first spacer on the inactive area.

7. The semiconductor structure according to claim 3, wherein: Also includes: A second isolation layer is located on the sidewall surface of the fourth opening, and the sidewall of the second isolation layer is flush with the sidewall of the second sidewall on the active area.

8. The semiconductor structure according to claim 1, wherein: Also includes: An isolation structure is located on the surface of the substrate, the dielectric layer is located on the surface of the isolation structure, and a top surface of the isolation structure is lower than top surfaces of the first fin structure and the second fin structure.

9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an inactive area and an active area, the inactive area having a first fin structure, and the active area having a second fin structure; forming a first dummy gate structure across the first fin structure on the inactive area, wherein the first dummy gate structure is located on a portion of the top surface and sidewall surface of the first fin structure; forming a dielectric layer on the substrate to cover surfaces of the first fin structure and the second fin structure, wherein the dielectric layer exposes a top surface of the first dummy gate structure; removing the first dummy gate structure, and forming a first opening in the dielectric layer on the inactive region, wherein a bottom of the first opening exposes a portion of a top surface and a sidewall surface of the first fin structure; removing the first fin structure exposed at the bottom of the first opening, forming a second opening in the first fin structure, wherein the second opening exposes the surface of the substrate; The device formed on the invalid area is an invalid device; wherein, The method for forming the first fin structure and the second fin structure includes: forming an initial fin structure on the substrate, the initial fin structure including a plurality of channel layers overlapping along a normal direction of the substrate surface and a sacrificial layer located on the surface of the channel layer; removing the channel layer on the inactive area, forming grooves between adjacent sacrificial layers on the inactive area and between the bottommost sacrificial layer and the substrate, the channel layer and the sacrificial layer located on the active area forming the second fin structure; forming a filling layer in the groove, the filling layer and the sacrificial layer located on the inactive area forming the first fin structure; The material of the filling layer is different from the material of the channel layer; The material of the filling layer is the same as or different from the material of the sacrificial layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The method for removing the channel layer on the invalid area includes: forming a first mask layer on the initial fin structure, the first mask layer exposing the surface of the initial fin structure on the invalid area; using the first mask layer as a mask, etching the channel layer on the invalid area to form grooves between adjacent sacrificial layers on the invalid area and between the bottom sacrificial layer and the substrate; after forming the grooves, removing the first mask layer.

11. The method for forming a semiconductor structure according to claim 9, wherein: A second mask layer is formed on a top surface of the initial fin structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the filling layer includes: forming a filling film in the groove; and etching the filling film using the second mask layer as a mask to form the filling layer.

13. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: forming a first gate structure within the first opening and the second opening; The method for forming the first gate structure includes: forming a gate dielectric film on the surfaces of the first opening and the second opening, and on the surface of the dielectric layer; A gate electrode film is formed on the surface of the gate dielectric film, and the gate electrode film fills the first opening and the second opening; the gate electrode film and the gate dielectric film are flattened until the surface of the dielectric layer is exposed, so that the gate dielectric film forms a gate dielectric layer, and the gate electrode film forms a gate electrode layer, and the first gate structure is formed in the first opening and the second opening.

14. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: Before forming the dielectric layer, a first sidewall spacer is formed on the sidewall surface of the first dummy gate structure.

15. The method for forming a semiconductor structure according to claim 9, wherein: Also includes: Before forming the dielectric layer, forming a second dummy gate structure across the second fin structure on the active area, wherein the second dummy gate structure is located on a portion of the top surface and sidewall surface of the second fin structure, and the dielectric layer exposes the top surface of the second dummy gate structure; A second spacer is formed on the sidewall surface of the second dummy gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: After forming the dielectric layer and before forming the second opening, the second dummy gate structure is removed, and a third opening is formed in the dielectric layer on the active area, wherein the third opening exposes a portion of the top surface and sidewall surface of the second fin structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: Also includes: After the third opening is formed, the sacrificial layer exposed by the third opening is removed to form a fourth opening between adjacent channel layers.

18. The method for forming a semiconductor structure according to claim 17, wherein: Also includes: A second gate structure is formed in the third opening and the fourth opening, wherein the second gate structure surrounds each of the channel layers.

19. The method for forming a semiconductor structure according to claim 15, wherein: Also includes: After forming the second dummy gate structure and before forming the dielectric layer, the second fin structures on both sides of the second dummy gate structure are removed, and source-drain openings are formed in the second fin structures on both sides of the second dummy gate structure; a source-drain doping layer is formed in the source-drain opening; after forming the source-drain doping layer, the dielectric layer is formed on the substrate, and the dielectric layer is located on the surface of the source-drain doping layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: After forming the source / drain openings and before forming the source / drain doping layers, the portion of the sacrificial layer exposed by the sidewalls of the source / drain openings is removed to form a second fin groove between adjacent channel layers; and a second isolation layer is formed in the second fin groove.

21. The method for forming a semiconductor structure according to claim 20, wherein: The method for forming the source and drain openings also includes: removing the first fin structure on both sides of the first dummy gate structure, and the source and drain openings are also located in the first fin structure on both sides of the first dummy gate structure; the method for forming the semiconductor structure also includes: removing the portion of the first fin structure exposed by the sidewalls of the source and drain openings, forming a first fin groove at the bottom of the first dummy gate structure; and forming a first isolation layer in the first fin groove.

22. The method for forming a semiconductor structure according to claim 21, wherein: The first isolation layer and the second isolation layer are formed in the same process.

23. The method for forming a semiconductor structure according to claim 22, wherein: The method for forming the first isolation layer and the second isolation layer includes: forming an isolation material film on the substrate surface, the first fin groove, the top surface and sidewall surface of the first pseudo gate structure, the second fin groove, and the top surface and sidewall surface of the second pseudo gate structure; etching back the isolation material film until the substrate surface and the channel layer sidewall surface are exposed to form the first isolation layer and the second isolation layer, the first isolation layer is located in the first fin groove at the bottom of the first pseudo gate structure, and the second isolation layer is located in the second fin groove.

Images