Semiconductor element and method for manufacturing the same

Abstract

The present invention discloses a semiconductor element and a method for manufacturing the same, wherein the semiconductor element comprises: a substrate having a first conductivity type; a well region having a second conductivity type and arranged in the substrate; a source region and a drain region having the second conductivity type and being located in the substrate and the well region respectively, wherein the source region and the drain region include a plurality of straight line regions and a plurality of turning regions; a gate structure arranged on the substrate between the source region and the drain region; a plurality of first top doped regions having the first conductivity type and being arranged in each of the plurality of straight line regions; and a plurality of second top doped regions having the first conductivity type and being arranged in each of the plurality of turning regions and conforming to each of the turning regions.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to an ultra-high voltage semiconductor element and a manufacturing method thereof. Background Art

[0002] Ultra-high voltage semiconductor devices must have a higher breakdown voltage and a lower on-state resistance during operation. It is currently found that the breakdown voltage of ultra-high voltage semiconductor devices is highly sensitive to the resistance of the substrate, making the breakdown voltage of ultra-high voltage semiconductor devices susceptible to the influence of the resistance of the substrate and thus decreasing. Summary of the invention

[0003] The present invention provides a semiconductor element and a manufacturing method thereof, which can reduce the sensitivity of the breakdown voltage of the semiconductor element to the resistance value of the substrate, thereby preventing the breakdown voltage of the formed semiconductor element from being reduced due to the influence of the resistance value of the substrate.

[0004] The semiconductor element of the present invention includes: a substrate having a first conductivity type; a well region having a second conductivity type and arranged in the substrate; a source region and a drain region having the second conductivity type, the drain region being located in the substrate, and the drain region being located in the well region, wherein the source region and the drain region include a plurality of straight line regions and a plurality of turning regions; a gate structure being arranged on the substrate between the source region and the drain region; a plurality of first top doped regions having the first conductivity type and arranged in each of the plurality of straight line regions; and a plurality of second top doped regions having the first conductivity type, arranged in each of the plurality of turning regions and conforming to each of the turning regions.

[0005] The manufacturing method of the semiconductor element of the present invention includes the following steps. A well region is formed in a substrate having a first conductivity type, and the well region has a second conductivity type; a plurality of top doped regions having the first conductivity type are formed in the well region; an isolation structure is formed on the substrate, wherein the plurality of top doped regions are located below the isolation structure; a gate structure is formed on the substrate, wherein the gate structure covers a portion of the isolation structure; and a source region and a drain region having the second conductivity type are formed in the substrate on one side of the gate structure and one side of the isolation structure, respectively, wherein the source region is adjacent to the gate structure, and the drain region is adjacent to the isolation structure. A plurality of straight line regions and a plurality of turning regions are included between the source region and the drain region, and the plurality of top doped regions in each turning region are conformal with each turning region.

[0006] Based on the above, the present invention sets a plurality of conformal top doping regions in the turning region of the semiconductor element to reduce the sensitivity of the breakdown voltage of the semiconductor element to the resistance of the substrate, thereby preventing the breakdown voltage of the formed semiconductor element from being affected by the resistance of the substrate.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A FIG. 4 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 1B for Figure 1A Magnified view of region Z.

[0010] Figure 2A to Figure 2H is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein Figure 2H Based on Figure 1A A schematic cross-sectional view of a semiconductor element taken along line AA′.

[0011]

Explanation of symbols

[0012] 10: Semiconductor components

[0013] 100: Substrate

[0014] 102, 106, 114: patterned mask layer

[0015] 104, 108, 116, 118: Ion implantation process

[0016] 110: First well region

[0017] 112: Second well region

[0018] 120, 120a, 120b, 120b0, 120b1, 120b2, 120b3: top doping region

[0019] 122: Ladder area

[0020] 130: Source region

[0021] 132, 134: Doping area

[0022] 140: Drain region

[0023] 200: Isolation structure

[0024] 200a: First isolation structure

[0025] 200b: Second isolation structure

[0026] 200c: Third isolation structure

[0027] 200d: Fourth isolation structure

[0028] 300: Gate structure

[0029] 302: Gate oxide layer

[0030] 304: Gate

[0031] 306: Gap wall

[0032] AA′: Section line

[0033] C: Turning area

[0034] C1, C2, C3: Area

[0035] d1, d2, d3: inner diameter

[0036] D1, D2: Direction

[0037] E1, E1′, E2, E2′, E3, E3′: end

[0038] G L , G C , G C0 , G C1 , G C2 , G C3 : Gap width

[0039] H C , H C0 :high

[0040] H C1 , H C2 , H C3 :high

[0041] IR: Inner Region

[0042] L: Straight line area

[0043] L L :length

[0044] L C , L C0 , L C1 , L C2 , L C3 :length

[0045] MF: Multiple finger regions

[0046] OR: Outlying area

[0047] P L , P C , PC1 , P C2 , P C3 :spacing

[0048] W L , W C , W C0 , W C1 , W C2 , W C3 :width

[0049] Z: Zone DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0051] In the following embodiments, the first conductivity type is P type, and the second conductivity type is N type; however, the present invention is not limited thereto. In other embodiments, the first conductivity type may be P type, and the second conductivity type may be N type. The P type doping may be boron, for example, and the N type doping may be phosphorus or arsenic, for example.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0053] The schematic diagrams herein are only used to illustrate some embodiments of the present invention. Therefore, the shapes, quantities and proportions of the various elements shown in the schematic diagrams should not be used to limit the present invention.

[0054] Figure 1A FIG. 4 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Figure 1B for Figure 1A Magnified view of region Z. Figure 2H Based on Figure 1A A schematic cross-sectional view of a semiconductor element. It should be noted that Figure 2H is corresponding to Figure 1A Schematic cross-sectional view along line AA′.

[0055] Please also refer to Figure 1A , Figure 1B as well as Figure 2H, the semiconductor device 10 of the present embodiment is, for example, an ultra-high voltage device, and its operating voltage is, for example, 300V to 1000V. In one embodiment, the semiconductor device 10 includes a substrate 100, a first well region 110, a top doped region 120, an isolation structure 200, a gate structure 300, a source region 130, and a drain region 140. In the present embodiment, a plurality of finger regions MF are formed between the source region 130 and the drain region 140, and therefore, the semiconductor device 10 of the present embodiment can also be referred to as a finger-shaped ultra-high voltage device. In detail, the source region 130 and the drain region 140 include, for example, a plurality of straight regions L and a plurality of turning regions C. Two straight regions L parallel to each other and a turning region C connecting the two straight regions L can constitute a finger region, and therefore, a plurality of straight regions L and a plurality of turning regions C are connected to each other to form a plurality of finger regions MF. Each turning region C is, for example, a C-shaped, U-shaped, or racetrack-shaped turning region.

[0056] The substrate 100 is, for example, a semiconductor substrate having a first conductivity type. For example, in the present embodiment, the substrate 100 is a P-type substrate, and the material of the substrate 100 may be, for example, at least one material selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP. In another embodiment, the substrate 100 may also be a silicon-on-insulator (SOI) substrate. In yet another embodiment, the substrate 100 may be a P-epi wafer.

[0057] The first well region 110 has the second conductivity type and is disposed in the substrate 100. The first well region 110 is, for example, an N-type well region, and is, for example, a high voltage N-type well region (HVNW).

[0058] In this embodiment, the semiconductor device 10 may further include a second well region 112. The second well region 112 has a first conductivity type. The second well region 112 is, for example, a P-type well region. In this embodiment, the second well region 112 is formed in the substrate 100, and its sidewalls extend into the first well region 110. The second well region 112 is, for example, used as a source well region of the semiconductor device 10.

[0059] The source region 130 and the drain region 140 are, for example, of the second conductivity type and are disposed in the substrate 100. The source region 130 and the drain region 140 are, for example, N-type doped regions. In this embodiment, the source region 130 is located in the second well region 112, and the drain region 140 is located in the first well region 110. Figure 1A In the embodiment, the source region 130 is located in the peripheral region OR of the plurality of finger regions MF, and the drain region 140 is located in the inner region IR surrounded by the plurality of finger regions MF.

[0060] In this embodiment, the semiconductor device 10 may further include doped regions 132 and 134. The doped regions 132 and 134 have a first conductivity type, such as a P-type doped region. The doped region 132 is also called a bulk doped region, which is located in the second well region 112 and adjacent to the source region 130. The doped region 134 is located in the substrate 100.

[0061] The isolation structure 200 is located on the substrate 100 and between the source region 130 and the drain region 140. In the present embodiment, the isolation structure 200 includes a first isolation structure 200a, a second isolation structure 200b, a third isolation structure 200c and a fourth isolation structure 200d. The first isolation structure 200a is located on the substrate 100 and is adjacent to the doping region 134. The second isolation structure 200b is located between the doping region 134 and the doping region 132 and covers a portion of the second well region 112. The third isolation structure 200c is located on the first well region 110 and between the source region 130 and the drain region 140.

[0062] The third isolation structure 200c is disposed on a plurality of finger regions MF between the source region 130 and the drain region 140. The fourth isolation structure 200d is located on the first well region 110 and is adjacent to the drain region 140. In other words, the source region 130 is located between the second isolation structure 200b and the third isolation structure 200c, and the drain region 140 is located between the third isolation structure 200c and the fourth isolation structure 200d. In the present embodiment, the isolation structure 200 is, for example, a field oxide layer. That is, the material of the isolation structure 200 is, for example, an insulating material, and is, for example, undoped silicon oxide, silicon nitride, or a combination thereof.

[0063] The gate structure 300 is, for example, disposed on the substrate 100 and the third isolation structure 200c between the source region 130 and the drain region 140. From another perspective, the gate structure 300 covers a portion of the first well region 110, the second well region 112 and is adjacent to the source region 130, and the gate structure 300 covers a portion of the third isolation structure 200c. In the present embodiment, the gate structure 300 includes a gate oxide layer 302, a gate 304, and a spacer 306. The gate oxide layer 302 is, for example, disposed on the substrate 100 and is located between the source region 130 and the third isolation structure 200c. The gate 304 is, for example, disposed on the gate oxide layer 302 and the third isolation structure 200c. The spacer 306 is, for example, disposed on the sidewall of the gate 304. The material of the gate oxide layer 302 and the spacer 306 is, for example, silicon oxide, silicon nitride, or a combination thereof. The material of the gate 304 is, for example, a metal or its alloy, polysilicon, or a combination thereof.

[0064] In the embodiment of the present invention, the top doped region 120 has a first conductivity type, such as a P type. The top doped region 120 is disposed in the first well region 110 below the third isolation structure 200 c.

[0065] Please refer to Figure 1A and Figure 2H , the third isolation structure 200c is disposed in the plurality of finger regions MF. Although the top doped region 120 is located below the third isolation structure 200c, for the sake of clarity, Figure 1A In the figure, the position of the top doping region 120 is still shown. The top doping region 120 is, for example, disposed in a plurality of finger regions MF formed by a plurality of straight regions L and a plurality of turning regions C between the source region 130 and the drain region 140 .

[0066] The top doping region 120 includes a plurality of top doping regions 120a and a plurality of top doping regions 120b. The top doping region 120a may also be referred to as a first top doping region; the top doping region 120b may also be referred to as a second top doping region. The plurality of top doping regions 120a are disposed in the straight line region L; the plurality of top doping regions 120b are disposed in the turning region C. The shapes of the plurality of top doping regions 120a are different from the shapes of the plurality of top doping regions 120b.

[0067] Please refer to Figure 1B For example, the multiple top doping regions 120a disposed in the straight region L are separated from each other. Each top doping region 120a is in the shape of an elongated strip, and its extension direction D1 is different from the extension direction D2 of the straight region L. The directions D1 and D2 are substantially perpendicular. In some embodiments, the multiple top doping regions 120a may have substantially the same shape and size, but the present invention is not limited thereto. The cross-section of the top doping region 120a disposed in the straight region L parallel to the surface of the substrate 100 is rectangular. The multiple rectangular top doping regions 120a may have substantially equal lengths L. L , substantially equal width W L , substantially equal gap width G L , and / or substantially equal spacing P L Length L L For example, less than or equal to 80μm, the length L will be adjusted according to different voltage requirements L , width W L For example, the gap width G is less than or equal to 5 μm. L For example, less than or equal to 7 μm, the pitch P L For example, the width W is less than or equal to 7 μm, but the present invention is not limited thereto. L With gap width G L The ratio range is, for example, 0.6 to 1.4.

[0068] In contrast, the top doped regions 120b disposed in the turning region C are separated from each other. In one embodiment, the plurality of top doped regions 120b are conformal to the turning region C, such as a racetrack shape, a C-shape, or a U-shape. In some embodiments, the plurality of top doped regions 120a may have substantially similar shapes but different lengths. Specifically, the cross-sections of the plurality of top doped regions 120b parallel to the surface of the substrate 100 are all racetrack-shaped, C-shaped, or U-shaped, but have different lengths L. C .

[0069] In some embodiments, the turning region C may include regions C1, C2, and C3. Region C3 is close to the drain region 140, region C1 is far from the drain region 140, and region C2 is located between region C1 and region C3. In this embodiment, the turning region C is divided into three regions. However, this is not limited to this. In other embodiments, the turning region C may be divided into more regions, or fewer regions.

[0070] The inner diameter d of the top doped region 120b in the turning region C gradually increases from the region C1 to the region C3. The inner diameter d1 of the top doped region 120b1 in the region C1 is smaller than the width W of the source region 130 between the straight regions L. S The inner diameter d2 of the top doped region 120b2 in the region C2 is larger than the inner diameter d1 of the top doped region 120b1 in the region C1, and is larger than the width W of the source region 130 between the straight line regions L. S The inner diameter d3 of the top doping region 120b3 in the region C3 is greater than the inner diameter d2 of the top doping region 120b2 in the region C2. That is, d1 <W S <d2<d3。

[0071] The two ends E1 and E1′ of the top doped region 120b1 in the region C1 overlap with the gate structure 300. The two ends E2 and E2′ of each top doped region 120b2 in the region C2 and the two ends E3 and E3′ of each top doped region 120b3 in the region C3 do not overlap with the gate structure 300, and are respectively adjacent to one side of the topmost top doped region 120a in the linear region L. In some embodiments, the ends E2, E2′ and E3, E3′ of these top doped regions 120b3 and 120b2 are substantially at the same distance from the adjacent top doped region 120a, but the present invention is not limited thereto.

[0072] The height H of any top doped region 120b3 in the region C3 is C3 With length L C3 is greater than the height H of any top doped region 120b2 in region C2 C2 With length L C2, the height H of any top doped region 120b2 in region C2 C2 With length L C2 is greater than the height H of any top doped region 120b1 in region C1 C1 With length L C1 In some embodiments, the length L of the top doped region 120b from the top doped region 120b3 closest to the drain region 140 to the top doped region 120b1 farthest from the drain region 140 is C From the length L C3 The gradient is reduced to length L C1 , the height H of the top doped region 120b C From height H C3 The gradient decreases to a height H C1 .

[0073] In this example, each top doped region 120b has a substantially uniform width W. C In some embodiments, the plurality of top doped regions 120b have substantially equal widths W C In some other embodiments, the width W of the top doped regions 120b3 in the region C3 is C3 Similarly, the width W of the top doped regions 120b2 in the region C2 is C2 The same, and the width W of the plurality of top doped regions 120b1 in the region C1 is C1 However, the width W of the top doped region 120b3 in region C3 is C3 The width W of the top doped region 120b2 in the region C2 is C2 is different from the width W of the top doped region 120b1 in the region C1. C1 For example, the width W of any top doped region 120b3 in region C3 is C3 is greater than the width W of any top doped region 120b2 in region C2 C2 , the width W of any top doped region 120b2 in region C2 C2 is greater than the width W of any top doped region 120b1 in region C1 C1 In some embodiments, the width W of the top doped region 120b from the top doped region 120b3 closest to the drain region 140 to the top doped region 120b1 farthest from the drain region 140 is C From the width W C3 The gradient is reduced to width W C1 .

[0074] In addition, in some embodiments, the top doped regions 120b may have substantially equal spacings P between them. CIn some other embodiments, the spacing P between the top doped regions 120b3 in the region C3 is C3 Similarly, the spacing P between the top doped regions 120b2 in region C2 C2 The spacing P between the top doped regions 120b1 in the region C1 is the same as C1 However, the spacing P between the top doped regions 120b3 in region C3 is C3 , and the spacing P between the top doping region 120b2 in the region C2 C2 different from the spacing P between the top doped regions 120b1 in the region C1. C1 For example, the spacing P between the top doped regions 120b3 in region C3 is C3 is greater than the spacing P between the top doped regions 120b2 in region C2. C2 , the spacing P between the top doped regions 120b2 in region C2 C2 is greater than the spacing P between the top doped regions 120b1 in the region C1. C1 In some embodiments, the spacing P between the top doped regions 120b from the top doped region 120b3 closest to the drain region 140 to the top doped region 120b1 farthest from the drain region 140 is C From the spacing P C3 The gradient is reduced to a spacing P C1 .

[0075] In addition, in some embodiments, the plurality of top doped regions 120 b may have substantially equal gap widths G C In some other embodiments, the gap width G between the top doped regions 120b3 in the region C3 is C3 Similarly, the gap width G between the top doped regions 120b2 in region C2 is C2 The same, and the gap width G between the top doped regions 120b1 in the region C1 C1 However, the gap width G between the top doped regions 120b3 in region C3 is C3 , and the gap width G between the top doped region 120b2 in the region C2 C2 Different from the gap width G between the top doped region 120b1 in the region C1 C1 For example, the gap width G between the top doped regions 120b3 in region C3 is C3 is greater than the gap width G between the top doped regions 120b2 in region C2 C2 , the gap width G between the top doped regions 120b2 in region C2 C2is greater than the gap width G between the top doped regions 120b1 in the region C1 C1 In some embodiments, the gap width G between the top doped regions 120b from the top doped region 120b3 closest to the drain region 140 to the top doped region 120b1 farthest from the drain region 140 is C From the gap width G C3 The gradient decreases to the gap width G C1 .

[0076] The gap width G between the top doped regions 120b1 in the region C1 is C1 The width W of the top doped region 120b1 is C1 G C1 / W C1 The ratio range of the gap width G between the multiple top doping regions 120b2 in the region C2 C2 The width W of the top doped region 120b2 is C2 G C2 / W C2 The ratio range is different from that of the gap width G between the plurality of top doping regions 120b3 in the region C3. C3 The width W of the top doped region 120b3 is C3 G C3 / W C3 In some embodiments, the gap width G between the top doped regions 120b1 in the region C1 is C1 The width W of the top doped region 120b1 is C1 G C1 / W C1 The ratio range of is, for example, 0.8 to 1.2. The gap width G between the top doped regions 120b2 in the region C2 C2 The width W of the top doped region 120b2 is C2 G C2 / W C2 The ratio range of is, for example, 1.0 to 1.4. The gap width G between the top doped regions 120b3 in the region C3 C3 The width W of the top doped region 120b3 is C3 G C3 / W C3 The ratio range is, for example, 1.0 to 2.0.

[0077] In some embodiments, the plurality of top doping regions 120b further include a top doping region 120b0. The top doping region 120b0 is surrounded by the top doping region 120b1. The top doping region 120b0 is, for example, disposed on the center line of the top doping region 120b1. The shape of the top doping region 120b0 is different from that of the top doping region 120b1 and the top doping region 120b2. The cross section of the top doping region 120b0 parallel to the surface of the substrate 100 is, for example, rectangular. The end of the rectangular top doping region 120b0 overlaps with the gate structure 300. The height H0 of the rectangular top doping region 120b0 is less than the height H1 of the top doping region 120b1. The width W of the rectangular top doping region 120b0 is C0 The width W of the top doped region 120b1 is C1 In one embodiment, the width W of the top doped region 120b0 is substantially equal to or different from that of the top doped region 120b0. C0 , the width W of the top doped region 120b1 C1 and the width W of the top doped region 120b2 C2 For example, 1.2μm to 3.6μm.

[0078] In this embodiment, the semiconductor device 10 may further include a step region 122. The step region 122 has a second conductivity type, such as N type. The step region 122 is located between the third isolation structure 200c and the top doped region 120. The step region 122 and the top doped region 120 may have the same or similar shapes.

[0079] Figure 2A to Figure 2H The cross-sectional view of the method for manufacturing a semiconductor element according to an embodiment of the present invention is shown in FIG. It must be noted that the description of some of the same technical contents described above is omitted in this embodiment. The description of the omitted parts can refer to the description and effects of the above embodiments, and the following embodiments will not be repeated.

[0080] Please refer to Figure 2A , providing a substrate 100 having a first conductivity type. Then, forming a first well region 110 having a second conductivity type in the substrate 100. In the present embodiment, the substrate 100 is a P-type substrate, and the first well region 110 is an N-type high-voltage well region. The method for forming the first well region 110 in the substrate 100, for example, includes the following steps. First, a patterned mask layer 102 is formed on the substrate 100. Then, an ion implantation process 104 is performed to implant dopants in the substrate 100. The dopants implanted by the ion implantation process 104 are, for example, phosphorus or arsenic, and the doping dose is, for example, 2E 12 cm -2 To 5E 12 cm -2 After removing the patterned mask layer 102 , a heat treatment process may be performed to form the first well region 110 .

[0081] Please refer to Figure 2B , a second well region 112 having a first conductivity type is formed in the first well region 110. In the present embodiment, the second well region 112 is a P-type well region. The method for forming the second well region 112 includes, for example, the following steps. First, a patterned mask layer 106 is formed on the substrate 100. Next, an ion implantation process 108 is performed through the patterned mask layer 106. The dopant implanted in the above-mentioned ion implantation process 108 is, for example, boron, and the doping dose is, for example, 8E 12 cm -2 To 1.2E 13 cm -2 Afterwards, the patterned mask layer 106 is removed and a heat treatment process is performed to form a second well region 112 in the first well region 110 .

[0082] Please refer to Figure 2C , a top doped region 120 is formed in the first well region 110. In the present embodiment, the conductivity type of the top doped region 120 is P type. In some embodiments, the method for forming the top doped region 120 includes the following steps. First, a patterned mask layer 114 is formed on the substrate 100. Next, an ion implantation process 116 is performed using the patterned mask layer 114 as a mask to form the top doped region 120 in the first well region 110. The dopant implanted by the above ion implantation process 116 is, for example, boron, and the doping dose is, for example, 5E 12 cm -2 To 1E 13 cm -2 Afterwards, the patterned mask layer 114 is removed. The formed top doped region 120 extends downward from the top surface of the first well region 110 .

[0083] Please refer to Figure 2D , a step region 122 having a second conductivity type is formed in the first well region 110. In the present embodiment, the conductivity type of the step region 122 is N type. The step region 122 can be formed simultaneously in the same step. In some embodiments, forming the step region 122 in the first well region 110 includes, for example, the following steps. An ion implantation process 118 is performed using the patterned mask layer 114 as a mask. The dopant implanted in the ion implantation process 118 is, for example, phosphorus or arsenic, and the doping dose is, for example, 1E 12 cm -2 To 5E 12 cm -2 After that, the patterned mask layer 114 is removed. After the patterned mask layer 114 is removed, a heat treatment process is performed to diffuse the doping in the top doping region 120 and the terrace region 122 to a predetermined width and depth, so that the top doping region 120 and the terrace region 122 have a desired profile. The temperature of the heat treatment process is, for example, 1000°C.

[0084] The formed terrace region 122 extends downward from the top surface of the first well region 110 . The depth of the terrace region 122 in the substrate 100 is less than the depth of the top doped region 120 in the substrate 100 . In other words, the terrace region 122 is located above the top doped region 120 .

[0085] Please refer to Figure 2E , an isolation structure 200 is formed on the substrate 100. The isolation structure 200 may be formed by, for example, a local oxidation isolation method or a shallow trench isolation method. In the present embodiment, the isolation structure 200 is formed by a local area oxidation method. The isolation structure 200 includes a first isolation structure 200a, a second isolation structure 200b, a third isolation structure 200c, and a fourth isolation structure 200d.

[0086] Please refer to Figure 2F , a gate structure 300 is formed on the substrate 100, and the formed gate structure 300 covers part of the third isolation structure 200c. In the present embodiment, the gate structure 300 includes a gate oxide layer 302, a gate 304 and a spacer 306. The method for forming the gate structure 300 on the substrate 100 includes, for example, the following steps. First, a gate oxide material layer is formed on the substrate 100 by thermal oxidation or chemical vapor deposition to form a gate material layer. Thereafter, the gate material layer is patterned with the gate oxide material layer by photolithography and etching processes to form a gate 304 and a gate oxide layer 302. Thereafter, a spacer material layer is formed by thermal oxidation or chemical vapor deposition, and then an anisotropic etching process is performed on the spacer material layer to form a spacer 306 on the sidewall of the gate 304. The formed gate oxide layer 302 is, for example, adjacent to the third isolation structure 200c and located between the second isolation structure 200b and the third isolation structure 200c. The formed gate 304 is, for example, located on the gate oxide layer 302 and the third isolation structure 200 c .

[0087] Please refer to Figure 2G , a source region 130 and a drain region 140 are formed in the substrate 100 on one side of the gate structure 300 and one side of the third isolation structure 200c, respectively. In the present embodiment, the source region 130 and the drain region 140 have a second conductivity type, for example, an N-type. The formation of the source region 130 and the drain region 140, for example, includes the following steps. First, a patterned mask layer (not shown) is formed on the substrate 100. Then, an ion implantation process is performed through the patterned mask layer. The dopant implanted by the ion implantation process is, for example, phosphorus or arsenic, and the doping dose is, for example, 1E 15 cm -2 To 5E 15 cm -2. Afterwards, the patterned mask layer is removed, and a heat treatment process is performed to form a source region 130 and a drain region 140 in the substrate 100. The formed source region 130 is, for example, located in the second well region 112 and adjacent to the gate structure 300, and is located between the second isolation structure 200b and the third isolation structure 200c. The formed drain region 140 is, for example, located in the first well region 110 and between the third isolation structure 200c and the fourth isolation structure 200d.

[0088] Please refer to Figure 2H , doped regions 132 and 134 are formed in the substrate 100 and the second well region 112, respectively. In the present embodiment, the doped regions 132 and 134 have a first conductivity type, such as a P type. The method of forming the doped regions 132 and 134 in the substrate 100 and the second well region 112, respectively, includes the following steps. First, a patterned mask layer (not shown) is formed on the substrate 100. Then, an ion implantation process is performed through the patterned mask layer. The dopant implanted by the ion implantation process is, for example, boron, and the doping dose is, for example, 1E 15 cm -2 To 5E 15 cm -2 Afterwards, the patterned mask layer is removed and a heat treatment process is performed to form doped regions 132 and 134 in the substrate 100 and the second well region 112, respectively. The doped region 134 is formed between the first isolation structure 200a and the second isolation structure 200b. The doped region 132 is formed between the second isolation structure 200b and the source region 130.

[0089] Please also refer to Figure 1A , Figure 1B as well as Figure 2H In the embodiment of the present invention, the top doped regions 120b in each region of the turning region C have substantially the same width W. C , the top doped regions 120b have substantially the same gap width G between them. C Therefore, when the doping in two adjacent top doping regions 120b diffuses, the gap between them will have a substantially uniformly distributed doping concentration. Therefore, the sensitivity of the breakdown voltage of the semiconductor element to the resistance of the substrate can be reduced, thereby preventing the breakdown voltage of the formed semiconductor element from being affected by the resistance of the substrate. On the other hand, since the process method of the present invention can reduce the sensitivity of the breakdown voltage of the semiconductor element to the resistance of the substrate, the process margin (process window) can be increased.

[0090] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor element, comprising: A substrate having a first conductivity type; A well region, having a second conductivity type, is disposed in the substrate; A source region and a drain region, having the second conductivity type, the drain region is located in the substrate, and the drain region is located in the well region, wherein a plurality of straight line regions and a plurality of turning regions are included between the source region and the drain region; A gate structure, disposed on the substrate between the source region and the drain region; A plurality of first top doped regions, having the first conductivity type, disposed in each of the plurality of linear regions; as well as A plurality of second top doped regions, having the first conductivity type, disposed in each of the plurality of turning regions and conforming to each of the turning regions; Wherein, each turning area includes a first area, a second area and a third area, the second area is located between the first area and the third area, and the third area is closer to the drain area than the first area, the gap width between the multiple second top doping areas in the first area and the width of the multiple second top doping areas have a first ratio range, the gap width between the multiple second top doping areas in the second area and the width of the multiple second top doping areas have a second ratio range, the gap width between the multiple second top doping areas in the third area and the width of the multiple second top doping areas have a third ratio range, the first ratio range is different from the second ratio range, and different from the third ratio range. 2 . The semiconductor device according to claim 1 , wherein a cross-section of the plurality of second top doped regions parallel to the surface of the substrate has a racetrack shape, a C shape, or a U shape. 3 . The semiconductor device as claimed in claim 1 , wherein the plurality of second top doped regions have substantially the same width, and each second top doped region has substantially a single width. 4 . The semiconductor device according to claim 1 , wherein the first ratio ranges from 0.8 to 1.2; the second ratio ranges from 1.0 to 1.4; and the third ratio ranges from 1.0 to 2.

0.

5. A method for manufacturing a semiconductor element, comprising: forming a well region in a substrate having a first conductivity type, the well region having a second conductivity type; forming a plurality of top doped regions having the first conductivity type in the well region; forming an isolation structure on the substrate, wherein the plurality of top doped regions are located below the isolation structure; forming a gate structure on the substrate, wherein the gate structure covers a portion of the isolation structure; as well as forming a source region and a drain region having the second conductivity type in the substrate on one side of the gate structure and one side of the isolation structure, respectively, wherein the source region is adjacent to the gate structure, and the drain region is adjacent to the isolation structure; The plurality of top doped regions in each turn region are conformal to the each turn region; Wherein, each turning area includes a first area, a second area and a third area, the second area is located between the first area and the third area, and the third area is closer to the drain area than the first area, the gap width between the multiple top doping areas in the first area and the width of the multiple top doping areas have a first ratio range, the gap width between the multiple top doping areas in the second area and the width of the multiple top doping areas have a second ratio range, the gap width between the multiple top doping areas in the third area and the width of the multiple top doping areas have a third ratio range, the first ratio range is different from the second ratio range, and different from the third ratio range. 6 . The method for manufacturing a semiconductor device according to claim 5 , wherein a cross-section of the plurality of top doped regions in each of the turn regions parallel to the surface of the substrate comprises a racetrack shape, a C shape, or a U shape. 7 . The method for manufacturing a semiconductor device according to claim 5 , wherein the plurality of top doped regions have substantially the same width, and each top doped region has substantially a single width. 8 . The method for manufacturing a semiconductor element according to claim 5 , wherein the first ratio ranges from 0.8 to 1.2; the second ratio ranges from 1.0 to 1.4; and the third ratio ranges from 1.0 to 2.0.

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