Electrical devices and coils

Abstract

The present disclosure provides an electrical device and a coil, wherein the electrical device includes a dielectric layer having a first surface and a second surface. The device further includes a first set of high-aspect ratio plated structures disposed on the first surface of the dielectric layer and a second set of high-aspect ratio plated structures disposed on the second surface of the dielectric layer opposite the first set of high-aspect ratio plated structures.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 693,169, filed on November 22, 2019, and further claims the benefit of U.S. Provisional Application No. 62 / 771,442, filed on November 26, 2018, the entire contents of each of which are hereby incorporated by reference. Technical Field

[0003] The present invention generally relates to electroplating structures and electroplating processes. Background Art

[0004] Electroplating processes for fabricating structures such as copper or copper alloy circuit structures such as leads, traces, and via interconnects are generally known and are disclosed, for example, in US Pat. No. 4,315,985 to Castellani et al., entitled "Fine-Line Circuit Fabrication and Photoresist Application Therefor." These types of processes are used, for example, in conjunction with the manufacture of disk drive head suspensions disclosed in U.S. Patent 8,885,299, entitled “Low Resistance Ground Joints for Dual Stage Actuation Disk Drive Suspensions” by Bennin et al.; U.S. Patent 8,169,746, entitled “Integrated Lead Suspension with Multiple Trace Configurations” by Rice et al.; U.S. Patent 8,144,430, entitled “Multi-Layer Ground Plane Structures for Integrated Lead Suspensions” by Hentges et al.; U.S. Patent 7,929,252, entitled “Multi-Layer Ground Plane Structures for Integrated Lead Suspensions” by Hentges et al.; U.S. Patent 7,388,733, entitled “Method for Making Noble Metal Conductive Leads for Suspension Assemblies” by Swanson et al.; and U.S. Patent 7,388,733, entitled “Method for Making Noble Metal Conductive Leads for Suspension Assemblies” by Peltoma et al. These types of processes are also used in conjunction with the manufacture of camera lens suspensions, such as disclosed in Miller's U.S. Patent 9,366,879, entitled "Camera Lens Suspension with Polymer Bearings."

[0005] Superfilling and superconformal plating processes and compositions are also known and disclosed in, for example, the following articles: "The chemistry of additives in damascene copper plating" by Vereecken et al., IBM J. of Res. & Dev., vol. 49, no. 1, January 2005; "Damascene copper electroplating for chip interconnections" by Andricacos et al., IBM J. of Res. & Dev., vol. 42, no. 5, September 1998; and "Curvature enhanced adsorbate coverage mechanism for bottom-up superfilling and bump control in damascene processing" by Moffat et al., Electrochimica Acta 53, pp. 145-154, 2007. With these processes, in-trench electroplating (e.g., a photoresist mask trench defines the space for the structure to be plated) occurs preferentially at the bottom. Voids in the deposited structure can thereby be avoided. All of the above patents and articles are incorporated herein by reference in their entirety and for all purposes.

[0006] There remains a continuing need for enhanced circuit structures. There is also a need for efficient and effective processes, including electroplating processes, for fabricating circuits and other structures. Summary of the Invention

[0007] Apparatus including high-aspect ratio electroplated structures and methods of forming high-aspect ratio electroplated structures are described. A method of fabricating a metal structure comprises providing a substrate having a metal base, the metal base characterized by a height-to-width aspect ratio; and electroplating a metal crown on the base to form the metal structure, the metal structure having a height-to-width aspect ratio greater than the aspect ratio of the base.

[0008] Other features and advantages of embodiments of the present invention will be apparent from the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] By way of example, and not limitation, embodiments of the invention are illustrated in the figures of the accompanying drawings in which like reference numerals indicate similar elements, and in which:

[0010] Figure 1 The diagram shows a coil manufactured using current printed circuit technology;

[0011] Figure 2 Figure 1 illustrates a high-density precision coil including a high-aspect-ratio electroplated structure according to an embodiment;

[0012] Figure 3 Figures illustrate a diagram for representing electromagnetic forces generated by a high-density precision coil including a high-aspect-ratio electroplated structure according to an embodiment;

[0013] Figure 4 Figure illustrates an apparatus configured for linear motor type applications including multiple layers of high aspect ratio electroplated structures according to embodiments;

[0014] Figure 5 Figure 1 illustrates a high aspect ratio electroplated structure according to some embodiments;

[0015] Figure 6 Figure 1 illustrates a high aspect ratio electroplated structure according to some embodiments;

[0016] Figure 7 Figure 1 illustrates a high aspect ratio electroplated structure according to some embodiments;

[0017] Figure 8 Figure illustrates a device having multiple layers of high aspect ratio plated structures having a high density cross-sectional area according to some embodiments;

[0018] Figure 9 Figures illustrate graphs indicating SPS coverage during high current density plating techniques and low current density plating techniques according to embodiments;

[0019] Figure 10a -f illustrates a process for forming a high aspect ratio electroplated structure according to an embodiment;

[0020] Figure 11 Figure 1 illustrates a high aspect ratio electroplated structure according to some embodiments;

[0021] Figure 12 Figure 1 illustrates a perspective view of a high aspect ratio electroplated structure according to some embodiments;

[0022] Figure 13a 、 13b Figure 1 illustrates a high-density precision coil formed using a high-aspect-ratio electroplating structure according to an embodiment;

[0023] Figure 14 Figure illustrates a high aspect ratio electroplated structure including high resolution stacked conductor layers according to an embodiment;

[0024] Figure 15 Figure 1 illustrates a high-density precision coil including a high-aspect-ratio electroplated structure according to an embodiment;

[0025] Figure 16a-c illustrates a process for forming a high aspect ratio electroplated structure according to another embodiment;

[0026] Figure 17 Figure illustrates the selective formation of high aspect ratio electroplated structures according to an embodiment;

[0027] Figure 18 1. A perspective view of a high aspect ratio electroplated structure according to an embodiment is shown, wherein a metal crown portion is selectively formed on a trace;

[0028] Figure 19 Figure 1 illustrates a hard drive platter suspension flexure including a high aspect ratio plated structure according to an embodiment;

[0029] Figure 20 The diagram shows Figure 19 A cross-sectional view of a flexure of a hard drive suspension is shown;

[0030] Figure 21a 、 21b Figure illustrates a process for forming high aspect ratio electroplated structures according to embodiments using photoresist during a conformal plating process;

[0031] Figure 22 illustrates exemplary chemistries for a process for forming an initial metal layer, a standard / conformal plating process, and a crown plating process according to various embodiments;

[0032] Figure 23 FIGURE 1 illustrates a perspective view of a top surface of an inductively coupled coil formed by a high aspect ratio electroplated structure according to an embodiment;

[0033] Figure 24 Figure 21 shows a perspective view of the rear surface of the embodiment of the inductive coupling coil;

[0034] Figure 25 FIG. 1 shows a perspective view of a top surface of an inductive coupling coil 2502 according to an embodiment coupled to an RFID chip;

[0035] Figure 26a -j illustrates a method of forming an inductively coupled coil formed from a high aspect ratio electroplated structure according to an embodiment;

[0036] Figure 27 Figure 1 illustrates a plan view of a flexure of a suspension for a hard disk drive including a high aspect ratio plating structure according to an embodiment;

[0037] Figure 28 The figure shows that along Figure 27 A cross section of the gap portion of the bend at the gap portion taken along line A shown;

[0038] Figure 29Figure 1 shows a gimbal portion having a mass structure according to an embodiment;

[0039] Figure 30 FIG. 1 shows a proximal portion of a bend including a high aspect ratio plated structure according to an embodiment. Figure 27 A cross section taken along line B is shown;

[0040] Figure 31 FIG. 1 shows a proximal portion of a curved portion including a high aspect ratio structure according to an embodiment. Figure 27 A cross section taken along line C is shown; and

[0041] Figure 32 Figure illustrates a plan view of a proximal portion of a bend including a high aspect ratio structure according to an embodiment;

[0042] Figure 33 Figure illustrates a process for forming a high aspect ratio electroplated structure according to an embodiment;

[0043] Figure 34 The diagram shows something similar to Figure 33 A more detailed process of the type described; and

[0044] Figure 35 The diagram illustrates a coil according to an embodiment manufactured using the process described herein. DETAILED DESCRIPTION

[0045] The following describes high aspect ratio electroplating structure and manufacturing method according to an embodiment of the present invention.High aspect ratio electroplating structure provides a conductor spacing tighter than current technology.For example, according to various embodiments, high aspect ratio electroplating structure includes a conductor stack, wherein the cross-sectional area of ​​the conductor stack is greater than 50%.In addition, high aspect ratio electroplating structure makes it possible to realize the multilayer conductor according to an embodiment.In addition, according to various embodiments, high aspect ratio electroplating structure makes it possible to realize precision alignment (alignment) between layer and layer.For example, high aspect ratio electroplating structure can have an alignment less than 0.030mm between layer and layer.According to various embodiments, high aspect ratio electroplating structure makes it possible to reduce total stack height.

[0046] According to various embodiments, the high aspect ratio plating structure enables a thin dielectric material to be achieved between the magnet and the coil formed using the high aspect ratio plating structure. This enables the coil to produce thinner dielectric materials than current printed circuit coils such as Figure 1 Thus, high aspect ratio electroplated structures are more cost-effective, produce higher performance devices, and reduce the required footprint of the device compared to current technology.

[0047] Figure 2The figure shows a high-density precision coil including high-aspect ratio plated structures according to an embodiment. The high-aspect ratio plated structures 202 are formed in rows with dielectric material between each row and each high-aspect ratio plated structure 204. The high-density precision coil can be formed as a spiral coil or other coil type.

[0048] Figure 3 The figure shows a diagram illustrating the electromagnetic forces generated by a high-density precision coil including a high-aspect-ratio electroplated structure according to an embodiment. The diagram includes a cross-section 302 of the coil near a magnet 304. The highest electromagnetic force 306 is in the coil layer 308 closer to the magnet 304. Coil layers 310 farther from the magnet 304 exert less force. The primary factor influencing the force is derived from the Lorentz equation: because The magnitude of the intensity decreases with the distance between the coil and the magnet, so is the current flowing through the copper. Any cross-sectional area of ​​the cross section 302 that is not a conductor has a negative effect on the force No contribution.

[0049] The main factors affecting the force capability of a coil include the number of turns within the magnetic field (the turns closest to the poles of the magnet provide the greatest force), the distance of the coil from the magnet (layers closer to the magnet will exert greater force), and the total percentage of the copper cross-sectional area within the magnetic field. The use of high-aspect ratio plated structures according to various embodiments improves these aspects compared to coils using current coil technology.

[0050] For example, a coil having two layers using current technology has a total thickness of approximately 210 microns, a conductor spacing of 38 microns, a cross-sectional percentage of copper of approximately 20%, an estimated resistance of 3.1 ohms, an estimated force ratio of 1.0 (an estimated B ratio of 1.0 and an estimated J ratio of 1.0), and an estimated power ratio of 1.0. In contrast, according to various embodiments, a high-density precision coil including a high-aspect ratio electroplated structure has a total thickness of approximately 116 microns, a conductor spacing of 40 microns, a cross-sectional percentage of copper of approximately 60%, an estimated resistance of 5.5 ohms, an estimated force ratio of 1.2 (an estimated B ratio of 1.5 and an estimated J ratio of 0.8), and an estimated power ratio of 0.71. Thus, according to various embodiments, a high-density precision coil including a high-aspect ratio electroplated structure is a higher performance device. Thus, according to some embodiments, such a high-density precision coil provides 20% more force and 30% less power at half the thickness of a coil using the current state of the art.

[0051] Figure 4The figure shows a device configured for linear motor type applications including multiple layers of high aspect ratio electroplated structures according to an embodiment. Due to the size advantage compared to the current technology, each layer 402a-d of the high aspect ratio electroplated structure is larger than the current technology (such as Figure 1 404. In addition, each layer 402a-d is closer to the magnet 404 by utilizing the volume The force capability of a linear motor is improved by reducing the magnetic field (flux density). Therefore, using a multi-layer, high-aspect-ratio electroplated structure for a linear motor requires fewer layers than structures using current technology. Furthermore, such a structure offers greater flexibility in achieving desired electrical properties, such as low resistance.

[0052] Figure 5 The figure shows a high aspect ratio electroplated structure at a stage during the manufacturing process according to some embodiments. The layer 602 of the high aspect ratio electroplated structure at this stage during the manufacturing process is formed using a semi-additive technique to create a fine pitch, resist-defined conductor with an initial height to width aspect ratio (A / B) of approximately 1 to 1. For example, the high aspect ratio electroplated structure can have a height of 20 microns and a width of 20 microns. According to some embodiments, the plating process is stopped at this time to remove the seed layer and the defining workpiece such as a photoresist mask using techniques including those known in the art.

[0053] Figure 6 The figure shows a high aspect ratio electroplated structure at another stage during the manufacturing process according to some embodiments. The layer 702 of the high aspect ratio electroplated structure at this stage during the manufacturing process is formed using crownplate technology to convert the semi-amended conductor into a high aspect ratio, high percentage metal conductor circuit. For example, the high aspect ratio electroplated structure has a final height to width ratio (A / S) greater than 1 to 1. According to various embodiments, the final height to width ratio can be in a range including 1.2 to 3.0. Other embodiments include a final height to width ratio greater than 3.0. However, those skilled in the art will understand that any final height to width ratio can be obtained using the techniques described herein to meet design and performance criteria. In the example of FIG. Figure 5 The previous stage is shown as Figure 6 At the stages of formation shown, there is no particular limitation on the ultimate height of the high aspect ratio plated structures as disclosed in the various embodiments.

[0054] Figure 7The figure shows a high aspect ratio electroplated structure at yet another stage during the manufacturing process according to some embodiments. The layers 802a, b of the high aspect ratio electroplated structure at this stage during the manufacturing process are converted using a planarization technique to allow multiple layers of the high aspect ratio electroplated structure to be stacked using a semi-additive technique to form subsequent layers. Figure 8 The figure shows a device having a multi-layer high aspect ratio electroplated structure with a high fractional conductor cross-sectional area 901 in accordance with some embodiments.

[0055] For use from Figure 5 Those structures shown in form the method for high aspect ratio electroplating structure and comprise and use low current density plating technology.This plating technology plates sidewall, until obtain desired space between high aspect ratio electroplating structure.For various embodiments, if the space between high aspect ratio electroplating structure is not narrow enough, then undesirable extrusion of top may occur.Extrusion occurs in the place where the top edge of adjacent structure grows together and pinches off gap, and this causes short circuit.For various embodiments, strengthen low current density plating process by enough fluid exchange, so that fresh plating bath can be used for the surface that copper plating occurs continuously.In addition, the method for forming high aspect ratio electroplating structure comprises and uses high current density plating technology.This high current density plating technology operates under the high percentage of mass transfer limit.This mainly or only plates on the top of the conductive material that forms high aspect ratio electroplating structure.High current density plating process has been enhanced by accurate current density control. Figure 9 The figure shows a graph having an upper line 1002 and a lower line 1004, where the upper line 1002 indicates high SPS coverage during a high current density plating technique according to an embodiment, and the lower line 1004 indicates low, very uniform catalyst (promoter) coverage during a low current density plating technique according to an embodiment.

[0056] Figure 10a Figures 1-f illustrate a process for forming a high aspect ratio electroplated structure according to an embodiment. Figure 10a The figure shows trace 1102 formed at the thickness limit of the resist capability (Resist) at time T1 of the process.For some embodiments, the pre-plated conventional trace is formed from copper using a process such as a damascene process, or using etching and deposition techniques including those known in the art. Figure 10bThe figure shows the formation of high aspect ratio electroplating structure at time T2 during low current density or conformal plating process. According to an embodiment, the conformal plating process grows all surfaces of the trace at approximately the same rate. In addition, the conformal plating process suppresses plating kinetics (low catalyst coverage). The conformal plating process also provides a fairly uniform metal concentration, which has a high, uniform inhibitor coverage to compensate. The effect of suppressing plating kinetics can be enhanced by including a leveler in the plating bath. Obtaining a uniform metal concentration and obtaining a high, uniform inhibitor coverage requires a lower current density. According to some embodiments, a conformal plating process of 2 amperes per square decimeter is used for plating, such as copper, brightener additives, the temperature of the plating device and fluid mechanics. Examples of such conformal plating processes include but are not limited to low current density plating processes. At low current density, the plating bath maintains a uniformly suppressed state to provide conformal plating. For another embodiment, a leveler can be added to the plating bath to provide a higher current density and faster plating. For yet another embodiment, the current density can be further increased by increasing the copper content to near the solubility limit of copper sulfate in the plating bath. This provides the ability to double the current density or even greater to achieve the same conformal plating quality. For example, the copper content can be as high as 40 g / L with a reduced acid content to prevent common ionic effects.

[0057] For some embodiments, the low current density plating process deposits a conductive material, such as copper, onto the top and sidewalls of trace 1102 , eg, T2 is approximately five minutes into the process ( T1 + 5 minutes) during the low current density plating process. Figure 10c The figure shows the formation of a high aspect ratio electroplated structure during a low current density plating process at time T3 into the process. For an embodiment, the low current density plating process deposits a conductive material (such as copper) onto the top and sidewalls of the trace 1102. For example, T3 is approximately five minutes into the process (T1+15 minutes) during the low current density plating process.

[0058] Figure 10dThe figure shows the formation of a high-aspect ratio electroplated structure at time T4 into the process during a crown plating process, such as a high current anisotropic super plating process. For example, T4 is approximately 15 minutes and 10 seconds into the process (T1 + 15 minutes and 10 seconds). For some embodiments, the high current anisotropic super plating process is crown plating. Crown plating is based on balancing the interaction between the following factors: metal concentration in solution; brightener additives; suppressor additives; mass transfer-fluid exchange rate to the surface; levelers; and current density at the substrate. The metal concentration in solution can include, but is not limited to, copper. Brightener additives can include, but are not limited to, SPS (bis(3-sulfopropyl)-disulfide), DPS (3-N,N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid), and MPS (mercaptopropylsulfonic acid). Inhibitor additives may include, but are not limited to, linear PEGs of various molecular weights (including those known to those skilled in the art), poloxamines, co-block polymers of polyethylene and polypropylene glycol, such as water-soluble poloxamers known under various commercial names, such as BASF pluronic f127, and PEGs such as The UCON series of high-performance fluids are random copolymers (again in various proportions of monomers and various molecular weights) and polyvinyl pyrrolidone of various molecular weights.

[0059] According to some embodiments, the high current anisotropic super plating process includes a suppressed exchange current of 1% of the accelerating current. In addition, the sidewall of the high aspect ratio electroplating structure formed has almost zero catalyst coverage. Almost zero catalyst coverage is achieved by shifting the Nernst potential for copper deposition to help suppressor coverage. In addition, high overpotential and copper availability (transmission phenomenon) result in high catalyst coverage at the top of the structure formed. Copper mixed concentrate can also be adjusted to support almost zero catalyst coverage during this process. For example, the copper mixed concentrate for the high current anisotropic super plating process is 14 grams per liter or lower. For some embodiments, the copper mixed concentrate depends on specific fluid mechanics. Because the various embodiments of this process operate under the high fraction of mass transfer limit, the small difference in fluid velocity across the article to be plated will affect the mass transfer limit, and it is difficult to achieve sufficient control of the gap between the plating lines without the height control of the fluid velocity across all regions of the article to be plated. According to some embodiments, the high current anisotropic super plating process includes a leveler additive to disable catalyst coverage, thereby minimizing or eliminating plating on the sidewalls of the structure being formed. For other embodiments, the plating bath is used without the leveler additive.

[0060] According to some embodiments, at elevated current densities (such as those used in high current anisotropic superplating processes), a triple feedback mechanism operates. The mass transfer effect depletes the copper in the space between the traces. In addition, high current densities support surfaces dominated by catalysts (e.g., SPS). In order to maintain suppressed sidewalls, mass transfer is regulated by the copper mass transfer effect to reduce the Nernst potential. For example, the fluid boundary layer thickness and the spacing between each trace are designed to reduce the Nernst potential.

[0061] In addition, according to some embodiments, high current anisotropy super plating process comprises operating with certain copper concentration, and under this copper concentration, these differences can create concentration differences greater than four times.Under such conditions, lower copper concentration and Nernst potential help to reduce plating rate.For example, when Nernst potential is approximately shifted in the scope of 50 millivolts (" mV ") to 60mV, this may help to reduce 20 times of plating rate.Such condition induces Tafel dynamics, and for copper plating, it is the change for every 120mV of applied voltage (not rectifier voltage), the change of ten times of electric current.Lower sidewall current is fed back to the top surface of the structure being formed, and wherein diffusion length is short, and this promotes metal from plating bath (solution) to the faster transport and higher catalyst coverage on surface rather than suppressing, and high Nernst potential.For some embodiments, use two additive systems (for example, brightener and inhibitor).Leveler reduces feedback mechanism by the SPS action on the top side of blocking plating feature.

[0062] As the spacing between metal conductors or traces continues to shrink, the aspect ratio of the height to width of the spaces between the metal conductors increases substantially. According to some embodiments, the electroplating processes provided herein achieve plating in spaces between metal conductors at aspect ratios of 7:1 and greater.

[0063] According to some embodiments, a method of forming a high aspect ratio electroplated structure provides selective formation of metal crown plating at selective locations or regions. In one exemplary embodiment, selective formation of the metal crown is achieved by performing the electroplating process according to the following relationship:

[0064]

[0065] Where C is the concentration of the metal (copper in this case) being plated and C∞ is the volume concentration in the plating bath. This relationship can also be expressed as performing a plating process where Equal to or greater than sixty-seven percent (67%) of the mass transfer limit. According to other embodiments, the selective formation of the metal crown is achieved by performing the electroplating process according to the following relationship:

[0066]

[0067] or in In another aspect, the selective formation of the metal crown is achieved by performing the electroplating process according to the following relationship:

[0068]

[0069] Here i is the current density, i limit is the current density limit.

[0070] Figure 10e The figure shows the formation of a high aspect ratio electroplated structure at time T5 during a high current anisotropic super plating process. For example, T5 is about 15 minutes and 30 seconds into the process (T1 + 15 minutes and 30 seconds). For another embodiment, as shown in FIG. Figure 10e The formation of the high aspect ratio plated structure shown occurs at time T5 = T1 + 5 minutes. Figure 10f The figure shows the formation of a high aspect ratio electroplated structure at time T6 during a high current anisotropic super plating process. This figure shows the end of the crown plating process, which ends the formation of a high aspect ratio electroplated structure according to some embodiments. For example, T6 is about 20 minutes into the process (T1 + 20 minutes). For another embodiment, as shown in FIG. Figure 10f The formation of the high aspect ratio plated structure shown occurs at time T6 = T1 + 10 minutes.

[0071] For some embodiments, the method for forming high aspect ratio electroplating structure uses the process including conformal plating and anisotropic plating described in this article. According to some embodiments, conformal plating process uses 2 / 3 of the total plating time. For other embodiments, conformal plating process uses 1 / 3 of the total plating time. In addition, conformal plating process starts with 2 amperes per square decimeter (" ASD ") for low metal plating plating bath or starts with 4ASD for high metal plating plating bath. For example, the plating plating bath includes the copper of 12 grams per liter and the sulfuric acid of 1.85 moles (mol / L). Alternatively, conformal plating process is the process of plating at a rate of 0.4 to 1.2 microns per minute. According to an embodiment, conformal plating process proceeds until the space between the traces is in the range of 6-8 microns. As the surface area of ​​the structure formed increases, current density will slowly decrease. However, this process will realize uniform current density and growth rate on all surfaces formed. For some embodiments, as the surface area of ​​the formed high aspect ratio structures increases, the current may be increased to maintain the current density.

[0072] According to some embodiments, an anisotropic plating process uses 1 / 3 of the total plating time to form a high aspect ratio electroplated structure. The anisotropic plating process increases the ASD to 7 ASD (3.5 times the current of the conformal plating process), but on average, it is twice as high at the top of the formed metal structure. The same fluid flow rate as used in the conformal plating process can be maintained. For example, the plating rate is 3 microns / minute at the top of the formed structure, with a plating rate of almost zero on the sidewalls of the structure. As the structure grows, the average current drops by half, but according to an embodiment, the peak current density maintains about 14 ASD at the top of the structure. For example, the peak current density just exceeds 50% of the mass transfer limit at the top surface, and even if the sidewalls are exposed to about 3 grams / liter of copper, the sidewalls are plated at a plating rate of less than 10% of the mass transfer limit or 5:1. At a higher fraction of the mass transfer limit, a higher plating rate ratio can be obtained.

[0073] The embodiment of the method for forming high aspect ratio electroplating structure includes those variations described above, to form high aspect ratio electroplating structure including different characteristics. For example, as mentioned above, the copper content in the plating bath configured as an anisotropic plating bath can be different from 13.5 grams per liter. Changing the copper content in the flat trace plating bath while using the same current density can be used to control the interval between high aspect ratio electroplating structures. Another embodiment of the method described herein includes using a flat trace plating bath with a copper content of 12 grams per liter, to form a high aspect ratio electroplating structure spaced apart by 8 microns. Another embodiment of the method described herein includes using a flat trace plating bath with a copper content of 15 grams per liter, to form a high aspect ratio electroplating structure spaced apart by 4 microns. Therefore, it will be understood by those skilled in the art that adjusting other parameters of the method described herein can be used to change the characteristics of the high aspect ratio electroplating structure. Some embodiments of the method described herein include adjusting the current density to match current plating conditions, such as the metal contained in the mass transfer rate, the plating bath, the fluid velocity, the copper concentration, the additive used, and the temperature.

[0074] The method for forming high aspect ratio plated structures also includes using a thin dielectric process. According to some embodiments, photosensitive polyimide is used as a dielectric between each high aspect ratio plated structure. Liquid photosensitive polyimide enables small via capabilities, good coverage between high aspect ratio conductors, good alignment / edge capabilities, is a high reliability material, and has a coefficient of thermal expansion ("CTE") that closely matches copper. Liquid photosensitive polyimide can easily fill gaps between high aspect ratio plated structures. According to some embodiments, liquid photosensitive polyimide is used to create via paths as low as 0.030 mm. Other dielectrics that can be used include, but are not limited to, KMPR and SU-8.

[0075] Figure 11 The figure illustrates high-aspect ratio plated structures formed using methods described herein, according to some embodiments. Each high-aspect ratio plated structure 1202 includes a plurality of texture lines 1204, which illustrate how the electroplating process proceeds to form the structure. A thin dielectric 1206 is formed between and over the high-aspect ratio plated structures 1202. Figure 12 The figure shows a perspective view of a high aspect ratio plated structure 1302 formed using methods described herein, according to some embodiments.

[0076] The methods described herein can be used to form high aspect ratio plated structures that form high density precision coils. Figure 13a The figure shows a high-density precision coil formed using a high-aspect ratio electroplating structure according to an embodiment. Coil 1402 is formed by a high-aspect ratio electroplating structure such as those described herein. The high-density precision coil also includes a center coil via 1404. The center coil via 1404 reduces the voltage drop across the coil during the manufacturing steps described herein. In addition, the center coil via 1404 enables the following capabilities to be achieved, that is, by better controlling the voltage drop and current during the anisotropic plating process described herein to better control the variability of the spacing within the coil. The center coil via 1404 also enables better control of the voltage drop of the formed high-density precision coil. Figure 13b The figure shows a cross section of a center coil via 1404 as part of a high density precision coil as described herein.

[0077] Figure 14 The figure illustrates a high-aspect ratio plated structure including high-resolution stacked conductor layers according to an embodiment. A first conductor layer 1502a includes high-aspect ratio plated structures 1504 formed using techniques, including those described herein. A first dielectric layer 1508 is formed using a thin dielectric process using techniques, including those described herein. First dielectric layer 1508 fills all spaces between the high-aspect ratio plated structures of first conductor layer 1502a and forms a coating over high-aspect ratio plated structures 1504. First dielectric layer 1508 is planarized using techniques known in the art. A second conductor layer 1502b includes high-aspect ratio plated structures 1506 formed over the planarized surface of first dielectric layer 1508. A second dielectric layer 1510 is formed using a thin dielectric process using techniques, including those described herein, to fill all spaces between the high-aspect ratio plated structures 1506 of second conductor layer 1502b and form a coating over high-aspect ratio plated structures 1506. Second dielectric layer 1510 may also be planarized. Additional layers including high aspect ratio plated structures may be formed using the techniques described herein.

[0078] Figure 15The figure illustrates a high-density precision coil including high-aspect ratio plated structures according to an embodiment, comprising high-resolution stacked conductor layers. First conductor layer 1602a includes high-aspect ratio plated structures formed using techniques including those described herein. First dielectric layer 1608 is formed using a thin dielectric process using techniques including those described herein. First dielectric layer 1608 fills all spaces between the high-aspect ratio plated structures of first conductor layer 1602a and forms a coating over the high-aspect ratio plated structures. First dielectric layer 1608 is planarized using techniques known in the art. Second conductor layer 1602b includes high-aspect ratio plated structures formed over the planarized surface of first dielectric layer 1608. Second dielectric layer 1610 is formed using a thin dielectric process using techniques including those described herein to fill all spaces between the high-aspect ratio plated structures of second conductor layer 1602b and form a coating over the high-aspect ratio plated structures. Second dielectric layer 1610 may also be planarized. Additional layers including high-aspect ratio plated structures may be formed using techniques described herein.

[0079] The high-density precision coil is formed with a first distance 1614 between the high-aspect ratio plated structures of the first conductor layer 1602a and the high-aspect ratio plated structures of the second conductor layer 1602b. For various embodiments, first distance 1614 is less than 0.020 mm. For another embodiment, first distance 1614 is 0.010 mm. The high-density precision coil is formed with a second distance 1616 between the surface 1618 of the second dielectric layer 1610 and the high-aspect ratio plated structures of the first conductor layer 1602a. For various embodiments, second distance 1616 is less than 0.010 mm. For some embodiments, second distance 1616 is 0.005 mm. For some embodiments, second distance 1616 may be the starting gap minus the final desired gap divided by two. The high-density precision coil is formed with a third distance 1620 between the high-aspect ratio plated structures of the first conductor layer 1602a and the surface of the first dielectric layer 1622. For various embodiments, third distance 1620 is less than 0.020 mm. For some embodiments, third distance 1620 is less than 0.015 mm. For another embodiment, third distance 1620 is 0.010 mm. For various embodiments, a first dielectric layer is formed on substrate 1624 using techniques, including those described herein. For some embodiments, substrate 1624 is a stainless steel layer. Those skilled in the art will appreciate that substrate 1624 can be formed from other materials, including but not limited to steel alloys, copper alloys such as bronze, pure copper, nickel alloys, beryllium copper alloys, and other metals, including those known in the art.

[0080] Other advantages of using high aspect ratio electroplating structure as described herein to form device include the device with high structural strength, high reliability, and high heat dissipation capacity.High structural strength is provided by the ability of the metal high aspect ratio electroplating structure that forms very dense concentration on all layers of device. In addition, the process for forming metal high aspect ratio electroplating structure as described herein provides the lateral alignment of the structure between layer and layer, thereby increases high structural strength. The high structural strength of the device formed using the process for forming metal high aspect ratio electroplating structure as described herein is also the result of the good adhesion of dielectric layer material (such as photosensitive polyimide layer) and structure. For some embodiments, the high aspect ratio electroplating structure formed using technology described herein is coated with non-magnetic nickel layer to increase the adhesion of dielectric layer. This will further increase the high structural strength of the final device formed using high aspect ratio electroplating structure as described herein.

[0081] The reliability of devices formed using the high-aspect ratio electroplated structures described herein is also high due to the use of high-reliability materials, such as photosensitive polyimide for the dielectric layer, which provides robust electrical performance. Using the techniques described herein provides the ability to form devices with less dielectric material and reduce the overall thickness of the formed device. Consequently, heat dissipation is increased through increased thermal conductivity compared to devices using current process technologies.

[0082] Figure 16a Figure 3-c shows a process for forming a high aspect ratio electroplated structure according to another embodiment. Figure 16a The figure shows trace 1802 formed on substrate 1804 using subtractive etching. According to some embodiments, a metal layer is formed on substrate 1804. A photoresist layer is formed on the metal layer using techniques known in the art. For some embodiments, the photoresist layer is a photosensitive polyimide deposited in liquid form on the metal layer. The photoresist is patterned and developed using techniques known in the art. The metal layer is then etched using techniques known in the art. After the etching process, trace 1802 is formed.

[0083] Figure 16b The figures illustrate the formation of high aspect ratio electroplated structures using conformal plating processes such as those described herein. Figure 16c The figures show the formation of high aspect ratio electroplated structures using a crown plating process such as those described herein. Figure 16b In contrast, in the case of forming a high aspect ratio electroplated structure as described above, Figure 16a The trace 1802 shown is then plated using a crown plating process (such as reference Figure 16c process described).

[0084] Figure 17 The figure illustrates the selective formation of high-aspect ratio electroplated structures according to an embodiment. Once traces 1902 are formed using techniques including those described herein, a photoresist layer 1904 is formed over portions of one or more of the formed traces 1902. Photoresist layer 1904 can be a photosensitive polyimide and is deposited and formed using techniques including those described herein. A metal crown 1906 is formed over traces 1902 using one or both of a conformal plating process and a crown plating process as described herein. Figure 18 The figure shows a perspective view of a high-aspect ratio electroplated structure according to an embodiment having a metal crown portion selectively formed on a trace. According to some embodiments, selectively forming a metal crown portion on a trace is used to improve the structural properties of the high-aspect ratio electroplated structure, improve the electrical performance of the high-aspect ratio electroplated structure, improve heat transfer characteristics, and meet customized dimensional requirements of devices formed using the high-aspect ratio electroplated structure. Examples of improved electrical performance include, but are not limited to, capacitance, inductance, and resistance properties of the high-aspect ratio electroplated structure. Additionally, selectively forming a metal crown portion on a trace can be used to adjust the mechanical or electrical properties of a circuit formed using the high-aspect ratio electroplated structure.

[0085] Figure 19 A hard drive platter suspension flexure 2102 is shown that includes high aspect ratio plated structures according to embodiments formed using selective forming as described herein. Figure 20 The figure shows a section taken along line AA. Figure 19 A cross-sectional view of a hard drive suspension flexure is shown in FIG. The cross-section of flexure 2102 includes high-aspect ratio plated structures 2104 and traces 2106. High-aspect ratio plated structures 2104 are formed using selective formation techniques as described herein. Forming high-aspect ratio plated structures 2104 to serve as conductors in predetermined areas of the flexure can achieve a reduction in DC resistance. This allows for the formation of fine lines and spaces where needed on the flexure while meeting design requirements for DC resistance and improving the electrical performance of the flexure.

[0086] Figure 21a , b illustrate a process for forming a high aspect ratio electroplated structure according to an embodiment using photoresist during a conformal plating process. Figure 21a The figure shows traces 2302 formed on a substrate 2304 using techniques including those described herein. Figure 21bThe figure illustrates the formation of high aspect ratio electroplated structures using a plating process as described herein. A photoresist portion 2306 is formed over a substrate 2304 using deposition and patterning techniques, including those described herein. Once the photoresist portion 2306 is formed, one or both of a conformal plating process and a crown plating process are performed to form metal portions 2308 over the trace 2302. The photoresist portion 2306 can be used to better define the spacing between the high aspect ratio electroplated structures.

[0087] Figure 22 Exemplary chemistries for a process for forming an initial metal layer, a standard / conformal plating process, and a crown plating process are illustrated according to various embodiments.

[0088] Figure 23 The figure shows a perspective view of the top surface 2501 of an inductively coupled coil 2502 with an integrated tuning capacitor formed from a high-aspect ratio electroplated structure 2504 according to an embodiment. Using a high-aspect ratio electroplated structure to form the inductively coupled coil reduces the footprint of the inductively coupled coil compared to inductively coupled coils formed using current techniques. This enables the inductively coupled coil 2502 to be used in applications where space is limited. Furthermore, using a capacitor integrated into the inductively coupled coil further reduces the footprint of the inductively coupled coil because no additional space is required to accommodate discrete capacitors, such as surface mount technology ("SMT") capacitors.

[0089] Figure 24 The figure shows Figure 23 A perspective view of the rear surface 2604 of an embodiment of the inductively coupled coil 2502 is shown. Figure 25 The figure shows a perspective view of the top surface of an inductive coupling coil 2502 according to an embodiment coupled with a radio frequency identification (“RFID”) chip 2704 .

[0090] Figure 26a Figure 2501 shows a method of forming an inductively coupled coil 2502 formed from a high aspect ratio electroplated structure 2504 according to an embodiment. According to various embodiments, the inductively coupled coil includes an integrated tuning capacitor. Figure 26aThe figure shows a substrate 2802 formed using techniques known in the art. In some embodiments, substrate 2802 is formed from stainless steel. Other materials that can be used for the substrate include, but are not limited to, steel alloys, copper, copper alloys, aluminum, and non-conductive materials that can be metallized using techniques including plasma vapor deposition, chemical vapor deposition, and electroless chemical deposition. A shadow mask 2804 is formed over substrate 2802. In some embodiments, shadow mask 2804 is a high-K dielectric. Examples of high-K dielectrics that can be used include, but are not limited to, titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, SU-8, KMPR, and other high-K dielectric materials. In some embodiments, shadow mask 2804 is formed using a sputtering process using techniques known in the art. In some embodiments, shadow mask 2804 is formed to have a thickness ranging from 500 to 1000 angstroms. In other embodiments, shadow mask 2804 is formed using screen printing of a high-K ink. Examples of high dielectric constant inks include inks comprising epoxy resin loaded with particles made of one or more of titanium dioxide (TiO2), niobium oxide (Nb2O5), tantalum oxide (TaO), aluminum oxide (Al2O3), silicon dioxide (SiO2), polyimide, and other high dielectric constant dielectric materials. In yet other embodiments, the shadow mask 2804 is formed using a slot die application of a photoimageable dielectric doped with a high-K filler. An example of a high-K filler includes zirconium dioxide (ZrO2).

[0091] Figure 26b The figure shows a metal capacitor plate 2806 formed on a shadow mask 2804. Metal capacitor plate 2806 and substrate 2802 form the two capacitor plates of the integrated capacitor. The thickness of shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. In addition, the purity of the high-K dielectric used to form shadow mask 2804 can be used to set the effective capacitance of the integrated capacitor. The surface area of ​​metal capacitor plate 2806 can also be used to set the effective capacitance of the integrated capacitor.

[0092] Figure 26c The figure shows a base dielectric layer 2808 formed over the shadow mask 2804, the metal capacitor plate 2806, and at least a portion of the substrate 2802. According to some embodiments, the base dielectric layer 2808 is formed by depositing a dielectric material, patterning the dielectric material, and curing the dielectric material using techniques including those known in the art. Examples of dielectric materials that may be used include, but are not limited to, polyimide, SU-8, KMPR, and hard-baked photoresists (such as those made of (See those sold here.) Base dielectric layer 2808 may also be patterned or etched to form vias. For example, jumper vias 2812 and shunt capacitor vias 2810 are formed in base dielectric layer 2808. Shunt capacitor vias 2810 are formed to interconnect the integrated capacitor with the rest of the circuit to be formed. Similarly, jumper vias 2812 are used to interconnect the circuit elements to be formed with substrate 2802.

[0093] Figure 26d The figure shows a coil 2814 formed on a base dielectric layer 2808 using techniques, including those described herein, using high-aspect ratio plating structures for forming coils. For some embodiments, coil 2814 is a single-layer coil. Coil 2814 includes a central connecting portion 2816 that connects to one of the shunt capacitor vias 2810 and one of the crossover vias 2812 that electrically contacts the metal capacitor plate 2806 of the integrated capacitor. Coil 2814 also includes a capacitor connecting portion 2818 that connects coil 2814 to another of the shunt capacitor vias 2810, which is in electrical contact with substrate 2802, which is configured as the lower plate of the integrated capacitor. According to various embodiments, terminal pads 2820 are formed using high-aspect ratio plating structures using techniques, including those described herein. Terminal pads 2820 can be formed during the same process used to form coil 2814.

[0094] Figure 26e The figure shows a cover coating 2822 formed over the coil 2814, the terminal pad 2820, and the base dielectric layer 2808 to wrap the coil side of the inductive coupling coil. The cover coating 2822 is formed using deposition, etching, and patterning steps including those known in the art. For example, the cover coating 2822 can be formed from a polyimide solder mask, SU-8, KMPR, or epoxy resin.

[0095] Figure 26f The figure shows the back side of an inductively coupled coil formed in accordance with an embodiment. At least a first pad 2824 and a second pad 2826 are formed on a side of substrate 2802 opposite coil 2814. According to some embodiments, first pad 2824 and second pad 2826 are formed of gold using deposition and patterning techniques, including those known in the art. First pad 2824 and second pad 2826 are formed to provide electrical contact for attaching an integrated circuit chip (such as an RFID chip) to substrate 2802.

[0096] Figure 26gThe figure illustrates a backside dielectric layer 2828 formed on the backside of an inductively coupled coil formed according to an embodiment. The method of forming the inductively coupled coil may optionally include forming the backside dielectric layer 2828 on the substrate 2802. The backside dielectric layer 2828 is formed using techniques similar to those used to form the base dielectric layer 2808. According to some embodiments, the backside dielectric layer 2828 is patterned to prevent short circuits between the substrate 2802 and an attached integrated circuit chip. According to various embodiments, the backside dielectric layer 2828 is patterned to provide a bridge pattern 2830 for etching the substrate 2802 to form a bridge path in subsequent steps. Additional patterns in the backside dielectric may be formed to also etch other portions of the substrate 2802.

[0097] Figure 26h The figure shows an inductively coupled coil 2834 formed into its final shape according to an embodiment. The portion of substrate 2802 not covered by backside dielectric layer 2828 is etched. The etched portion includes a jumper pattern 2830 to form a jumper path 2832. The etching is performed using techniques including those known in the art. Those skilled in the art will understand that other portions of substrate 2802 can be etched to form other conductive paths similar to jumper path 2832. Figure 26i The figure shows the coil side of the inductively coupled coil 2834 including the crossover path 2832 according to an embodiment.

[0098] Figure 26j The figure shows the coil side of an inductive coupling coil 2834 including an integrated chip 2836 attached to the back side of the inductive coil according to an embodiment. The method for forming the inductive coupling coil 2834 may optionally include the step of attaching an integrated chip 2836 (such as an RFID chip) to the inductive coupling coil 2834 using techniques including those known in the art. Such an integrated chip 2836 is attached using an adhesive including, but not limited to, conductive epoxy, solder, and other materials for achieving electrical connection.

[0099] The integration of capacitors into devices including high aspect ratio electroplated structures provides the ability to utilize the small footprint requirements that can be achieved by using high aspect ratio electroplated structures. Other embodiments of the inductively coupled coil include an inductively coupled coil having multiple integrated capacitors. As is known in the art, the integrated capacitors can be connected in parallel or in series. Other devices including high aspect ratio electroplated structures that may also include integrated capacitors include, but are not limited to, step-down transformers, signal conditioning devices, tuning devices, and other devices including one or more inductors and one or more capacitors.

[0100] The high aspect ratio electroplated structures according to the embodiments described herein can be used to form devices or parts of devices to optimize performance and achieve a small footprint. Such devices include, but are not limited to, power converters (e.g., step-down transformers, voltage dividers, AC transformers), actuators (e.g., linear, VCM), antennas (e.g., RFID, wireless power transfer for battery charging, and security chips), wireless passive coils, rechargeable cell phone and medical device batteries, proximity sensors, pressure sensors, contactless connectors, micromotors, microfluidics, cooling / heat sinks on packages, long narrow flexible circuits with air core capacitors and inductors (e.g., for catheters), interdigitated acoustic wave transducers, tactile vibrators, implants (e.g., pacemakers, stimulators, bone growth devices), Magnetic resonance imaging ("MRI") devices for surgery (e.g., esophageal, colonoscopy), beyond tactile (e.g., clothing, gloves), coated surfaces for detection / filter release, security systems, high energy density batteries, induction heating devices (for small local areas), magnetic fields for fluid / drug distribution and dose delivery achieved by channel pulses, tracking and information devices (e.g., agriculture, food, valuables), credit card security, audio systems (e.g., speaker coils, recharging mechanisms in headphones, earplugs), heat transfer, mechanically conductive seals, energy harvesters, and interlocking shapes (similar to hook and loop fasteners). In addition, high aspect ratio electroplating structures as described herein can be used to form high bandwidth, low impedance interconnects. The use of high aspect ratio electroplating structures in interconnect applications can be used to improve electrical properties (e.g., resistance, inductance, capacitance), improve heat transfer properties, and customize dimensional requirements (thickness control). Interconnect applications including high aspect ratio electroplating structures as described herein can be used to adjust the bandwidth of one or more circuits for a given frequency range. Other interconnect applications including high aspect ratio electroplating structures can integrate one or more circuits that change current (e.g., signal and power). The use of high-aspect ratio plated structures allows for the implementation of circuits with varying cross-sections, allowing some circuits to have greater current-carrying capacity so they can be fabricated closer together to maintain a dense overall package size. High-aspect ratio plated structures can also be used in interconnect applications for mechanical purposes. For example, it may be desirable to have some areas of a circuit protrude above other areas to serve as mechanical stops, supports, electrical contact areas, or to increase rigidity.

[0101] Figure 27The figure shows a plan view of a flexure for a suspension of a hard disk drive including a high-aspect ratio electroplated structure according to an embodiment. Flexure 2900 includes a distal portion 2901, a gimbal portion 2902, a middle portion 2904, a gap portion 2906, and a proximal portion 2908. Proximal portion 2908 is configured to be attached to a base plate such that distal portion 2901 extends above the rotating disk media. According to some embodiments, gimbal portion 2902 is configured to include: one or more motors, such as piezoelectric motors; and one or more electrical components, such as a head slider for reading from or writing to the disk media; and components for heat-assisted magnetic recording ("HAMR") / thermal-assisted magnetic recording ("TAMR") or microwave-assisted magnetic recording ("MAMR"). The one or more motors and one or more electrical components are electrically connected to other circuitry via one or more traces formed on a conductive layer of the flexure, which extends from distal portion 2901 of flexure 2900 through middle portion 2904, over gap portion 2906, and beyond proximal portion 2908. The gap portion 2906 is a portion of the bend where the base layer (such as the stainless steel layer) is partially or completely removed. As a result, one or more traces in the conductor layer of the bend extend over the gap portion 2906 without any support. Those skilled in the art will appreciate that the bend may have one or more gap portions 2906 at any location along the bend.

[0102] Figure 28 The figure shows that along Figure 27 A cross-section of the gap portion of the bend at the gap portion is shown, taken along line A. Gap portion 2906 includes trace 3002 disposed on dielectric layer 3004. A dielectric layer, such as a polyimide layer, is disposed on substrate 3006, such as a stainless steel layer. Substrate 3006 and dielectric layer 3004 define a void 3008 such that trace 3002 extends over void 3008. Trace 3002 includes a metal crown portion to form a high-aspect ratio structure. The metal crown portion is selectively formed on trace 3002 using the techniques described herein. The metal crown portion is formed on trace 3002 to provide additional strength across void 3008 and, when in use, electrically couples with an interconnect application in the area of ​​void 3008.

[0103] Figure 29The figure shows a gimbal portion 2902 having a mass structure 3102 according to an embodiment. The mass structure 3102 is formed using the techniques described herein using a high-aspect ratio electroplated structure. For some embodiments, the mass structure 3102 acts as a counterweight to adjust the resonance of the gimbal portion 2902. Thus, the shape, size, and position of the mass structure 3102 can be determined to adjust the resonance of the gimbal portion 2902, thereby enhancing the performance of the hard drive suspension. The process described herein for forming the high-aspect ratio structure can be used to maintain the size of the high-aspect ratio structure so that the resonance can be finely tuned. In addition, the process can form high-aspect ratio structures at sizes beyond the capabilities of current photolithographic processes, thereby providing greater control over the final structure formed.

[0104] The mass structure 3102 can also be configured to act as a mechanical stop. For example, one or more mechanical stops can be formed into any shape to act as a backstop and / or to align components mounted on the universal joint portion 2902 or other portion of the flexure.

[0105] Figure 30 FIG. 1 shows a proximal portion of a bend including a high aspect ratio plated structure according to an embodiment. Figure 27 A cross section taken along line B is shown. Proximal portion 2904 includes a conductor layer comprising traces 3002a, b, c, and d disposed on a dielectric layer 3004. Dielectric layer 3004 is disposed on substrate 3006. Covering layer 3001 is disposed on the conductor and dielectric layers. The conductor layer includes conventional traces 3002a, b and traces 3002c, d, which are formed such that at least a portion of the traces include metal crowns 3202a, b to form high-aspect-ratio electroplated structures using the techniques described herein. One or more portions of traces 3002a, b, c, and d can be formed to include metal crowns 3202a, b to adjust the impedance of each trace. For example, the resistance of the traces can be adjusted as needed to meet desired performance characteristics. Another example includes using metal crowns to adjust impedance by closing the distance between adjacent traces 3002a, b, c, and d.

[0106] Figure 31 FIG. 1 shows a proximal portion of a curved portion including a high aspect ratio structure according to an embodiment of the present invention. Figure 27A cross-section taken along line C is shown. The proximal portion of the bend includes a conductor layer comprising at least trace 3002 disposed on a dielectric layer 3004. Dielectric layer 3004 is disposed on a substrate 3008. Furthermore, a cover layer 3001 is formed over the substrate to include a metal crown portion to form a high-aspect ratio plated structure using the techniques described herein. Trace 3002 is configured as a high-aspect ratio structure to match the impedance of the trace to the terminal connector and provide strength to the joint that electrically couples trace 3002 to the connector. Figure 32 The figure shows a plan view of the proximal portion 2908 of the flexure including a high aspect ratio structure according to an embodiment. The use of high aspect ratio structures as described with reference to use with the flexure is also applicable to other circuit board technologies, such as for microcircuits and radio frequency ("RF") circuits.

[0107] Figure 33 The figure illustrates a process for forming a high aspect ratio electroplated structure according to an embodiment. As shown, a copper layer 3318 serves as a substrate. However, other conductive materials may also serve as a substrate. At 3301, a dielectric layer 3320, such as those described herein, is placed on the copper layer 3318 and marked and perforated. The dielectric layer 3320 may be formed using materials including, but not limited to, photoimageable or non-photoimageable materials, polymers, ceramics, and other insulating materials. For some embodiments, the copper layer 3318 is a copper alloy layer such as those described herein. For some embodiments, one or more through holes or vias 3322 are marked and perforated in the dielectric layer to expose the copper layer 3318. According to some embodiments, the dielectric layer 3320 is a photoimageable dielectric material, and patterning and development techniques, including those described herein, are used to create the one or more through holes or vias 3322. Other embodiments include using a laser, drilling, or etching the dielectric layer 3320 to create the one or more through holes or vias 3322. For some embodiments, the copper alloy layer has a thickness in the range of 15 microns to 40 microns. At 3302, traces 3324 or other conductive features are provided on the side of the dielectric layer 3320 opposite the copper layer 3318. For some embodiments, a seed layer is sputtered using techniques including those described herein to form a pattern on the dielectric layer 3320. Other embodiments include using electroless plating to form the seed layer. Using techniques including those described herein, one or more traces 3324 and conductive features are formed to a desired thickness using a plating process (such as those described herein).

[0108] At 3304, a conformal plating process, such as those described herein, is used to build up one or more traces and conductive features using techniques including those described herein to increase the thickness or further enhance the shape of the one or more traces and conductive features on the side of the dielectric layer 3320 opposite the copper layer 3318. For some embodiments, a crown plating process, such as those described herein, is used in addition to the conformal plating process at 3304 on the side of the dielectric layer 3320 opposite the copper layer 3318. For some embodiments, the crown plating process is used instead of the conformal plating process.

[0109] At 3306, a dielectric layer 3326 (such as a covercoat) is disposed over the one or more traces 3324 and conductive features on the side of the dielectric layer opposite the copper layer 3318 using techniques including those described herein. For some embodiments, a covercoat is not included. For example, the formed one or more traces 3324 and conductive features may be plated with a layer of gold. At 3308, the copper layer 3318 is etched using techniques including those described herein to form a pattern. For some embodiments, the copper layer 3318 is etched to form one or more traces 3328 and / or one or more conductive features.

[0110] At 3310, one or more traces 3328 and conductive features are constructed using a conformal plating process, such as those described herein, using techniques including those described herein, to increase the thickness or further enhance the shape of one or more traces 3328 and conductive features formed in copper layer 3318. For some embodiments, a crown plating process, such as those described herein, is used in addition to the conformal plating process at 3310 on copper layer 3318. For some embodiments, the crown plating process is used instead of the conformal plating process.

[0111] At 3312, a dielectric layer 3330 (such as a covercoat) is applied over one or more traces 3328 and conductive features formed from copper layer 3318 using techniques including those described herein. For some embodiments, a covercoat is not included. For example, the formed one or more traces 3328 and conductive features may be plated with a layer of gold. For some embodiments, the process is used to fabricate multiple circuits or devices on a single substrate. At 3316, for such embodiments, the circuits or devices are separated (single) and may optionally be packaged using techniques including those known in the art. For some embodiments, the circuits and / or devices are separated using techniques including, but not limited to, laser ablation, cracking, cutting, etching, etc. For some embodiments, the covercoat described herein may be patterned using patterning techniques described herein. For example, the covercoat is applied in a blanket layer. According to some embodiments, the covercoat is applied using slot die coating to apply the photoimageable dielectric material. Other techniques such as roller coating, spray coating, dry film lamination, or other known methods for applying photoimageable or non-photoimageable materials may be used. If the material is not photoimageable, it can be patterned using other methods (e.g., laser or etching). For some embodiments, one or both of the dielectric layer / cover coating can be formed with a surface finish, for example, to aid adhesion to other structures or substrates. For some embodiments, the surface finish is formed on the dielectric layer / cover coating by texturing or patterning the dielectric layer / cover coating.

[0112] At 3314, for some embodiments, terminal pads 3332 (such as nickel terminals plated with a gold layer) can be formed on substrate 3318 using electroless plating and solder can be applied thereto. According to some embodiments, the surface treatment formed on the exposed copper layer provided on the top and / or bottom sides is plated using electroless or electrolytic plating of nickel, gold, or other industry standard surface treatments. Additionally, solder can be applied to these areas.

[0113] Figure 34 The figure shows a similar Figure 33 A more detailed process of the type described for forming high aspect ratio electroplated structures according to some embodiments is provided.

[0114] Figure 35 The figure shows a coil manufactured using the process described herein. Coil 3501 includes multiple (e.g., three or more) coil segments electrically coupled to form coil 3501. For some embodiments, such as Figure 35In the embodiment shown, the number of turns in the outer coil segment 3504 is the same as the number of turns in the inner coil segment 3502 between the two outer coil segments 3504. For some embodiments, the inner coil segment 3402 includes more turns than the outer coil segments 3504. Other embodiments include multiple coil segments, where subsets of the multiple coil segments are electrically coupled, for example, with reference to Figure 35 , two of the plurality of coil segments are electrically coupled, and the remaining coil segment is not electrically coupled with the other two coil segments. Thus, any combination of any number of coil segments can be included in any number of coil segments that are electrically coupled with any coil segment of the other coil segments.

[0115] Multiple layers including any one or more of the traces and conductive features fabricated using the techniques described herein can be formed by stacking each layer, and connections between each layer can be made through vias passing through the layers filled with a conductive material, such as a conductive adhesive.

[0116] According to some embodiments, the processes described herein are used to form coils in conjunction with other circuit components, such as resistance temperature detectors (RTDs), strain gauges, and other sensors.

[0117] According to some embodiments, the processes described herein are used to form any one or more of mechanical structures and electromechanical structures.

[0118] Although described with reference to these embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention.

Claims

1. An electrical device comprising: a conductive substrate etched to include at least a first set of traces; a dielectric layer disposed on the conductive substrate and having a first surface and a second surface; at least a second set of traces disposed on the first surface of the dielectric layer; a first metal crown portion formed over at least a portion of each trace in the second set of traces to form a first set of high aspect ratio plated structures disposed on the first surface of the dielectric layer; A second metal crown portion is formed on at least a portion of each trace in the first set of traces to form a second set of high aspect ratio plated structures disposed on the second surface of the dielectric layer opposite the first set of high aspect ratio plated structures. 2 . The electrical device of claim 1 , comprising a second dielectric layer disposed on the first set of high aspect ratio plated structures. 3 . The electrical device of claim 1 , comprising a third dielectric layer disposed on the second set of high aspect ratio plated structures.

4. The electrical device according to claim 1, wherein The dielectric layer includes a via to electrically couple at least one high-aspect ratio plated structure of the first set of high-aspect ratio plated structures with at least one high-aspect ratio plated structure of the second set of high-aspect ratio plated structures.

5. The electrical device according to claim 1, wherein The first set of high aspect ratio plated structures and the second set of high aspect ratio plated structures are configured to form a coil. 6 . The electrical device of claim 1 , configured to form a coil having two outer coil segments and an inner coil segment located between the two outer coils. 7 . The electrical device of claim 1 , comprising a first terminal pad coupled to at least one high-aspect ratio plated structure of the first set of high-aspect ratio plated structures.

8. The electrical device according to claim 7, wherein: The first terminal pad is a nickel terminal plated with a gold layer.

9. The electrical device according to claim 1, wherein At least a portion of the first set of high aspect ratio plated structures is formed using a crown plating process.

10. The electrical device according to claim 1, wherein The second set of high aspect ratio electroplated structures is formed by etching the substrate.

11. The electrical device according to claim 1, wherein At least a portion of the second set of high aspect ratio plated structures is formed using a crown plating process.

12. A coil comprising: a conductive substrate etched to include a first plurality of traces; a dielectric layer disposed on the conductive substrate and having a first surface and a second surface; a plurality of second traces disposed on the first surface of the dielectric layer; a first metal crown portion formed over at least a portion of each of the plurality of second traces to form a first set of high aspect ratio plated structures disposed on the first surface of the dielectric layer; A second metal crown portion is formed on at least a portion of each of the plurality of first traces to form a second set of high aspect ratio plated structures disposed on the second surface of the dielectric layer opposite the first set of high aspect ratio plated structures.

13. The coil according to claim 12, wherein The dielectric layer includes a via to electrically couple at least one high-aspect ratio plated structure of the first set of high-aspect ratio plated structures with at least one high-aspect ratio plated structure of the second set of high-aspect ratio plated structures.

14. The coil according to claim 12, wherein The first set of high aspect ratio plated structures and the second set of high aspect ratio plated structures are used for a first coil segment of the coil.

15. The coil of claim 14, comprising a third set of high aspect ratio plated structures and a fourth set of high aspect ratio plated structures for a second coil segment of the coil.

16. The coil of claim 15, comprising a fifth set of high aspect ratio plated structures and a sixth set of high aspect ratio plated structures for a third coil segment of the coil.

17. The coil according to claim 16, wherein The first coil segment is electrically coupled to the second segment and the third coil segment.

18. The coil according to claim 16, wherein The second coil segment is electrically coupled to the third coil segment.

19. The coil according to claim 12, wherein The second set of high aspect ratio electroplated structures is formed by etching the substrate.

20. The coil according to claim 19, wherein At least a portion of the second set of high aspect ratio plated structures is formed using a crown plating process.

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