Semiconductor device

Abstract

The semiconductor device of the present invention includes: a first MOS transistor and a second MOS transistor, the drain electrodes of the first MOS transistor and the second MOS transistor are connected in series between a first line to which a power supply voltage is applied and a second line to which a load is connected; a third line, the third line is connected to the gate electrode of the first MOS transistor; and a fourth line, the fourth line is connected to the gate electrode of the second MOS transistor and is provided separately from the third line electrically.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] In an ECU (Electronic Control Unit) provided between a battery and a load such as an electric motor in a normal automobile, a switch for supplying power from the battery to the load is provided (for example, Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Laid-Open No. 7-184318 Summary of the Invention

[0006] Technical Problem to be Solved by the Invention

[0007] In addition, as a switch for supplying power to a load, for example, two MOS transistors (especially NMOS transistors) having a common gate electrode are sometimes used. However, generally, the gate capacitances of the two MOS transistors constituting the switch are large, so there is a problem that the switching period during turn-on and turn-off of the switch becomes long.

[0008] The present invention has been completed in view of the above-described conventional problems, and an object thereof is to provide a semiconductor device including a switch capable of shortening the switching period.

[0009] Technical Means for Solving the Technical Problem

[0010] A main aspect of the present invention for solving the above problems is a semiconductor device including: a first MOS transistor and a second MOS transistor, wherein the drain electrodes of the first MOS transistor and the second MOS transistor are connected in series between a first line to which a power supply voltage is applied and a second line to which a load is connected; a third line connected to the gate electrode of the first MOS transistor; and a fourth line connected to the gate electrode of the second MOS transistor and provided separately from the third line in an electrically isolated manner.

[0011] Advantageous Effects of the Invention

[0012] According to the present invention, a semiconductor device including a switch capable of shortening the switching period can be provided. Brief Description of the Drawings

[0013] Figure 1 It is a diagram showing an example of a motor control device 10.

[0014] Figure 2This is a diagram showing an example of the IPS 21.

[0015] Figure 3 This is a cross-sectional view of the NMOS transistors M1 and M2.

[0016] Figure 4 This is a diagram showing an example of the charge pump circuit 72.

[0017] Figure 5 This is a diagram showing an example of the change in the output voltage Vout of the IPS 21.

[0018] Figure 6 This is a diagram showing an example of the IPS 25.

[0019] Figure 7 This is a diagram showing an example of the change in the output voltage Vout of the IPSs 21 and 25.

[0020] Figure 8 This is a diagram for explaining the operation of the IPS 21 when the battery 11 is reversely connected.

[0021] Figure 9 This is a cross-sectional view of the NMOS transistor 120. Detailed Description

[0022] Cross-Reference to Related Applications

[0023] This application claims priority based on Japanese Patent Application No. 2019-144555 filed on August 6, 2019, and incorporates its content.

[0024] From the descriptions in this specification and the drawings, at least the following matters can be understood.

[0025] =====This Embodiment=====

[0026] Figure 1 This is a diagram showing the structure of the motor control device 10 as an embodiment of the present invention. The motor control device 10 is a device for controlling a motor 12 provided in an automobile by using the power from a battery 11, and includes an ECU 20 containing an IPS (Intelligent Power Switch). In addition, the battery 11 is, for example, a lithium-ion battery for an automobile and outputs a power supply voltage Vcc of 12V.

[0027] The ECU 20 is a device for controlling the motor 12, and is configured to include an IPS 21 (described later), a microcomputer 30, and a switch 31.

[0028] The microcomputer 30 controls the IPS 21 and the switch 31 based on an instruction (not shown) input from the outside. The switch 31 is an element for applying the power supply voltage Vcc of the battery 11 output via the IPS 21 to the motor 12. In addition, hereinafter, for convenience in this embodiment, the case where the microcomputer 30 turns on the switch 31 will be described.

[0029] The IPS 21 is a "semiconductor device" that switches whether to supply the power supply voltage Vcc of the battery 11 to the motor 12 based on the instruction signal Sa output from the microcomputer 30.

[0030] The IPS 21 includes terminals VCC, GND, IN, and OUT. The power supply voltage Vcc of the battery 11 is applied to the terminal VCC, and the terminal GND is grounded. In addition, the instruction signal Sa from the microcomputer 30 is input to the terminal IN, and when a switch (described later) inside the IPS 21 is turned on, the voltage Vcc is output from the terminal OUT. In this embodiment, the voltage of the terminal GND is set to the ground voltage Vgnd (0 V).

[0031] In addition, although the details will be described later, the IPS 21 appropriately protects the motor 12 and the ECU 20 when the battery 11 is reversely connected. In addition, "reverse connection" means a state where the positive electrode of the battery 11 is connected to the grounded terminal (for example, the terminal GND) and the negative electrode of the battery 11 is connected to the power supply side terminal (for example, the terminal VCC).

[0032] <<< Structure of IPS 21 >>>

[0033] Figure 2 FIG. is an example showing the structure of the IPS 21. The IPS 21 is configured to include an IC (Integrated Circuit) 50 in which a switch (described later) is formed and an IC 51 having a circuit for turning on and off the switch.

[0034] === IC 50 ===

[0035] The IC 50 includes two MOS transistors that constitute a switch (hereinafter referred to as "switch X1") for switching whether to output the power supply voltage Vcc from the terminal OUT. In particular, in this embodiment, the two transistors are NMOS transistors M1 and M2.

[0036] In the NMOS transistor M1, the source electrode S1 is connected to the "power supply line L1" to which the power supply voltage Vcc is applied. In addition, a diode 60 is formed as a body diode between the source electrode S1 and the drain electrode D1 of the NMOS transistor M1.

[0037] In the NMOS transistor M2, the source electrode S2 is connected to the "load line L2" connected to a load such as the ECU 20, and the drain electrode D2 is connected to the drain electrode D1 of the NMOS transistor M1. In addition, a diode 61 is formed as a body diode between the source electrode S2 and the drain electrode D2 of the NMOS transistor M2.

[0038] Here, the drain electrodes D1 and D2 of the NMOS transistors M1 and M2 are connected in series with each other. Therefore, if both the NMOS transistors M1 and M2 are turned on, the power supply voltage Vcc of the terminal VCC is output from the terminal OUT.

[0039] In addition, the anode of the diode 60 is connected to the power supply line L1, and the cathode of the diode 60 is connected to the cathode of the diode 61. Moreover, the anode of the diode 61 is connected to the load line L2. Therefore, the cathodes of the diodes 60 and 61 provided between the power supply line L1 and the load line L2 are connected to each other relatively.

[0040] Therefore, when both the NMOS transistors M1 and M2 are turned off, for example, the power supply voltage Vcc applied to the terminal VCC is cut off by the diode 61. On the other hand, for example, when the battery 11 is reversely connected and the power supply voltage Vcc is applied to the terminal OUT, the power supply voltage Vcc of the terminal OUT is cut off by the diode 60.

[0041] As a result, when both the NMOS transistors M1 and M2 are turned off, the "switch X1" can prevent current from flowing through the load connected to the terminal OUT, thus appropriately protecting the load.

[0042] In addition, the NMOS transistor M1 corresponds to the "first MOS transistor", and the NMOS transistor M2 corresponds to the "second NMOS transistor". In addition, the power supply line L1 corresponds to the "first line", and the load line L2 corresponds to the "second line".

[0043] == Structure of NMOS transistors M1 and M2 ==

[0044] Figure 3 is a diagram showing the cross-section of the NMOS transistors M1 and M2. The NMOS transistors M1 and M2 are formed on the semiconductor substrate 200 of the IC 50.

[0045] The semiconductor substrate 200 is an n-type substrate formed of, for example, silicon, and a drain electrode 210 is formed on the back side, and source electrodes 211a, 211b, and substrate electrodes 212a, 212b are formed on the front side. Here, the drain electrode 210, the source electrodes 211a, 211b, and the substrate electrodes 212a, 212b can be formed of a conductive material such as polysilicon or a metal electrode. In addition, since the NMOS transistors M1 and M2 have the same structure, hereinafter, the NMOS transistor M1 will be described.

[0046] In addition, in Figure 2 and Figure 3 for convenience, the electrodes of the NMOS transistors M1 and M2 are given different labels, but the drain electrode 210 of the NMOS transistor M1 corresponds to the "drain electrode D1", and the source electrode 211a corresponds to the "source electrode S1". In addition, the gate electrode 241a (described later) corresponds to the "gate electrode G1".

[0047] Inside the semiconductor substrate 200, an n-type drift region 220, an n-type drain region 221, a p-type well region 222a, an n+-type source region 223, a p+-type contact region 224a, and a gate trench portion 230a are formed.

[0048] The drift region 220 is a region containing an n-type impurity such as phosphorus, and the drain region 221 is a region containing an n-type impurity such as phosphorus at a higher concentration than the drift region 220 and formed on the back side of the drift region 220.

[0049] The well region 222a is a region formed on the front side of the drift region 220, and the source region 223a is an n+-type region formed in a part of the well region 222a. In addition, hereinafter, when described as n+-type or p+-type, this means that the doping concentration is higher than that of the n-type or p-type. In addition, a p+-type contact region 224a containing a p-type impurity at a higher concentration than the well region 222a is formed on the front side of the semiconductor substrate 200 in the well region 222a. In addition, a diode 60 as a body diode is formed between the p-type well region 222a and the n-type drift region 220.

[0050] The gate trench portion 230a includes a gate oxide film 240a formed on the inner wall of the trench and a gate electrode 241a covering the gate oxide film 240a in the trench. In addition, the gate electrode 241a is formed of a conductive material such as polysilicon. In addition, the gate trench portion 230a is covered with an oxide film 231a, and the source electrode 211a is formed on the front side of the oxide film 231a so as to cover the oxide film 231a.

[0051] Here, if the gate-source voltage of NMOS transistor M1 and the gate-source voltage of NMOS transistor M2 become higher than their respective threshold voltages, channels are formed in the well regions 222a and 222b, and NMOS transistors M1 and M2 are turned on.

[0052] As a result, for example, if the power supply voltage Vcc is applied to the source electrode S1 of NMOS transistor M1 and the source electrode S2 of NMOS transistor M2 becomes the ground voltage, current flows along the Figure 3 path indicated by the single dotted line.

[0053] In addition, although the detailed description of NMOS transistor M2 is omitted, the drain electrode 210 of NMOS transistor M2 corresponds to "drain electrode D2", the source electrode 211b corresponds to "source electrode S2", and the gate electrode 241b corresponds to "gate electrode G2".

[0054] ===IC51===

[0055] Figure 2 The IC 51 of

[0056] is a circuit for turning on / off "switch X1" based on the indication signal Sa, and is configured to include a power supply circuit 70, a control circuit 71, a charge pump circuit 72, a separation circuit 73, a discharge circuit 74, gate protection circuits 75 and 76, and resistors 80 to 82.

[0057] The power supply circuit 70 generates a power supply voltage Vdd for operating circuits such as the control circuit 71 and the charge pump circuit 72 based on the power supply voltage Vcc from the battery 11. In addition, the power supply voltage Vdd is a voltage lower than the power supply voltage Vcc.

[0058] The control circuit 71 is a logic circuit that generates an indication signal Sb (first indication signal) for turning on "switch X1" and an indication signal Sc (second indication signal) for turning off "switch X1" based on the indication signal Sa.

[0059] The charge pump circuit 72 is a circuit for generating a specified voltage Vcp (specified voltage) for turning on NMOS transistors M1 and M2 that constitute "switch X1" based on the indication signal Sb. In addition, the detailed situation of the charge pump circuit 72 will be described later.

[0060] A voltage Vcp is applied to the anode of diode 100, and the cathode is connected to the anode of diode 101. In addition, the anode of diode 101 is connected to one end of resistor 104, and the other end of resistor 104 is connected to gate line L3.

[0061] Here, gate line L3 is a wiring connected to gate electrode G1 of NMOS transistor M1 via resistor 80.

[0062] In addition, a voltage Vcp is applied to the anode of diode 102, and the cathode is connected to the anode of diode 103. The anode of diode 103 is connected to one end of resistor 105, and the other end of resistor 105 is connected to gate line L4.

[0063] Here, gate line L4 is a wiring connected to gate electrode G2 of NMOS transistor M2 via resistor 81.

[0064] Therefore, the series-connected diodes 100, 101 and resistor 104 apply a voltage corresponding to voltage Vcp only to gate line L3 among gate lines L3 and L4. On the other hand, the series-connected diodes 102, 103 and resistor 105 apply a voltage corresponding to voltage Vcp only to gate line L4 among gate lines L3 and L4. By using such a separation circuit 73, the voltage Vcp output from one charge pump circuit 72 can be applied to each of the electrically separated gate lines L3 and L4.

[0065] In addition, in the present embodiment, for example, two diodes are connected to gate lines L3 and L4, but other numbers (for example, one, three or more) may also be used. By increasing the number of diodes in separation circuit 73, even when power supply voltage Vcc becomes very high, a relatively high voltage can be prevented from being applied to charge pump circuit 72.

[0066] In addition, gate line L3 only needs to be a wiring that “electrically connects” the output from separation circuit 73 and gate electrode G1. Therefore, resistor 80 may not be included in gate line L3. In addition, gate line L4 is the same as gate line L3. Here, gate line L3 corresponds to the “third line”, and gate line L4 corresponds to the “fourth line”. In addition, each of diodes 100 and 101 corresponds to the “first diode”, and each of diodes 102 and 103 corresponds to the “second diode”.

[0067] Discharge circuit 74 is a circuit for turning off NMOS transistors M1 and M2 constituting “switch X1”, and is configured to include NMOS transistor 120, switches 121 and 122.

[0068] The NMOS transistor 120 is a depletion-type transistor. The drain electrode D3 is connected to the gate line L3, and the gate electrode G3 and the source electrode S3 are connected to the load line L2 via the resistor 82. Thus, the NMOS transistor 120 is always on, and accordingly, the gate capacitance of the NMOS transistor M1 is discharged via the NMOS transistor 120.

[0069] In addition, the current value when the NMOS transistor 120 discharges the gate capacitance of the NMOS transistor M1 is set to a sufficiently small value so as not to affect the NMOS transistor M1 when it is on. Further, the NMOS transistor 120 corresponds to the "third transistor".

[0070] The switch 121 is provided between the gate line L4 and the ground line L5 connected to the terminal GND, and the switch 122 is provided between the gate line L4 and the load line L2. Then, the switches 121 and 122 are turned on, for example, based on the indication signal Sc for turning off the "switch X1". Accordingly, the gate capacitance of the NMOS transistor M2 is discharged via the "path A1" of the gate line L4, the switch 121, and the ground line L5, and the "path A2" of the gate line L4, the switch 122, and the load line L2.

[0071] In addition, when the "switch X1" is on, a voltage corresponding to the power supply voltage Vcc is applied to the load line L2. Thus, the gate capacitance of the NMOS transistor M2 is first discharged via the "path A1". Here, the ground line L5 corresponds to the "fifth line", the switch 121 corresponds to the "first switch", and the switch 122 corresponds to the "second switch".

[0072] The gate protection circuit 75 is a circuit for preventing the voltage of the source electrode S1 from becoming too high with respect to the gate electrode G1 of the NMOS transistor M1, and is configured to include diodes 130 and 131.

[0073] The anode of the diode 130 is connected to the power supply line L1, and the cathode is connected to the anode of the diode 131. Further, the cathode of the diode 130 is connected to the gate line L3. In addition, the forward voltage of each of the diodes 130 and 131 is set to Vf.

[0074] In such a case, if the voltage of the source electrode S1 becomes higher than the voltage of the gate electrode G1 by the forward voltages (2×Vf) of the two diodes 130 and 131, the diodes 130 and 131 become on. As a result, the gate protection circuit 75 suppresses the source voltage of the NMOS transistor M1 from becoming excessively larger than the gate voltage. Thus, in the present embodiment, it is possible to prevent the gate oxide film 240a of the NMOS transistor M1 (refer to Figure 3)Damaged. In addition, since the gate capacitance of the gate electrode G1 of the NMOS transistor M1 is pre-charged, this achieves the effect of shortening the switching period.

[0075] The gate protection circuit 76 is a circuit for preventing the voltage of the source electrode S2 from becoming too high with respect to the gate electrode G2 of the NMOS transistor M2, and is configured to include diodes 132, 133, and resistor 134. In addition, when the connection direction of the battery 11 is normal, the voltage of the source electrode S2 does not rise, but if the battery 11 is reversely connected, the voltage of the source electrode S2 rises.

[0076] The anode of the diode 132 is connected to the load line L2, and the cathode is connected to the anode of the diode 133. In addition, the cathode of the diode 133 is connected to the gate line L4 via a resistor 134 for limiting current. In addition, the forward voltage of each of the diodes 132, 133 is set to Vf.

[0077] In such a case, if the voltage of the source electrode S2 becomes higher than the voltage of the gate electrode G2 by the forward voltages (2×Vf) of two diodes 132, 133, the diodes 132, 133 become conductive. As a result, the gate protection circuit 76 suppresses the source voltage of the NMOS transistor M2 from becoming excessively greater than the gate voltage. Therefore, in the present embodiment, it is possible to prevent the gate oxide film 240b of the NMOS transistor M2 (refer to Figure 3 ) from being damaged.

[0078] In addition, each of the diodes 130, 131 having the anode side connected to the power supply line L1 and the cathode side connected to the gate line L3 corresponds to a "third diode". In addition, each of the diodes 132, 133 having the anode side connected to the load line L2 and the cathode side connected to the gate line L4 corresponds to a "fourth diode".

[0079] == Structure of Charge Pump Circuit 72 ==

[0080] Figure 4 is a diagram showing an example of the charge pump circuit 72. The charge pump circuit 72 is configured to include an oscillator 300, inverters 310, 311, diodes 320 to 323, and capacitors 330, 331. In addition, here, the forward voltage of the diodes 320 to 323 is set to Vf.

[0081] The oscillator 300 is, for example, a circuit that outputs a clock signal CLK of a specified frequency based on an indication signal Sb for turning on the "switch X1", and the inverters 310, 311 invert the logic level of the input signal and output it.

[0082] The inverter 310, the diode 320, and the capacitor 330 form the first - stage boosting circuit of the charge - pump circuit 72. The power - supply voltage Vdd is applied to the anode of the diode 320, and the cathode is connected to one end of the capacitor 330. In addition, the output of the inverter 310 is connected to the other end of the capacitor 330.

[0083] The inverter 311, the diodes 321, 322, and the capacitor 331 form the second - stage boosting circuit of the charge - pump circuit 72.

[0084] The anode of the diode 321 is connected to one end of the capacitor 330, and the cathode is connected to one end of the capacitor 331. The power - supply voltage Vdd is applied to the anode of the diode 322, and the cathode is connected to one end of the capacitor 331. In addition, the other end of the capacitor 331 is connected to the output of the inverter 311.

[0085] Moreover, the voltage Vc2 at one end of the capacitor 331 of the second - stage boosting circuit is output as the voltage Vcp via the diode 323.

[0086] ==Operation of the charge - pump circuit 72==

[0087] Here, when the clock signal CLK is at a high level (hereinafter referred to as the "H" level), the output of the inverter 310 becomes a low level (hereinafter referred to as the "L" level), and the voltage Vc1 at one end of the capacitor 330 is charged via the diode 320. As a result, the voltage Vc1 at one end of the capacitor 330 is represented by Equation (1).

[0088] Vc1 = Vdd - Vf ··· (1)

[0089] Moreover, when the clock signal becomes the L level, the output of the inverter 310 becomes the H level (power - supply voltage Vdd), and the voltage Vc1 at one end of the capacitor 330 is represented by Equation (2).

[0090] Vc1 = 2×Vdd - Vf ··· (2)

[0091] In addition, at this timing, since the output of the inverter 311 is at the L level, the other end of the capacitor 331 becomes the ground voltage Vgnd (0V). As a result, the voltage Vc2 at one end of the capacitor 331 is represented by Equation (3).

[0092] Vc2 = 2×Vdd - 2×Vf ··· (3)

[0093] In addition, when the clock signal CLK becomes the H level, the output of the inverter 311 becomes the H level. Thus, the voltage Vc2 at one end of the capacitor 331 is represented by Equation (4).

[0094] Vc2 = 3×Vdd - 2×Vf ··· (4)

[0095] Moreover, the isolation circuit 73 is connected to the cathode of the diode 323. Thus, the voltage Vcp output from the diode 323 is represented by Equation (5).

[0096] Vc2 = 3 × Vdd - 3 × Vf ··· (5)

[0097] In addition, the charge pump circuit 72 according to the present embodiment is provided with a two-stage boosting circuit, but is not limited thereto. Any structure may be adopted as long as the voltage Vcp is a voltage capable of turning on the NMOS transistors M1 and M2.

[0098] <<<Operation of IPS 21>>>

[0099] Here, the output voltage Vout when the "switch X1" of the IPS 21 in the motor control device 10 described Figure 1 here is turned on and off will be described. Here, the battery 11 is connected in the normal direction, so the power supply voltage Vcc is applied to the terminal VCC, and the ground voltage is applied to the terminal OUT via the coil (not shown) of the motor 12. In addition, in the charge pump circuit 72, the period of the clock signal CLK is set to generate a desired voltage Vcp in a sufficiently short time.

[0100] Figure 5 is a diagram showing an example of the change in the output voltage Vout of the IPS 21. Here, it is assumed that an instruction signal Sb of "H" level for turning on the "switch X1" is input at time t0. In addition, it is assumed that an instruction signal Sc of "H" level for turning off the "switch X1" is input before time t0. Therefore, before time t0, through Figure 2 the NMOS transistor 120 of the discharge circuit 74 and the turned-on switches 121 and 122, the NMOS transistors M1 and M2 ("switch X1") are turned off.

[0101] First, at time t0, if the instruction signal Sb becomes "H" level and the instruction signal Sc becomes "L" level to turn on the "switch X1", the charge pump circuit 72 outputs the voltage Vcp, and the switches 121 and 122 are turned off.

[0102] If the charge pump circuit 72 outputs the voltage Vcp, the isolation circuit 73 applies voltages corresponding to the voltage Vcp to the gate lines L3 and L4, respectively. Here, the voltage of the source electrode S1 of the NMOS transistor M1 is the power supply voltage Vcc, and the voltage of the source electrode S2 of the NMOS transistor M2 is the ground voltage Vgnd (0V). Therefore, among the NMOS transistors M1 and M2, the NMOS transistor M2 is turned on first.

[0103] Then, if the voltage applied to the gate line L3 becomes higher than the threshold voltage of the NMOS transistor M1 by the threshold voltage of the NMOS transistor M1, which is the voltage of the source electrode S1 of the NMOS transistor M1, i.e., the power supply voltage Vcc, the NMOS transistor M1 turns on. As a result, at the time t1 when both the NMOS transistors M1 and M2 are on, the output voltage Vout rises to the power supply voltage Vcc. Here, for convenience, the voltage drop due to the on-resistance of the NMOS transistors M1 and M2 is not considered.

[0104] Moreover, for example, at the time t2, if the indication signal Sb becomes the "L" level and the indication signal Sc becomes the "L" level to turn off the "switch X1", the charge pump circuit 72 stops the output of the voltage Vcp, and the switches 121 and 122 turn on.

[0105] Here, in the present embodiment, the current value for discharging the gate capacitance of the NMOS transistor M1 by the NMOS transistor 120 is set to a sufficiently small value so as not to affect the NMOS transistor M1 when it is on. On the other hand, the switches 121 and 122 are switches with a sufficiently small on-resistance. Therefore, the gate capacitance of the NMOS transistor M2 is discharged via the switches 121 and 122 in a short time, and the NMOS transistor M2 immediately turns off. Then, if the NMOS transistor M2 turns off, the power supply voltage Vcc is cut off by the diode 61. As a result, for example, at the time t3, the output voltage Vout decreases to the ground voltage.

[0106] Therefore, at the time t3, the NMOS transistor M1 is in the on state, but by turning off the NMOS transistor M2, the "switch X1" provided between the terminal VCC and the terminal OUT turns off.

[0107] In the present embodiment, the NMOS transistors M1 and M2 constituting the "switch X1" are respectively driven by the electrically separated gate lines L3 and L4. Next, the change time of the output voltage Vout is compared between the case of using such a structure of the "switch X1" and the case of using a "switch" composed of two NMOS transistors with a common gate electrode.

[0108] <<< Structure of the IPS 25 according to the comparative example >>>

[0109] Figure 6 FIG. is an example showing the structure of the IPS 25 according to the comparative example. Similar to the IPS 21, the IPS 25 is configured to include an IC 55 in which a switch (described later) is formed and an IC 56 having a circuit for turning on and off the switch. In addition, Figure 2 in the IPS 21 and Figure 6 in the IPS 25, the elements and modules with the same reference numerals are the same.

[0110] Similar to IC 50, IC 55 includes NMOS transistors M1 and M2. Among them, the gate electrodes G1 and G2 of each of the NMOS transistors M1 and M2 are connected. In addition, in IC 55, the connections of the electrodes other than the gate electrodes G1 and G2 of the NMOS transistors M1 and M2 are the same as those in IC 50. Furthermore, hereinafter, in IC 55, the switch formed by the NMOS transistors M1 and M2 is referred to as "switch X2".

[0111] IC 56 is a circuit for turning on or off "switch X2", and is configured to include a power supply circuit 70, a control circuit 71, a charge pump circuit 72, a discharge circuit 77, and a resistor 85. Here, since the power supply circuit 70, the control circuit 71, and the charge pump circuit 72 of IC 56 are the same as the modules included in IC 51, the discharge circuit 77 and the resistor 85 will be described.

[0112] The discharge circuit 77 is a circuit for turning off the NMOS transistors M1 and M2 that form "switch X2", and is configured to include switches 125 and 126.

[0113] The switch 125 is provided between the gate line L6 connected to the gate electrodes of the NMOS transistors M1 and M2 and the ground line L5 connected to the terminal GND, and the switch 126 is provided between the gate line L6 and the load line L2.

[0114] Then, the switches 125 and 126 are turned on, for example, based on an indication signal Sc for turning off "switch X2". Therefore, the gate capacitances of the NMOS transistors M1 and M2 are discharged through the paths of the gate line L6, the switch 125, and the ground line L5 and the paths of the gate line L6, the switch 126, and the load line L2.

[0115] The resistor 85 is the gate resistor of the NMOS transistors M1 and M2, and has, for example, the same resistance value as Figure 2 the gate resistors of each of the NMOS transistors M1 and M2 of the IPS 21 of

[0116] <<<Operation of IPS 25 related to the comparative example>>>

[0117] Figure 7 is a diagram showing an example of the change in the output voltage Vout of IPS 25. In addition, here, Figure 5 the waveform of the output voltage Vout of the IPS 21 shown in

[0118] is shown as a comparison object for illustration. Figure 5 In addition, here, similar to

[0119] First, at time t0, when the indication signal Sb becomes the "H" level and the indication signal Sc becomes the "L" level to turn on the "switch X2", the charge pump circuit 72 outputs the voltage Vcp, and the switches 125 and 126 are turned off.

[0120] If the charge pump circuit 72 outputs the voltage Vcp, the voltage Vcp is applied to the gate line L6. Here, since the gate electrodes of the NMOS transistors M1 and M2 are common, the charge pump circuit 72 needs to drive a larger capacitance than the "switch X1" of the IPS 21. As a result, the "switch X2" is turned on at the timing of time t10, which is later than the time t1 when the above "switch X1" is turned on, and the output voltage Vout rises to the power supply voltage Vcc. Thus, since the period from time t0 to time t1 is shorter than the period from time t0 to time t10, the IPS 21 can turn on the "switch X1" in a shorter period.

[0121] In addition, for example, at time t2, if the indication signal Sb becomes the "L" level and the indication signal Sc becomes the "L" level to turn off the "switch X2", the charge pump circuit 72 stops outputting the voltage Vcp, and the switches 125 and 126 are turned on.

[0122] Here, in Figure 2 the IPS 21, the switches 121 and 122 only discharge the gate capacitance of the NMOS transistor M2, but Figure 6 the switches 125 and 126 of the IPS 25 need to discharge the gate capacitances of the NMOS transistors M1 and M2. As a result, the "switch X2" is turned on at the time t11, which is later than the time t3 when the "switch X1" is turned off, and the output voltage Vout drops to the ground voltage. Thus, since the period from time t2 to time t3 is shorter than the period from time t2 to time t11, the IPS 21 can turn on the "switch X1" in a shorter period.

[0123] ===Case where the battery 11 is reversely connected===

[0124] Figure 8 is a diagram for explaining the operation of the IPS 21 when the battery 11 is reversely connected. Additionally, for convenience, Figure 8 only shows Figure 2 a part of the modules of the IPS 21 related to the reverse connection operation among the multiple modules.

[0125] Figure 9It is a diagram showing a cross-section of the NMOS transistor 120. The NMOS transistor 120 is formed on the semiconductor substrate 400 of the IC 51 and includes a gate electrode 410, a source electrode 411, a drain electrode 412, and substrate electrodes 413 and 414 formed of a conductive material such as polysilicon.

[0126] In addition, in Figure 2 and Figure 8 , Figure 9 for convenience, the electrodes of the NMOS transistor 120 are given different labels, but the gate electrode 410 of the NMOS transistor 120 corresponds to the "gate electrode G3", and the source electrode 411 corresponds to the "source electrode S3". In addition, the drain electrode 412 corresponds to the "drain electrode D3", and the substrate electrodes 413 and 414 correspond to each of the "substrate electrode B3" and "substrate electrode Bx".

[0127] Inside the semiconductor substrate 400, an n-type drift region 420, a p-type well region 421, an n+-type source region 422, an n+-type drain region 423, an n-type gate region 424, a p+-type contact region 425, and an n+-type contact region 426 are formed..

[0128] The drift region 420 is a region containing an n-type impurity such as phosphorus, and the well region 421 is a p-type region formed on the surface side closer to the surface than the drift region 421. In addition, the drift region 420 corresponds to the "first region", and the well region 421 corresponds to the "second region".

[0129] The source region 422 and the drain region 423 are n+-type regions formed in a part of the well region 421, and an n-type gate region 424 is formed between the source region 422 and the drain region 423.

[0130] In addition, a contact region 425 containing a p-type impurity with a higher concentration than the well region 421 is formed on the surface side of the semiconductor substrate 400 in the well region 421. In addition, a diode 500 as a parasitic diode is formed between the p-type well region 421 and the n-type drift region 420.

[0131] In addition, a contact region 426 containing a high concentration of n-type impurity is formed on the surface side of the semiconductor substrate 400 in the n-type drift region 420.

[0132] In Figure 8 if the battery 11 is reversely connected, the power supply voltage Vcc of the positive electrode of the battery 11 is applied to the terminal OUT via the motor coil (not shown) of the motor 12 and the switch 31. On the other hand, the voltage of the negative electrode of the battery 11 is applied to the terminal VCC.

[0133] In such a state, the power supply voltage Vcc applied to the terminal OUT is applied to the source electrode S3, gate electrode G3, and substrate electrode B3 of the NMOS transistor 120 via the motor coil (not shown) of the motor 12, the load line L2, etc.

[0134] Here, since the NMOS transistor 120 is formed on the n-type semiconductor substrate 400, the substrate electrode Bx of the n-type semiconductor substrate 400 is connected to the power supply line L1 of the terminal VCC so that the highest potential, i.e., the power supply voltage Vcc, is usually applied.

[0135] However, in the state where the battery 11 is reversely connected, since the voltage of the negative electrode of the battery 11 is applied to the substrate electrode Bx, Figure 9 the parasitic diode shown, i.e., the diode 500, conducts. As a result, the voltages of the source electrode S3, gate electrode G3, and substrate electrode B3 of the NMOS transistor 120 are reduced from the power supply voltage Vcc to the "forward voltage Vfx" of the diode 500.

[0136] Therefore, even assuming that charge is stored in the gate capacitance of the NMOS transistor M1, the gate capacitance of the NMOS transistor M1 discharges via the gate line L3, the drain electrode D3 of the NMOS transistor 120, the diode 500, and the substrate electrode B3. In addition, in Figure 8 the path of the gate capacitance discharge of the NMOS transistor M1 is shown by a dashed line.

[0137] Furthermore, in the present embodiment, the threshold voltage of the NMOS transistor M1 is set to be higher than the "forward voltage Vfx" of the diode 500. Therefore, the gate of the NMOS transistor M1 discharges through such a path, whereby the NMOS transistor M1 is reliably turned off.

[0138] Therefore, if the battery 11 is reversely connected, the power supply voltage Vcc applied to the terminal OUT is output to the NMOS transistor M1 via the diode 61, but the turned-off NMOS transistor M1 is cut off. As a result, in the present embodiment, even when the battery 11 is reversely connected, the IPS 21 can appropriately protect the motor 12 and the like.

[0139] ===Summary===

[0140] As described above, the motor control device 10 of the present embodiment has been described. In the present embodiment, the gate lines L3 and L4 of the NMOS transistors M1 and M2 constituting the "switch X1" are electrically separated. Therefore, for example, as Figure 7 shown, the switching period of the "switch X1" becomes shorter.

[0141] In addition, in the present embodiment, the voltage Vcp is applied to the gate line L3 via the diodes 100 and 101, and is applied to the gate line L4 via the diodes 102 and 103. Therefore, the voltage Vcp output from one charge pump circuit 72 can be applied to the gate lines L3 and L4 in an electrically separated manner.

[0142] In addition, for example, a charge pump circuit may be provided on each of the gate lines L3 and L4. However, if such a structure is adopted, the circuit scale will increase. In the present embodiment, the separation circuit 73 is used, so that the voltage can be applied to the electrically separated gate lines L3 and L4 while maintaining a small circuit scale.

[0143] In addition, the diodes 130 and 131 of the present embodiment can prevent the voltage of the source electrode S1 from becoming too high with respect to the gate electrode G1 of the NMOS transistor M1, so that damage to the gate oxide film of the NMOS transistor M1 can be suppressed. In addition, the diodes 130 and 131 achieve the effect of pre-charging the gate capacitance of the gate electrode G1 of the NMOS transistor M1 before turning on the switch X1.

[0144] In addition, the diodes 132 and 133 of the present embodiment prevent the voltage of the source electrode S2 from becoming too high with respect to the gate electrode G2 of the NMOS transistor M2, so that damage to the gate oxide film of the NMOS transistor M2 can be suppressed.

[0145] In addition, the discharge circuit 74 discharges the gate capacitance of the NMOS transistor M2 based on the indication signal Sc, so that the NMOS transistor M2 is reliably turned off.

[0146] In addition, for example, the switch 121 of the discharge circuit 74 discharges the gate capacitance of the NMOS transistor M2 to the ground line L5. Therefore, for example, compared with the case where there is only the switch 121, the period for turning off the NMOS transistor M2 can be shortened.

[0147] In addition, resistors 80 and 81 are provided on each of the gate lines L3 and L4, so that the noise when the NMOS transistors M1 and M2 are turned on is suppressed.

[0148] In addition, the gate capacitance of the NMOS transistor M1 is discharged through the depletion-type NMOS transistor 120. The NMOS transistor 120 can reliably turn off the NMOS transistor M1 without using a complex circuit.

[0149] In addition, the NMOS transistor 120 is formed, for example, in a p-type well region 421 formed on an n-type drift region 420. With such a structure, when the battery 11 is reversely connected, the parasitic transistor diode 500 of the NMOS transistor 120 conducts. As a result, the gate capacitance of the NMOS transistor M1 can be discharged.

[0150] In addition, in the present embodiment, the threshold voltage of the NMOS transistor M1 is a value larger than the "forward voltage Vfx" of the diode 500. Therefore, if the gate capacitance of the NMOS transistor M1 is discharged via the diode 500, the NMOS transistor M1 is reliably turned off. Thus, even when the battery 11 is reversely connected, the IPS 21 can reliably protect the load.

[0151] The above-described embodiment is for facilitating the understanding of the present invention and is not for limiting and interpreting the present invention. In addition, without departing from the idea of the present invention, the present invention can be changed or improved, and the equivalent inventions of the present invention are also included within the scope of the present invention.

[0152] For example, in the present embodiment, it is assumed that the output voltage Vout of the IPS 21 is applied to the motor 12 as a load via the switch 31 of the ECU 20, but it is not limited thereto. For example, it can be assumed that the output voltage Vout of the IPS 21 is directly applied to the motor 12.

[0153] In addition, the IC 51 is an n-type semiconductor substrate, but for example, it can also be a p-type semiconductor substrate. In addition, when a p-type semiconductor substrate is used for the IC 51, if a semiconductor device with a double-well or triple-well structure is used so that a parasitic diode 500 is formed in the NMOS transistor 120, the same effect as the present embodiment can be obtained.

[0154] Reference Numeral Explanation

[0155] 10 Motor control device,

[0156] 11 Battery,

[0157] 12 Motor,

[0158] 20 ECU,

[0159] 21, 25 IPS,

[0160] 50, 51, 55, 56 IC,

[0161] 60, 61, 100 - 103, 130 - 133, 320 - 323, 500 Diode,

[0162] 70 Power supply circuit,

[0163] 71 Control circuit,

[0164] 72 Charge pump circuit,

[0165] 73 Separation circuit,

[0166] 74, 77 Discharge circuits,

[0167] 75, 76 Gate protection circuits,

[0168] 80 - 82, 85, 104, 105, 134 Resistors,

[0169] 120, M1, M2 NMOS transistors,

[0170] 121, 122, 125, 126 Switches,

[0171] 200, 400 Semiconductor substrates,

[0172] 220, 420 Drift regions,

[0173] 222, 421 Well regions,

[0174] 223, 422 Source regions,

[0175] 221, 423 Drain regions,

[0176] 224, 425, 426 Contact regions,

[0177] 230 Gate trench part,

[0178] 231 Oxide film,

[0179] 240 Insulating film,

[0180] 300 Oscillator,

[0181] 310, 311 Inverters,

[0182] 330, 331 Capacitors,

[0183] G1 - G3, 241, 410 Gate electrodes,

[0184] S1 - S3, 211, 411 Source electrodes,

[0185] D1 - D3, 210, 412 Drain electrodes,

[0186] B3, Bx, 212, 413, 414 Substrate electrodes,

[0187] 424 Gate region.

Claims

1. A semiconductor device, characterized in that, comprising: a first MOS transistor and a second MOS transistor, wherein the drain electrodes of the first MOS transistor and the second MOS transistor are connected in series between a first line to which a power supply voltage is applied and a second line to which a load is connected; a third line connected to the gate electrode of the first MOS transistor; a fourth line connected to the gate electrode of the second MOS transistor and electrically separated from the third line; and a third diode, an anode side of which is connected to the first line and a cathode side of which is connected to the third line.

2. The semiconductor device according to claim 1, characterized in that, comprising: a first diode that applies a specified voltage for turning on the first MOS transistor and the second MOS transistor to the third line; and a second diode that applies the specified voltage to the fourth line.

3. The semiconductor device according to claim 2, characterized in that, comprising: a charge pump circuit that outputs the specified voltage to the first diode and the second diode based on a first indication signal indicating conduction of the first MOS transistor and the second MOS transistor.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, comprising: a fourth diode, an anode side of which is connected to the second line and a cathode side of which is connected to the fourth line.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, comprising: a discharge circuit that discharges a gate capacitance of the second MOS transistor based on a second indication signal indicating cutoff of the second MOS transistor.

6. The semiconductor device according to claim 5, characterized in that, the discharge circuit includes: a first switch disposed between the fourth line and a fifth line on the ground side and turned on based on the second indication signal; and a second switch disposed between the fourth line and the second line and turned on based on the second indication signal.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, resistors are respectively provided on the third line and the fourth line.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, including a depletion-type third MOS transistor, in the third MOS transistor, a gate electrode and a source electrode are connected to the second line, and a drain electrode is connected to the third line.

9. The semiconductor device according to claim 8, characterized in that, the third MOS transistor is an NMOS transistor formed in a p-type second region formed in an n-type first region of a semiconductor substrate.

10. The semiconductor device according to claim 9, characterized in that, a threshold voltage of the first MOS transistor is larger than a forward voltage of a parasitic diode formed in the first region and the second region.

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