Display device

Abstract

The display device includes: a display panel including a front surface and a rear surface opposite to the front surface, an image is displayed at the front surface; a circuit board connected to the display panel and facing the rear surface of the display panel; and a heat dissipation layer between the rear surface of the display panel and the circuit board. The heat dissipation layer includes: a first heat dissipation sheet electrically connected to the circuit board; and a second heat dissipation sheet spaced apart from the first heat dissipation sheet in a direction along the display panel.

Description

Technical Field

[0001] The present disclosure relates to a display device and more particularly to a display device having improved electrostatic characteristics. Background Art

[0002] Rollable and / or foldable display panels (hereinafter referred to as "flexible display modules") are being developed. The flexible display module includes a flexible display panel and various functional components. The flexible display panel includes a base member, various functional layers on the base member, and pixels on the base member.

[0003] The rollable display device or the foldable display device includes a flexible display module. Summary of the invention

[0004] The present disclosure provides a display device having improved electrostatic characteristics.

[0005] An embodiment provides a display device, which includes a display panel that displays an image, a circuit board connected to the display panel and facing a rear surface of the display panel, and a heat dissipation layer between the rear surface of the display panel and the circuit board. The heat dissipation layer includes a first heat dissipation sheet electrically connected to the circuit board and a second heat dissipation sheet spaced apart from the first heat dissipation sheet.

[0006] According to one or more embodiments, the heat dissipation layer is divided into a first heat sink and a second heat sink spaced apart from each other, and the first heat sink is electrically connected to a ground line of a circuit board. Therefore, damage to the driving chip caused by static electricity introduced through the second heat sink can be reduced or effectively prevented, and the electrostatic characteristics of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other advantages of the present disclosure will become apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0008] Figure 1A is a perspective view showing an embodiment of a display device;

[0009] Figure 1B is an exploded perspective view showing an embodiment of a display device;

[0010] Figure 2A is along Figure 1B A cross-sectional view taken along line II' shown;

[0011] Figure 2B It is shown Figure 1B An exploded perspective view of an embodiment of a cover panel in FIG.

[0012] Figure 3 is along Figure 1B A cross-sectional view taken along line II-II' shown;

[0013] Figure 4A is a rear view of an embodiment showing a portion of a rear surface of a display device;

[0014] Figure 4B It is shown Figure 4A A rear view of an embodiment of the first heat sink, the second heat sink and the circuit board;

[0015] Figure 5A is along Figure 4A The cross-sectional view taken along line III-III' is a cross-sectional view showing an inverted state of the cross section;

[0016] Figure 5B It is shown Figure 5A An enlarged cross-sectional view of an embodiment of part BB in FIG.

[0017] Fig. 6A is a rear view of an embodiment showing a portion of a rear surface of a display device;

[0018] Figure 6B It is shown Fig. 6A A rear view of an embodiment of the first heat sink, the second heat sink and the circuit board;

[0019] Fig. 7A It is along Fig. 6A A cross-sectional view taken along line IV-IV' showing an inverted state of the cross section;

[0020] Figure 7B It is shown Fig. 7A An enlarged cross-sectional view of an embodiment of part CC in FIG.

[0021] Figure 8 is an exploded perspective view showing an embodiment of a display device;

[0022] Fig. 9 is along Figure 8 A cross-sectional view taken along line V-V' as shown; and

[0023] FIG. 10A to FIG. 10D is a cross-sectional view showing an embodiment of a manufacturing process of a display device. DETAILED DESCRIPTION

[0024] The present invention will be described more fully below with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0025] It will be understood that when an element or layer is referred to as being associated with another element, such as being on, connected to, or coupled to another element or layer, it may be directly on, directly connected to, or directly coupled to another element or layer, or there may be intervening elements or layers. Conversely, when an element or layer is referred to as being associated with another element, such as being directly on, directly connected to, or directly coupled to another element or layer, there may be no other elements or layers or intervening elements or layers.

[0026] The same reference numerals always denote the same elements. In the drawings, the thickness, proportion and size of components are exaggerated in order to effectively describe the technical contents.

[0027] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element." "At least one" should not be interpreted as limiting "one" or "a kind." "Or" means "and / or."

[0028] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present disclosure, the first element discussed below can be referred to as the second element.

[0029] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0030] For ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. are used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the accompanying drawings.

[0031] It should also be understood that when used in this specification, the terms "include" and / or "includes" specify the presence of the recited features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0033] Embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. As such, variations from the shapes illustrated are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific zone shapes as shown herein, but should include shape deviations, for example, caused by manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, sharp corners shown may be rounded. Therefore, the zones shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the zones and are not intended to limit the scope of the claims.

[0034] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1A is a perspective view showing an embodiment of a display device DD, and Figure 1B It is an exploded perspective view showing an embodiment of the display device DD. Figure 2A is along Figure 1B A cross-sectional view taken along line II' as shown, and Figure 2B It is shown Figure 1B An exploded perspective view of an embodiment of a cover panel CVP is shown.

[0036] refer to Figure 1A and Figure 1B , the display device DD may be activated in response to the electrical signal. The display device DD may be applied to various electronic devices. In an embodiment, for example, the display device DD may be applied to an electronic device such as a smart watch, a tablet computer, a notebook computer, a computer, or a smart TV.

[0037] The display device DD may display an image IM in a third direction DR3 through a display surface IS disposed in a plane substantially parallel to a plane defined by the first direction DR1 and the second direction DR2 crossing each other. The display surface IS through which the image IM is displayed may correspond to a front surface of the display device DD. The image IM may include a still image as well as a moving image.

[0038] In the present disclosure, the front (or upper) surface and the rear (or lower) surface of the member are defined relative to the direction of displaying the image IM. The front surface and the rear surface are opposite to each other along the third direction DR3, and the normal direction of each of the front surface and the rear surface is substantially parallel to the third direction DR3.

[0039] The distance between the front surface and the rear surface along the third direction DR3 may correspond to the thickness of the display device DD and its various components. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are opposite to each other, and thus, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to other directions.

[0040] The display device DD may sense an external input applied thereto from outside the display device DD. The external input may include various forms of input provided from outside the display device DD.

[0041] In an embodiment, for example, the external input may include an external input (e.g., a hovering input) near or approaching the display device DD at a predetermined distance and a touch input or a contact input by an input tool (e.g., a user's hand). In addition, the external input may include various forms such as force, pressure, temperature, and / or light.

[0042] The front surface of the display device DD may be divided into a transmission area TA (e.g., an image transmission area) and a frame area BZA. The image IM may be displayed through the transmission area TA. The transmission area TA may be referred to as a display area. The image IM may be viewed through the transmission area TA from the outside of the display device DD. In a top view (e.g., in a direction opposite to the third direction DR3), the transmission area TA may have a quadrilateral planar shape with rounded vertices. However, this is merely exemplary, and the transmission area TA may have various planar shapes and should not be particularly limited.

[0043] The border area BZA may be defined as being adjacent to the transmission area TA. The border area BZA may have a predetermined color. The image IM may not be displayed through the border area BZA, and the border area BZA may be referred to as a non-display area. In a top view, the border area BZA may surround the transmission area TA. Therefore, the planar shape of the transmission area TA may be defined by the shape of the border area BZA, however, this is merely exemplary. That is, the border area BZA may be arranged to be adjacent to only one side of the transmission area TA, or may be omitted from the display device DD. The display device DD may be implemented in various embodiments and should not be particularly limited.

[0044] like Figure 1B and Figure 2AAs shown, the display device DD may include a window WM, a display module DM, a cover panel CVP and a housing EDC. The display module DM may include a display panel DP, an input sensing unit ISP (eg, an input sensing layer) and an anti-reflection unit RPP (eg, an anti-reflection layer).

[0045] The window WM may include a transparent material through which the image IM may be transmitted. In an embodiment, for example, the window WM may include glass, sapphire, or plastic. The window WM is shown as a single layer, however, it should not be limited to this or thereby. The window WM may include a plurality of layers. Although not shown in the figure, the border area BZA of the display device DD may be obtained by providing (such as by printing) a material having a predetermined color on an area of ​​the window WM. As an example, the window WM may include a light blocking pattern WBM that defines the border area BZA. The light blocking pattern WBM may be a colored organic material layer and may be provided or formed by a coating method.

[0046] The display panel DP may be a light-emitting display panel, however, it should not be particularly limited. In an embodiment, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and / or quantum rods. Hereinafter, the organic light-emitting display panel will be described as a representative example of the display panel DP.

[0047] The input sensing unit ISP may be directly disposed on the display panel DP. According to an embodiment, the input sensing unit ISP may be disposed or formed on the display panel DP through a continuous process. That is, when the input sensing unit ISP is directly disposed on the display panel DP, an adhesive film (e.g., an intermediate layer) may not be disposed between the input sensing unit ISP and the display panel DP.

[0048] The display panel DP may generate an image IM, and the input sensing unit ISP may obtain coordinate information about the above-mentioned external input (eg, a touch event).

[0049] The anti-reflection unit RPP can reduce the reflectivity of external light incident thereon from the outside of the window WM. The anti-reflection unit RPP may include a retarder and a polarizer. The retarder may be a thin film type or a liquid crystal coating type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may be a thin film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a predetermined orientation. The retarder and the polarizer may be implemented as one polarizing film. The anti-reflection unit RPP may also include a protective film disposed above or below the polarizing film.

[0050] The anti-reflection unit RPP may be disposed on the input sensing unit ISP. That is, the anti-reflection unit RPP may be disposed between the input sensing unit ISP and the window WM facing each other. The input sensing unit ISP, the anti-reflection unit RPP, and the window WM may be respectively connected to each other by intervening members (e.g., adhesive members). The first adhesive film AF1 (e.g., a first adhesive layer) may be disposed between the input sensing unit ISP and the anti-reflection unit RPP, and the second adhesive film AF2 (e.g., a second adhesive layer) may be disposed between the anti-reflection unit RPP and the window WM. Therefore, the anti-reflection unit RPP may be connected to the input sensing unit ISP by the first adhesive film AF1, and the window WM may be connected to the anti-reflection unit RPP by the second adhesive film AF2.

[0051] In an embodiment, for example, the first adhesive film AF1 and the second adhesive film AF2 may be an optically clear adhesive ("OCA") film including OCA. However, the first adhesive film AF1 and the second adhesive film AF2 should not be limited thereto or thereby, and may include a commonly used adhesive. In an embodiment, for example, the first adhesive film AF1 and the second adhesive film AF2 may include an optically clear resin ("OCR") and / or a pressure sensitive adhesive ("PSA") film.

[0052] The display module DM may generate and / or display an image IM in response to an electrical signal, and may transmit / receive information about an external input. The display module DM may include an active area AA and a peripheral area NAA. The active area AA may be defined as an area through which an image IM provided from the display module DM is transmitted.

[0053] The peripheral area NAA may be defined as being adjacent to the active area AA. In an embodiment, for example, in a top view, the peripheral area NAA may surround the active area AA, however, the peripheral area NAA may be defined as various shapes and should not be particularly limited. According to an embodiment, the active area AA of the display module DM may correspond to at least a portion of the transmissive area TA.

[0054] The display module DM may further include a circuit board MCB and a driving chip DIC. The circuit board MCB may be electrically connected to the display panel DP. An electrical signal may be provided from the circuit board MCB to the display panel DP to drive the display panel DP and display the image IM. The circuit board MCB may include a plurality of driving elements. The driving element may include a circuit unit that drives the display panel DP.

[0055] The driving chip DIC may be mounted on the display panel DP. An electrical signal may be provided from or through the driving chip DIC to drive the display panel DP and display the image IM. In this case, a portion of the display panel DP on which the driving chip DIC is mounted may be bent to face the rear surface of the display module DM.

[0056] The driving chip DIC may include driving elements, such as a data driving circuit, that drive the pixels of the display panel DP. Figure 1B The structure in which the driving chip DIC is mounted on the display panel DP is shown, however, it should not be limited to or thereby. In an embodiment, for example, the driving chip DIC may be mounted on a flexible circuit film FCB disposed between the display panel DP and the circuit board MCB (refer to Figure 8 and Fig. 9 ). The following will refer to Figure 8 and Fig. 9 The structure in which the driver chip DIC is mounted on the flexible circuit film FCB is described.

[0057] The input sensing unit ISP may be electrically connected to the circuit board MCB, however, it should not be limited thereto or thereby. That is, the display module DM may further include an independent flexible circuit film FCB to electrically connect the input sensing unit ISP to the circuit board MCB.

[0058] The cover panel CVP may be disposed on the rear surface of the display panel DP. The cover panel CVP may include a heat dissipation layer MS. The heat dissipation layer MS may effectively dissipate heat generated by the display panel DP.

[0059] The heat dissipation layer MS may include a first heat dissipation sheet MS1 (e.g., a first heat dissipation member) and a second heat dissipation sheet MS2 (e.g., a second heat dissipation member). The first heat dissipation sheet MS1 and the second heat dissipation sheet MS2 may be disposed to be spaced apart from each other by a predetermined distance in a direction along the display panel DP. The circuit board MCB faces the display panel DP, and the first heat dissipation sheet MS1 is located between the circuit board MCB and the display panel DP.

[0060] As an example, the first heat sink MS1 and the second heat sink MS2 may include the same conductive material, such as the same metal material. In an embodiment, for example, the first heat sink MS1 and the second heat sink MS2 may include a metal material having high thermal conductivity, such as copper (Cu), aluminum (Al), gold (Au), etc., however, it should not be limited to this or thereby. That is, the first heat sink MS1 and the second heat sink MS2 may include metal materials different from each other. In addition, the first heat sink MS1 may include a material having a higher electrical conductivity than the material of the second heat sink MS2. In an embodiment, for example, the first heat sink MS1 may include gold, and the second heat sink MS2 may include copper.

[0061] The cover panel CVP may further include a first layer PF and a second layer CH, each of which is disposed between the heat dissipation layer MS and the display panel DP. The first layer PF may be a polyimide ("PI") film. The first layer PF may be a base member or layer on which the first heat sink MS1 and the second heat sink MS2 are disposed. Adhesive layers may also be disposed between the first heat sink MS1 and the second heat sink MS2 and the first layer PF, respectively. Therefore, the first heat sink MS1 and the second heat sink MS2 may each be attached to the first layer PF by an adhesive layer. The first layer PF may be common to each of the first heat sink MS1 and the second heat sink MS2.

[0062] The second layer CH may be a shock absorbing layer. The second layer CH may be disposed on the rear surface of the display panel DP and may improve the shock resistance of the display device DD. In an embodiment, the second layer CH is disposed between the display panel DP and the first layer PF, however, it should not be limited thereto or thereby. In an embodiment, the second layer CH may be disposed between the first layer PF and the heat dissipation layer MS.

[0063] According to the present disclosure, since the heat dissipation layer MS is disposed on the rear surface of the display panel DP, heat generated by the display panel DP may be easily dissipated to the outside of the display device DD through the heat dissipation layer MS.

[0064] In an embodiment, at least one of the first layer PF and the second layer CH may be omitted, or another functional layer may be added to the cover panel CVP in addition to the first layer PF and the second layer CH.

[0065] The cover panel CVP may be fixed to the rear surface of the display panel DP by an adhesive layer. The adhesive layer may include a pressure sensitive adhesive ("PSA"), an optically clear adhesive ("OCA"), or an optically clear resin ("OCR").

[0066] The housing EDC may house the display module DM. The housing EDC may be connected to the window WM and may define the exterior of the display device DD. The housing EDC may absorb impact applied thereto from the exterior of the display device DD and may prevent impurities / moisture from entering the display module DM to protect components housed in the housing EDC. In an embodiment, the housing EDC may be an assembly of a plurality of separately disposed housing members.

[0067] Figure 3 is along Figure 1B A cross-sectional view taken along line II-II' is shown.

[0068] Reference Figure 3, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layers, semiconductor layers, and conductive layers may be disposed or formed by a coating or deposition process. The insulating layers, semiconductor layers, and conductive layers may be selectively patterned by a photolithography process. The semiconductor patterns, conductive patterns, and signal lines included in the circuit element layer 110-2 and the display element layer 110-3 may be disposed or formed on the base layer 110-1. An encapsulation layer 110-4 may be disposed or formed to cover the display element layer 110-3.

[0069] The base layer 110-1 may include a synthetic resin film. The synthetic resin film may include a heat-curable resin. The base layer 110-1 may have a multilayer structure. In an embodiment, for example, the base layer 110-1 may have a three-layer structure of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material used for the synthetic resin layer should not be particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. The base layer 110-1 may include a glass substrate or an organic / inorganic composite substrate.

[0070] At least one inorganic layer may be disposed or formed on the upper surface of the base layer 110-1. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be disposed or formed of a plurality of layers. The inorganic layer may form a barrier layer and / or a buffer layer BFL. Figure 3 , the display panel DP may include a buffer layer BFL.

[0071] The buffer layer BFL may increase a coupling force between the base layer 110 - 1 and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer stacked on each other.

[0072] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, however, it should not be limited thereto or thereby. The semiconductor pattern may include amorphous silicon or an oxide semiconductor.

[0073] like Figure 3As shown, the first semiconductor pattern of the first transistor 111 and the second semiconductor pattern of the second transistor 112 may be disposed on the buffer layer BFL. The first semiconductor pattern may include a first source S1, a first channel A1, and a first drain D1, and the second semiconductor pattern may include a second source S2, a second channel A2, and a second drain D2. In a direction along the base layer 110-1, the first channel A1 may be disposed between the first source S1 and the first drain D1, and the second channel A2 may be disposed between the second source S2 and the second drain D2. Figure 3 A portion of the connection signal line SCL is shown Although not shown in the drawing, the connection signal line SCL may be connected to the second drain D2 of the second transistor 112 in a plan view.

[0074] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover a plurality of semiconductor patterns. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may have a silicon oxide layer with a single-layer structure. The first insulating layer 10 and the insulating layer of the circuit element layer 110-2 described later may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0075] The first gate G1 of the first transistor 111 and the second gate G2 of the second transistor 112 may be disposed on the first insulating layer 10. The first gate G1 and the second gate G2 may overlap or correspond to the first channel A1 and the second channel A2, respectively.

[0076] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the first gate G1 and the second gate G2. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multilayer structure. In an embodiment, the second insulating layer 20 may have a silicon oxide layer of a single layer structure.

[0077] The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the second gate G2 of the second transistor 112. A portion of the second gate G2 and a portion of the upper electrode UE overlapping the portion of the second gate G2 may form a portion of a capacitor.

[0078] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE. In an embodiment, the third insulating layer 30 may have a silicon oxide layer of a single-layer structure. The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a first contact hole CNT-1 defined to extend through each of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0079] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may have a silicon oxide layer of a single-layer structure. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. The second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CNT-2 defined to extend through each of the fourth insulating layer 40 and the fifth insulating layer 50.

[0080] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connection electrode CNE2. The sixth insulating layer 60 may be an organic layer. The first electrode AE ​​may be disposed on the sixth insulating layer 60. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a third contact hole CNT-3 defined to extend through the sixth insulating layer 60.

[0081] The opening 70 -OP may be defined to extend through the pixel defining layer 70 . The first electrode AE ​​may be exposed to the outside of the pixel defining layer 70 at or through the opening 70 -OP of the pixel defining layer 70 .

[0082] Effective area AA (reference Figure 1B ) may include a plurality of light-emitting areas PXA (e.g., a plurality of light-emitting areas PXA) and a plurality of non-light-emitting areas NPXA (e.g., a plurality of non-light-emitting areas NPXA) defined adjacent to the light-emitting areas PXA. In a top view, the non-light-emitting areas NPXA may surround the light-emitting areas PXA. Each of the light-emitting areas PXA may be defined to correspond to a portion of the first electrode AE ​​exposed to the outside of the pixel defining layer 70 through the opening 70-OP.

[0083] The hole control layer HCL may be generally disposed in the light emitting area PXA and the non-light emitting area NPXA. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer. The light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in an area corresponding to the opening 70-OP. That is, the light emitting layer EML may be disposed or formed in each pixel of the display panel DP after being divided into a plurality of parts.

[0084] The electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be disposed or formed together in the light emitting region PXA, such as by using an open mask.

[0085] The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have an integral shape and may be commonly disposed in each light emitting region PXA.

[0086] The capping layer 80 may be disposed on the second electrode CE. The capping layer 80 may include an organic material. The capping layer 80 may protect the second electrode CE from the process of setting the display device DD (such as a sputtering process) and may improve the light emitting efficiency of the light emitting element 114 or the display element. In an embodiment, the capping layer 80 may be omitted.

[0087] The encapsulation layer 110-4 may be disposed on the display element layer 110-3. The encapsulation layer 110-4 may include a first inorganic layer 91, an organic layer 92, and a second inorganic layer 93. The first inorganic layer 91 and the second inorganic layer 93 may protect the display element layer 110-3 from moisture and oxygen, and the organic layer 92 may protect the display element layer 110-3 from impurities such as dust particles. The first inorganic layer 91 and the second inorganic layer 93 may include one of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. In an embodiment, the first inorganic layer 91 and the second inorganic layer 93 may include a titanium oxide layer or an aluminum oxide layer. The organic layer 92 may include an acrylic-based organic layer, however, it should not be particularly limited.

[0088] The input sensing unit ISP may include a base insulating layer 120-1, a first conductive layer 120-2, a sensing insulating layer 120-3 (eg, an intermediate insulating layer), a second conductive layer 120-4, and a cover insulating layer 120-5. After the display panel DP is provided or formed, the input sensing unit ISP may be provided or formed through a continuous process, however, it should not be limited thereto or thereby.

[0089] The base insulating layer 120-1 may be directly disposed on the display panel DP. In an embodiment, for example, the base insulating layer 120-1 may contact (e.g., form an interface) with the second inorganic layer 93. The base insulating layer 120-1 may have a single-layer structure or a multi-layer structure. In an embodiment, the base insulating layer 120-1 may be omitted. In an embodiment, the base insulating layer 120-1 may be disposed or formed as a separate base layer, and the separate base layer may be coupled to the display panel DP through an intervening member (such as an adhesive member).

[0090] Each of the first conductive layer 120-2 and the second conductive layer 120-4 may have a single layer structure or a multilayer structure of layers stacked along the third direction DR3. The conductive layer having a single layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, their alloys, or a combination thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide ("ZnO"), indium tin zinc oxide ("ITZO"). In addition, the transparent conductive layer may include a conductive polymer (e.g., poly (3,4-ethylenedioxythiophene) ("PEDOT")), a metal nanowire, and graphene.

[0091] The conductive layer having a multi-layer structure may include a plurality of metal layers. The metal layer may have a three-layer structure of titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0092] Each of the first conductive layer 120-2 and the second conductive layer 120-4 may include a conductive pattern forming a sensing electrode. The input sensing unit ISP may obtain information on an external input based on a capacitance change between the sensing electrodes.

[0093] The sensing insulating layer 120-3 may be disposed between the first conductive layer 120-2 and the second conductive layer 120-4 and may cover the first conductive layer 120-2. A portion of the second conductive layer 120-4 may be electrically connected to a portion of the first conductive layer 120-2 through a contact hole defined as extending through the sensing insulating layer 120-3. A covering insulating layer 120-5 may be disposed on the sensing insulating layer 120-3 and may cover the second conductive layer 120-4.

[0094] In an implementation, at least one of the sensing insulating layer 120-3 and the capping insulating layer 120-5 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0095] In an embodiment, at least one of the sensing insulating layer 120-3 and the cover insulating layer 120-5 may include an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0096] Figure 4A is a rear view showing an embodiment of a part of the rear surface of the display device DD, and Figure 4B It is shown Figure 4A A rear view of an embodiment of the first heat sink MS1 and the second heat sink MS2 and the circuit board MCB is shown. Figure 5A is along Figure 4A A cross-sectional view taken along line III-III', and Figure 5B It is shown Figure 5A An enlarged cross-sectional view of an embodiment of portion BB is shown.

[0097] Reference Figure 4A , Figure 4B , Figure 5A and Figure 5B The cover panel CVP may be disposed on a rear surface of the display panel DP. The rear surface is opposite to the front surface of the display panel DP along a third direction DR3. The cover panel CVP may include a heat dissipation layer MS, a first layer PF, and a second layer CH.

[0098] The heat dissipation layer MS may include a first heat dissipation fin MS1 ​​and a second heat dissipation fin MS2. The first heat dissipation fin MS1 ​​and the second heat dissipation fin MS2 may be disposed to be spaced apart from each other along a plane defined by a first direction DR1 and a second direction DR2 intersecting each other. In an embodiment, the first heat dissipation fin MS1 ​​and the second heat dissipation fin MS2 may be spaced apart from each other by a first distance dt1. The first distance dt1 should not be particularly limited. A gap GP may be defined between the first heat dissipation fin MS1 ​​and the second heat dissipation fin MS2. Figure 4A , for example, in a plan view, the gap GP may not overlap with the driving chip DIC. In a curved display panel DP, the first heat sink MS1 may be arranged to overlap or correspond to the driving chip DIC and the circuit board MCB. In an embodiment, the first heat sink MS1 may have a planar shape corresponding to the circuit board MCB. That is, the first heat sink MS1 may have an amorphous shape, and the shape of the first heat sink MS1 should not be particularly limited.

[0099] The display panel DP may include a flat portion FP and a bent portion BP at which the display panel DP is bendable. The flat portion FP extends from the bent portion BP. The flat portion FP may be a portion of the display panel DP that is not bendable or remains flat when the bent portion BP is bent. The bent portion BP may be bent to face the flat portion FP along a third direction DR3 ( Figure 5A ). The driving chip DIC may be mounted on the bent portion BP of the display panel DP. The display panel DP bent at the bent portion BP disposes the bent portion BP to face the flat portion FP.

[0100] Reference Figure 4A , the first heat sink MS1 may be arranged to overlap the driving chip DIC and the curved portion BP of the display panel DP. The uncurved or flat display panel DP ( Figure 4B ) The driving chip DIC and the circuit board MCB are arranged so as not to overlap with the heat dissipation layer MS. The curved display panel DP ( Figure 4A ) The driving chip DIC and the circuit board MCB are arranged to face the heat dissipation layer MS.

[0101] Curved display panel DP( Figure 4A ) The second heat sink MS2 is arranged to not overlap with the driving chip DIC and the bent portion BP of the display panel DP. Figure 4A The structure in which the second heat sink MS2 partially overlaps the circuit board MCB is shown, however, the second heat sink MS2 and the circuit board MCB should not be limited to this structure. In an embodiment, for example, the curved display panel DP ( Figure 4A ) The second heat sink MS2 can be arranged to not overlap with the circuit board MCB.

[0102] The display device DD may further include a conductive adhesive film CAF (e.g., a conductive adhesive layer) to attach the first heat sink MS1 to the circuit board MCB. The circuit board MCB may be fixed to the rear surface of the first heat sink MS1 by the conductive adhesive film CAF. Some wires or signal lines (e.g., Figure 5B The ground line GRL shown in FIG. 1 may be electrically connected to the first heat sink MS1 via the conductive adhesive film CAF. That is, the circuit board MCB may be electrically connected to the first heat sink MS1 and may form an electrostatic path. The second heat sink MS2 may be disposed to be spaced apart from the first heat sink MS1 (e.g., electrically insulated from the first heat sink MS1), and therefore, the second heat sink MS2 may be electrically insulated from the circuit board MCB electrically connected to the first heat sink MS1.

[0103] The conductive adhesive film CAF may be a double-sided adhesive film. Therefore, the conductive adhesive film CAF may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB. Figure 5A and Figure 5B , the display panel DP bent at the bent portion BP disposes the rear surface of the first heat sink MS1 to face the rear surface of the circuit board MCB.

[0104] like Figure 5B As shown, the conductive adhesive film CAF may include a first conductive film CF1 (e.g., a first conductive pattern), a first conductive adhesive CA1 (e.g., a first conductive adhesive pattern), and a second conductive adhesive CA2 (e.g., a second conductive adhesive pattern). The first conductive film CF1 may include a conductive fabric or a metal film as its base film. The first conductive adhesive CA1 may be disposed between the first conductive film CF1 and the rear surface of the first heat sink MS1, and the second conductive adhesive CA2 may be disposed between the first conductive film CF1 and the rear surface of the circuit board MCB.

[0105] Each of the first conductive adhesive CA1 and the second conductive adhesive CA2 may include a conductive adhesive material. In an embodiment, for example, each of the first conductive adhesive CA1 and the second conductive adhesive CA2 may be a film provided or formed by distributing metal particles of gold, silver, platinum, nickel, copper, or carbon in a synthetic resin. The synthetic resin may include a material of epoxy, silicon, polyimide, or polyurethane.

[0106] The conductive adhesive film CAF may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB by the first conductive adhesive CA1 and the second conductive adhesive CA2, respectively.

[0107] The circuit components CM such as a control chip, a plurality of passive components, a plurality of active components, etc. may be arranged by being mounted on a circuit board MCB. The circuit board MCB may include a display panel DP ( Figure 4A , Figure 5A and Figure 5B ) in the rear surface of the first heat sink MS1 (for example, in Figure 4B The upper surface of the circuit board MCB (e.g. Figure 4A ) may be opposite to the rear surface of the circuit board MCB.

[0108] The circuit board MCB may include a ground line GRL, a first cover layer CVL1, a second cover layer CVL2, and a step difference compensation film SCF (e.g., a step difference compensation pattern). The first cover layer CVL1 and the second cover layer CVL2 may include an insulating material. The upper surface of the circuit board MCB may be defined by the first surface of the first cover layer CVL1, however, it should not be limited to or defined thereby. In addition to the first cover layer CVL1 and the second cover layer CVL2, the circuit board MCB may also include a plurality of cover layers. In this case, the upper surface of the circuit board MCB may be defined by the upper surface of the outermost cover layer among the cover layers (e.g., the cover layer farthest from the flat portion FP of the display panel DP). The ground line GRL may be disposed on the second surface of the first cover layer CVL1 opposite to the first surface of the first cover layer CVL1. The ground line GRL may be a copper wire and may receive a ground voltage.

[0109] The ground wire GRL may be covered by the second cover layer CVL2. The second cover layer CVL2 may be provided with a first opening OP1 and a second opening OP2, through which a portion of the ground wire GRL is exposed. That is, each of the first opening OP1 and the second opening OP2 is defined by the second cover layer CVL2, and a portion of the ground wire GRL is exposed to the outside of the second cover layer CVL2 to define an exposed portion of the ground wire GRL. In addition to the ground wire GRL, other wires or signal wires may be provided on the second surface of the first cover layer CVL1, however, for ease of explanation, in Figure 5B Other wires or signal lines are omitted.

[0110] The step difference compensation film SCF may be disposed to correspond to each of the first opening OP1 and the second opening OP2, and may be electrically connected to the ground line GRL at the first opening OP1 and the second opening OP2. The step difference compensation film SCF forms an interface with both the conductive adhesive film CAF and the exposed portion of the ground line GRL. In addition, the step difference compensation film SCF may compensate for the step difference occurring in the second cover layer CVL2 caused by the first opening OP1 and the second opening OP2.

[0111] The step difference compensation film SCF may include a second conductive film CF2 (e.g., a second conductive pattern) and a third conductive adhesive CA3 (e.g., a third conductive adhesive pattern). The second conductive film CF2 may be used as a base film of the step difference compensation film SCF. The second conductive film CF2 may have a thickness sufficient to compensate for the step difference occurring in the second cover layer CVL2. The second conductive film CF2 may include a material having conductivity. In an embodiment, for example, the second conductive film CF2 may include the same material as the first conductive film CF1. The third conductive adhesive CA3 may be disposed between the second conductive film CF2 and the ground line GRL. The third conductive adhesive CA3 may include a conductive adhesive material. In an embodiment, for example, the third conductive adhesive CA3 may include the same material as the first conductive adhesive CA1 and the second conductive adhesive CA2 or be formed of the same material as the first conductive adhesive CA1 and the second conductive adhesive CA2.

[0112] In an embodiment, the circuit board MCB may further include a protective metal layer PL, which covers the portion of the ground line GRL exposed through the first opening OP1 and the second opening OP2. The protective metal layer PL may be used to reduce or effectively prevent the ground line GRL from being oxidized or corroded. In an embodiment, for example, the protective metal layer PL may include an oxidation-resistant and corrosion-resistant metal material, such as gold (Au).

[0113] In the case where the protective metal layer PL is provided, the step difference compensation film SCF may be attached to the protective metal layer PL through the third conductive adhesive CA3. When the protective metal layer PL is omitted, the step difference compensation film SCF may be directly attached to the ground line GRL.

[0114] The second conductive film CF2 of the step difference compensation film SCF may be attached to the second conductive adhesive CA2 of the conductive adhesive film CAF. Accordingly, the conductive adhesive film CAF may be electrically connected to the ground line GRL through the step difference compensation film SCF. Therefore, the first heat sink MS1 and the ground line GRL are electrically connected to each other through the conductive adhesive film CAF together with the step difference compensation film SCF, and therefore, an electrostatic path may be set or formed between the cover panel CVP and the circuit board MCB.

[0115] Therefore, when static electricity is generated, the static electricity can be dissipated through the static electricity path, and therefore, damage to the circuit component CM mounted on the circuit board MCB or the driver chip DIC mounted on the display panel DP due to static electricity can be reduced or effectively prevented. In particular, since the first heat sink MS1 is separated from the second heat sink MS2 (for example, electrically insulated from the second heat sink MS2), damage to the circuit component CM mounted on the circuit board MCB or the driver chip DIC mounted on the display panel DP due to static electricity introduced through the second heat sink MS2 can be reduced or effectively prevented.

[0116] like Figure 5B As shown, the second layer CH of the cover panel CVP may include a buffer layer CH1 and an embossed structure layer CH2 (e.g., an embossed layer). The buffer layer CH1 is disposed facing the display panel DP, and the embossed structure layer CH2 is located between the buffer layer CH1 and the display panel DP. The buffer layer CH1 may include a porous structure having elasticity. The buffer layer CH1 may include a synthetic resin foam. In an embodiment, for example, the buffer layer CH1 may include at least one of acrylonitrile butadiene styrene copolymer ("ABS"), polyurethane ("PU"), polyethylene ("PE"), ethylene vinyl acetate copolymer ("EVA"), and polyvinyl chloride ("PVC").

[0117] The embossed structure layer CH2 may include a plurality of protrusions protruding in the third direction DR3. The protrusions may have an embossed shape defined by peaks and valleys alternating with each other in the direction along the display panel DP. The protrusions may protrude toward the display panel DP. When viewed in a cross section, each protrusion may have a semicircular shape. However, each protrusion may have a triangular shape and should not be particularly limited. The embossed structure layer CH2 may include an elastic material. Accordingly, the embossed structure layer CH2 and the buffer layer CH1 may improve the impact resistance of the cover panel CVP.

[0118] In an embodiment, the embossed structure layer CH2 may include a light blocking material. Since the light blocking material is included, the embossed structure layer CH2 may reduce or effectively prevent components disposed on the rear surface of the display panel DP from being visible from the outside of the display panel DP.

[0119] Fig. 6A is a rear view showing an embodiment of a part of the rear surface of the display device DD, and Figure 6B It is shown Fig. 6A A rear view of an embodiment of the first heat sink MS1 and the second heat sink MS2 and the circuit board MCB is shown. Fig. 7A It is along Fig. 6A A cross-sectional view taken along line IV-IV' as shown, and Figure 7B It is shown Fig. 7AAn enlarged cross-sectional view of an embodiment of portion CC is shown. Fig. 6A , Figure 6B , Fig. 7A and Figure 7B In the same reference numerals, FIG. 4A to FIG. 5B and therefore will be FIG. 6A to FIG. 7B Detailed description of the same elements is omitted.

[0120] Reference FIG. 6A to FIG. 7B The cover panel CVP may be disposed on the rear surface of the display panel DP. The cover panel CVP may include a heat dissipation layer MS, a first layer PF, and a second layer CH.

[0121] The heat dissipation layer MS may include a first heat dissipation fin MS1 ​​and a second heat dissipation fin MS2. The first heat dissipation fin MS1 ​​and the second heat dissipation fin MS2 may be disposed to be spaced apart from each other along a plane defined by a first direction DR1 and a second direction DR2 intersecting each other. In an embodiment, the first heat dissipation fin MS1 ​​and the second heat dissipation fin MS2 may be disposed to be spaced apart from each other by a first distance dt1. The first distance dt1 should not be particularly limited. A gap GP may be defined between the first heat dissipation fin MS1 ​​and the second heat dissipation fin MS2. Reference Fig. 6A , for example, in a plan view, the gap GP may not overlap with the driving chip DIC.

[0122] In the curved display panel DP( Fig. 6A ), the first heat sink MS1 may be arranged to overlap or correspond to the driving chip DIC and the circuit board MCB. In an embodiment, the first heat sink MS1 may have a planar quadrilateral shape and may partially overlap the circuit board MCB. The first heat sink MS1 may be arranged to overlap the driving chip DIC and the bent portion BP of the display panel DP.

[0123] Curved display panel DP( Fig. 6A ) The second heat sink MS2 is arranged to not overlap with the driving chip DIC and the bent portion BP of the display panel DP. Fig. 7A The display panel DP is bent and the second heat sink MS2 is disposed to partially overlap the circuit board MCB, however, it should not be limited thereto or thereby. In an embodiment, for example, the bent display panel DP may dispose the second heat sink MS2 to not overlap the circuit board MCB.

[0124] The display device DD may further include a first conductive adhesive film CAF1 (e.g., a first conductive adhesive layer) and a second conductive adhesive film CAF2 (e.g., a second conductive adhesive layer). The first conductive adhesive film CAF1 faces the display panel DP, and the first heat sink MS1 is located between the first conductive adhesive film CAF1 and the display panel DP, and the second conductive adhesive film CAF2 faces the display panel DP, and the second heat sink MS2 is located between the second conductive adhesive film CAF2 and the display panel DP.

[0125] The circuit board MCB may be fixed to the rear surface of the first heat sink MS1 by the first conductive adhesive film CAF1, and may be fixed to the rear surface of the second heat sink MS2 by the second conductive adhesive film CAF2. Figure 7B The ground line GRL shown in the figure can be electrically connected to the first heat sink MS1 via the first conductive adhesive film CAF1. That is, the circuit board MCB can be electrically connected to the first heat sink MS1 and an electrostatic path can be formed. The second heat sink MS2 can be electrically connected to the ground line GRL of the circuit board MCB through the second conductive adhesive film CAF2. That is, the circuit board MCB can be electrically connected to the second heat sink MS2 to form an electrostatic path.

[0126] Each of the first conductive adhesive film CAF1 and the second conductive adhesive film CAF2 may be a double-sided adhesive film. Therefore, the first conductive adhesive film CAF1 may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB, and the second conductive adhesive film CAF2 may be attached to each of the rear surface of the second heat sink MS2 and the rear surface of the circuit board MCB.

[0127] like Figure 7B As shown, the first conductive adhesive film CAF1 may include a first conductive film CF1-1, a first conductive adhesive CA1-1, and a second conductive adhesive CA2-1. The first conductive adhesive CA1-1 may be disposed between the first conductive film CF1-1 and the rear surface of the first heat sink MS1, and the second conductive adhesive CA2-1 may be disposed between the first conductive film CF1-1 and the rear surface of the circuit board MCB. Accordingly, the first conductive adhesive film CAF1 may be attached to each of the rear surface of the first heat sink MS1 and the rear surface of the circuit board MCB by the first conductive adhesive CA1-1 and the second conductive adhesive CA2-1.

[0128] The second conductive adhesive film CAF2 may include a first conductive film CF1-2, a first conductive adhesive CA1-2, and a second conductive adhesive CA2-2. The first conductive adhesive CA1-2 may be disposed between the first conductive film CF1-2 and the rear surface of the second heat sink MS2, and the second conductive adhesive CA2-2 may be disposed between the first conductive film CF1-2 and the rear surface of the circuit board MCB. Accordingly, the second conductive adhesive film CAF2 may be attached to each of the rear surface of the second heat sink MS2 and the rear surface of the circuit board MCB by the first conductive adhesive CA1-2 and the second conductive adhesive CA2-2.

[0129] The first conductive adhesive film CAF1 and the second conductive adhesive film CAF2 may be disposed to correspond to the gap GP between the first heat sink MS1 and the second heat sink MS2, and may be separated from each other (e.g., disconnected from each other) by the gap GP. In an embodiment, the first heat sink MS1 and the second heat sink MS2 may be separated from each other by a first distance dt1, and the first conductive adhesive film CAF1 and the second conductive adhesive film CAF2 may be separated from each other by a second distance dt2. In an embodiment, the second distance dt2 may be equal to or greater than the first distance dt1.

[0130] The circuit board MCB may include a first step difference compensation film SCF1 (e.g., a first step difference compensation pattern) and a second step difference compensation film SCF2 (e.g., a second step difference compensation pattern). The first step difference compensation film SCF1 may be disposed to correspond to the first opening OP1 and may be electrically connected to the ground line GRL. The second step difference compensation film SCF2 may be disposed to correspond to the second opening OP2 and may be electrically connected to the ground line GRL.

[0131] The first step difference compensation film SCF1 may include a second conductive film CF2-1 and a third conductive adhesive CA3-1. The first conductive adhesive film CAF1 may be electrically connected to the ground line GRL via the first step difference compensation film SCF1. Accordingly, the first heat sink MS1 and the ground line GRL may be electrically connected to each other through the first conductive adhesive film CAF1 and the first step difference compensation film SCF1, and thus an electrostatic path may be formed.

[0132] The second step difference compensation film SCF2 may include a second conductive film CF2-2 and a third conductive adhesive CA3-2. The second conductive adhesive film CAF2 may be electrically connected to the ground line GRL via the second step difference compensation film SCF2. Accordingly, the second heat sink MS2 and the ground line GRL may be electrically connected to each other through the second conductive adhesive film CAF2 and the second step difference compensation film SCF2, and thus an electrostatic path may be formed.

[0133] Since an electrostatic path is provided to each of the first heat sink MS1 and the second heat sink MS2 in a structure in which the first heat sink MS1 and the second heat sink MS2 are spaced apart from each other, the electrostatic dissipation characteristics of the display device DD can be improved. In particular, since the first heat sink MS1 is electrically separated from the second heat sink MS2, damage to the driving chip DIC mounted on the display panel DP due to static electricity introduced through the second heat sink MS2 can be reduced or effectively prevented.

[0134] Figure 8 is an exploded perspective view showing an embodiment of a display device DD, and Fig. 9 is along Figure 8 The cross-sectional view is taken along the line V-V' shown. Figure 8 In the same reference numerals, Figures 1B to 7B , and therefore, detailed description of the same elements will be omitted.

[0135] Reference Figure 8 and Fig. 9 , the display device DD may further include a flexible circuit film FCB disposed between the display panel DP and the circuit board MCB. The circuit board MCB may be electrically connected to the display panel DP through the flexible circuit film FCB. The flexible circuit film FCB may be connected to the display panel DP at a first end of the flexible circuit film FCB, and the flexible circuit film FCB may be connected to the circuit board MCB at a second end of the flexible circuit film FCB opposite to the first end thereof.

[0136] The display panel DP may be connected to the flexible circuit film FCB at the peripheral area NAA of the display panel DP, such as by a bonding process. The driving chip DIC may be mounted on the flexible circuit film FCB. The flexible circuit film FCB bent to surround the side surface of the display panel DP, the driving chip DIC, and the circuit board MCB coupled to the flexible circuit film FCB may be disposed on the rear surface of the display panel DP. The bent flexible circuit film FCB disposes the driving chip DIC and a portion of the flexible circuit film FCB to face the first heat sink MS1.

[0137] The electrical connection relationship between the first heat sink MS1 and the circuit board MCB is basically the same as that of the reference FIG. 4A to FIG. 5B The electrical connection relationship between the first heat sink MS1 and the circuit board MCB described above is the same, and therefore, the details thereof will be omitted. In an embodiment, the electrical connection relationship between the heat sink MS and the circuit board MCB may be substantially the same as that described above. FIG. 6A to FIG. 7B The electrical connection relationship between the heat dissipation layer MS and the circuit board MCB described is the same, and therefore, the details thereof will be omitted.

[0138] FIG. 10A to FIG. 10D 2 is a cross-sectional view showing an embodiment of a manufacturing process of the display device DD.

[0139] Reference Fig. 10A The manufacturing process of the display device DD may include providing the display module DM as described above as a completed component. The completed display module DM may include a display panel DP (refer to Figure 1B ) and input sensing unit ISP (reference Figure 1B ). For the sake of explanation, Fig. 10A The detailed configuration of the display module DM is omitted.

[0140] Reference Fig. 10B , a preliminary cover panel P-CVP may be provided on the rear surface of the display module DM. The preliminary cover panel P-CVP may be coupled to the rear surface of the display module DM, such as by an adhesive film.

[0141] The preliminary cover panel P-CVP may include a preliminary heat dissipation layer P-MS, a first layer PF, and a second layer CH. The preliminary heat dissipation layer P-MS may be disposed on the rear surface of the first layer PF, and the second layer CH may be disposed on the front surface or upper surface of the first layer PF. The preliminary heat dissipation layer P-MS may include a metal material. In an embodiment, for example, the preliminary heat dissipation layer P-MS may include a metal material having high thermal conductivity, such as copper (Cu), aluminum (Al), gold (Au), etc.

[0142] The first layer PF may be a polyimide ("PI") film. An adhesive layer may be further disposed between the first layer PF and the preliminary heat dissipation layer P-MS. The second layer CH may be a shock absorbing layer. The second layer CH may be disposed between the display module DM and the first layer PF.

[0143] Reference Fig. 10C , the manufacturing method of the display device DD may include removing a portion of the preliminary heat dissipation layer P-MS along a cutting line CL defined in the preliminary heat dissipation layer P-MS, such as by cutting in a cutting process. The cutting line CL may correspond to a gap GP between portions of the heat dissipation layer MS. The cutting process may include irradiating a laser beam along the cutting line CL. The laser unit LD may be disposed adjacent to the rear surface of the preliminary cover panel P-CVP, and may irradiate the laser beam to the preliminary heat dissipation layer P-MS while moving along the cutting line CL.

[0144] like Fig. 10C and Fig. 10D As shown, the preliminary heat dissipation layer P-MS may be separated into the first heat dissipation fins MS1 and the second heat dissipation fins MS2 by a laser beam. Accordingly, the heat dissipation layer MS including the first heat dissipation fins MS1 and the second heat dissipation fins MS2 may be disposed within the cover panel CVP.

[0145] exist FIG. 10A to FIG. 10DIn the embodiment, the method of irradiating a laser beam is described as a method of forming the first heat sink MS1 and the second heat sink MS2 from the preliminary heat sink layer P-MS, however, it should not be limited thereto or thereby. In an embodiment, the first heat sink MS1 and the second heat sink MS2 are each manufactured as a separate sheet and provided to the cover panel CVP, respectively, to omit the cutting process.

[0146] Although embodiments have been described, it should be understood that the present disclosure should not be limited to these embodiments, but those of ordinary skill in the art can make various changes and modifications within the spirit and scope of the present disclosure claimed. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the present invention should be determined according to the appended claims.

Claims

1. A display device, comprising: A display panel including a front surface and a rear surface opposite to the front surface, an image being displayed at the front surface; a circuit board connected to the display panel and facing the rear surface of the display panel; as well as A heat dissipation layer, between the rear surface of the display panel and the circuit board, the heat dissipation layer comprising: A first heat sink electrically connected to the circuit board; and a second heat sink spaced apart from the first heat sink in a direction along the display panel, Wherein, the first heat sink is electrically insulated from the second heat sink.

2. The display device according to claim 1, wherein: The circuit board faces the display panel, and the first heat sink is located between the circuit board and the display panel.

3. The display device according to claim 2, wherein: Each of the first heat sink and the circuit board has a planar shape, and The planar shape of the first heat sink corresponds to the planar shape of the circuit board.

4. The display device according to claim 1, wherein: The display panel includes a curved portion and a flat portion, the display panel is bendable at the curved portion, the flat portion extends from the curved portion, and The display panel bent at the bent portion disposes the bent portion to face the flat portion.

5. The display device according to claim 4, further comprising a driving chip disposed on the curved portion of the display panel, and The display panel bent at the bent portion disposes each of a portion of the bent portion and the driving chip to face the first heat sink.

6. The display device according to claim 1, further comprising a flexible circuit film which is bendable and electrically connects the display panel and the circuit board to each other, in, The flexible circuit film includes a driving chip.

7. The display device according to claim 6, wherein: The driving chip is disposed on the bent flexible circuit film and faces the first heat sink.

8. The display device according to claim 1, wherein: The circuit board facing the rear surface of the display panel includes a ground line, and The first heat sink is electrically connected to the ground line of the circuit board. 9 . The display device according to claim 8 , further comprising a conductive adhesive film electrically connecting the first heat sink and the ground line of the circuit board to each other.

10. The display device according to claim 9, wherein: The circuit board comprises: a cover layer between the ground line and the conductive adhesive film; an opening defined to pass through the cover layer and expose a portion of the ground line to the outside of the cover layer to define an exposed portion of the ground line; and A step difference compensation pattern is located in the opening and electrically connects the conductive adhesive film to the exposed portion of the ground line.

11. The display device according to claim 10, wherein: The step difference compensation pattern forms an interface with both the conductive adhesive film and the exposed portion of the ground line.

12. The display device according to claim 8, further comprising: a first conductive adhesive film electrically connecting the first heat sink and the ground line of the circuit board to each other; as well as a second conductive adhesive film electrically connecting the second heat sink and the ground line of the circuit board to each other, Wherein, the second heat sink is electrically connected to the circuit board.

13. The display device according to claim 12, wherein: The second heat sink is spaced apart from the first heat sink by a first distance in the direction along the display panel, The first conductive adhesive film and the second conductive adhesive film are spaced apart from each other by a second distance in the direction along the display panel, and the second distance is greater than the first distance, and The first conductive adhesive film faces the display panel with the first heat sink located therebetween, and the second conductive adhesive film faces the display panel with the second heat sink located therebetween.

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