Semiconductor device

Abstract

A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes: a first connection pattern; a bit line disposed above the first connection pattern in a vertical direction; and a bit line contact pad disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, such that the bit line contact pad resembles an island when viewed in the vertical direction.

Description

Technical Field

[0001] The technologies and implementations disclosed herein generally relate to semiconductor devices, and more particularly to three-dimensional (3D) semiconductor memory devices. Background Art

[0002] A semiconductor device may include a memory cell array provided with a plurality of memory cells. The memory cell array may include a plurality of memory cells arranged in various shapes. To increase the integration degree of the semiconductor device, memory cells may be three-dimensionally arranged (3D) above a semiconductor substrate. In a manufacturing process for forming a three-dimensional (3D) semiconductor device, a plurality of material films may be stacked to form a stacked structure. Summary of the Invention

[0003] Various embodiments of the disclosed technologies relate to semiconductor devices for increasing the degree of freedom of line (or wiring) connections.

[0004] According to an embodiment of the disclosed technology, a semiconductor device may include: a first connection pattern; a bit line disposed above the first connection pattern in a vertical direction; and a bit line contact pad disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed in an island shape when viewed along the vertical direction.

[0005] According to another embodiment of the disclosed technology, a semiconductor device may include: a plurality of gate electrodes formed to extend in a second direction and spaced apart from each other by a predetermined distance in a first direction when viewed from the vertical direction; and a plurality of bit line contact pads spaced apart from each other by a predetermined distance in the first direction, wherein each of the plurality of bit line contact pads disposed between the bit line and a lower connection structure in the vertical direction to electrically connect the bit line to the lower connection structure has an island shape when viewed along the vertical direction.

[0006] According to still another embodiment of the disclosed technology, a semiconductor device may include a substrate in which a first region and a second region are defined; a logic circuit stacked on the substrate, the logic circuit including a page buffer circuit; a memory cell array stacked on the logic circuit; a bit line formed above the memory cell array; a bit line contact pad formed in the first region, the bit line contact pad electrically connecting the bit line to the page buffer circuit; and a plurality of connection patterns formed in a vertical direction below the bit line contact pad, wherein the bit line and the bit line contact pad are electrically coupled to a junction region of a transistor of the page buffer circuit through the plurality of connection patterns.

[0007] It should be understood that the above general description and the following detailed description of the technologies disclosed herein are both exemplary and explanatory, and are intended to provide a further explanation of the scope of the present disclosure to those skilled in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features and advantageous aspects of the disclosed technology will become apparent when considering the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2 is illustrative of an embodiment according to the present disclosure Figure 1 of a semiconductor device.

[0011] Figure 3 is illustrative of an embodiment according to the present disclosure Figure 2 of a layout structure of a page buffer circuit in.

[0012] Figure 4 is illustrative of an embodiment according to the present disclosure Figure 1 of a structure in.

[0013] Figure 5 is illustrative of an embodiment according to the present disclosure Figure 4 of a layout of elements of a semiconductor device in.

[0014] Figure 6 is illustrative of an embodiment according to the present disclosure Figure 2 of a connection relationship between transistors included in a page buffer circuit and a bit line contact region in.

[0015] Figure 7 is illustrative of an embodiment according to the present disclosure Figure 6 of a layout structure of a bit line contact pad in.

[0016] Figure 8 and Figure 9 is illustrative of an embodiment according to the present disclosure Figure 6 of a layout structure of a bit line contact pad in.

[0017] The symbol of each element in the figure

[0018] 121: First conductive contact plug

[0019] 123: Connection pattern

[0020] 125: Second conductive contact plug

[0021] BLCP: Bit line contact pad DETAILED DESCRIPTION

[0022] This patent document provides implementations and examples of semiconductor devices that substantially solve one or more problems related to the limitations or disadvantages of the related art. Some implementations of the disclosed technology present semiconductor devices with improved and greater degrees of freedom in wire connections.

[0023] Reference will now be made in detail to aspects of the disclosed technology, whose embodiments and examples are illustrated in the accompanying drawings. As far as possible, the same reference numerals are used throughout the drawings to refer to the same or similar parts.

[0024] In connection with the embodiments of the disclosed technology, specific structural and functional descriptions are disclosed only for illustrative purposes. The embodiments represent a limited number of possible embodiments. However, the embodiments of the disclosed technology can be implemented in various different ways without departing from the scope or spirit of the disclosed technology.

[0025] In describing the disclosed technology, the terms "first" and "second" may be used to describe multiple components, but the components are not limited by the terms in terms of quantity or order. These terms can be used to distinguish one component from another. For example, without departing from the scope of the present disclosure, the first component can be referred to as the second component, and the second component can be referred to as the first component.

[0026] The terms used in this application are only for describing specific embodiments and are not intended to limit the disclosed technology. Unless otherwise explicitly stated, singular expressions may include plural expressions.

[0027] Unless otherwise defined, all terms, including technical or scientific terms, used herein have the same meaning as understood by those skilled in the art. Terms defined in a general dictionary can be analyzed to have the same meaning as the context of the relevant field, and unless explicitly defined in this application, they should not be analyzed as having an ideal meaning or being overly formal. The terms used in the disclosed technology are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0028] Figure 1 is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure. In Figure 1 , the third direction (TD) is a direction perpendicular to the horizontal plane, which is formed to extend in each of the first direction (FD) and the second direction (SD). For example, the third direction (TD) can be perpendicular to each of the first direction (FD) and the second direction (SD).

[0029] Referring to Figure 1 , the semiconductor device may include a logic circuit 20 and a memory cell array 30 disposed above a substrate 10.

[0030] The substrate 10 may be a single-crystalline semiconductor film. For example, the substrate 10 may be any one of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, and a silicon-germanium substrate, or may be an epitaxial thin film formed by a selective epitaxial growth (SEG) process.

[0031] The memory cell array 30 may include a plurality of memory blocks, each represented by "BLK" which will be described later. Each memory block may include a plurality of cell strings, each represented by "CST" which will be described later. Each cell string may be electrically connected in series to a gate stack, a bit line, and a source line. The gate stack may include a plurality of word lines and a plurality of select lines. Each select line may serve as a gate electrode of a corresponding select transistor, and each word line may serve as a gate electrode of a corresponding memory cell.

[0032] The logic circuit 20 may include NMOS transistors, PMOS transistors, at least one resistor, and at least one capacitor electrically connected to the memory cell array 30. The NMOS transistors, PMOS transistors, resistors, and capacitors may serve as components of a row decoder, a column decoder, a page buffer circuit, and a control circuit.

[0033] In some embodiments, the logic circuit 20 may be disposed between the memory cell array 30 and the substrate 10. For example, the memory cell array 30 may be formed to overlap the logic circuit 20 when viewed in the third direction (TD). If the memory cell array 30 overlaps the logic circuit 20, the size of the region on the substrate 10 where the memory cell array 30 and the logic circuit 20 are disposed can be reduced. In other embodiments, the memory cell array 30 may be disposed between the logic circuit 20 and the substrate 10.

[0034] Figure 2 is an illustration of a Figure 1 three-dimensional view of a semiconductor device according to an embodiment of the present disclosure.

[0035] Referring to Figure 2 , the logic circuit 20 may be disposed above the substrate 10, and the memory cell array 30 may be disposed above a source plate 31 located or disposed above the logic circuit 20.

[0036] The substrate 10 may be a first-conductive semiconductor substrate, for example, a P-type conductive semiconductor substrate. The source plate 31 may be formed of a polysilicon layer.

[0037] The logic circuit 20 may include a row decoder 21, a page buffer circuit 22, and a peripheral circuit 23. The row decoder 21 may be formed to extend in the first direction (FD) at or near an edge of the substrate 10.

[0038] The page buffer circuit 22 may be formed to extend in the second direction (SD). The page buffer circuit 22 may be formed under the memory cell array 30. The page buffer circuit 22 may be formed to overlap with the lower part of the memory cell array 30 and the memory cell array 30.

[0039] The peripheral circuit 23 may be disposed on opposite sides of the page buffer circuit 22 on the substrate 10 and arranged with the page buffer circuit 22 in the first direction (FD). For ease of description, the portion of the peripheral circuit 23 disposed on one side of the page buffer circuit 22 in the first direction (FD) will be defined hereinafter as the first peripheral circuit 23A, and the portion of the peripheral circuit 23 disposed on the other side of the page buffer circuit 22 will be defined hereinafter as the second peripheral circuit 23B.

[0040] The first peripheral circuit 23A may be electrically connected to the second peripheral circuit 23B through a line (RW) arranged to cross the upper part of the page buffer circuit 22 in the first direction (FD). The line (RW) may transmit power and signals to the first peripheral circuit 23A and the second peripheral circuit 23B.

[0041] In some embodiments, the first peripheral circuit 23A and the second peripheral circuit 23B may be respectively disposed on both sides of the page buffer circuit 22. Similarly, the row decoder 21 may be divided and connected in parallel to opposite sides of the page buffer circuit 22 arranged in the first direction or the second direction (FD, SD). However, the scope or spirit of the disclosed technology is not limited thereto, and in other embodiments, the directions and positions of the page buffer circuit 22, the peripheral circuit 23, and the row decoder 21 may be changed, and the numbers of the page buffer circuit 22, the peripheral circuit 23, and the row decoder 21 may also be changed as needed.

[0042] The bit line (BL) may be disposed above the memory cell array 30. The bit line (BL) may be formed to extend in the first direction (FD) and may be arranged along the second direction (SD). The bit line (BL) may be used to interconnect the memory cell array 30 and the page buffer circuit 22 and may be electrically connected to the memory cell array 30 and the page buffer circuit 22.

[0043] The page buffer circuit 22 and the bit lines (BL) can be electrically connected through a plurality of bit line contact pads (BLCP). The plurality of bit line contact pads (BLCP) are electrically connected to the page buffer circuit 22 and are disposed in any one of the line layers provided between the page buffer circuit 22 and the source electrode plate 31. The bit lines (BL) can be coupled to the bit line contact pads (BLCP) through bit line contacts (BLC). The bit line contacts (BLC) are formed to penetrate through the memory cell array 30 and the source electrode plate 31 in the third direction (TD). The bit line contact pads (BLCP) can be used as landing pads for the bit line contacts (BLC).

[0044] Figure 3 is an illustration of Figure 2 the layout structure of the page buffer circuit 22 in accordance with an embodiment of the present disclosure.

[0045] Referring to Figure 3 , the page buffer circuit 22 can include a plurality of page buffers (PB). The page buffers (PB) can be formed in a matrix shape having 8 rows. For example, the rows or page buffers can extend in the second direction (SD), and the rows can be spaced apart in the first direction (FD) or arranged along the first direction (FD). The page buffer circuit 22 can include 8 stages from Stage<0> to Stage<7>. The number of stages of the page buffer circuit 22 can be understood as the number of page buffers (PB) arranged in the extending direction of the bit lines (BL). Although, for ease of description, Figure 3 an example case where the page buffer circuit 22 includes 8 stages is illustrated, the scope or spirit of the disclosed technology is not limited thereto, and the number of stages can be changed in other embodiments.

[0046] The bit line contact regions (BLOFC) can be provided between two adjacent or neighboring stages (i.e., a pair of stages). For example, the bit line contact regions (BLOFC) can be provided between Stage<0> and Stage<1>, between Stage<2> and Stage<3>, between Stage<4> and Stage<5>, and between Stage<6> and Stage<7>.

[0047] In Figure 1 the stacked semiconductor device shown, signal communication between the logic circuit 20 and the memory cell array 30 requires lines for electrically connecting a lower connection structure (such as the lower part of the memory cell array) to the bit lines (BL). Such lines can be provided in a specific region of the stacked semiconductor device. For example, in the bit line contact region (BLOFC), lines for connecting transistors included in the page buffers (PB) of the logic circuit 20 to the bit lines of the memory cell array 30, and corresponding pads, can be provided.

[0048] A connection pattern 123 connected to a page buffer (PB) included in an adjacent stage may be disposed in a bit line contact region (BLOFC). The connection pattern 123 may be connected to an upper line through a second conductive contact plug 125.

[0049] Figure 3 An exemplary case where the connection pattern 123 is disposed in two columns in a second direction (SD) is illustrated. The connection pattern 123 in the first column (i.e., the upper column) may be connected to a page buffer (PB) of a stage located on one side (i.e., the upper side) in a first direction (FD) of the bit line contact region (BLOFC). The connection pattern 123 in the second column (i.e., the lower column) may be connected to a page buffer (PB) of a stage located on the other side (i.e., the lower side) of the bit line contact region (BLOFC). Although for ease of description, Figure 3 an exemplary case where the connection pattern 123 is disposed in two columns is illustrated, the number of columns included in the connection pattern 123 is not limited thereto.

[0050] Figure 4 is a schematic diagram illustrating a structure Figure 1 in accordance with an embodiment of the present disclosure. For clarity, an interlayer insulating film is not shown in Figure 4 . Figure 4 The first direction (FD) and the third direction (TD) shown in Figure 1 are the same as the directions in

[0051] Figure 4 An exemplary structure in which a transistor (TR) included in a page buffer circuit 22 disposed in a lower layer or a lower portion close to or adjacent to a substrate 10 is connected to a bit line disposed in an upper layer of the page buffer circuit 22 is illustrated. The transistor (TR) may be connected through a lower connection structure 130, a bit line contact pad (BLCP), and a bit line contact (BLC) such that the transistor (TR) can be electrically connected to a corresponding bit line (BL).

[0052] The transistor (TR) may be included in the Figure 3 shown page buffer (PB). In addition to the Figure 4 shown transistor (TR), the Figure 3 shown page buffer (PB) may further include a plurality of transistors.

[0053] The transistor (TR) may include a junction Jn1 and a junction Jn2 defined in an active region (ACT) of the substrate 10, and a gate electrode (G) formed in the active region (ACT) of the substrate 10. The active region (ACT) of the substrate 10 may be defined between device isolation layers (not shown) formed in the substrate 10.

[0054] The gate electrode (G) may be formed together with the gate insulating film (GIF) over the active region (ACT) of the substrate 10, and the gate insulating film (GIF) is interposed between the gate electrode (G) and the active region (ACT). Each of the junctions Jn1 and Jn2 may be a region defined by implanting conductive impurities in the active region (ACT) of the substrate 10, and the junctions Jn1 and Jn2 may be disposed on opposite sides of the gate electrode (G). For example, each of the junctions Jn1 and Jn2 may include N-type impurities. Each of the junctions Jn1 and Jn2 may be used as a source junction or a drain junction.

[0055] The junction (Jn1) of the transistor (TR) may be in contact with the lower connection structure 130. The junction (Jn1) may be one of the junctions of the transistor (TR), and may be defined in the active region (ACT) of the substrate 10 separated by one or more device isolation layers (not shown).

[0056] The lower connection structure 130 may include a first conductive contact plug 121, a connection pattern 123, a second conductive contact plug 125, a connection pattern 131, and a third conductive contact plug 133 stacked between the junction (Jn1) of the transistor (TR) and the bit line contact pad (BLCP).

[0057] In this example, the first conductive contact plug 121 may be in contact with the junction (Jn1). The connection pattern 123 may be disposed above the first conductive contact plug 121. When viewed in the third direction (TD), the connection pattern 123 is larger in size than the first conductive contact plug 121, thereby increasing the contact margin. The second conductive contact plug 125 may be formed to extend in a direction from the connection pattern 123 to the bit line contact pad (BLCP).

[0058] The connection pattern 131 may be a metal pattern, and may be disposed on the second conductive contact plug 125. When viewed in the third direction (TD), the connection pattern 131 may be larger in size than the second conductive contact plug 125, thereby increasing the contact margin. The third conductive contact plug 133 may be disposed between the connection pattern 131 and the bit line contact pad (BLCP). The third conductive contact plug 133 may be disposed above the connection pattern 131, and may be formed to extend in a direction from the connection pattern 131 to the bit line contact pad (BLCP) such that the extended third conductive contact plug 133 can be in contact with both the bit line contact pad (BLCP) and the connection pattern 131.

[0059] The bit line contact pad (BLCP) may be a bit line connection pad that couples the lower connection structure 130 to the bit line (BL). The bit line contact pad (BLCP) may be used as a landing pad for landing the bit line contact (BLC), and may be arranged to correspond to the arrangement structure of the bit line (BL).

[0060] The bit line contact pad (BLCP) can be electrically connected to Figure 3 the connection pattern 123 and the second conductive contact plug 125 shown. The bit line contact pad (BLCP) can be formed of a wire. The bit line contact pad (BLCP) can be formed or disposed in the same layer as the wire (A). The bit line contact pad (BLCP) can be disconnected from the wire (A) such that the bit line contact pad (BLCP) can be formed in an island shape. That is, the wire (A) can be truncated or segmented to obtain an independent bit line contact pad (BLCP). As a result, the degree of freedom of the wire connection of the remaining part of the wire (A) that is now disconnected from the bit line contact pad (BLCP) can be improved.

[0061] The cell string (CST) can be included in the memory block (BLK). Each cell string (CST) can be connected to the bit line (BL) after passing through the bit line contact plug (BCT). The cell string (CST) can be formed in various shapes. The cell string (CST) can be connected to the bit line contact pad (BLCP) through the bit line (BL) and the bit line contact (BLC). In this case, the bit line contact (BLC) can be formed as a conductive contact plug.

[0062] In some embodiments, the bit line (BL), the bit line contact (BLC), the bit line contact pad (BLCP), the third conductive contact plug 133, the connection pattern 131, the second conductive contact plug 125, and the connection pattern 123 can be vertically connected to each other in a column in the third direction (TD) to form a vertical structure. The lower connection pattern 123 can be electrically connected to the wire of the transistor (TR) of the page buffer (PB) through the first conductive contact plug 121.

[0063] As viewed in the third direction (TD), a specific area in which the bit line (BL), the bit line contact (BLC), the bit line contact pad (BLCP), the third conductive contact plug 133, the connection pattern 131, the second conductive contact plug 125, and the connection pattern 123 are arranged can be defined as the bit line contact area (BLOFC) (i.e., the first area to be described later). In addition, areas on both sides of the bit line contact area (BLOFC) in the first direction (FD) can be defined as the second area (SR) (described later). The transistor (TR) of the page buffer (PB) can be disposed above the second area (SR). In the second area (SR), the connection pattern 123 can be electrically connected to the junction (Jn1) of the transistor (TR) through the first conductive contact plug 121.

[0064] Figure 5 is an exemplary layout diagram of elements of a semiconductor device in Figure 4 accordance with an embodiment of the present disclosure. For simplicity of the drawings, in Figure 5Only the line layers necessary for further explaining the embodiments of the present disclosure are illustrated herein.

[0065] Referring to Figure 5 , a first region (BLOFC) and a second region (SR) can be defined in a substrate (not shown). Bit line contact pads (BLCP) connected to page buffers (PB) included in an adjacent pair of stages can be arranged in the first region (BLOFC).

[0066] In Figure 5 , the first region (BLOFC) can be substantially the same as the bit line contact region (BLOFC) shown in Figure 4 . The second region (SR) can be located on both sides of the bit line contact region (BLOFC) in the first direction (FD). Figure 4 The page buffers (PB) shown in

[0067] can be provided above the second region SR.

[0068] The connection pattern 131 can be provided in the lower plane of the bit line contact pad (BLCP). The connection pattern 131 can be formed in a line shape extending in the first direction (FD). However, when viewed in the third direction (TD), some portions of the connection pattern 131 can be configured to have an angle, curve, or bend that causes the connection pattern 131 to cross the connection pattern 123 of the bit line contact pad (BLCP). For example, the connection pattern 131 can be formed as a dogleg surrounding the bit line contact pads (BLCP) that are offset from each other in the second direction (SD) in the bit line contact region (BLOFC).

[0069] The bit line contact pads (BLCP) can be provided in the lower plane or lower portion of the bit line (not shown). That is, the bit line contact pads (BLCP) can be provided above the connection pattern 131 or above the upper surface of the connection pattern 131 and above the lower connection structure 130. The bit line contact pads (BLCP) can be formed in the bit line contact region (BLOFC). Each bit line contact pad (BLCP) can be formed in a rectangular island shape by disconnecting and removing some portions or segments of the connection lines. For example, the rectangular island shape is different from the line shape formed by a wire formed by extending in a predetermined direction on the same layer, but can refer to an integrated pad in which at least some portions of the rectangular island shape are disconnected and constructed independently of each other.

[0070] Not only the lower connection structure 130, but also a contact plug (not shown) for electrically coupling a bit line contact (BLC) to a bit line can be formed above the bit line contact pad (BLCP). The bit line contact pad (BLCP) can be electrically connected to the lower connection pattern 123 through a second conductive contact plug 125. A third conductive contact plug 133 can be formed below the bit line contact pad (BLCP) such that the third conductive contact plug 133 can be electrically connected to the lower connection pattern 131. The bit line contact (BLC) can be formed above the bit line contact pad (BLCP) such that the bit line contact (BLC) can be electrically coupled to the bit line.

[0071] The wire (A) is disposed in a second region (SR) located on both sides (i.e., the upper side and the lower side) with respect to the first region (BLOFC). However, within the first region (BLOFC), the wire (A) can be disconnected from the bit line contact pad (BLCP) such that the wire (A) is not coupled to the bit line (not shown). That is, as Figure 4 shown, although the wire (A) is formed or disposed in the same layer as the bit line contact pad (BLCP), the wire (A) is not electrically coupled to the bit line contact pad (BLCP). As a result, the wire (A) has an improved degree of freedom in line connection because they are not electrically connected to the bit line (not shown) (i.e., the wire (A) is not used as a bit line connection pad). Although for ease of description, the wire (A) shown in Figure 5 is disposed in the horizontal direction as an example, the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that the wire (A) can also be disposed in the vertical direction or other directions.

[0072] The wire (A) and the connection pattern 131 disposed in a second region (SR) located on both sides (i.e., the upper side and the lower side) with respect to the bit line contact region (BLOFC) can be electrically coupled to a page buffer (PB) of a stage also located or disposed in the second region (SR) (see Figure 3 ).

[0073] The bit line contact pad (BLCP) can be used as a landing pad for the bit line contact such that the bit line contact pad (BLCP) can be coupled to the bit line through the bit line contact (BLC). Referring to Figure 5 , a virtual line represented by the line “VL” is formed to cross the central portion of the bit line contact region (BLOFC) in the second direction (SD). As a result, the bit line contact pad (BLCP) disposed on one side (i.e., the upper side) of the virtual line (VL) can be electrically coupled to a page buffer (PB) of a stage located on the same side (i.e., the upper side) in the first direction (FD) (see Figure 3)。Similarly, a bit line contact pad (BLCP) located on the other side (lower side) of the virtual line (VL) can be electrically coupled to a page buffer (PB) of a stage located on the same side (lower side) in the first direction (FD) (see Figure 3 ).

[0074] A bit line contact pad (BLCP) located on one side of the virtual line (VL) and other bit line contact pads (BLCP) located on the other side of the virtual line (VL) can be mirror images of each other with respect to the virtual line (VL). Bit line contact pads (BLCP) in adjacent regions within the bit line contact region (BLOFC) can have a mirror symmetric structure with a central portion arranged in the second direction (SD) based on the first direction (FD) (i.e., the vertical direction intersecting the virtual line VL).

[0075] A predetermined number of bit line contact pads (BLCP) provided above the bit line contact region (BLOFC) can be paired (or grouped) such that the bit line contact pads (BLCP) can be formed into paired bit line contact pads (BLCP). As a result, such paired patterns can be provided above the same connection pattern 131 in the first direction (FD). When viewed in the third direction (TD), a predetermined number of bit line contact pads (BLCP) can be continuously formed in the first direction (FD).

[0076] For example, the bit line contact pads (BLCP) can be configured in such a way that four patterns (i.e., four bit line contact pads) on one side of the virtual line VL are arranged in the form of a line in the first direction (FD). However, one of the four bit line contact pads (BLCP) can be set to deviate or be offset in the second direction (SD) with respect to the remaining three bit line contact pads (BLCP). Accordingly, the offset bit line contact pad (BLCP) can correspond to a connection pattern 131 different from the connection pattern 131 corresponding to the other three bit line contact pads (BLCP).

[0077] Although, for ease of description, Figure 5 exemplarily disclosed is an arrangement of bit line contact pads (BLCP) in such a way that three bit line contact pads (BLCP) are arranged in one direction and the remaining one bit line contact pad (BLCP) is offset in another direction, the scope or spirit of the disclosed technology is not limited thereto, and other configurations can be used.

[0078] Figure 6 is a schematic diagram illustrating the connection relationship between transistors included in a page buffer circuit included in Figure 2 and a bit line contact region (BLOFC).

[0079] Referring to Figure 6, a transistor (TR) may be included in Figure 3 the page buffer (PB) shown. The transistor (TR) may be used to read data from the cell string (CST) or may be used to program the cell string (CST). Each transistor (TR) may be coupled between a bit line connection node (BLN) and another bit line connection node (BLCM).

[0080] The line of the bit line connection node (BLN) may be coupled to the bit line contact region (BLOFC) through the line of the high-voltage page buffer (HV). Additionally, the line of the bit line connection node (BLCM) may be coupled to the line of the low-voltage page buffer (LV). The transistor (TR) may be coupled to the lower conductor (i.e., the connection pattern 123). The connection pattern 123 may be electrically coupled to the bit line contact pad (BLCP) included in the bit line contact region (BLOFC).

[0081] In a stacked semiconductor device, the transistor (TR) included in the page buffer (PB) may be formed under the memory cell array 30 based on the third direction (TD). The connection pattern 123 (i.e., the line HV) of the transistor (TR) may be electrically coupled to the bit line (BL) of the memory cell array 30 formed on the upper part of the stacked semiconductor device.

[0082] Figure 7 is a plan view illustrating the layout structure of the Figure 6 bit line contact pad according to an embodiment of the present disclosure.

[0083] Referring to Figure 7 , the gate electrode (G) may correspond to Figure 6 the gate electrode of each transistor (TR) shown. The gate electrode (G) may be disposed above the active region (ACT). Each gate electrode (G) may extend in the second direction (SD). The gate electrodes (G) may be spaced apart from each other by a predetermined distance in the first direction (FD).

[0084] In the bit line contact region (BLOFC), the bit line contact pads (BLCP) may be spaced apart from each other by a predetermined distance in the first direction (FD). The bit line contact pads (BLCP) may be coupled to the corresponding connection patterns.

[0085] The bit line contact pad (BLCP) may be electrically connected to the corresponding connection pattern 123 through the second conductive contact plug 125. The bit line contact pad (BLCP) may be electrically coupled to the lower connection pattern 131 through the third conductive contact plug 133. The bit line contact pad (BLCP) may be electrically coupled to the bit line (BL) through the bit line contact (BLC).

[0086] For ease of description, the details related to the combination with Figure 4Detailed description of substantially the same connection patterns 123, connection pattern 131, and bit line contact (BLC).

[0087] The bit line contact pad (BLCP) can be set to overlap some portions of the gate electrode (G). For example, Figure 3 Four bit line contact pads (BLCP) are illustrated, and two of the four bit line contact pads (BLCP) can be set to overlap adjacent gate electrodes (G). Although three adjacent bit line contact pads among the four bit line contact pads (BLCP) are arranged in a line form in the first direction (FD), only one bit line contact pad (BLCP) can be set to deviate from the remaining three bit line contact pads (BLCP) in the second direction (SD).

[0088] At least one of the connection patterns (e.g., connection pattern 123) coupled to the four bit line contact pads (BLCP) can be disposed at least above the junction (Jn1) of the transistor (TR). That is, at least one of the four connection patterns 123 can be disposed in the space between gate electrodes (G) adjacent to each other in the first direction (FD). In other words, when viewed in the third direction (TD), the connection pattern 123 coupled to the bit line contact pad (BLCP) disposed in the bit line contact region (BLOFC) can be disposed above the junction (Jn1) of the lower transistor (TR). When viewed along the third direction (TD), the bit line contact pad (BLCP) can be electrically coupled to the junction (Jn1) of the lower transistor (TR) through the connection pattern 123.

[0089] In the above-described embodiment of the disclosed technology, the bit line contact pad (BLCP) can be formed above the bit line contact region (BLOFC), and each bit line contact pad (BLCP) can be formed in an island shape, where the line structure of the bit line contact pad (BLCP) is disconnected from other connection lines formed in the same layer. Therefore, the semiconductor device according to the embodiment of the disclosed technology can improve the freedom of wire connection of the wire (A) in the remaining regions other than the bit line contact region (BLOFC).

[0090] Figure 8 and Figure 9 are plan views illustrating the layout structure of the bit line contact pad (BLCP) in accordance with an embodiment of the present disclosure Figure 6 in.

[0091] Referring to Figure 8, bit line contact pads (BLCPs) in a bit line contact region (BLOFC) can be arranged in the same pattern. Each pattern including four bit line contact pads (BLCPs) can be arranged in four columns in a second direction (SD). Two rows of each pattern including four bit line contact pads (BLCPs) can be arranged in two levels within the bit line contact region (BLOFC) in a first direction (FD).

[0092] Referring to Figure 9 , each same pattern including four bit line contact pads (BLCPs) in the bit line contact region (BLOFC) can be arranged in four columns in a second direction (SD). Each pattern including four bit line contact pads (BLCPs) can be arranged in a zigzag, broken line, or angled arrangement. Additionally, each pattern including four bit line contact pads (BLCPs) can be arranged in four levels within the bit line contact region (BLOFC) in a first direction (FD).

[0093] The above embodiments have exemplarily disclosed that patterns each including four bit line contact pads (BLCPs) in the bit line contact region (BLOFC) are arranged in two or four levels in a first direction (FD). However, the scope or spirit of the disclosed technology is not limited thereto, and in other embodiments, the number of bit line contact pads (BLCPs) and the arrangement shape of the bit line contact pads (BLCPs) can also be changed as needed.

[0094] It is obvious from the above description that a semiconductor device based on the implementation of the disclosed technology can improve the degree of freedom of wire connection.

[0095] Those skilled in the art will understand that the embodiments can be implemented in other specific ways different from those described herein without departing from the spirit and essential characteristics of the present disclosure. Therefore, the above embodiments are to be construed as exemplary in all aspects and not restrictive. The scope of the present disclosure should be determined by the appended claims and their legal equivalents, not by the above description. Additionally, all variations falling within the meaning and equivalent scope of the appended claims are intended to be included therein. Further, those skilled in the art will understand that after the application is filed, claims that do not have an explicit citation relationship with each other in the appended claims can be presented in combination as embodiments, or included as new claims.

[0096] Although a number of exemplary embodiments have been described, it will be appreciated that those skilled in the art may devise numerous other modifications and embodiments that will fall within the spirit and scope of the principles of the present disclosure. In particular, within the scope of the present disclosure, the drawings, and the appended claims, a variety of variations and modifications may be made in the component parts and / or arrangements. In addition to variations and modifications in the component parts and / or arrangements, alternative uses will also be apparent to those skilled in the art.

[0097] CROSS-REFERENCE TO RELATED APPLICATIONS

[0098] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0032053, filed on March 16, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: A first connection pattern; A bit line, the bit line extending in a first direction and disposed above the first connection pattern; And A bit line contact pad, the bit line contact pad being disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern and being formed in an island shape in a plan view, Wherein, in the plan view, a predetermined number of the bit line contact pads are continuously formed in the first direction, and a plurality of bit line contact pads arranged adjacent to each other in the first direction are disposed in the same line, and Wherein, the arrangement of the plurality of bit line contact pads has a mirror symmetry structure with respect to a virtual line, the virtual line being formed to cross the center of the bit line contact area in a second direction perpendicular to the first direction.

2. The semiconductor device according to claim 1, the semiconductor device further comprising: A wire, the wire being disposed in the first layer, the wire not being electrically connected to the bit line contact pad.

3. The semiconductor device according to claim 1, wherein, In the plan view, the predetermined number of the bit line contact pads are spaced apart from each other by a predetermined distance in the first direction.

4. The semiconductor device according to claim 3, wherein, In the plan view, at least one of the predetermined number of bit line contact pads is offset in the second direction with respect to the other bit line contact pads of the predetermined number of bit line contact pads.

5. The semiconductor device according to claim 3, wherein, The predetermined number of bit line contact pads are disposed above the same line in the first direction.

6. The semiconductor device according to claim 1, the semiconductor device further comprising: A contact, the contact coupling the bit line to the bit line contact pad and coupling the bit line contact pad to a lower connection structure.

7. The semiconductor device according to claim 1, the semiconductor device further comprising: A second connection pattern, the second connection pattern being below the first connection pattern; A first conductive contact plug, the first conductive contact plug being coupled to the bottom surface of the second connection pattern; A second conductive contact plug, the second conductive contact plug being coupled between the bottom surface of the first connection pattern and the top surface of the second connection pattern; A third conductive contact plug, the third conductive contact plug being coupled between the bottom surface of the bit line contact pad and the top surface of the first connection pattern; And A bit line contact, the bit line contact being coupled between the bit line and the bit line contact pad.

8. The semiconductor device according to claim 7, the semiconductor device further comprising: A transistor, the transistor being disposed below the second connection pattern, Wherein, the second connection pattern is disposed above the junction region of the transistor.

9. The semiconductor device according to claim 1, wherein, The first connection pattern is angled to couple to the bit line contact pad.

10. A semiconductor device, the semiconductor device comprising: A plurality of gate electrodes, the plurality of gate electrodes being formed to extend in a second direction, and in a plan view, the plurality of gate electrodes being spaced apart from each other by a predetermined distance in a first direction perpendicular to the second direction; and a plurality of bit line contact pads, the plurality of bit line contact pads extending in the second direction and being spaced apart from each other by a predetermined distance in the first direction, wherein, in a plan view, each of the plurality of bit line contact pads disposed between a bit line extending in the first direction and a lower connection structure in a third direction perpendicular to the first direction and the second direction to electrically connect the bit line to the lower connection structure has an island shape, wherein, each of the plurality of gate electrodes corresponds to a corresponding bit line contact pad among the plurality of bit line contact pads, each gate electrode overlapping the entire length of the corresponding bit line contact pad in the second direction in the plan view, and each of the plurality of bit line contact pads is electrically connected to a corresponding lower connection pattern through a corresponding conductive contact plug.

11. The semiconductor device according to claim 10, wherein, a part of the plurality of bit line contact pads overlaps the plurality of gate electrodes.

12. The semiconductor device according to claim 11, wherein, the part is linearly arranged in the first direction.

13. The semiconductor device according to claim 12, wherein, one of the plurality of bit line contact pads is offset from the remaining bit line contact pads of the plurality of bit line contact pads in the second direction.

14. The semiconductor device according to claim 10, wherein, at least one of the plurality of bit line contact pads is disposed above a junction region of a transistor.

15. The semiconductor device according to claim 10, wherein, The plurality of bit line contact pads are arranged in a pattern.

16. A semiconductor device, the semiconductor device comprising: a substrate in which a first region and a second region are defined; a logic circuit stacked on the substrate, the logic circuit including a page buffer circuit; a memory cell array stacked on the logic circuit; a bit line extending in a first direction and formed above the memory cell array; a bit line contact pad formed in the first region, the bit line contact pad electrically connecting the bit line to the page buffer circuit; and a plurality of connection patterns formed below the bit line contact pad, wherein the bit line and the bit line contact pad are electrically connected to a junction region of a transistor of the page buffer circuit through the plurality of connection patterns, wherein, in a plan view, a predetermined number of the bit line contact pads are continuously formed in the first direction, and a plurality of bit line contact pads adjacent to each other in the first direction are disposed in the same line, and wherein the arrangement of the plurality of bit line contact pads has a mirror symmetry structure with respect to a virtual line, the virtual line being formed to cross the center of a bit line contact region in a second direction perpendicular to the first direction.

17. The semiconductor device according to claim 16, wherein, In a plan view, the bit line contact pad is formed in a rectangular island shape.

18. The semiconductor device according to claim 16, wherein, The plurality of connection patterns include: A first connection pattern formed under the bit line contact pad; and A second connection pattern formed under the first connection pattern, the second connection pattern being electrically coupled to the junction region of the transistor.

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