High-density 3D FERAM

Abstract

The present application relates to a high-density 3D FERAM. A device includes: a first channel; a second channel, the second channel is above the first channel; and a gate structure, the gate structure surrounding the first channel and the second channel, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first channel and the second channel and a gate metal layer surrounding the FE layer. The device also includes: two first electrodes, the two first electrodes are connected to both sides of the first channel; two second electrodes, the two second electrodes are connected to both sides of the second channel; a dielectric layer, the dielectric layer is between the two first electrodes and the two second electrodes; and an internal spacer layer, the internal spacer layer is between the two first electrodes and the gate structure.

Description

Technical Field

[0001] The present application relates to high-density 3D FERAM. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. During the evolution of ICs, functional density (e.g., the number of interconnected devices per chip area) has generally increased while geometric size (e.g., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This shrinking process generally provides benefits by improving production efficiency and reducing associated costs. This shrinking also increases the complexity of processing and manufacturing ICs. Therefore, semiconductor manufacturing processes need to continue to improve. One aspect of improvement is how to increase the cell density of ferroelectric memory (FeRAM, FRAM, F-RAM or FERAM) for various applications including embedded memory and stand-alone memory. Due to its fast write / read speed and small size, FERAM is one of the candidates for the next generation of non-volatile memory (NVM). Therefore, it is very desirable to increase the density of FERAM. Summary of the invention

[0003] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a first channel; a second channel, the second channel being above the first channel; a gate structure, the gate structure surrounding the first channel and the second channel, wherein the gate structure comprises a ferroelectric (FE) layer surrounding the first channel and the second channel and a gate metal layer surrounding the FE layer; two first electrodes, the two first electrodes being connected to both sides of the first channel; two second electrodes, the two second electrodes being connected to both sides of the second channel; a dielectric layer, the dielectric layer being between the two first electrodes and the two second electrodes; and an internal spacer layer, the internal spacer layer being between the two first electrodes and the gate structure.

[0004] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a stack of multiple layers, each of the multiple layers comprising a first isolation layer, a semiconductor layer above the first isolation layer, and a first metal layer above the semiconductor layer; etching the stack of multiple layers to form a gate trench in a channel region of the stack of multiple layers; removing the first isolation layer and the first metal layer from the channel region to obtain a channel portion of the semiconductor layer exposed in the gate trench; making the first metal layer laterally recessed relative to the gate trench to form a gap between the first isolation layer and adjacent layers of the semiconductor layer; forming an internal spacer layer in the gap; forming a ferroelectric (FE) layer surrounding each of the channel portions of the semiconductor layer and above the sidewalls of the gate trench, wherein the internal spacer layer is laterally disposed between the FE layer and the first metal layer; and depositing a metal gate layer above the FE layer and filling the gate trench.

[0005] According to a third aspect of the present disclosure, a semiconductor device is provided, comprising: a plurality of transistors; and a 3D FERAM structure, wherein the 3D FERAM structure comprises a plurality of unit cells stacked vertically on each other, each unit cell comprising: a semiconductor layer, a ferroelectric (FE) layer surrounding a portion of the semiconductor layer, a gate layer above the FE layer and surrounding the portion of the semiconductor layer, an isolation layer below the semiconductor layer, a metal layer above the semiconductor layer, and a dielectric spacer layer above the semiconductor layer and between the FE layer and the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various structures are not drawn to scale and are drawn for illustration purposes only. In fact, the dimensions of various structures may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A perspective view partially illustrates a stacked FERAM structure according to various aspects of the present disclosure. Figure 1B and Figure 1C They are shown respectively Figure 1A Top view and cross-sectional view of the stacked FERAM structure. Figure 1D It shows that according to the embodiment Figure 1A A perspective view of some components of the stacked FERAM structure.

[0008] Figure 2A stacked FERAM structure (eg, Figure 1A A perspective view of a portion of a semiconductor device having a structure shown in FIG.

[0009] Figure 3 A flow chart of a method of forming a stacked FERAM structure according to various aspects of the present disclosure is shown.

[0010] Figure 4A , Figure 4B , Figure 4C , Figure 4D-1 , Figure 4D-2 , Figure 4D-3 , Figure 4E-1 , Figure 4E-2 , Figure 4E-3 , Figure 4F-1 , Figure 4F-2 , Figure 4F-3 , Figure 4G , Figure 4H , Fig. 4I , Figure 4J , Figure 4K and Figure 4L According to some embodiments of the present disclosure, Figure 3 Various perspective and cross-sectional views of a portion of a stacked FERAM structure during various manufacturing stages of the method in FIG.

[0011] Figure 5A , Figure 5B and Figure 5C A schematic diagram of a semiconductor device having a stacked FERAM structure according to some embodiments of the present disclosure is shown.

[0012] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E and Fig. 6F Various embodiments of single-bit (1T) FERAMs according to the present disclosure that may be stacked in a stacked FERAM structure are shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] In addition, spatially related terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to easily describe the relationship of one element or feature shown in the figure relative to another (one or more) elements or (one or more) features. These spatially related terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the figure. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used here can also be interpreted accordingly. Further, when "about," "approximately," etc. are used to describe a number or a range of numbers, unless otherwise stated, the term covers numbers within certain variations (e.g., + / -10% or other variations) of the number according to the knowledge of those skilled in the art in combination with the specific technology disclosed herein. For example, the term "about 5nm" can cover size ranges of 4.5nm to 5.5nm, 4.0nm to 5.0nm, etc.

[0015] The present disclosure generally relates to semiconductor manufacturing processes and structures thereof, and more specifically, to a process for forming a three-dimensional (3D) ferroelectric RAM (FeRAM, FERAM, F-RAM, or FRAM) memory array for realizing high-density memory. The disclosed 3D FERAM can be a stand-alone memory IC, or it can be integrated in an IC together with a MOSFET (e.g., a CMOSFET, a FinFET, a gate all-around (GAA) transistor (e.g., a nanowire FET and a nanosheet FET, or other types of multi-gate FETs)) to increase the functionality of the IC. The disclosed 3D FERAM realizes high-density memory. According to the present disclosure, a 3D FERAM array includes a plurality of layers stacked on each other, and each layer includes a two-dimensional (2D) array of 1-T (single channel or single transistor) FERAM cells. The 2D arrays at different layers are vertically aligned and stacked to form a 3D FERAM array. In each layer, the 1-T FERAM cells are arranged in rows and columns. FERAM cells in the same column share source and drain electrodes connected to the power line (SL) and bit line (BL) of the FERAM array. FERAM cells in the same row share the common word line (WL) of the FERAM array. Vertically aligned FERAM cells share a common gate electrode, which can be connected to WL. Access to the FERAM cells can be achieved by setting appropriate voltages for SL, BL, and WL. Dielectric internal spacers are provided between the gate electrode (e.g., a metal gate) and the source electrode / drain electrode to reduce the coupling capacitance between them. The present disclosure provides the following benefits. First, by using the disclosed 3D FERAM structure, a high-density FERAM memory array can be achieved. Second, in some embodiments, the source electrode / drain electrode is formed as part of the stack of the initial multilayer before the gate electrode is formed, and naturally connects all channel layers in the same row. Therefore, no additional process steps are required to form the source electrode / drain electrode (but it can certainly be achieved if necessary), thereby simplifying the manufacturing process. Third, the dielectric inner spacer reduces the coupling capacitance between the gate electrode and the source / drain electrodes, thereby increasing the operating speed of the FERAM. These and other aspects of the present disclosure are further described with reference to the accompanying drawings.

[0016] Figure 1A 2 shows a portion of a 3D FERAM structure 200 constructed according to an embodiment of the present disclosure. In the present disclosure, the 3D FERAM structure 200 is also referred to as a structure 200 or a FERAM array 200. Figure 1AIn the illustrated embodiment, the structure 200 includes three FERAM layers 201 stacked vertically to each other (along the "z" direction), and each FERAM layer 201 includes three FERAM cells (or unit cells) 250 arranged in a column (along the "y" direction). Figure 1A The illustrated embodiment includes 9 unit cells 250. In various embodiments, the structure 200 may include two or more (e.g., 2, 3, 4, 5, etc.) FERAM layers 201, and each FERAM layer 201 may include any number of unit cells 250 in a column and may include any number of columns to form a 2D array in the corresponding FERAM layer 201. Furthermore, in various embodiments, the 3D FERAM structure 200 may be a standalone memory device, an embedded memory integrated in an IC with other circuits, or part of a stacked 3D IC structure. In the present disclosure, for ease of discussion, the 3D FERAM structure 200 may be a standalone memory device, an embedded memory integrated in an IC with other circuits, or a part of a stacked 3D IC structure. Figure 1A In FIG. 1 , a column of unit cells 250 is arranged along the “y” direction and Figure 1A , a row of unit cells 250 is arranged along the “x” direction.

[0017] Figure 1B 2 shows a top view of a portion of a FERAM layer 201 according to an embodiment, Figure 1C shows a cross-sectional view of a portion of a structure 200 according to an embodiment, Figure 1D A perspective view is shown of certain components of the unit cell 250 in a disassembled state according to an embodiment.

[0018] refer to Figure 1D , the unit cell 250 includes an isolation structure 202, a semiconductor layer 204 (e.g., providing a source region 204s, a drain region 204d, and a channel region 204c for the unit cell 250), a FE layer 210 surrounding the channel region 204c, a metal layer 206 (e.g., providing a source electrode and a drain electrode thereon and supporting a source via 220 and a drain via 222, respectively), an inter-spacer feature (or internal spacer) 208, and a gate electrode 212 wrapped around the FE layer 210. The semiconductor layer 204 is disposed on the isolation structure 202. The metal layer 206 is disposed on the semiconductor layer 204. The internal spacer 208 is disposed on the semiconductor layer 204 and is disposed laterally (along the "x" direction) between the FE layer 210 and the metal layer 206.

[0019] refer to Figure 1A , Figure 1B and Figure 1C, structure 200 includes a gate spacer (or gate isolation) 214, which extends vertically from the isolation structure 199 (e.g., an interlayer dielectric layer) and is laterally arranged (along the "y" direction) between adjacent rows of gate electrodes 212 for isolating the gate electrodes 212 from each other.

[0020] In an embodiment, the isolation structure 202 includes a dielectric material, such as silicon nitride (Si3N4), or silicon oxide (SiO2), other suitable dielectric materials, or combinations of the foregoing. In some embodiments, the isolation structure 202 may have a thickness (along the "z" direction) in a range of about 10 nm to about 100 nm. In an embodiment, the semiconductor layer 204 includes an oxide semiconductor, such as indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), zinc oxide (ZnO), other suitable oxide semiconductors, or combinations of the foregoing. In another embodiment, the semiconductor layer 204 includes polysilicon. In yet another embodiment, the semiconductor layer 204 includes silicon or other suitable semiconductor materials. In some embodiments, the semiconductor layer 204 may have a thickness (along the "z" direction) in a range of about 10 nm to about 60 nm. In an embodiment, the metal layer 206 includes a conductive material, such as titanium nitride, tantalum nitride, ruthenium, tungsten, other suitable conductive materials, or combinations of the foregoing. In some embodiments, metal layer 206 may have a thickness (along the “z” direction) in a range from about 10 nm to about 60 nm.

[0021] In an embodiment, the FE layer 210 includes: hafnium oxide (HfO2); hafnium zirconium oxide (Hf x Zr 1-x O2); HfO2 doped with Si, Y, Ge, La or other suitable elements; Aluminum nitride (Al 1-x Sc xN); aluminum nitride (AlN); or other suitable ferroelectric materials. In some embodiments, the FE layer 210 may have a thickness in a range of about 5 nm to about 30 nm. In an embodiment, the internal spacer 208 includes a low-k dielectric material, for example, a dielectric material having a dielectric constant (k value) less than 10 (e.g., in a range of about 3 to about 10). For example, the internal spacer 208 may include SiCN, SiC, SiON, SiOCN, Al2O3, or other suitable dielectric materials. Because the FE layer 210 is typically a high-k dielectric material, forming the internal spacer 208 from a low-k (or lower k) dielectric material reduces the coupling capacitance between the gate electrode 212 and the metal layer 206, thereby increasing the operating speed of the MRAM 200. In some embodiments, the internal spacer 208 may have a length (dimension along the "x" direction) in a range of about 5 nm to about 30 nm. If the inner spacer 208 is too thin (e.g., less than about 5 nm), it may not be able to effectively reduce the coupling capacitance between the gate electrode 212 and the metal layer 206, and the risk of shorting the gate electrode 212 and the metal layer 206 may be too great. If the inner spacer 208 is too thick (e.g., greater than about 30 nm), it will unnecessarily increase the footprint of the unit cell 250 and will reduce the memory density of the 3D FERAM structure 200.

[0022] In an embodiment, the gate electrode 212 includes a p-type work function layer so that the FERAM unit cell 250 has a positive threshold voltage. For example, the gate electrode 212 may include a metal having a sufficiently large effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination of the foregoing. The gate electrode 212 may also include a low-resistance metal, such as aluminum, tungsten, cobalt, copper, and / or other suitable materials. In some embodiments, the gate electrode 212 includes an n-type work function layer, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or a combination of the foregoing. In some embodiments, the through holes 220 and 222 may each include one or more conductive materials, such as Co, W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, TaN, Ni, TiSiN, or a combination of the foregoing. In some embodiments, the gate isolation 214 includes a dielectric material, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials.

[0023] Figure 2A perspective view of a portion of a semiconductor device 100 (e.g., an integrated circuit) having a 3D FERAM structure 200 integrated therein according to various aspects of the present disclosure is shown. The FERAM layer 201 is patterned into a stepped structure 260. Vias 220 and 222 are disposed on the metal layer 206 on each step of the stepped structure 260. In addition to the features of the 3D FERAM structure 200 discussed above, the semiconductor device 100 also includes a source line (SL) 230 and a bit line (BL) 232 connected to the vias 220 and 222, respectively, and a word line (WL) 112 connected to the gate electrode 212. Figure 2 In the illustrated embodiment, WL 112 is also connected to a gate via 110 disposed above a gate electrode 106 of each transistor 150. Transistor 150 is implemented in or on substrate 102 and includes source / drain regions 104, gate electrodes 106, and gate spacers 108. Transistors 150 are isolated from each other by isolation structures (e.g., shallow trench isolation STI) 105. Transistor 150 may be a planar MOS transistor, a FinFET, a gate all around (GAA) transistor, or other types of transistors. Figure 2 In the illustrated embodiment, WL 112 is connected to gate electrode 212 from below the bottommost FERAM layer 201. In another embodiment, WL 112 is connected to gate electrode 212 from above the topmost FERAM layer 201. Figure 2 In the illustrated embodiment, the 3D FERAM structure 200 may be implemented at the Nth interconnect layer (or metal layer) of the semiconductor device 100 above the transistor 150, where N is a natural number. For example, the 3D FERAM structure 200 may be implemented at the 4th interconnect layer of the semiconductor device 100 (in other words, the 3D FERAM structure 200 may be implemented between the 3rd interconnect layer and the 5th interconnect layer of the semiconductor device 100). Figure 2 The device 100 shown in FIG. 1 is an example in which a 3D FERAM structure 200 is implemented at the BEOL of the device 100 and over a transistor 150 implemented at the FEOL of the device 100 .

[0024] Figure 3 1 is a flow chart of a method 10 for manufacturing a semiconductor device according to various aspects of the present disclosure. The present disclosure contemplates additional processes. Additional operations may be provided before, during, and after the method 10, and some of the operations described may be moved, replaced, or eliminated for additional embodiments of the method 10. FIG. 4A to FIG. 4L Description Method 10, FIG. 4A to FIG. 4LVarious perspective views and cross-sectional views of a 3D FERAM structure 200 at various manufacturing steps according to method 10 are shown according to some embodiments. In some embodiments, the 3D FERAM structure 200 is a stand-alone memory device. In some embodiments, the 3D FERAM structure 200 is an IC chip, a system on chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations of the foregoing. For example, the 3D FERAM structure 200 can be implemented at the back end of the IC (BEOL) and above a CMOS transistor implemented at the front end of the IC (FEOL). For clarity, the 3D FERAM structure 200 has been simplified. FIG. 4A to FIG. 4L , to better understand the inventive concepts of the present disclosure. Additional features may be added to the structure 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the structure 200.

[0025] At operation 12, method 10 ( Figure 1A ) provides a stack of multiple layers 201 as an intermediate structure of the 3D FERAM structure 200. Figure 4A In the present embodiment, each multilayer 201 includes an isolation layer 202, a semiconductor layer 204 on the isolation layer 202, and a metal layer 206 on the semiconductor layer 204. In the present embodiment, the 3D FERAM structure 200 further includes another isolation layer 202 on top of the stack of multilayers 201. In other words, both the bottommost layer and the topmost layer are isolation layers 202. Figure 4A The illustrated embodiment has three multilayers 201 in the stack. In various embodiments, the structure 200 may include two or more multilayers 201 in the stack. The materials and thicknesses of the layers 202, 204, and 206 have been described above with reference to Figures 1A to 1D Each of layers 202, 204, and 206 may be formed by CVD, PVD, ALD, or other suitable methods.

[0026] At operation 14, method 10 ( Figure 1A ) A gate trench 205 is formed in the stacked channel region 203 of the multilayer 201, as shown in FIG. Figure 4BAs shown. In an embodiment, operation 14 includes performing a photolithography process to form an etching mask over the structure 200. The photolithography process may include: forming a resist layer over the structure 200 (e.g., by spin coating); performing a pre-exposure bake process; performing an exposure process using a photomask; performing a post-exposure bake process; and developing the exposed resist layer in a developer. After development, the patterned resist layer includes a resist pattern corresponding to the photomask, wherein the resist pattern provides an opening corresponding to the gate trench 205 while covering the rest of the structure 200. Alternatively, the exposure process may be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or a combination of the foregoing.

[0027] After the etching mask is formed, operation 14 etches the stack of multiple layers 201 through the openings in the etching mask to form gate trenches 205. Operation 14 may apply one or more etching processes selectively targeting the materials of layers 206, 204, and 202. In an embodiment, operation 14 may apply a cyclic multi-etching process. For example, operation 14 may apply a first etching process for the material of layer 202, a second etching process for the material of layer 206, and a third etching process for the material of layer 204. Operation 14 may repeatedly apply the first, second, and third etching processes in a cyclic sequence until all layers in structure 200 are etched through. In the present embodiment, the various etching processes may include dry etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process can be implemented with fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), ammonia, argon, other suitable gases and / or plasmas, and / or combinations of the foregoing. After etching the gate trench 205, operation 14 removes the etching mask, for example, using resist stripping or other methods.

[0028] At operation 16, method 10 ( Figure 1A ) A suspended channel layer 204c is formed in the gate trench 205, such as Figure 4CAs shown. In an embodiment, operation 16 includes performing a photolithography process to form an etching mask over the structure 200. The etching mask exposes the channel region 203 of the structure 200 while covering the rest of the structure 200. After the etching mask is formed, operation 16 applies one or more etching processes that selectively etches the isolation layer 202 and the metal layer 206 while minimally etching (or even not etching) the semiconductor layer 204, thereby forming a suspended channel layer 204c. In an embodiment, the various etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. For example, the dry etching process may implement a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), other suitable gases and / or plasmas, and / or combinations of the foregoing. For example, the wet etching process may include etching in the following etchants: hydrofluoric acid (HF); diluted hydrofluoric acid (DHF); sulfuric acid (H2SO4); hydrogen chloride (HCl); phosphoric acid (H3PO4); or other suitable wet etchants. As a result of etching, the semiconductor layer 204 may extend slightly beyond the isolation layer 202 and the metal layer 206 (also in the "x" direction) toward the gate trench 205. Figure 4D-2 and Figure 4D-3 ).

[0029] At operation 18, method 10 ( Figure 1A ) The metal layer 206 is laterally recessed relative to the gate trench 205 to vertically form a gap 207 between the adjacent layers 204 and 202, such as Figure 4D-1 , Figure 4D-2 and Figure 4D-3 As shown. In an embodiment, the etching mask formed in operation 16 can be retained and reused during operation 18. Alternatively, before performing operation 18, the etching mask formed in operation 16 is removed. Operation 18 applies one or more etching processes that selectively etches the metal layer 206 while minimally etching (or even not etching) the isolation layer 202 and the semiconductor layer 204, thereby forming a gap 207. In an embodiment, the various etching processes may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In various embodiments, the gap 207 ( Figure 4D-3) is controlled to be in a range of about 5 nm to about 30 nm when measured along the “x” direction from the edge of the isolation layer 202 toward the gate trench 205. Moreover, the semiconductor layer 204 extends over the isolation layer 202 and the metal layer 206 along the “x” direction toward the gate trench 205. In some embodiments, the thickness t1 of the metal layer 206 (that is, the height of the gap 207 along the “z” direction) is in a range of about 10 nm to about 60 nm.

[0030] At operation 20, method 10 ( Figure 1A ) depositing an internal spacer layer on the surfaces of layers 202, 204 (including 204c) and 206 exposed by gate trench 205 and gap 207, such as Figure 4E-1 , Figure 4E-2 and Figure 4E-3 As shown. In particular, the inner spacer layer 208 fills the gap 207. In an embodiment, the inner spacer layer 208 includes a low-k dielectric material, for example, a dielectric material having a dielectric constant less than 10 (for example, in a range of about 3 to about 10). For example, the inner spacer layer 208 may include SiCN, SiC, SiON, SiOCN, Al2O3, or other suitable dielectric materials. Example low-k dielectric materials suitable for the inner spacer layer 208 include: fluorine-doped quartz glass, carbon-doped silicon oxide, dry gel, aerogel, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene (BCB), polyimide, other low-k dielectric materials, or a combination of the foregoing. In the present embodiment, ALD is used to deposit the inner spacer layer 208. In alternative embodiments, CVD or other suitable methods may be used to deposit the inner spacer layer 208. In the present embodiment, the inner spacer layer 208 has a thickness t2( in a range of about 5 nm to about 20 nm). Figure 4E-3 ). In particular, the thickness t2 is greater than half of the thickness t1 so that the inner spacer layer 208 blends into the gap 207 and completely fills the gap 207 .

[0031] At operation 22, method 10 ( Figure 1A ) deep etching the inner spacer layer 208 to remove it from the surfaces of the layers 202 and 204 facing the gate trench 205, thereby leaving the remaining portion of the inner spacer layer 208 in the gap 207 as the inner spacer feature 208, as shown in FIG. Figure 4F-1 , Figure 4F-2 and Figure 4F-3As shown. In various embodiments, the deep etching process may apply dry etching, wet etching, or reactive ion etching (which is adjusted to be selective for the material of the inner spacer layer 208 and to minimally etch (or even not etch) the semiconductor layer 204 and the isolation layer 202). For example, the deep etching process may apply an isotropic wet etching process. As a result of operation 22, the channel region 204c is exposed in the gate trench 205, and the surfaces of the layers 202 and 204 facing the gate trench 205 are also exposed. In an embodiment, the inner spacer feature 208 completely fills the gap 207, and the length L1 of the inner spacer feature 208 along the "x" direction is substantially equal to the depth d1 of the gap 207, as shown in FIG. Figure 4F-3 As shown. In another embodiment, the internal spacer feature 208 partially fills the gap 207, and the length L1 of the internal spacer feature 208 along the "x" direction is less than the depth d1 of the gap 207. For example, the length L1 is about 80% to about 90% of the depth d1. In various embodiments, the length L1 can be in the range of about 5nm to about 30nm. If the length L1 is too small (e.g., less than about 5nm), the internal spacer feature 208 may not effectively reduce the coupling capacitance between the gate electrode 212 and the metal layer 206, and the risk of shorting the gate electrode 212 and the metal layer 206 may be too great. If the length L1 is too large (e.g., greater than about 30nm), the internal spacer feature 208 will unnecessarily increase the footprint of the unit cell 250 and will reduce the memory density of the 3D FERAM structure 200.

[0032] At operation 23, method 10 ( Figure 1A ) Optionally, source / drain (S / D) features 209 are formed in the semiconductor layer 204. Figure 6B , Fig.6D , Fig. 6E and Fig. 6F As shown, in some embodiments of the MRAM unit cell 250, an S / D feature 209 may be formed. In the semiconductor layer 204 including an oxide semiconductor material (e.g., Figure 6B and Fig.6D In an embodiment shown in FIG. 2 , the S / D feature 209 may be formed by annealing the device 200 (e.g., in an oxygen environment or a nitrogen environment) so that the metal layer 206 reacts with the semiconductor layer 204 to form the S / D feature 209. In the case where the semiconductor layer 204 includes polysilicon or other non-oxide semiconductor materials (e.g., Fig. 6E and Fig. 6F In the embodiment shown in FIG. 1 , the S / D features 209 may be formed by doping the semiconductor layer 204 with appropriate p-type or n-type dopants (eg, by ion implantation).

[0033] At operation 24, method 10 ( Figure 1A ) deposits a FE layer 210 on various surfaces exposed in the gate trench 205 (including the surfaces of the isolation structure 202, the semiconductor layer 204, and the internal spacer feature 208). Figure 4G In particular, the FE layer 210 is deposited to surround each channel region 204c while leaving a space S between the FE layers 210 on vertically adjacent channel regions 204c (see Figure 1C ). The interval S is large enough so that the gate electrode 212 can be filled in the interval S for a desired deposition technique (e.g., ALD, CVD, PVD, or plating). In an embodiment, the FE layer 210 is deposited to have a substantially uniform thickness on the various surfaces described above. In various embodiments, the thickness of the FE layer 210 may be in the range of about 5 nm to about 30 nm. In an embodiment, the FE layer 210 is deposited using ALD to control the accuracy of the deposition thickness. In some embodiments, the FE layer 210 may be deposited using CVD, PVD, or other deposition techniques. In the present embodiment, the FE layer 210 includes: hafnium oxide (HfO2); hafnium zirconium oxide (Hf x Zr 1-x O2); HfO2 doped with Si, Y, Ge, La or other suitable elements; Aluminum nitride (Al 1-x Sc x N); aluminum nitride (AlN); or other suitable ferroelectric materials.

[0034] In some embodiments, before depositing the FE layer 210, operation 24 may optionally deposit an interface layer 211 on various surfaces exposed in the gate trench 205, and then deposit the FE layer 210 on the interface layer. Figure 6B , Fig.6D , Fig. 6E and Fig. 6F An interface layer 211 is provided in the illustrated embodiment. For example, the interface layer can increase adhesion between the FE layer 210 and various surfaces below the FE layer 210. The material for the interface layer 211 can be selected according to the material of the semiconductor layer 204. In various embodiments, when the semiconductor layer 204 includes an oxide semiconductor material, the interface layer 211 may include aluminum oxide (e.g., Al2O3), silicon oxide (e.g., SiO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), or other suitable materials. In various embodiments, when the semiconductor layer 204 includes silicon, polysilicon, or another non-oxide semiconductor material, the interface layer 211 may include silicon oxide (e.g., SiO2), a native oxide of a material included in the semiconductor layer 204, or other suitable materials.

[0035] At operation 26, method 10 ( Figure 1A) depositing one or more gate electrode layers 212 in the gate trench 205, wherein the gate electrode layers 212 fill the gate trench 205 and surround the FE layer 210, such as Figure 4H As shown in . In an embodiment, the gate electrode 212 includes a p-type work function layer, for example, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination of the foregoing. In an alternative embodiment, the gate electrode 212 includes an n-type work function layer, for example, titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or a combination of the foregoing. In some embodiments, the gate electrode 212 may include both (one or more) p-type work function layers and (one or more) n-type work function layers to achieve the desired work function. In some embodiments, the gate electrode 212 may also include a low-resistance metal, for example, aluminum, tungsten, cobalt, copper, and / or other suitable materials deposited on the p-type and / or n-type work function layers. The gate electrode 212 may be deposited using ALD, CVD, PECVD, electroplating, or other suitable methods.

[0036] At operation 28, method 10 ( Figure 1A ) to etch the gate electrode 212 and the FE layer 210 to form a gate isolation trench 215 (eg, Fig. 4I ). As a result of operation 28, a plurality of stacks of unit cells 250 are formed. Operation 28 may involve a plurality of processes, such as photolithography and etching. In an embodiment, operation 28 includes performing a photolithography process to form an etching mask (e.g., a structure including a resist pattern) over structure 200, similar to the photolithography process discussed with reference to operation 14. The etching mask provides an opening corresponding to the gate isolation trench 215. After the etching mask is formed, operation 28 etches the gate electrode 212 and the FE layer 210 through the opening in the etching mask to form the gate isolation trench 215. Operation 28 may apply one or more etching processes that selectively target the materials of layers 212 and 210 without (or minimally) etching the isolation structure 202, the semiconductor layer 204, and the internal spacer feature 208. In the present embodiment, the various etching processes may include dry etching, reactive ion etching (RIE), and / or other suitable processes. After etching the gate isolation trench 215, operation 28 removes the etching mask, for example, using resist stripping or other methods.

[0037] At operation 30, method 10 ( Figure 1A ) forming a gate isolation 214 in the gate isolation trench 215, (eg, Figure 4J). In an embodiment, after the dielectric material is deposited and overfilled in the gate isolation trench 215, operation 30 performs a CMP process to planarize the top surface of the structure 200 and expose the gate electrode 212. The remaining dielectric material becomes the gate isolation 214. In some embodiments, the gate isolation 214 includes a dielectric material, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating materials. In various embodiments, the gate isolation 214 can be deposited using CVD, PECVD, flowable CVD, or other suitable methods.

[0038] At operation 32, method 10 (FIG. 1a) forms a stepped structure 260 (e.g., as shown in FIG. 4k). Each step in the stepped structure 260 includes a FERAM layer 201. In the central region (channel region) of the FERAM layer 201, there are the following features: a plurality of channel regions 204c arranged in a column (along the "y" direction) (see FIG. Figure 1A , Figure 1B and Figure 1C ); FE layers 210 surrounding a plurality of channel regions 204c, respectively; gate electrodes 212 surrounding the FE layers 210, respectively; and gate isolations 214 separating and isolating the gate electrodes 212. On both sides of the central region, the FERAM layer 201 includes an isolation structure 202, a semiconductor layer 204 (source and drain regions), an internal spacer feature 208, and a metal layer 206. The stepped structure 260 may be formed using multiple photolithography, etching, and trimming processes. For example, a first etching mask is formed to cover an area of ​​the structure 200 corresponding to the uppermost step of the stepped structure 260, and then the structure 200 is etched until the metal layer 206 is exposed. Then, a second etching mask is formed to cover an area of ​​the structure 200 corresponding to the uppermost step of the stepped structure 260 and the next step of the uppermost step, and then the structure 200 is etched until the next metal layer 206 is exposed. This process may be repeated until the stepped structure 260 is formed. The various etching processes may include dry etching, reactive ion etching (RIE), and / or other suitable processes. Photolithography and trimming processes may be used to achieve a desired shape to form an etching mask for the various etching processes.

[0039] At operation 34, method 10 ( Figure 1A ) vias 220 and 222 are formed to contact the metal layer 206 in the S / D region at each step of the step structure 260, and via 224 is formed to contact the gate electrode 212, for example, as Figure 4LAs shown. In an embodiment, operation 34 includes: depositing one or more dielectric layers (not shown) on the stepped structure 260; forming an etching mask on the one or more dielectric layers (e.g., using a photolithography process), wherein the etching mask provides openings corresponding to the through-holes 220, 222, and 224; etching through-holes into the one or more dielectric layers to expose the metal layer 206 at each step of the stepped structure 260; and depositing one or more conductive materials in the through-holes to form the through-holes 220, 222, and 224. For simplicity, the one or more dielectric layers are not shown. Figure 4L . The one or more dielectric layers may include an oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluoride-doped silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG)), and / or other suitable dielectric materials. The one or more dielectric layers may be formed by PECVD (plasma enhanced CVD), FCVD (flowable CVD), or other suitable methods. The through holes 220, 222, and 224 may include one or more conductive materials (e.g., Co, W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, TaN, Ni, TiSiN, or a combination of the foregoing) and may be formed by ALD, CVD, PVD, electroplating, and / or other suitable processes.

[0040] At operation 36, method 10 ( Figure 1A ) performs further manufacturing. For example, it can form an interconnect layer above the MRAM 200. For example, the interconnect layer can include a word line (WL), a bit line (BL), and a source line (SL) that are electrically connected to the vias 224, 222, and 220, respectively. For example, Figure 2 SL 230 and BL 232 are shown electrically connected to vias 220 and 222, respectively. Figure 2 The WL is shown formed below the MRAM 200 in an embodiment. In an alternative embodiment (not shown), the WL may be formed above the MRAM 200 and electrically connected to the gate via 224.

[0041] Figure 5A A schematic top view of an MRAM 200 according to an embodiment is shown. Figure 5B Shows Figure 5A A portion of the 3D equivalent circuit of the MRAM 200 is shown. Figure 5C Shows Figure 5A A portion of a 2D compression circuit of an MRAM 200 is shown in FIG. Figure 5A, word line WL is oriented along the "x" direction and is connected to the gate electrode through via 224. Bit line BL and source line SL are oriented along the "y" direction and are connected to the source / drain features through vias 222 and 220, respectively. Figure 5A In the illustrated embodiment, each column of MRAM cells has m bit lines BL and m source lines SL (e.g., there are m steps in the staircase structure 260). Two columns of MRAM cells are arranged in a staggered manner, and each column provides a stack of L unit cells 250 (therefore, two columns provide a stack of 2L unit cells 250), wherein each stack of unit cells 250 is addressed by a word line WL. The word line WL is routed to a WL decoder. The bit line is routed to a BL decoder. The source line is routed to a SL decoder. By controlling the WL decoder, the BL decoder, and the SL decoder, each MRAM unit cell 250 can be accessed.

[0042] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E and Fig. 6F Various embodiments of a portion of a unit cell 250 that can be implemented in an MRAM 200 according to the present disclosure are shown. Specifically, Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E and Fig. 6F Schematic cross-sectional views of the semiconductor layer 204 (including the optional S / D 209 and the channel region 204c), the metal layer 206, the optional interface layer 211, the FE layer 210, and the gate electrode 212 in various configurations are shown. These are non-limiting examples of unit cells 250 according to the present disclosure. Fig. 6A In the illustrated embodiment, the FE layer 210 is directly on the semiconductor layer 204 including the oxide semiconductor material. This embodiment does not include the S / D 209 and the interface layer 211. Figure 6B In the illustrated embodiment, the FE layer 210 is directly on such an interface layer 211, which is directly on the semiconductor layer 204 including an oxide semiconductor material. This embodiment does not include the S / D 209. Figure 6C In the illustrated embodiment, the FE layer 210 is directly on the semiconductor layer 204 including the oxide semiconductor material. In this embodiment, the semiconductor layer 204 includes the S / D 209 formed in the semiconductor layer 204. Fig.6DIn the illustrated embodiment, the FE layer 210 is directly on such an interface layer 211, which is directly on the semiconductor layer 204 including an oxide semiconductor material. In this embodiment, the semiconductor layer 204 includes a S / D 209 formed in the semiconductor layer 204. Fig. 6E In the illustrated embodiment, the FE layer 210 is directly on such an interface layer 211, which is directly on the semiconductor layer 204 including polycrystalline silicon. In this embodiment, the semiconductor layer 204 includes S / D 209 formed in the semiconductor layer 204. Compared with the embodiment using crystalline silicon as the semiconductor material in the semiconductor layer 204, the use of polycrystalline silicon as the semiconductor material in the semiconductor layer 204 reduces the cost of manufacturing the MRAM 200. Fig. 6F In the illustrated embodiment, the FE layer 210 is directly on such an interface layer 211, which is directly on the semiconductor layer 204 including silicon (e.g., crystalline silicon) or another suitable semiconductor material. In this embodiment, the semiconductor layer 204 includes S / D 209 formed in the semiconductor layer 204. Fig. 6E and Fig. 6F In the embodiment shown in FIG. 1 , in an embodiment, the interface layer 211 may include silicon oxide (SiO 2 ). Fig. 6A , Figure 6B , Figure 6C and Fig.6D In the embodiment shown in FIG. 1 , the semiconductor layer 204 may include indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tin oxide (ITO), zinc oxide (ZnO), other suitable oxide semiconductors, or a combination of the foregoing. Figure 6B In some embodiments, the interface layer 211 may include aluminum oxide (Al2O3), silicon oxide (SiO2), or other suitable materials. Fig.6D In various embodiments, the interface layer 211 may include aluminum oxide (eg, Al 2 O 3 ), silicon oxide (eg, SiO 2 ), hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), or other suitable materials, as shown in the embodiment.

[0043] Embodiments of the present disclosure provide one or more of the following advantages, but this is not intended to be limiting. For example, embodiments of the disclosed 3D FERAM structure implement a high-density FERAM memory array. For another example, in some embodiments, the source / drain electrodes of the disclosed FEAM array are formed as part of the stack of the initial multiple layers before the gate electrode is formed, and naturally connect all channel layers in the same row. Therefore, no additional process steps are required to form the source / drain electrodes, thereby simplifying the manufacturing process. For another example, the dielectric internal spacer in the disclosed FEAM array reduces the coupling capacitance between the gate electrode and the source / drain electrodes, thereby increasing the operating speed of the FERAM array.

[0044] In one exemplary aspect, the present disclosure relates to a device, the device comprising: a first channel; a second channel, the second channel being above the first channel; and a gate structure, the gate structure surrounding the first channel and the second channel, wherein the gate structure comprises a ferroelectric (FE) layer surrounding the first channel and the second channel and a gate metal layer surrounding the FE layer. The device also comprises: two first electrodes, the two first electrodes being connected to both sides of the first channel; two second electrodes, the two second electrodes being connected to both sides of the second channel; a dielectric layer, the dielectric layer being between the two first electrodes and the two second electrodes; and an internal spacer layer, the internal spacer layer being between the two first electrodes and the gate structure.

[0045] In some embodiments, the internal spacer layer is also between the two second electrodes and the gate structure. In an embodiment, the device further includes: a gate via disposed on and connected to the gate structure; a source via disposed on and connected to one of the two first electrodes; a bit line via disposed on and connected to the other of the two first electrodes. In another embodiment, the device further includes: one or more transistors; and an Nth metal layer above the one or more transistors, N being a natural number, wherein the first channel is disposed above the Nth metal layer. In yet another embodiment, the device further includes an interface layer between the FE layer and each of the first channel and the second channel.

[0046] In an embodiment of the device, the FE layer includes: HfO2; Hf x Zr 1-x O2; HfO2 doped with Si, Y, Ge or La; AlScN; or AlN. In another embodiment, the first channel and the second channel include an oxide semiconductor or polysilicon. In some embodiments, the inner spacer layer includes a dielectric material having a dielectric constant less than 10.

[0047] In an embodiment of the device, the first electrode and the second electrode include TiN, TaN, Ru or W. In another embodiment of the device, the first electrode and the second electrode extend longitudinally along a first direction, and the first electrode extends longer than the second electrode.

[0048] In another example aspect, the present disclosure relates to a device comprising: a plurality of transistors; and a 3D FERAM structure above the plurality of transistors, wherein the 3D FERAM structure comprises a plurality of unit cells stacked vertically on one another, each unit cell comprising: a semiconductor layer, a ferroelectric (FE) layer surrounding a portion of the semiconductor layer, a gate layer above the FE layer and surrounding the portion of the semiconductor layer, an isolation layer below the semiconductor layer, a metal layer above the semiconductor layer, and a dielectric spacer layer above the semiconductor layer and between the FE layer and the metal layer.

[0049] In an embodiment of the device, the dielectric spacer layer comprises a dielectric material having a dielectric constant less than 10. In an embodiment, the FE layer comprises HfO2, HfxZr1-xO2, HfO2 doped with Si, Y, Ge or La, AlScN, or AlN; the metal layer comprises TiN, TaN, Ru or W; the semiconductor layer comprises an oxide semiconductor or polysilicon. In an embodiment, the device further comprises an interface layer between the FE layer and the portion of the semiconductor layer.

[0050] In another example aspect, the present disclosure relates to a method, the method comprising: forming a stack of multiple layers, wherein each of the multiple layers comprises a first isolation layer, a semiconductor layer on the first isolation layer, and a first metal layer on the semiconductor layer. The method also comprises: etching the stack of multiple layers to form a gate trench in a channel region of the stack of multiple layers; removing the first isolation layer and the first metal layer from the channel region to obtain a channel portion of the semiconductor layer exposed in the gate trench; recessing the first metal layer laterally relative to the gate trench to form a gap between the first isolation layer and adjacent layers of the semiconductor layer; forming an internal spacer layer in the gap; forming a ferroelectric (FE) layer surrounding each of the channel portions of the semiconductor layer and on the sidewalls of the gate trench, wherein the internal spacer layer is laterally disposed between the FE layer and the first metal layer; and depositing a metal gate layer on the FE layer and filling the gate trench.

[0051] In an embodiment of the method, forming an internal spacer layer includes: depositing a dielectric material that surrounds a channel portion of the semiconductor layer and fills a gap; and etching the dielectric material so that the dielectric material is removed from an outer surface of the channel portion of the semiconductor layer but at least a portion of the dielectric material remains in the gap, wherein the portion of the dielectric material that remains in the gap becomes the internal spacer layer.

[0052] In an embodiment, the method further includes etching the metal gate layer and the FE layer to form a metal gate separated by an isolation trench, and filling the isolation trench with a second isolation layer. In another embodiment, the method includes etching the second isolation layer and a stack of multiple layers to form a stepped structure having a plurality of steps one above another, each step including: a portion of the second isolation layer, two portions of the internal spacer layer adjacent to the portion of the second isolation layer, and two portions of one of the multiple layers sandwiching the two portions of the second isolation layer and the internal spacer layer. In another embodiment, the method includes forming a through hole on the first metal layer at each step in the plurality of steps. In some embodiments of the method, the internal spacer layer includes a dielectric material having a dielectric constant less than 10.

[0053] In another example aspect, the present disclosure relates to a method comprising: forming a stack of multiple layers, wherein each of the multiple layers comprises: a first isolation layer, a semiconductor layer above the first isolation layer, and a first metal layer above the semiconductor layer; forming a gate trench in a channel region of the stack of multiple layers, wherein a channel portion of the semiconductor layer is exposed in the gate trench; causing the first metal layer to be laterally recessed relative to the gate trench to obtain a gap between the first isolation layer and adjacent layers of the semiconductor layer; forming an internal spacer layer in the gap; forming a ferroelectric (FE) layer surrounding each channel portion of the semiconductor layer and above the sidewalls of the gate trench, wherein the internal spacer layer is laterally disposed between the FE layer and each first metal layer; forming a metal gate above the FE layer, wherein each metal gate is bonded to multiple channel portions of the semiconductor layer stacked on top of each other.

[0054] In an embodiment of the method, forming a gate trench includes: etching a stack of multiple layers in a channel region of the stack of multiple layers through a first etching process to obtain a gate trench; removing a first isolation layer and a first metal layer from the channel region through a second etching process different from the first etching process, thereby exposing a channel portion of the semiconductor layer in the gate trench.

[0055] In an embodiment of the method, forming an internal spacer layer includes: depositing a dielectric material that surrounds a channel portion of the semiconductor layer and fills a gap; etching the dielectric material so that the dielectric material is removed from the channel portion of the semiconductor layer but at least a portion of the dielectric material remains in the gap, wherein the portion of the dielectric material that remains in the gap becomes the internal spacer layer.

[0056] In an embodiment of the method, the formation of the metal gate includes: depositing one or more metal gate layers, which are above the FE layer and fill the gate trench; etching one or more metal gate layers and the FE layer to form a metal gate separated by an isolation trench; and filling the isolation trench with a second isolation layer.

[0057] The features of some embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the present disclosure. Those of ordinary skill in the art will recognize that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those of ordinary skill in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can be variously changed, substituted and altered without departing from the spirit and scope of the present disclosure.

[0058] Example 1. A semiconductor device, comprising: a first channel; a second channel, the second channel being above the first channel; a gate structure, the gate structure surrounding the first channel and the second channel, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first channel and the second channel and a gate metal layer surrounding the FE layer; two first electrodes, the two first electrodes being connected to both sides of the first channel; two second electrodes, the two second electrodes being connected to both sides of the second channel; a dielectric layer, the dielectric layer being between the two first electrodes and the two second electrodes; and an internal spacer layer, the internal spacer layer being between the two first electrodes and the gate structure.

[0059] Example 2. The semiconductor device of Example 1, wherein the inner spacer layer is also between the two second electrodes and the gate structure.

[0060] Example 3. The semiconductor device according to Example 1 further includes: a gate through hole, which is arranged on the gate structure and connected to the gate structure; a source through hole, which is arranged on one of the two first electrodes and connected to the one first electrode; and a bit line through hole, which is arranged on the other first electrode of the two first electrodes and connected to the other first electrode.

[0061] Example 4. The semiconductor device according to Example 1 further includes: one or more transistors; and an Nth metal layer, the Nth metal layer being above the one or more transistors, N being a natural number, wherein the first channel is disposed above the Nth metal layer.

[0062] Example 5. The semiconductor device of Example 1, further comprising: an interface layer between the FE layer and each of the first channel and the second channel.

[0063] Example 6. The semiconductor device according to Example 1, wherein the FE layer comprises: HfO2; Hf x Zr 1-x O2; HfO2 doped with Si, Y, Ge or La; AlScN; or AlN.

[0064] Example 7. The semiconductor device of Example 1, wherein the first channel and the second channel include an oxide semiconductor or polysilicon.

[0065] Example 8. The semiconductor device of Example 1, wherein the inner spacer layer comprises a dielectric material having a dielectric constant less than 10.

[0066] Example 9. The semiconductor device of Example 1, wherein the two first electrodes and the two second electrodes include TiN, TaN, Ru, or W.

[0067] Example 10 The semiconductor device according to Example 1, wherein the two first electrodes and the two second electrodes extend along a first direction in a longitudinal direction, and the two first electrodes extend longer than the two second electrodes.

[0068] Example 11. A method for manufacturing a semiconductor device, comprising: forming a stack of multiple layers, each of the multiple layers including a first isolation layer, a semiconductor layer above the first isolation layer, and a first metal layer above the semiconductor layer; etching the stack of multiple layers to form a gate trench in a channel region of the stack of multiple layers; removing the first isolation layer and the first metal layer from the channel region to obtain a channel portion of the semiconductor layer exposed in the gate trench; causing the first metal layer to be laterally recessed relative to the gate trench to form a gap between the first isolation layer and adjacent layers of the semiconductor layer; forming an internal spacer layer in the gap; forming a ferroelectric (FE) layer, the FE layer surrounding each of the channel portions of the semiconductor layer and above the sidewalls of the gate trench, wherein the internal spacer layer is laterally disposed between the FE layer and the first metal layer; and depositing a metal gate layer, the metal gate layer being above the FE layer and filling the gate trench.

[0069] Example 12. A method according to Example 11, wherein forming the internal spacer layer includes: depositing a dielectric material, the dielectric material surrounding the channel portion of the semiconductor layer and filling the gap; and etching the dielectric material so that the dielectric material is removed from the outer surface of the channel portion of the semiconductor layer but at least a portion of the dielectric material remains in the gap, wherein the portion of the dielectric material remaining in the gap becomes the internal spacer layer.

[0070] Example 13. The method according to Example 11 further includes: etching the metal gate layer and the FE layer to form a metal gate separated by an isolation trench; and filling the isolation trench with a second isolation layer.

[0071] Example 14. The method according to Example 13 further includes: etching the second isolation layer and the stack of the multilayers to form a stepped structure, the stepped structure having a plurality of steps one above another, each step including: a portion of the second isolation layer, two portions of the internal spacer layer adjacent to the portion of the second isolation layer, and two portions of one of the multilayers sandwiching the portion of the second isolation layer and the two portions of the internal spacer layer.

[0072] Example 15. The method of Example 14 further includes: forming a through hole on the first metal layer at each step of the plurality of steps.

[0073] Example 16. The method of Example 11, wherein the inner spacer layer comprises a dielectric material having a dielectric constant less than 10.

[0074] Example 17. A semiconductor device comprising: a plurality of transistors; and a 3D FERAM structure, the 3D FERAM structure being above the plurality of transistors, wherein the 3D FERAM structure comprises a plurality of unit cells stacked vertically on each other, each unit cell comprising: a semiconductor layer, a ferroelectric (FE) layer surrounding a portion of the semiconductor layer, a gate layer above the FE layer and surrounding the portion of the semiconductor layer, an isolation layer below the semiconductor layer, a metal layer above the semiconductor layer, and a dielectric spacer layer above the semiconductor layer and between the FE layer and the metal layer.

[0075] Example 18. The semiconductor device of Example 17, wherein the dielectric spacer layer comprises a dielectric material having a dielectric constant less than 10.

[0076] Example 19. The semiconductor device of Example 17, further comprising: an interface layer between the FE layer and the portion of the semiconductor layer.

[0077] Example 20. The semiconductor device according to Example 17, wherein the FE layer comprises HfO2, Hf x Zr 1-x O2, HfO2 doped with Si, Y, Ge or La, AlScN, or AlN; and the metal layer includes TiN, TaN, Ru or W; and the semiconductor layer includes an oxide semiconductor or polysilicon.

Claims

1. A semiconductor device, comprising: one or more transistors; An Nth metal layer, the Nth metal layer being above the one or more transistors, where N is a natural number; A first channel, wherein the first channel is disposed on the Nth metal layer; a second channel, the second channel being above the first channel; a gate structure, the gate structure surrounding the first channel and the second channel, wherein the gate structure comprises a ferroelectric layer surrounding the first channel and the second channel and a gate metal layer surrounding the ferroelectric layer; two first electrodes, the two first electrodes being connected to two sides of the first channel; two second electrodes, the two second electrodes being connected to two sides of the second channel; a dielectric layer between the two first electrodes and the two second electrodes; and An inner spacer layer is between the two first electrodes and the gate structure.

2. The semiconductor device according to claim 1, wherein The inner spacer layer is also between the two second electrodes and the gate structure.

3. The semiconductor device according to claim 1, further comprising: a gate via disposed on and connected to the gate structure; a source through hole, the source through hole being disposed on one of the two first electrodes and connected to the one first electrode; as well as A bit line via is provided on the other first electrode of the two first electrodes and connected to the other first electrode.

4. The semiconductor device according to claim 1, further comprising: An interface layer is between the ferroelectric layer and each of the first channel and the second channel.

5. The semiconductor device according to claim 1, wherein The ferroelectric layer comprises: HfO2; Hf x Zr 1-x O2; HfO2 doped with Si, Y, Ge or La; AlScN; or AlN.

6. The semiconductor device according to claim 1, wherein The first channel and the second channel include an oxide semiconductor or polysilicon.

7. The semiconductor device according to claim 1, wherein The inner spacer layer includes a dielectric material having a dielectric constant less than 10.

8. The semiconductor device according to claim 1, wherein The first electrode and the second electrode include TiN, TaN, Ru or W.

9. The semiconductor device according to claim 1, wherein: The first electrode and the second electrode extend along a first direction in a longitudinal direction, and the first electrode extends longer than the second electrode.

10. A method for manufacturing a semiconductor device, comprising: forming a stack of multiple layers, each of the multiple layers comprising a first isolation layer, a semiconductor layer on the first isolation layer, and a first metal layer on the semiconductor layer; etching the multi-layer stack to form a gate trench in a channel region of the multi-layer stack; removing the first isolation layer and the first metal layer from the channel region, thereby obtaining a channel portion of the semiconductor layer exposed in the gate trench; recessing the first metal layer laterally relative to the gate trench to form a gap between the first isolation layer and an adjacent layer of the semiconductor layer; forming an inner spacer layer in the gap; forming a ferroelectric layer surrounding each of the channel portions of the semiconductor layer and over sidewalls of the gate trench, wherein the inner spacer layer is laterally disposed between the ferroelectric layer and the first metal layer; as well as A metal gate layer is deposited over the ferroelectric layer and fills the gate trench.

11. The method according to claim 10, wherein: Forming the inner spacer layer includes: depositing a dielectric material surrounding the channel portion of the semiconductor layer and filling the gap; and The dielectric material is etched such that the dielectric material is removed from an outer surface of the channel portion of the semiconductor layer but at least a portion of the dielectric material remains in the gap, wherein the portion of the dielectric material remaining in the gap becomes the inner spacer layer.

12. The method according to claim 10, further comprising: etching the metal gate layer and the ferroelectric layer to form metal gates separated by isolation trenches; as well as The isolation trench is filled with a second isolation layer.

13. The method according to claim 12, further comprising: The second isolation layer and the stack of the multiple layers are etched to form a stepped structure having a plurality of steps one above another, each step comprising: a portion of the second isolation layer, two portions of the internal spacer layer adjacent to the portion of the second isolation layer, and two portions of one of the multiple layers sandwiching the portion of the second isolation layer and the two portions of the internal spacer layer.

14. The method according to claim 13, further comprising: A through hole is formed on the first metal layer at each step of the plurality of steps.

15. The method according to claim 10, wherein: The inner spacer layer includes a dielectric material having a dielectric constant less than 10.

16. A semiconductor device comprising: Multiple transistors; as well as A 3D FERAM structure, the 3D FERAM structure is above the multiple transistors, wherein the 3D FERAM structure includes a plurality of unit cells stacked vertically on each other, each unit cell including: a semiconductor layer, a ferroelectric layer surrounding a portion of the semiconductor layer, a gate layer above the ferroelectric layer and surrounding the portion of the semiconductor layer, an isolation layer below the semiconductor layer, a metal layer above the semiconductor layer, and a dielectric spacer layer above the semiconductor layer and between the ferroelectric layer and the metal layer.

17. The semiconductor device according to claim 16, wherein: The dielectric spacer layer includes a dielectric material having a dielectric constant less than 10.

18. The semiconductor device according to claim 16, further comprising: An interface layer is between the ferroelectric layer and the portion of the semiconductor layer.

19. The semiconductor device according to claim 16, wherein: The ferroelectric layer includes HfO2, Hf x Zr 1-x O2, HfO2 doped with Si, Y, Ge or La, AlScN, or AlN; the metal layer includes TiN, TaN, Ru or W; and the semiconductor layer includes an oxide semiconductor or polysilicon.

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