Semiconductor device

Abstract

A transistor including an oxide semiconductor film having stable electric characteristics is provided. In the transistor, a first oxide semiconductor film which can at least inhibit release of oxygen from an oxide film capable of releasing oxygen by heating is formed over the oxide film. A second oxide semiconductor film is formed over the first oxide semiconductor film. By employing a structure in which oxide semiconductor films are stacked, release of oxygen from the oxide film can be inhibited when the second oxide semiconductor film is formed, and oxygen is released from the oxide film by heat treatment performed later. Thus, oxygen can be appropriately supplied to the second oxide semiconductor film through the first oxide semiconductor film through which oxygen can pass. By supplying oxygen to the second oxide semiconductor film, oxygen vacancies are inhibited, and stable electric characteristics are obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device including an oxide semiconductor.

[0002] Note that in this specification, a semiconductor device means all devices that can function by utilizing semiconductor characteristics, and a transistor, an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices. BACKGROUND

[0003] A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. This transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (display devices). As a semiconductor thin film which can be used for a transistor, a silicon-based semiconductor material is widely known. However, an oxide semiconductor has attracted attention as another material.

[0004] For example, a transistor in which an active layer of the transistor includes an amorphous oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) has been disclosed (see Patent Document 1).

[0005] [Patent Document 1] Japanese Published Patent Application No. 2006-165528

[0006] A transistor including an oxide semiconductor film has characteristics that it operates at higher speed (also referred to as higher field-effect mobility) than a transistor including an amorphous silicon film and is manufactured more easily than a transistor including a polycrystalline silicon film.

[0007] However, a transistor including an oxide semiconductor film has been pointed out to have several problems, one of which is instability of electrical characteristics of the transistor. Specifically, a problem in which threshold voltage of the transistor is negatively shifted due to irradiation with visible light or ultraviolet light or a bias-temperature stress test (BT stress test), and the transistor tends to be normally on has been pointed out. One of the reasons for the problem is oxygen deficiency in the oxide semiconductor film.

[0008] For example, when the oxide semiconductor film is amorphous, the bonding state between a metal atom and an oxygen atom in the oxide semiconductor film is not ordered, so that oxygen deficiency is easily caused. Thus, a change in electrical characteristics (e.g., electrical conductivity) of the oxide semiconductor film is likely to be caused. Such a change can cause a change in electrical characteristics of the transistor, which leads to a reduction in reliability of a semiconductor device including the transistor.

[0009] Further, as one of methods for reducing oxygen vacancies generated in the oxide semiconductor film, there is a method in which oxygen is supplied to the oxide semiconductor film from an oxide film or the like formed in the vicinity of the oxide semiconductor film to fill the oxygen vacancies. However, before the oxide semiconductor film is formed (in other words, before oxygen is supplied to the oxide semiconductor film), oxygen is released from the oxide film or the like formed in the vicinity of the oxide semiconductor film due to heat treatment or the like, and thus oxygen cannot be sufficiently supplied to the oxide semiconductor film. SUMMARY

[0010] In view of the above problems, an object of one embodiment of the present application is to provide a transistor including an oxide semiconductor film, which has stable electric characteristics.

[0011] The first oxide semiconductor film in which release of oxygen from the oxide film is at least inhibited is formed over the oxide film from which oxygen can be released by heat, and the second oxide semiconductor film is formed over the first oxide semiconductor film. With the above structure in which the oxide semiconductor films are stacked, release of oxygen from the oxide film can be inhibited when the second oxide semiconductor film is formed, and oxygen can be released from the oxide film by heat treatment performed later. Thus, oxygen can be appropriately supplied to the second oxide semiconductor film through the first oxide semiconductor film. By supplying oxygen to the second oxide semiconductor film, generation of oxygen vacancies can be inhibited, and stable electric characteristics can be obtained.

[0012] Further, the first oxide semiconductor film and the second oxide semiconductor film are oxide films each containing indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film. Thus, the second oxide semiconductor film is formed over the first oxide semiconductor film containing the same kind of material, and a film including crystals grown from the interface with the first oxide semiconductor film can be formed. This will be described in detail below.

[0013] One embodiment of the present application is a semiconductor device including a first oxide semiconductor film and a second oxide semiconductor film formed over the first oxide semiconductor film. Each of the first oxide semiconductor film and the second oxide semiconductor film is an oxide film containing indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0014] Another embodiment of the present application is a semiconductor device including: a first oxide semiconductor film formed over an insulating film; a second oxide semiconductor film formed over the first oxide semiconductor film; a gate insulating film formed over the second oxide semiconductor film; and a gate electrode formed in a region which is in contact with the gate insulating film and overlaps with the second oxide semiconductor film. Each of the first oxide semiconductor film and the second oxide semiconductor film is an oxide film containing at least indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0015] Note that the content in this specification and the like is the proportion of the components included in each film. In particular, in many cases, the content of the first oxide semiconductor film and the second oxide semiconductor film is referred to.

[0016] Another embodiment of the present application is a semiconductor device including: a first oxide semiconductor film formed over an insulating film; a second oxide semiconductor film formed over the first oxide semiconductor film; a gate insulating film formed over the second oxide semiconductor film; a gate electrode formed in a region which is in contact with the gate insulating film and overlaps with the second oxide semiconductor film; a protective insulating film formed over the gate electrode; an interlayer insulating film formed over the protective insulating film; and a source electrode and a drain electrode formed over the interlayer insulating film and electrically connected to the second oxide semiconductor film. Each of the first oxide semiconductor film and the second oxide semiconductor film is an oxide film containing at least indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0017] Another embodiment of the present application is a semiconductor device including: a first oxide semiconductor film formed over an insulating film; a second oxide semiconductor film formed over the first oxide semiconductor film; a gate insulating film formed over the second oxide semiconductor film; a gate electrode formed in a region which is in contact with the gate insulating film and overlaps with the second oxide semiconductor film; a protective insulating film formed over the gate electrode; an interlayer insulating film formed over the protective insulating film; a first opening and a second opening formed in the gate insulating film, the protective insulating film, and the interlayer insulating film; and a source electrode and a drain electrode filled in the first opening and the second opening and electrically connected to the second oxide semiconductor film. Each of the first oxide semiconductor film and the second oxide semiconductor film is an oxide film containing at least indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0018] Another embodiment of the present application is a semiconductor device including: a first oxide semiconductor film formed over an insulating film; a second oxide semiconductor film formed over the first oxide semiconductor film; a gate insulating film formed over the second oxide semiconductor film; a gate electrode formed in a region overlapping with the second oxide semiconductor film with the gate insulating film interposed therebetween; a source electrode and a drain electrode formed in contact with the second oxide semiconductor film; and a protective insulating film and an interlayer insulating film formed over at least the source electrode and the drain electrode. The first oxide semiconductor film and the second oxide semiconductor film each are an oxide film containing at least indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0019] Another embodiment of the present application is a semiconductor device including: a first oxide semiconductor film formed over an insulating film; a second oxide semiconductor film formed over the first oxide semiconductor film; a gate insulating film formed over the second oxide semiconductor film; a gate electrode formed in a region overlapping with the second oxide semiconductor film with the gate insulating film interposed therebetween; a source electrode and a drain electrode formed in contact with one side surface of the second oxide semiconductor film and the other side surface of the second oxide semiconductor film, respectively, in a cross section in a channel length direction; a first conductive film formed in one side surface of the gate electrode; a second conductive film formed in the other side surface of the gate electrode; a side wall insulating film formed in side surfaces of the first conductive film and the second conductive film; and a protective insulating film and an interlayer insulating film formed over at least the gate electrode, the source electrode, and the drain electrode. The first oxide semiconductor film and the second oxide semiconductor film each are an oxide film containing at least indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0020] In any of the above structures, at least part of the first conductive film is formed over the source electrode with the gate insulating film interposed therebetween, and at least part of the second conductive film is formed over the drain electrode with the gate insulating film interposed therebetween.

[0021] Thus, by forming the first conductive film and the second conductive film in contact with the gate electrode, a region (also referred to as a Lov region) overlapping with the source electrode and the drain electrode with the gate insulating film interposed therebetween can be provided. Thus, a decrease in on-state current due to miniaturization can be suppressed.

[0022] Further, another embodiment of the present application is a semiconductor device including: a first oxide semiconductor film formed over an oxide film; a second oxide semiconductor film formed over the first oxide semiconductor film; a gate insulating film formed over the second oxide semiconductor film; a gate electrode in contact with the gate insulating film and covering an upper surface and side surfaces of the second oxide semiconductor film, a protective insulating film and an interlayer insulating film formed over the gate electrode; and a source electrode and a drain electrode in contact with side surfaces of the second oxide semiconductor film in an opening portion that passes through the interlayer insulating film, the protective insulating film, the gate insulating film, and the second oxide semiconductor film in a cross section in a channel length direction. The first oxide semiconductor film and the second oxide semiconductor film each are an oxide film containing at least indium, gallium, and zinc, and the content of indium in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, and the content of gallium in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

[0023] In any of the above structures, it is preferable that the source electrode and the drain electrode include a surface that is planarized by a chemical mechanical polishing process.

[0024] When the source electrode and the drain electrode having a surface that is planarized by a chemical mechanical polishing process are formed, an etching process using a resist mask is not performed, so that precise processing can be accurately performed even when the width in the channel length direction of the source electrode and the drain electrode is reduced.

[0025] In any of the above structures, it is preferable that the first oxide semiconductor film include a low-resistance region and a high-resistance region, and the high-resistance region be located at least further outward than the second oxide semiconductor film.

[0026] The high-resistance region of the first oxide semiconductor film formed outward of the second oxide semiconductor film serves as a separation layer between transistors. Such a structure can inhibit electrical connection between adjacent transistors.

[0027] Further, in any of the above structures, it is preferable that the second oxide semiconductor film include a channel region and a pair of low-resistance regions in contact with the channel region. By forming a pair of low-resistance regions in contact with the channel region of the second oxide semiconductor film, the contact resistance between the second oxide semiconductor film and the source electrode and the drain electrode can be reduced.

[0028] Further, in any of the above structures, it is preferable that the second oxide semiconductor film include a high-resistance region on both sides in a channel width direction. By forming a high-resistance region on both sides in the channel width direction of the second oxide semiconductor film, generation of a parasitic channel in the second oxide semiconductor film can be inhibited.

[0029] In addition, in each of the above structures, it is preferable that the content of gallium in the first oxide semiconductor film be equal to or greater than the content of indium, and the content of indium in the second oxide semiconductor film be greater than the content of gallium. When the content of indium in the second oxide semiconductor film is greater than the content of gallium, the crystallinity of the second oxide semiconductor film can be improved.

[0030] In addition, in each of the above structures, it is preferable that the first oxide semiconductor film be formed using an oxide having an atomic ratio of In:Ga:Zn = 1:1:1 or In:Ga:Zn = 1:3:2, and the second oxide semiconductor film be formed using an oxide having an atomic ratio of In:Ga:Zn = 3:1:2.

[0031] In addition, in each of the above structures, it is preferable that the second oxide semiconductor film include a crystal portion, and that the c-axes of the crystal portion be aligned in a direction parallel to a normal vector of a formed surface of the second oxide semiconductor film. By including the crystal portion in the second oxide semiconductor film, the bonding state of metal atoms and oxygen atoms in the second oxide semiconductor film is ordered, and thus oxygen defects can be suppressed.

[0032] In addition, in each of the above structures, it is preferable that the protective insulating film be an aluminum oxide film, and that the film density of the aluminum oxide be 3.2 g / cm 3 By using the above-described aluminum oxide film as the protective insulating film, a barrier effect of preventing impurities such as hydrogen and moisture from entering the second oxide semiconductor film or preventing oxygen from being detached from the second oxide semiconductor film can be obtained.

[0033] The present application can provide a transistor using an oxide semiconductor film, which has stable electric characteristics. BRIEF DESCRIPTION OF DRAWINGS

[0034] FIG. 1A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 1B and FIG. 1C is a cross-sectional view illustrating one embodiment of a semiconductor device;

[0035] FIG. 2A to FIG. 2D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0036] FIG. 3A to FIG. 3D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0037] FIG. 4A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 4B and FIG. 4C is a cross-sectional view illustrating one embodiment of a semiconductor device;

[0038] FIG. 5A to FIG. 5D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0039] FIG. 6A to FIG. 6C is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0040] FIG. 7A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 7B and FIG. 7C is a cross-sectional view illustrating one embodiment of a semiconductor device;

[0041] FIG. 8A to FIG. 8D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0042] FIG. 9A is a plan view illustrating one embodiment of a manufacturing process of a semiconductor device, and FIG. 9B and FIG. 9C is a cross-sectional view illustrating one embodiment of a manufacturing process of a semiconductor device;

[0043] FIG. 10A is a plan view illustrating one embodiment of a manufacturing process of a semiconductor device, and FIG. 10B and FIG. 10C is a cross-sectional view illustrating one embodiment of a manufacturing process of a semiconductor device;

[0044] FIG. 11A to FIG. 11D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0045] FIG. 12A to 12C is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0046] FIG. 13A is a plan view illustrating one embodiment of a semiconductor device, and FIG. 13B and FIG. 13C is a cross-sectional view illustrating one embodiment of a semiconductor device;

[0047] FIG. 14A to FIG. 14D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0048] FIG. 15A to FIG. 15D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0049] FIG. 16A to FIG. 16D is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0050] FIG. 17A and FIG. 17B is a cross-sectional view illustrating one example of a manufacturing process of a semiconductor device;

[0051] FIG. 18A is a plan view of one embodiment of a semiconductor device, and FIG. 18B and FIG. 18C are cross-sectional views each showing one embodiment of a semiconductor device;

[0052] FIG. 19A to FIG. 19D is a cross-sectional view of one example of a manufacturing process of a semiconductor device;

[0053] FIG. 20A to FIG. 20D is a cross-sectional view of one example of a manufacturing process of a semiconductor device;

[0054] FIG. 21A to FIG. 21C is a cross-sectional view of one example of a manufacturing process of a semiconductor device;

[0055] FIG. 22A to FIG. 22C is a cross-sectional view, a plan view, and a circuit diagram of one embodiment of a semiconductor device;

[0056] FIG. 23A and FIG. 23B are a circuit diagram and a perspective view of one embodiment of a semiconductor device;

[0057] FIG. 24A is a cross-sectional view of one embodiment of a semiconductor device, and FIG. 24B is a plan view of one embodiment of a semiconductor device;

[0058] FIG. 25A and FIG. 25B are a circuit diagram of one embodiment of a semiconductor device;

[0059] FIG. 26 is a block diagram of one embodiment of a semiconductor device;

[0060] FIG. 27 is a block diagram of one embodiment of a semiconductor device;

[0061] FIG. 28 is a block diagram of one embodiment of a semiconductor device;

[0062] FIG. 29 is a flow chart showing a manufacturing process of a sputtering target. DETAILED DESCRIPTION

[0063] Embodiments of the application disclosed in this specification will be described below with reference to the accompanying drawings. However, the application is not limited to the following description, and it will be readily appreciated by those skilled in the art that the modes and details of the present application can be changed in various ways without departing from the spirit and scope of the application. Accordingly, the application should not be construed as being limited to the content set forth herein below.

[0064] Note that the position, size, range, and the like of each structure illustrated in the drawings and the like are sometimes not actual ones. Thus, the disclosed application is not necessarily limited to the position, size, range, and the like disclosed in the drawings and the like.

[0065] In addition, ordinal numbers such as "first", "second", and "third" in the present specification and the like are attached to avoid confusion among components, and do not limit the number or order of components in any other way.

[0066] In addition, in the present specification and the like, "above" or "below" is not limited to the positional relationship of "directly above" or "directly below" of the components. For example, "a gate electrode over a gate insulating film" does not exclude the case where another component is present between the gate insulating film and the gate electrode.

[0067] In addition, in the present specification and the like, "an electrode" or "a wiring" is not limited to the function of the components. For example, "an electrode" is sometimes used as a part of "a wiring", and vice versa. Furthermore, "an electrode" or "a wiring" also includes the case where a plurality of "electrodes" or "wirings" are integrated, and the like.

[0068] In addition, in the present specification and the like, the function of "a source" and "a drain" is sometimes interchanged. Thus, in the present specification and the like, "a source" and "a drain" can be used interchangeably.

[0069] In addition, in the present specification and the like, "electrically connected" includes the case where "an element having a certain function" is connected. Here, "an element having a certain function" is not particularly limited as long as it can transmit and receive an electrical signal between connection objects. For example, "an element having a certain function" includes not only an electrode and a wiring but also a switching element such as a transistor, a resistance element, an inductor, a capacitor, an element having another function, and the like.

[0070] Embodiment 1

[0071] In this embodiment, one embodiment of a semiconductor device and a method for manufacturing a semiconductor device will be described with reference to FIG. 1A to 1C , FIG. 2A to 2D and FIG. 3A to FIG. 3D .

[0072] Structure Example 1 of Semiconductor Device

[0073] FIG. 1A to FIG. 1C A plan view and a cross-sectional view of a transistor having a top gate structure are shown as one example of a semiconductor device. FIG. 1A is a plan view, FIG. 1B corresponds to a cross-sectional view taken along FIG. 1Aa cross-sectional view of X1-Y1 in FIG. 1, FIG. 1C corresponds to a cross-sectional view of V1-W1 in FIG. 1. FIG. 1A FIG. 1A In FIG. 1, a part of constituent elements of the semiconductor device (e.g., the gate insulating film 110 and the like) is omitted in order to avoid complication.

[0074] FIG. 1A to FIG. 1C The semiconductor device illustrated in FIG. 1 includes the oxide film 104, the first oxide semiconductor film 106 formed over the oxide film 104, the second oxide semiconductor film 108 formed over the first oxide semiconductor film 106, the gate insulating film 110 formed over the second oxide semiconductor film 108, and the gate electrode 112 formed in a region which is in contact with the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0075] In addition, each of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is an oxide film containing at least indium, gallium, and zinc, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108.

[0076] In addition, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. In addition, the content of indium in the second oxide semiconductor film 108 is higher than that of gallium. By increasing the content of indium in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be increased.

[0077] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the composition of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0078] Here, a structure in which the first oxide semiconductor film 106 is not formed is considered. At this time, the second oxide semiconductor film 108 is directly formed over the oxide film 104. For example, when the second oxide semiconductor film 108 is formed by heating at a temperature of 400 °C or the like, the oxide film 104 releases oxygen before the second oxide semiconductor film 108 is formed. As a result, the amount of oxygen released from the oxide film 104 after the second oxide semiconductor film 108 is formed is reduced, and oxygen cannot be sufficiently supplied to the second oxide semiconductor film 108. Further, when the oxide film 104 is formed using a material different from that of the second oxide semiconductor film 108, for example, when the oxide film 104 is formed using a silicon oxide film, there is a concern that silicon contained in the oxide film 104 is mixed into the second oxide semiconductor film 108 as an impurity and hinders crystallization of the second oxide semiconductor film 108. ​

[0079] However, by employing the structure shown in this embodiment, for example, by forming the first oxide semiconductor film 106 at a low temperature (e.g., room temperature to 200 °C) after the formation of the oxide film 104 and forming the second oxide semiconductor film 108 at a high temperature (e.g., 250 °C to 500 °C, preferably, 300 °C to 400 °C), the release of oxygen from the oxide film 104 can be inhibited by the first oxide semiconductor film 106. Further, since the second oxide semiconductor film 108 is formed over the first oxide semiconductor film 106 formed using the same kind of material, impurities are not or less mixed into the second oxide semiconductor film 108, and thus an oxide semiconductor film including crystals grown from the interface with the first oxide semiconductor film 106 can be formed.

[0080] That is, the first oxide semiconductor film 106 inhibits the release of oxygen from the oxide film 104 at least when the second oxide semiconductor film 108 is formed and serves as a base film for the second oxide semiconductor film 108, and thus the crystallinity of the second oxide semiconductor film 108 can be improved. Further, after the formation of the second oxide semiconductor film 108, heat treatment or the like can be performed to release oxygen from the oxide film 104 and supply the oxygen to the second oxide semiconductor film 108 through the first oxide semiconductor film 106.

[0081] As described above, the structure in which the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked has an excellent effect of inhibiting the generation of oxygen vacancies in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0082] The high crystallinity of the second oxide semiconductor film 108 can order the bonding state of metal atoms and oxygen atoms in the second oxide semiconductor film, and thus the generation of oxygen vacancies can be inhibited. Further, even when oxygen vacancies are generated, oxygen can be supplied from the oxide film 104 to fill the oxygen vacancies.

[0083] Further, in the first oxide semiconductor film 106, a high-resistance region 106a is formed in a region overlapping with the gate electrode 112 and outside the second oxide semiconductor film 108, and a pair of low-resistance regions 106b is formed adjacent to the region overlapping with the gate electrode 112. Further, in the second oxide semiconductor film 108, a channel region 108a is formed in a region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b is formed adjacent to the region overlapping with the gate electrode 112.

[0084] Further, the high-resistance region 106a formed outside the second oxide semiconductor film 108 functions as a separation layer between transistors. This is because, for example, when a structure in which the high-resistance region 106a is not provided outside the second oxide semiconductor film 108 is employed, the adjacent transistors are prevented from being electrically connected.

[0085] Further, a structure including a protective insulating film 114 formed over the gate electrode 112, an interlayer insulating film 116 formed over the protective insulating film 114, and a source electrode 118a and a drain electrode 118b formed over the interlayer insulating film 116 and electrically connected to the second oxide semiconductor film 108 can be employed. Further, since the source electrode 118a and the drain electrode 118b are in contact with the pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0086] Next, each component of the semiconductor device which can be used in the present application will be described in detail.

[0087] [Detailed description of substrate]

[0088] Although there is no particular limitation on the substrate which can be used for the substrate 102, at least heat resistance to the following heat treatment is required. For example, a glass substrate of barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate or a polycrystal semiconductor substrate of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium or the like, an SOI substrate, or the like can be used.

[0089] [Detailed description of oxide film]

[0090] The oxide film 104 has an effect of preventing impurity elements such as hydrogen and moisture from diffusing from the substrate 102, and can be formed using a single layer structure or a stacked layer structure of one or more films selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. Further, as another effect of the oxide film 104, it is preferable to have an effect of supplying oxygen to the first oxide semiconductor film 106 and the second oxide semiconductor film 108 to be formed later. For example, when a silicon oxide film is used as the oxide film 104, a part of oxygen can be released by heating the oxide film 104, whereby oxygen can be supplied to the first oxide semiconductor film 106 and the second oxide semiconductor film 108 to fill oxygen vacancies in the first oxide semiconductor film 106 and the second oxide semiconductor film 108.

[0091] In particular, it is preferable that at least more than the stoichiometric composition of oxygen be contained in the oxide film 104, for example, it is preferable that a silicon oxide film in which the proportion of oxygen is more than the stoichiometric composition be used as the oxide film 104. For example, a silicon oxide film in which the proportion of oxygen is 2.0 times or more the stoichiometric composition, preferably 2.5 times or more the stoichiometric composition, and further preferably 3.0 times or more the stoichiometric composition can be used as the oxide film 104. 2+α(α > 0) indicates a silicon oxide film. By using the above-described silicon oxide film as the oxide film 104, oxygen can be supplied to the first oxide semiconductor film 106 and the second oxide semiconductor film 108.

[0092] [Detailed description of the first oxide semiconductor film]

[0093] The first oxide semiconductor film 106 uses an oxide film containing at least indium, gallium, and zinc, and thus an In-Ga-Zn-based oxide (also referred to as IGZO) can be used. Note that the In-Ga-Zn-based oxide refers to an oxide containing In, Ga, and Zn, and can contain metal elements other than In, Ga, and Zn. For example, an In-Sn-Ga-Zn-based oxide, an In-Hf-Ga-Zn-based oxide, and an In-Al-Ga-Zn-based oxide can be used.

[0094] Further, the content of indium in the first oxide semiconductor film 106 is lower than that in the second oxide semiconductor film 108, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108. Further, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. That is, it is preferable to use an oxide whose composition can be expressed as In < Ga. For example, it is preferable to use an In-Ga-Zn-based oxide whose atomic ratio is In:Ga:Zn = 1:1:1 or In:Ga:Zn = 1:3:2 or an oxide close to the composition thereof.

[0095] Further, as a method for forming the first oxide semiconductor film 106, a sputtering method, an ALD (Atomic Layer Deposition) method, an evaporation method, a coating method, or the like can be used. Further, the thickness of the first oxide semiconductor film 106 is greater than 5 nm and less than or equal to 200 nm, preferably greater than or equal to 10 nm and less than or equal to 30 nm. Further, the first oxide semiconductor film 106 is in a single crystal, a polycrystal (also referred to as a polycrystalline), or an amorphous state.

[0096] [Detailed description of the second oxide semiconductor film]

[0097] The second oxide semiconductor film 108 uses an oxide film containing at least indium, gallium, and zinc, and thus an In-Ga-Zn-based oxide (also referred to as IGZO) can be used. Note that the In-Ga-Zn-based oxide refers to an oxide containing In, Ga, and Zn, and can contain metal elements other than In, Ga, and Zn. For example, an In-Sn-Ga-Zn-based oxide, an In-Hf-Ga-Zn-based oxide, and an In-Al-Ga-Zn-based oxide can be used.

[0098] Further, the second oxide semiconductor film 108 contains indium at a higher concentration than the first oxide semiconductor film 106 and contains gallium at a lower concentration than the first oxide semiconductor film 106. Further, the second oxide semiconductor film 108 contains indium at a higher concentration than gallium. That is, an oxide whose composition can be expressed as In > Ga is preferably used. For example, an In-Ga-Zn-based oxide whose atomic ratio is In:Ga:Zn = 3:1:2 or In:Ga:Zn = 2:1:3 or an oxide close to the composition thereof can be used.

[0099] Further, as a method for forming the second oxide semiconductor film 108, a sputtering method, an ALD method, an evaporation method, a coating method, or the like can be used. Further, the thickness of the second oxide semiconductor film 108 is greater than or equal to 5 nm and less than or equal to 200 nm, preferably greater than or equal to 10 nm and less than or equal to 30 nm. Further, the second oxide semiconductor film 108 preferably has a structure having crystallinity such as single crystal, polycrystal, or microcrystal.

[0100] Further, the second oxide semiconductor film 108 is preferably a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure in which a crystal part is included in an amorphous phase. Further, in many cases, the size of the crystal part is such that the size of a cube whose edge length is less than 100 nm can be included. Further, in an image observed with a transmission electron microscope (TEM), a boundary between the amorphous part and the crystal part included in the CAAC-OS film is not clear. Further, a grain boundary (also referred to as a grain boundary) is not observed in the CAAC-OS film by TEM. Thus, in the CAAC-OS film, reduction in electron mobility due to a grain boundary is suppressed.

[0101] The c-axis of the crystal portion included in the CAAC-OS film is aligned in a direction parallel to a normal vector to a formation surface or a normal vector to a surface of the CAAC-OS film, has a triangle or hexagonal atomic arrangement when seen from a direction perpendicular to the a-b plane, and has a layered structure, or metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from a direction perpendicular to the c-axis. Further, the a-axis and b-axis of one crystal portion and the a-axis and b-axis of another crystal portion can be different.

[0102] Further, in the CAAC-OS film, the distribution of crystal portions is not necessarily uniform. For example, in formation of a CAAC-OS film, the proportion of crystal portions at the surface of the oxide semiconductor film is higher than that in some cases when crystal growth is performed from the surface side of the oxide semiconductor film. Further, by adding an impurity to a CAAC-OS film, crystal portions can be amorphized in the region to which the impurity is added.

[0103] Since the c-axes of the crystal portions included in the CAAC-OS film are aligned in a direction parallel to a normal vector to a formation surface or a normal vector to a surface, they sometimes point in different directions depending on the shape of the CAAC-OS film (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface). Further, the direction of the c-axis of the crystal portion is the direction parallel to a normal vector to a formation surface or a normal vector to a surface at the time of deposition of the CAAC-OS film.

[0104] A transistor using a CAAC-OS film has small variation in electrical characteristics of the transistor caused by irradiation with visible light or ultraviolet light. Further, the variation and deviation in threshold value can be reduced. Thus, the transistor has high reliability.

[0105] Further, the crystal portion or the oxide semiconductor having crystallinity can further reduce bulk defects. Furthermore, by improving the planarity of the surface of the crystal portion or the oxide semiconductor film, a transistor using the oxide semiconductor can have a field-effect mobility higher than that of a transistor using an amorphous oxide semiconductor. In order to improve the planarity of the surface of the oxide semiconductor film, it is preferable to form the oxide semiconductor over a flat surface, specifically, a surface with an average surface roughness (Ra) of 0.15 nm or less, preferably, 0.1 nm or less.

[0106] Note that Ra is a three-dimensional extension of the arithmetic average roughness defined in JIS B0601 so as to be applicable to a surface, and can be expressed as "a value obtained by averaging the absolute values of deviations from a reference surface to a specified surface", and is defined by the following equation.

[0107] [Equation 1]

[0108]

[0109] Here, the specified surface refers to a surface to be measured for roughness, and is a region of a quadrangle represented by four points of (x1, y1, f(x1, y1)), (x1, y2, f(x1, y2)), (x2, y1, f(x2, y1)), and (x2, y2, f(x2, y2)), and the area of a rectangle in the xy plane to which the specified surface is projected is SO, and the height of the reference surface (average height of the specified surface) is Z0. Ra can be measured using an atomic force microscope (AFM: Atomic Force Microscope).

[0110] In addition, when the CAAC-OS film is used as the second oxide semiconductor film 108, three methods can be given as a method for forming the CAAC-OS film. The first method is to form an oxide semiconductor film at a deposition temperature higher than or equal to 200 °C and lower than or equal to 450 °C. This forms a crystal portion included in the oxide semiconductor film in which the c-axes are aligned in a direction parallel to a normal vector or a surface normal of a surface formed by the film. The second method is to perform heat treatment at a temperature higher than or equal to 200 °C and lower than or equal to 700 °C after an oxide semiconductor film is formed in a thin thickness. This forms a crystal portion included in the oxide semiconductor film in which the c-axes are aligned in a direction parallel to a normal vector or a surface normal of a surface formed by the film. The third method is to perform heat treatment at a temperature higher than or equal to 200 °C and lower than or equal to 700 °C after a first layer of an oxide semiconductor film is formed in a thin thickness, and then to form a second layer of an oxide semiconductor film. This forms a crystal portion included in the oxide semiconductor film in which the c-axes are aligned in a direction parallel to a normal vector or a surface normal of a surface formed by the film.

[0111] In addition, by performing deposition while heating the substrate 102, the concentration of impurities such as hydrogen or water included in the formed second oxide semiconductor film 108 can be reduced. In addition, damage caused by sputtering can be reduced, which is preferable. Alternatively, the second oxide semiconductor film 108 can be formed by an ALD method, an evaporation method, a coating method, or the like.

[0112] In addition, when an oxide semiconductor film having crystallinity (single crystal or microcrystal) other than the CAAC-OS film is formed as the second oxide semiconductor film 108, there is no particular limitation on the deposition temperature.

[0113] Further, the energy gap of the second oxide semiconductor film 108 is 2.8 eV to 3.2 eV, which is larger than the energy gap of 1.1 eV of silicon. In addition, the minority carrier density of the second oxide semiconductor film 108 is 1 x 10 -9 / cm 3 , which is much smaller than the intrinsic carrier density of silicon, i.e., 1 x 10 11 / cm 3 .

[0114] The majority carriers (electrons) of the second oxide semiconductor film 108 flow only from the source of the transistor. In addition, since the channel formation region can be completely depleted, the off-state current of the transistor can be extremely small. The off-state current of the transistor using the second oxide semiconductor film 108 is extremely small, i.e., 10 yA / mm or less at room temperature and 1 yA / mm or less at a temperature of 85 °C to 95 °C.

[0115] Further, in the n-channel transistor, the off-state current described in this specification refers to a current flowing between the source and the drain when the potential of the drain is higher than the potentials of the source and the gate and the potential of the gate is 0 V or lower when the potential of the source is taken as a standard. Alternatively, in the p-channel transistor, the off-state current described in this specification refers to a current flowing between the source and the drain when the potential of the drain is lower than the potentials of the source and the gate and the potential of the gate is 0 V or higher when the potential of the source is taken as a standard.

[0116] Further, the transistor including the second oxide semiconductor film 108 has an ideal low S value. In addition, the transistor has high reliability.

[0117] [Detailed description of gate insulating film]

[0118] As the gate insulating film 110, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon oxynitride film, or the like can be used. The portion of the gate insulating film 110 in contact with the second oxide semiconductor film 108 preferably contains oxygen. In particular, the gate insulating film 110 preferably contains oxygen in an amount exceeding the stoichiometric composition in the film, for example, preferably a film of SiO 2+a (a > 0) is used when a silicon oxide film is used as the gate insulating film 110. By using such a silicon oxide film as the gate insulating film 110, oxygen can be supplied to the second oxide semiconductor film 108, which is favorable for the electrical characteristics.

[0119] Further, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y(x > 0, y > 0), hafnium silicate (HfSiO x N y (x > 0, y > 0), hafnium aluminate (HfAl x O y (x > 0, y > 0), and lanthanum oxide, and the like. By using the above-described materials, gate leakage current can be reduced. Further, the gate insulating film 110 can be either a single layer structure or a stacked layer structure.

[0120] Further, for example, the thickness of the gate insulating film 110 can be set to 1 nm or more and 500 nm or less. Further, the manufacturing method of the gate insulating film 110 is not particularly limited, and for example, a sputtering method, an MBE method, a PE-CVD method, a pulsed laser deposition method, an ALD method, or the like can be appropriately used.

[0121] [Detailed Description of Gate Electrode]

[0122] As the gate electrode 112, for example, a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material including these metal materials can be used. Further, as the gate electrode 112, a conductive metal oxide can be formed. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3-SnO2, sometimes abbreviated as ITO), indium zinc oxide (In2O3-ZnO), or a metal oxide formed by containing silicon or silicon oxide in these metal oxide materials can be used. Further, the gate electrode 112 can be formed in a single layer or a stacked layer using the above-described materials. The formation method thereof is not particularly limited, and various film formation methods such as an evaporation method, a PE-CVD method, a sputtering method, or a spin coating method can be used.

[0123] [Detailed Description of Protective Insulating Film]

[0124] As the protective insulating film 114, an inorganic insulating film is preferably used, and for example, a single layer or a stacked layer of an oxide insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, or a hafnium oxide film can be used. Further, a single layer or a stacked layer of a nitride insulating film such as a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film can be further formed on the above-described oxide insulating film. For example, a stacked layer of a silicon oxide film and an aluminum oxide film can be sequentially formed from the gate electrode 112 side by a sputtering method. Further, the manufacturing method of the protective insulating film 114 is not particularly limited, and for example, a sputtering method, an MBE method, a PE-CVD method, a pulsed laser deposition method, an ALD method, or the like can be appropriately used.

[0125] In addition, particularly, an inorganic insulating film having a high density can be provided as the protective insulating film 114. For example, an aluminum oxide film can be formed by a sputtering method. By setting the density of the aluminum oxide film to a high density (a film density of 3.2 g / cm 3 or more, preferably 3.6 g / cm 3 or more, preferably 3.6 g / cm 3 Thus, the aluminum oxide film serves as a protective film, and prevents the entry of impurities such as hydrogen and moisture into the second oxide semiconductor film 108, and prevents the release of oxygen as a main component material of the second oxide semiconductor film 108. In addition, the film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-Ray Reflection (XRR).

[0126] [Detailed Description of the Interlayer Insulating Film]

[0127] As the interlayer insulating film 116, an inorganic insulating film is preferably used, and a single layer or a stack of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, and a silicon nitride oxide film can be used. In addition, the method for manufacturing the interlayer insulating film 116 is not particularly limited, and for example, a sputtering method, an MBE method, a PE-CVD method, a pulsed laser deposition method, an ALD method, or the like can be appropriately used.

[0128] [Detailed Description of the Source and Drain Electrodes]

[0129] As the source and drain electrodes 118a and 118b, for example, a metal film containing an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, and a tungsten nitride film) containing the above element can be used. In addition, a structure in which a high-melting-point metal film or a metal nitride film (a titanium nitride film, a molybdenum nitride film, and a tungsten nitride film) of titanium, molybdenum, and tungsten is layered on one or both of the lower side and the upper side of a metal film of aluminum, copper, or the like can be employed. Further, a conductive metal oxide can be used to form a conductive film for the source and drain electrodes 118a and 118b. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium tin oxide (In2O3-SnO2, abbreviated as ITO), and indium zinc oxide (In2O3-ZnO) can be used. The conductive film for the source and drain electrodes can be formed by using the above material in a single layer or a stack. The formation method is not particularly limited, and various film formation methods such as an evaporation method, a PE-CVD method, a sputtering method, or a spin coating method can be used.

[0130] In addition, in the manufacturing method 1 of the semiconductor device described later, reference is made to FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3D Details of other components are described.

[0131] <Manufacturing method 1 of semiconductor device>

[0132] Next, reference is made to FIG. 2A to FIG. 2D and FIG. 3A to FIG. 3D Details of the manufacturing method 1 of the semiconductor device according to the present embodiment are described. FIG. 1A to FIG. 1C

[0133] First, a substrate 102 is prepared, and then, an oxide film 104, a first oxide semiconductor film 106, and a second oxide semiconductor film 108 are formed over the substrate 102 (see FIG. 1A). FIG. 2A

[0134] In addition, the substrate 102 can be subjected to plasma treatment or the like before the oxide film 104 is formed. As the plasma treatment, for example, reverse sputtering in which argon gas is introduced to generate plasma can be performed. Reverse sputtering is a method in which a voltage is applied to the substrate 102 side in an argon atmosphere using an RF power source to form plasma in the vicinity of the substrate 102 to perform surface modification. Alternatively, nitrogen, helium, oxygen, or the like can be used instead of the argon atmosphere. By performing reverse sputtering, powdery substances (also referred to as particles or dust) attached to the surface of the substrate 102 can be removed.

[0135] As a method for forming the second oxide semiconductor film 108, the oxide semiconductor film is etched by a dry etching method. As an etching gas, BCl3, Cl2, or O2, or the like can be used. A dry etching apparatus using a high-density plasma source such as ECR (electron cyclotron resonance) or ICP (inductively coupled plasma) can be used to increase the etching speed. In the step of forming the second oxide semiconductor film 108, the practitioner can appropriately select the etching conditions of the second oxide semiconductor film 108 and the like so that the first oxide semiconductor film 106 is not processed into an island shape. In addition, the end portion of the second oxide semiconductor film 108 preferably has a taper angle of 20° to 50°.

[0136] In addition, it is preferable that the oxide film 104, the first oxide semiconductor film 106, and the second oxide semiconductor film 108 be formed continuously without exposure to the atmosphere, and in particular, it is preferable that the first oxide semiconductor film 106 and the second oxide semiconductor film 108 be formed continuously. In this manner, by forming the oxide film 104, the first oxide semiconductor film 106, and the second oxide semiconductor film 108 continuously without exposure to the atmosphere, the entry of impurity elements such as moisture and hydrogen contained in the atmosphere into the interfaces can be inhibited.

[0137] ​​Further, in the process of forming the first oxide semiconductor film 106 and the second oxide semiconductor film 108, it is preferable that the first oxide semiconductor film 106 and the second oxide semiconductor film 108 do not contain hydrogen or water as much as possible. For example, as a pretreatment of the process of forming the first oxide semiconductor film 106 and the second oxide semiconductor film 108, it is preferable that the substrate 102 provided with the oxide film 104 be preheated in a preheating chamber of a sputtering apparatus, so that impurities such as hydrogen, moisture, and the like adsorbed on the substrate 102 and the oxide film 104 are removed and exhausted. However, it is preferable that the preheating temperature be set to a temperature at which oxygen is not released or a small amount of oxygen is released from the oxide film 104. Further, it is preferable that the first oxide semiconductor film 106 and the second oxide semiconductor film 108 be formed in a film formation chamber (also referred to as a film formation treatment chamber) in which residual moisture is exhausted, and it is further preferable that a sputtering apparatus having a multi-chamber structure of a plurality of film formation chambers be used and the first oxide semiconductor film 106 and the second oxide semiconductor film 108 be continuously formed in a vacuum.

[0138] Further, in order to remove moisture in the preheating chamber and the film formation chamber, it is preferable that a vacuum pump of an adsorption type, such as a cryopump, an ion pump, or a titanium sublimation pump, be used. Further, as an exhaust unit, a turbo pump provided with a cold trap can be used. Since, in the preheating chamber and the film formation chamber in which exhaustion is performed using a cryopump, for example, a compound containing a hydrogen atom such as a hydrogen atom, water (H2O), or the like (and more preferably, a compound containing a carbon atom) is exhausted, the concentration of impurities such as hydrogen, moisture, and the like contained in the first oxide semiconductor film 106 and the second oxide semiconductor film 108 can be reduced.

[0139] Further, in this embodiment, a metal oxide target having an atomic ratio of In:Ga:Zn = 1:1:1 is used as the first oxide semiconductor film 106, a metal oxide target having an atomic ratio of In:Ga:Zn = 3:1:2 is used as the second oxide semiconductor film 108, and the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are formed by a sputtering method. However, the target which can be used for the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is not limited to the materials and compositions of these targets. Further, as the target which can be used for the first oxide semiconductor film 106 and the second oxide semiconductor film 108, it is preferable that a target having crystallinity such as single crystal or polycrystal be used. By using a target having crystallinity, a thin film formed also has crystallinity, and in particular, a c-axis aligned crystal is easily formed in a thin film formed.

[0140] Here, a method for manufacturing a sputtering target including an oxide semiconductor having a crystal region in which a c-axis is parallel to a normal vector of an upper surface will be described (see Patent Document 1). FIG. 29 .

[0141] First, a raw material of a sputtering target is weighed (Step S101).

[0142] Here, as the raw material of the sputtering target, InO x Raw material (raw material containing In), GaO Y Raw material (raw material containing Ga) and ZnO Z Raw material (raw material containing Zn). Note that X, Y, and Z are arbitrary positive numbers, and for example, X can be set to 1.5, Y can be set to 1.5, and Z can be set to 1. Of course, the above raw materials are only an example, and the raw materials can be appropriately selected in order to obtain a desired compound. For example, MO Y Raw material instead of GaO Y Raw material. Here, M can be Sn, Hf, or Al. Alternatively, M can be La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu of lanthanoid. Although an example in which three kinds of raw materials are used is described in this embodiment, the present embodiment is not limited thereto. For example, the present embodiment can be applied to a case where four or more kinds of raw materials are used.

[0143] Next, InO x Raw material, GaO Y Raw material and ZnO Z Raw materials are mixed at a predetermined ratio.

[0144] As the predetermined ratio, for example, InO x Raw material, GaO Y Raw material and ZnO Z The molar ratio of the raw materials is set to 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1:1:2, 3:1:4, or 3:1:2. By using a mixed material having such a ratio, a sputtering target composed of an oxide semiconductor having a crystal region with a c-axis parallel to a normal vector of an upper surface can be easily formed.

[0145] Specifically, when an In-Ga-Zn-based oxide sputtering target having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] is manufactured, each raw material is weighed so as to satisfy In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio].

[0146] Further, when MO Y Raw material instead of GaO Y Raw material, InO X Raw material, MO Y Raw material and ZnO Z The molar ratio of the raw materials is set to 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1:1:2, 3:1:4, or 3:1:2.

[0147] First, a manufacturing method of a sputtering target using a wet method will be described. After weighing a raw material of a sputtering target, the raw material is pulverized and mixed by a ball mill or the like to manufacture a compound powder. Further, ion-exchange water, an organic additive or the like is mixed into the compound powder to manufacture a slurry (step Slll).

[0148] Next, the slurry is spread over a mold on which a filter sheet capable of permeating moisture is laid, and the moisture is removed. The mold can use a metal product or an oxide product whose top surface shape is rectangular or circular. In addition, the bottom of the mold can have one or a plurality of holes. By providing the holes, the moisture of the slurry can be quickly removed. The filter sheet can use a porous resin, a porous cloth or the like.

[0149] The moisture in the slurry is removed by performing decompression drainage from the holes provided in the bottom of the mold on which the slurry is spread. Next, the slurry from which the moisture is removed by the decompression drainage is subjected to natural drying. Thus, the slurry from which the moisture is removed is shaped into the shape of the inside of the mold (step S113).

[0150] Next, the shaped body obtained is baked at 1400°C in an oxygen (O2) atmosphere (step S114). By the above steps, a sputtering target can be obtained using a wet method.

[0151] Next, a manufacturing method of a sputtering target using a dry method will be described. After weighing a raw material of a sputtering target, the raw material is pulverized and mixed by a ball mill or the like to manufacture a compound powder (step S121).

[0152] Next, the obtained compound powder is spread over a mold and is shaped into a shaped body by pressing using a pressing device (step S122).

[0153] The obtained shaped body is set in a heating device such as an electric furnace and is baked at 1400°C in an oxygen (O2) atmosphere (step S123). In addition, in the present embodiment, a method in which the shaping process and the baking process are performed separately as in steps S122 and S123 is referred to as a cold-pressing method. Hereinafter, a hot-pressing method in which the shaping process and the baking process are performed simultaneously will be described.

[0154] First, the processes of steps S101 to S121 described above are performed. Next, while the obtained compound powder is spread over a mold and the mold is heated at 1000°C in an argon (Ar) atmosphere, the compound powder set in the mold is pressed using a pressing device. Thus, by performing the pressing while the compound powder is baked, the compound powder is shaped and a shaped body is obtained (step S125). By the above steps, a sputtering target can be obtained using a dry method.

[0155] Further, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 can be formed by a sputtering method in an atmosphere of a rare gas (typically, argon), in an atmosphere of oxygen, or in an atmosphere of a mixture of a rare gas and oxygen.

[0156] Further, the temperature at which the first oxide semiconductor film 106 is formed is preferably higher than or equal to room temperature and lower than or equal to 200 °C, and the temperature at which the second oxide semiconductor film 108 is formed is preferably higher than or equal to 250 °C and lower than or equal to 500 °C, further preferably higher than or equal to 300 °C and lower than or equal to 400 °C.

[0157] As described above, by forming the first oxide semiconductor film 106 at a low temperature (higher than or equal to room temperature and lower than or equal to 200 °C) and forming the second oxide semiconductor film 108 at a high temperature (higher than or equal to 250 °C and lower than or equal to 500 °C), the oxygen released from the oxide film 104 can be suppressed and the crystallinity of the second oxide semiconductor film 108 can be improved.

[0158] Further, immediately after the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are formed, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 preferably contain more oxygen than the stoichiometric composition, i.e., are in an oxygen supersaturated state. For example, in the case where the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are formed by a sputtering method, it is preferable to form the films in conditions where the proportion of oxygen in the deposition gas is high, and it is particularly preferable to form the films in an atmosphere of oxygen gas (100 % oxygen gas). For example, in the case where In-Ga-Zn-based oxide (IGZO) is used as the first oxide semiconductor film 106 and the second oxide semiconductor film 108 and the films are formed in conditions where the proportion of oxygen in the deposition gas is high (particularly in an atmosphere of 100 % oxygen gas), even when the deposition temperature is set to be higher than or equal to 300 °C, the release of Zn from the films can be suppressed.

[0159] Further, when the first oxide semiconductor film 106 is formed using the above metal oxide target, the composition of the target and the composition of the thin film formed on the substrate are not necessarily the same. For example, in the case where a metal oxide target with In:Ga:Zn = 1 : 1 : 1 [atomic ratio] is used, although depending on the deposition conditions, the composition of the first oxide semiconductor film 106 of the thin film is sometimes In:Ga:Zn = 1 : 1 : 0.6 to 0.8 [atomic ratio]. This is considered to be because of sublimation of ZnO or difference in sputtering rate of each component of In2O3, Ga2O3, and ZnO at the time of formation of the first oxide semiconductor film 106 and the second oxide semiconductor film 108.

[0160] Therefore, when a thin film having a desired composition is to be formed, the composition of the metal oxide target is adjusted in advance. For example, in the case where the composition of the first oxide semiconductor film 106 of the thin film is set to In:Ga:Zn = 1 : 1 : 1 [atomic ratio], the composition of the metal oxide target can be set to In:Ga:Zn = 1 : 1 : 1.5 [atomic ratio]. In other words, the content of ZnO in the metal oxide target can be increased in advance. Note that the composition of the target is not limited to the above values, and can be adjusted as appropriate in accordance with the film formation conditions or the composition of the thin film to be formed. Further, by increasing the content of ZnO in the metal oxide target, the crystallinity of the resulting thin film is improved, and thus is preferable. Further, the above description is given for the first oxide semiconductor film 106, and similarly, the composition of the metal oxide target can be adjusted when a thin film having a desired composition is to be formed for the second oxide semiconductor film 108.

[0161] Further, the relative density of the metal oxide target is higher than or equal to 90 % and lower than or equal to 100 %, preferably higher than or equal to 95 % and lower than or equal to 99.9 %. By using a metal oxide target with a high relative density, a dense first oxide semiconductor film 106 and a dense second oxide semiconductor film 108 can be formed.

[0162] Further, as a sputtering gas used when the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are formed, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or a hydride are removed is preferably used.

[0163] Further, heat treatment can be performed on the second oxide semiconductor film 108 after the second oxide semiconductor film 108 is formed. The temperature of the heat treatment is set to higher than or equal to 300 °C and lower than or equal to 700 °C, or lower than the strain point of the substrate. By performing the heat treatment, excess hydrogen (including water and a hydroxyl group) in the second oxide semiconductor film 108 can be removed. Note that the heat treatment is sometimes referred to as dehydration treatment (dehydrogenation treatment) in this specification and the like.

[0164] However, since it is possible that oxygen is detached from the oxide film 104 at the same time as the dehydration treatment is performed, the temperature of the dehydration treatment can be set to a temperature at which excess hydrogen (including water and a hydroxyl group) in the second oxide semiconductor film 108 can be removed and detachment of oxygen from the oxide film 104 is inhibited, as appropriate. Further, by the dehydrogenation treatment, it is possible that oxygen is detached from the oxide film 104, but since the first oxide semiconductor film 106 is formed, the dehydrogenation treatment can be effectively performed with detachment of oxygen from the oxide film 104 being inhibited.

[0165] As the heat treatment, for example, the object to be processed is put in an electric furnace using a resistance heating element or the like, heated at 450 °C for one hour in a nitrogen atmosphere. During the heat treatment, the second oxide semiconductor film 108 is not exposed to the air, so that entry of water or hydrogen is prevented.

[0166] The heat treatment apparatus is not limited to an electric furnace, and an apparatus for heat treatment using medium such as heat conduction or heat radiation from a heated gas can be used. For example, an RTA (rapid thermal anneal) apparatus such as a GRTA (gas rapid thermal anneal) apparatus or a LRTA (lamp rapid thermal anneal) apparatus can be used. A LRTA apparatus is an apparatus for heating an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A GRTA apparatus is an apparatus for heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or nitrogen which does not react with an object to be processed even when heat treatment is performed is used.

[0167] For example, as the heat treatment, a GRTA process can be performed, in which an object to be processed is put in an inert gas atmosphere which is heated, heated for several minutes, and then taken out of the inert gas atmosphere. With the use of the GRTA process, heat treatment at a high temperature can be performed in a short time. Further, even when the temperature condition exceeds the heat resistance of an object to be processed, this method can be used. In addition, the inert gas can be switched to a gas containing oxygen during the process.

[0168] Further, as the inert gas atmosphere, an atmosphere in which nitrogen or a rare gas (helium, neon, argon, or the like) is used as a main component and water, hydrogen, or the like is not contained is preferably used. For example, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into a heat treatment apparatus is set to be 6N (99.9999 %) or more, preferably 7N (99.99999 %) or more (i.e., the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0169] Further, when the dehydration treatment (dehydrogenation treatment) is performed, oxygen of the main component of the second oxide semiconductor film 108 can be reduced by being separated. In the second oxide semiconductor film 108, an oxygen vacancy exists in a portion from which oxygen is separated, and a donor level which causes fluctuation in electric characteristics of a transistor is generated due to the oxygen vacancy. Thus, when the dehydration treatment (dehydrogenation treatment) is performed, it is preferable to supply oxygen to the second oxide semiconductor film 108. By supplying oxygen to the second oxide semiconductor film 108, the oxygen vacancy of the second oxide semiconductor film 108 can be filled.

[0170] One example of a method for filling oxygen vacancies in the second oxide semiconductor film 108 is as follows: after dehydration treatment (dehydrogenation treatment) is performed on the second oxide semiconductor film 108, high-purity oxygen gas, high-purity nitrous oxide gas, or super-dry air (the amount of moisture measured by a dew-point meter using a CRDS (cavity ring-down laser spectroscopy) method is 20 ppm (dew point conversion, -55 °C) or less, preferably 1 ppm or less, and more preferably 10 ppb or less) is introduced into the same furnace. The oxygen gas or nitrous oxide gas preferably does not contain water, hydrogen, or the like. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment apparatus is preferably 6N (99.9999 %) or more, and more preferably 7N (99.99999 %) or more (that is, the concentration of impurities in the oxygen gas or nitrous oxide gas is preferably 1 ppm or less, and more preferably 0.1 ppm or less).

[0171] Another example of a method for supplying oxygen to the second oxide semiconductor film 108 is as follows: oxygen is supplied to the second oxide semiconductor film 108 by adding oxygen (at least any one of an oxygen radical, an oxygen atom, and an oxygen ion) to the second oxide semiconductor film 108. As a method for adding oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like is used.

[0172] Another example of a method for supplying oxygen to the second oxide semiconductor film 108 is as follows: oxygen is supplied to the second oxide semiconductor film 108 by causing a part of oxygen to be released from the oxide film 104 or a gate insulating film 110 formed later or the like by heating.

[0173] As described above, it is preferable that, after the second oxide semiconductor film 108 is formed, dehydration treatment (dehydrogenation treatment) be performed to remove hydrogen or moisture from the second oxide semiconductor film 108 to achieve high purity so that the oxide semiconductor film contains as few impurities as possible, and that oxygen which is reduced at the same time by the dehydration treatment (dehydrogenation treatment) be added to the second oxide semiconductor film 108 or that oxygen be supplied to fill oxygen vacancies in the second oxide semiconductor film 108. Note that in this specification and the like, a process for supplying oxygen to the second oxide semiconductor film 108 is sometimes referred to as oxidation treatment, and a process for making the second oxide semiconductor film 108 contain more oxygen than the stoichiometric composition is sometimes referred to as over-oxidation treatment.

[0174] In addition, although the above describes a structure in which dehydration treatment (dehydrogenation treatment) and oxidation treatment are performed after the second oxide semiconductor film 108 is processed into an island shape, one embodiment of the disclosed application is not limited to this. The treatment can be performed before the second oxide semiconductor film 108 is processed into an island shape. In addition, the heating treatment can be performed after formation of the interlayer insulating film 116 formed later, whereby oxygen is supplied to the second oxide semiconductor film 108 from the oxide film 104 or the gate insulating film 110.

[0175] As described above, by performing dehydration treatment (dehydrogenation treatment) to remove hydrogen or moisture from the second oxide semiconductor film 108 and performing oxidation treatment to compensate for oxygen vacancies of the second oxide semiconductor film 108, an oxide semiconductor film which is i-type (intrinsic) or an oxide semiconductor film which is close to i-type can be obtained. In the above oxide semiconductor film, the carrier due to a donor is small (close to 0), and the carrier concentration is lower than 1´10 14 / cm 3 , preferably lower than 1´10 12 / cm 3 , more preferably lower than 1´10 11 / cm 3 .

[0176] In addition, the second oxide semiconductor film 108 is preferably a high-purity film which contains almost no impurities such as copper, aluminum, and chlorine. In the manufacturing process of the transistor, a process in which these impurities are not mixed into the second oxide semiconductor film 108 or attached to the surface of the second oxide semiconductor film 108 is preferably selected as appropriate. In addition, when these impurities are attached to the surface of the second oxide semiconductor film 108, the impurities on the surface of the second oxide semiconductor film 108 are preferably removed by exposure to oxalic acid or dilute hydrofluoric acid or the like or by plasma treatment (e.g., N2O plasma treatment). Specifically, the concentration of copper in the second oxide semiconductor film 108 is 1 x 10 18 atoms / cm 3 or lower, preferably 1 x 10 17 atoms / cm 3 or lower. Furthermore, the concentration of aluminum in the second oxide semiconductor film 108 is 1 x 10 18 atoms / cm 3 or lower. In addition, the concentration of chlorine in the second oxide semiconductor film 108 is 2 x 10 18 atoms / cm 3 or lower.

[0177] Furthermore, the second oxide semiconductor film 108 is preferably made high-purity by sufficiently removing impurities such as hydrogen or by being supplied with sufficient oxygen to be in an oxygen supersaturated state. Specifically, the concentration of hydrogen in the second oxide semiconductor film 108 is 5´10 19atoms / cm 3 The following is preferred: 5×10 18 atoms / cm 3 Hereinafter, 5×10 is preferred. 17 atoms / cm 3 The hydrogen concentration in the second oxide semiconductor film 108 is measured using secondary ion mass spectrometry (SIMS). Furthermore, it is preferable to provide an insulating film (SiO2) containing excess oxygen in contact with the second oxide semiconductor film 108, in a manner that surrounds it. x (etc.) to supply sufficient oxygen so that the second oxide semiconductor film 108 becomes oxygen supersaturated.

[0178] As an insulating film containing excess oxygen, SiO₂ is prepared by appropriately setting the film formation conditions of PE-CVD or sputtering to contain a large amount of oxygen. X The insulating film may be a silicon oxynitride film. Furthermore, when it is necessary to contain a large amount of excess oxygen in the insulating film, oxygen is added to the insulating film by ion implantation, ion doping, or plasma treatment.

[0179] Additionally, because the hydrogen concentration in the insulating film containing excess oxygen is 7.2 × 10⁻⁶. 20 atoms / cm 3 At the above levels, the non-uniformity of the initial characteristics of the transistor increases, the L-length dependence of the transistor's electrical characteristics increases, and the electrical characteristics of the transistor deteriorate significantly during BT stress testing. Therefore, the hydrogen concentration of the insulating film containing excess oxygen is below 7.2 × 10⁻⁶. 20 atoms / cm 3 In other words, the hydrogen concentration of the second oxide semiconductor film 108 is preferably 5 × 10⁸. 19 atoms / cm 3 The hydrogen concentration of the insulating film containing excess oxygen is preferably below 7.2 × 10⁻⁶. 20 atoms / cm 3 .

[0180] Furthermore, it is preferable to provide a barrier film (e.g., AlO) that suppresses the release of oxygen from the second oxide semiconductor film 108 by surrounding the second oxide semiconductor film 108 and being disposed on the outside of the insulating film containing excess oxygen. x ).

[0181] By surrounding the second oxide semiconductor film 108 with an insulating or barrier film containing excess oxygen, the second oxide semiconductor film 108 can be made into a state that is substantially consistent with the stoichiometric composition or a supersaturated state in which oxygen is more abundant than the stoichiometric composition.

[0182] Next, a gate insulating film 110 and a conductive film 111 are formed over the first oxide semiconductor film 106 and the second oxide semiconductor film 108 (see FIG 1C). FIG. 2B ).

[0183] Next, a resist mask is formed over the conductive film 111 by a photolithography process, and etching is selectively performed to form a gate electrode 112, and then the resist mask is removed (see FIG 1D). FIG. 2C ).

[0184] Further, the resist mask used for forming the gate electrode 112 can be formed by an inkjet method. When the resist mask is formed by the inkjet method, a photomask is not needed, which can reduce manufacturing cost. As the etching of the gate electrode 112, either one of dry etching and wet etching or both can be employed.

[0185] Next, a resist mask 132 is formed over the gate insulating film 110 and the gate electrode 112 (see FIG 1E). FIG. 2D ).

[0186] Next, the resist mask 132 is selectively exposed and developed by a photolithography process to form a resist mask 132a. Then, a dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 with the gate electrode 112 and the resist mask 132a as masks. By the introduction of the dopant 142, a high-resistance region 106a and a pair of low-resistance regions 106b adjacent to a region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and a channel region 108a and a pair of low-resistance regions 108b adjacent to a region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see FIG 1F). FIG. 3A ).

[0187] The dopant 142 is an impurity which changes the conductivity of the first oxide semiconductor film 106 and the second oxide semiconductor film 108. As the dopant 142, one or more selected from Group 15 elements (typically, nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), argon (Ar), helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn) can be used.

[0188] Further, the dopant 142 can be introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 by an implantation method through another film (e.g., the gate insulating film 110). As the method for introducing the dopant 142, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. At this time, it is preferable to use a monatomic ion or ions of fluoride or chloride of the dopant 142.

[0189] The dopant 142 introduction process can be controlled by appropriately setting the implantation conditions such as accelerating voltage and dosage, or by adjusting the thickness of the film through which the dopant 142 penetrates. In this embodiment, phosphorus is used as the dopant 142 for phosphorus ion introduction via ion implantation. Alternatively, the dosage of the dopant 142 can be set to 1×10⁻⁶. 13 ions / cm 2 Above and 5×10 16 ions / cm 2 the following.

[0190] The concentration of dopant 142 in the low-resistivity region 108b is preferably 5 × 10⁻⁶. 18 / cm 3 Above and 1×10 22 / cm 3 the following.

[0191] Alternatively, dopant 142 can be introduced while heating substrate 102.

[0192] Furthermore, the process of introducing dopant 142 into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 can be performed multiple times, and a variety of dopants can be used.

[0193] Alternatively, heat treatment can be performed after the introduction of dopant 142. Preferred heating conditions include a temperature of 300°C or higher and 700°C or lower, preferably 300°C or higher and 450°C or lower; an oxygen atmosphere; and a duration of 1 hour. Alternatively, heat treatment can be performed under a nitrogen atmosphere, under reduced pressure, or in atmospheric (ultra-dry air) conditions.

[0194] Furthermore, when the second oxide semiconductor film 108 is a crystalline oxide semiconductor film or a CAAC-OS film, sometimes a portion of it becomes amorphous due to the introduction of dopant 142. In this case, the crystallinity of the second oxide semiconductor film 108 can be restored by performing a heat treatment after introducing dopant 142.

[0195] Next, the resist mask 132a is removed to form a protective insulating film 114 and an interlayer insulating film 116 on the gate insulating film 110 and the gate electrode 112 (see reference). FIG. 3B ).

[0196] Next, a photoresist mask is formed on the interlayer insulating film 116 using a photolithography process. The gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 are selectively etched to form an opening reaching the second oxide semiconductor film 108 (specifically, the low-resistance region 108b formed in the second oxide semiconductor film 108). Then, the photoresist mask is removed (see reference). FIG. 3C ).

[0197] Next, a conductive film is formed in the opening, and a photoresist mask is formed on the conductive film using a photolithography process. Then, selective etching is performed to form the source electrode 118a and the drain electrode 118b (see reference). FIG. 3D ).

[0198] In addition, in this embodiment, such as FIG. 3D As shown, in the cross-section along the channel length, the distance between the gate electrode 112 and the opening forming the active electrode 118a is not equal to the distance between the gate electrode 112 and the opening forming the drain electrode 118b. By adopting the above structure, the cutoff current can be suppressed.

[0199] Through the above processes, it is possible to manufacture FIG. 1A to FIG. 1C The semiconductor device shown.

[0200] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film, the generation of oxygen defects in the second oxide semiconductor film is suppressed, thereby providing a transistor with stable electrical characteristics.

[0201] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0202] Implementation Method 2

[0203] In this embodiment, refer to FIG. 4A to FIG. 4C , FIG. 5A to 5D as well as FIG. 6A to FIG. 6C A modified example of the semiconductor device shown in Embodiment 1 and a manufacturing method different from that of the semiconductor device shown in Embodiment 1 will be described. Furthermore, using... FIG. 1A to FIG. 1C , FIG. 2A to FIG. 2D as well as FIG. 3A to FIG. 3D The same symbols are shown, and their repeated descriptions are omitted. Furthermore, detailed descriptions of identical parts are also omitted.

[0204] <Structure Example 2 of a Semiconductor Device>

[0205] FIG. 4A to FIG. 4C The diagram shows a plan view and a cross-sectional view of a transistor with a top-gate structure as an example of a semiconductor device. FIG. 4A It's a floor plan. FIG. 4B Equivalent to along FIG. 4Aa cross-sectional view of X2-Y2 in FIG. 1, FIG. 4C corresponds to a cross-sectional view of V2-W2 in FIG. 1. FIG. 4A corresponds to a cross-sectional view of V2-W2 in FIG. 1. Note that, in FIG. 4A In FIG. 1, part of the components of the semiconductor device (e.g., the gate insulating film 110 and the like) is omitted in order to avoid complication.

[0206] FIG. 4A to FIG. 4C The semiconductor device illustrated in FIG. 1 includes an oxide film 104, a first oxide semiconductor film 106 formed over the oxide film 104, a second oxide semiconductor film 108 formed over the first oxide semiconductor film 106, a gate insulating film 110 formed over the second oxide semiconductor film 108, and a gate electrode 112 formed in a region which is in contact with the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0207] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films each containing at least indium, gallium, and zinc, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108.

[0208] In addition, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. In addition, the content of indium in the second oxide semiconductor film 108 is higher than that of gallium. By increasing the content of indium in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be increased.

[0209] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the composition of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0210] In addition, the second oxide semiconductor film 108 is formed over the first oxide semiconductor film 106 formed using the same kind of material, so that an oxide semiconductor film having a crystal portion at the interface with the first oxide semiconductor film 106 can be formed.

[0211] That is, the first oxide semiconductor film 106 suppresses release of oxygen from the oxide film 104 at least when the second oxide semiconductor film 108 is formed and serves as a base film for the second oxide semiconductor film 108, so that the crystallinity of the second oxide semiconductor film 108 can be increased. In addition, after the second oxide semiconductor film 108 is formed, heat treatment or the like can be performed to release oxygen from the oxide film 104 and supply the oxygen to the second oxide semiconductor film 108 through the first oxide semiconductor film 106.

[0212] As described above, the structure consisting of a first oxide semiconductor film 106 and a second oxide semiconductor film 108 stacked together has the excellent effect of suppressing oxygen defects in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0213] Furthermore, in the first oxide semiconductor film 106, high-resistance regions 106a are formed in the region overlapping with the gate electrode 112 and on the outer side of the second oxide semiconductor film 108, respectively, and a pair of low-resistance regions 106b are formed adjacent to the region overlapping with the gate electrode 112. Additionally, in the second oxide semiconductor film 108, a channel region 108a is formed in the region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b are formed adjacent to the region overlapping with the gate electrode 112.

[0214] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0215] Additionally, it may include: a protective insulating film 114 formed on the gate electrode 112; an interlayer insulating film 116 formed on the protective insulating film 114; a source electrode 118a and a drain electrode 118b filled in the first opening 151a and the second opening 151b of the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 and electrically connected to the second oxide semiconductor film 108; a wiring 119a electrically connected to the source electrode 118a; and a wiring 119b electrically connected to the drain electrode 118b. Furthermore, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0216] The semiconductor device shown in this embodiment differs from the semiconductor device shown in Embodiment 1 in that the semiconductor device shown in this embodiment includes: a source electrode 118a filled in a first opening 151a of the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116; a drain electrode 118b filled in a second opening 151b of the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116; and wiring 119a and wiring 119b electrically connected to the source electrode 118a and the drain electrode 118b.

[0217] In addition, as will be described later in the method for manufacturing the semiconductor device, the semiconductor device according to the present embodiment forms the opening portions (first opening portions 151a and second opening portions 151b) filled with the source electrode 118a and the drain electrode 118b in two steps. Further, the source electrode 118a and the drain electrode 118b are formed by dividing the conductive film 118 by a CMP process. Thus, the source electrode 118a and the drain electrode 118b can be formed without using a photolithography process when forming the source electrode 118a and the drain electrode 118b, and thus the source electrode 118a and the drain electrode 118b can be formed without being affected by the precision of an exposure machine or misalignment of a photomask. Thus, the semiconductor device according to the present embodiment has a structure suitable for miniaturization. Further, by adopting the above structure, for example, the distance between the source-side contact region or the drain-side contact region and the gate electrode 112 can be reduced to 0.05 μm or more and 0.1 μm or less. Thus, since the resistance between the source and the drain can be reduced, the electric characteristics of the semiconductor device (for example, the on-current characteristics of the transistor) can be improved.

[0218] Note that the details of each component of the semiconductor device according to the present embodiment are the same as those of the structure according to Embodiment 1, and thus the description thereof is omitted. The structures not used in Embodiment 1 are described below.

[0219] [Detailed Description of Wires]

[0220] As the wires 119a and 119b, for example, a metal film containing an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or a metal nitride film (a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing the above element can be used. Alternatively, a high-melting-point metal film or a metal nitride film (a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) of titanium, molybdenum, tungsten, or the like can be stacked on one or both of the lower side and the upper side of a metal film of aluminum, copper, or the like. Further, a conductive metal oxide can be used to form a conductive film for the wires 119a and 119b. As the conductive metal oxide, indium oxide (In203), tin oxide (Sn02), zinc oxide (ZnO), indium tin oxide (In203-Sn02, abbreviated as ITO), and indium zinc oxide (In203-ZnO) can be used. The conductive film for the wires 119a and 119b can be formed in a single layer or a stacked layer by using the above materials. There is no particular limitation on the formation method, and various film formation methods such as an evaporation method, a PE-CVD method, a sputtering method, or a spin coating method can be used.

[0221] In addition, in the method for manufacturing the semiconductor device 2 to be described later, the above-described structure is used with reference to FIG. 5A to 5D and FIG. 6A to FIG. 6C The details of other components are described.

[0222] [Method for Manufacturing Semiconductor Device 2]

[0223] Next, a semiconductor device of the state shown in FIG. 1A will be described with reference to FIGS. 2A to 2D. FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6C The manufacturing method of the semiconductor device shown in FIG. 1A will be described below as one example. FIG. 4A to FIG. 4C

[0224] First, the semiconductor device of the state shown in FIG. 1A can be manufactured by the manufacturing method shown in Embodiment 1. Note that the cross-sectional view shown in FIG. 1A is the same as the cross-sectional view shown in FIG. 2D. FIG. 5A FIG. 5A FIG. 3B

[0225] Next, a resist mask is formed over the interlayer insulating film 116 by a photolithography step, and the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 are selectively etched to form a first opening portion 151a reaching the second oxide semiconductor film 108 (specifically, the low-resistance region 108b), and then the resist mask is removed (see FIG. 2C). FIG. 5B

[0226] In addition, as the exposure of the photolithography step, it is preferable to use an extremely short wavelength, i.e., an extreme ultraviolet (Extreme Ultraviolet) having a wavelength of several nm to several tens of nm. The exposure using an ultraviolet ray has high resolution and a large depth of focus. Thus, a fine pattern can be formed. In addition, another method such as an inkjet method can be used to form a resist mask, as long as a pattern fine enough can be formed. In this case, as a material of the resist mask, a material having photosensitivity need not be used.

[0227] Next, a resist mask is formed over the first opening portion 151a and the interlayer insulating film 116 by a photolithography step, and the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116 are selectively etched to form a second opening portion 151b reaching the second oxide semiconductor film 108 (specifically, the low-resistance region 108b), and then the resist mask is removed (see FIG. 2D). Thus, a pair of opening portions is formed with the gate electrode 112 interposed between the gate insulating film 110, the protective insulating film 114, and the interlayer insulating film 116. FIG. 5C

[0228] Next, a conductive film 118 is formed over the interlayer insulating film 116 so as to fill the first opening portion 151a and the second opening portion 151b (see FIG. 3A). FIG. 5D

[0229] ​​​​​​​Next, the conductive film 118 is subjected to a CMP (Chemical Mechanical Polishing) treatment in a manner to remove the conductive film 118 provided on the interlayer insulating film 116 at least in the region overlapping with the gate electrode 112, to form the source electrode 118a and the drain electrode 118b filled in the first opening portion 151a and the second opening portion 151b (see FIG. 1C). FIG. 6A

[0230] In the present embodiment, the source electrode 118a and the drain electrode 118b are formed by subjecting the conductive film 118 to the CMP treatment under a condition that the surface of the interlayer insulating film 116 is exposed. Alternatively, it is possible that the surface of the protective insulating film 114 is also polished depending on the CMP treatment condition.

[0231] Here, the CMP treatment refers to a method of planarizing the surface of a work by a combined action of chemistry and mechanics. More specifically, the CMP treatment is a method in which a polishing cloth is attached to a polishing table, and the polishing table and the work are rotated or shaken while a slurry (polishing agent) is supplied between the work and the polishing cloth, to polish the surface of the work by chemical reaction between the slurry and the surface of the work and mechanical polishing of the polishing cloth and the work.

[0232] Alternatively, the CMP treatment can be performed only once, or can be performed a plurality of times. When the CMP treatment is performed a plurality of times, it is preferable to perform fine polishing at a low polishing rate after performing initial polishing at a high polishing rate. By combining polishing at different polishing rates in this way, the planarity of the surfaces of the source electrode 118a, the drain electrode 118b, and the interlayer insulating film 116 can be further improved.

[0233] In the present embodiment, the conductive film 118 is removed by the CMP treatment, but other polishing (grinding, cutting) treatment can also be used. Alternatively, the polishing treatment such as the CMP treatment can be combined with etching (dry etching, wet etching) treatment or plasma treatment, or the like. For example, dry etching treatment or plasma treatment (reverse sputtering, or the like) can be performed after the CMP treatment, to achieve improvement in the planarity of the treated surface. When the polishing treatment is combined with etching treatment, plasma treatment, or the like, there is no particular limitation on the order of the processes, and the order can be appropriately set depending on the material, thickness, and surface state of the conductive film 118.

[0234] ​As described above, the source electrode 118a and the drain electrode 118b are provided so as to fill the opening portions (first opening portion 151a and second opening portion 151b) provided in the interlayer insulating film 116, the protective insulating film 114, and the gate insulating film 110. Thus, the distance between the region where the source electrode 118a contacts the second oxide semiconductor film 108 (source side contact region) and the gate electrode 112 is determined depending on the width between the end portion of the first opening portion 151a and the gate electrode 112 (L FIG. 6A in FIG. 1C). SG Similarly, the distance between the region where the drain electrode 118b contacts the second oxide semiconductor film 108 (drain side contact region) and the gate electrode 112 is determined depending on the width between the end portion of the second opening portion 151b and the gate electrode 112 (L FIG. 6A in FIG. 1C). DG

[0235] When the first opening portion 151a for forming the source electrode 118a and the second opening portion 151b for forming the drain electrode 118b are formed by one treatment, the minimum processing size of the width in the channel length direction between the first opening portion 151a and the second opening portion 151b is limited by the resolution limit of an exposure device used for forming a mask. Thus, it is not easy to sufficiently reduce the distance between the first opening portion 151a and the second opening portion 151b, and as a result, it is not easy to reduce the distance between the source side contact region and the gate electrode 112 (L SG and L DG in FIG. 1C).

[0236] However, in the manufacturing method described in this embodiment, since the first opening portion 151a and the second opening portion 151b are formed using two masks, the positions of the opening portions can be freely set without depending on the resolution limit of an exposure device. Thus, for example, the distance between the source side contact region or the drain side contact region and the gate electrode 112 (L SG or L DG in FIG. 1C) can be reduced to 0.05 μm or more and 0.1 μm or less. By reducing L SG and L DG , the resistance between the source and the drain can be reduced, and thus the electrical characteristics of the semiconductor device (e.g., the on-state current characteristics of the transistor) can be improved.

[0237] Further, since the etching treatment using a resist mask is not used in the step of removing the conductive film 118 on the interlayer insulating film 116 to form the source electrode 118a and the drain electrode 118b, precise processing can be accurately performed when the width in the channel length direction of the source electrode 118a and the drain electrode 118b is miniaturized. Thus, in the manufacturing process of the semiconductor device, a microstructure with little variation in shape and characteristics can be manufactured at a high yield. ​

[0238] Next, a conductive film 119 is formed over the interlayer insulating film 116, the source electrode 118a, and the drain electrode 118b (see FIG. 1C). FIG. 6B ).

[0239] Next, a resist mask is formed over the conductive film 119 by a photolithography process, and a wiring 119a electrically connected to the source electrode 118a and a wiring 119b electrically connected to the drain electrode 118b are formed (see FIG. 1D). FIG. 6C ).

[0240] By the above process, a semiconductor device illustrated in FIG. 1E can be manufactured. FIG. 4A to FIG. 4C

[0241] As described in this embodiment, the technical idea of the present application is as follows: by a first oxide semiconductor film formed over an oxide film and a second oxide semiconductor film formed over the first oxide semiconductor film, at least at the time of forming the second oxide semiconductor film, oxygen released from the oxide film is suppressed, and further, the first oxide semiconductor film is used as a base film of the second oxide semiconductor film, and thus the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film, oxygen vacancies in the second oxide semiconductor film are suppressed, and thus a transistor with stable electrical characteristics can be provided.

[0242] The structure, method, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in other embodiments.

[0243] Embodiment 3

[0244] In this embodiment, a modification example of the semiconductor device described in Embodiment 1 and Embodiment 2 and a manufacturing method different from the manufacturing method of the semiconductor device described in Embodiment 1 and Embodiment 2 will be described with reference to FIGS. 9A to 9C, FIG. 7A to FIG. 7C , FIG. 8A to FIG. 8D , FIG. 9A FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12C . Note that the same symbols are used for the same portions as those in Embodiment 1 and Embodiment 2, and repetitive description is omitted. FIG. 1A to FIG. 1C , FIG. 2A to FIG. 2D , FIG. 3A to FIG. 3D , FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6C .

[0245] Structure Example 3 of Semiconductor Device

[0246] FIG. 7A to FIG. 7C A plan view and a cross-sectional view of a transistor having a top gate structure are shown as one example of a semiconductor device. FIG. 7A is a plan view, FIG. 7B corresponding to along​​FIG. 7A a cross-sectional view of X3-Y3 in FIG. 10B, FIG. 7C corresponds to a cross-sectional view of V3-W3 in FIG. 10A. FIG. 7A FIG. 7A In FIG. 10B, part of the components of the semiconductor device (e.g., the gate insulating film 110 and the like) is omitted in order to avoid complication.

[0247] FIG. 7A to FIG. 7C The semiconductor device illustrated in FIG. 10A includes the oxide film 104, the first oxide semiconductor film 106 formed over the oxide film 104, the second oxide semiconductor film 108 formed over the first oxide semiconductor film 106, the gate insulating film 110 formed over the second oxide semiconductor film 108, and the gate electrode 112 formed in a region which is in contact with the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0248] Further, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films each containing at least indium, gallium, and zinc, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108.

[0249] Further, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. Further, the content of indium in the second oxide semiconductor film 108 is higher than that of gallium. By increasing the content of indium in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be increased.

[0250] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the composition of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is different. Further, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0251] Further, the second oxide semiconductor film 108 is formed over the first oxide semiconductor film 106 formed using the same kind of material, so that an oxide semiconductor film having a crystal portion at the interface with the first oxide semiconductor film 106 can be formed.

[0252] That is, the first oxide semiconductor film 106 suppresses release of oxygen from the oxide film 104 at least when the second oxide semiconductor film 108 is formed and serves as a base film for the second oxide semiconductor film 108, so that the crystallinity of the second oxide semiconductor film 108 can be increased. Further, after the second oxide semiconductor film 108 is formed, heat treatment or the like can be performed to release oxygen from the oxide film 104 and supply the oxygen to the second oxide semiconductor film 108 through the first oxide semiconductor film 106. ​

[0253] As described above, by employing the structure in which the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, the oxygen deficiency of the second oxide semiconductor film 108 is suppressed and the crystallinity of the second oxide semiconductor film 108 is improved.

[0254] In addition, in the first oxide semiconductor film 106, a high-resistance region 106a is formed in a region overlapping with the gate electrode 112 and outside the second oxide semiconductor film 108, and a pair of low-resistance regions 106b is formed in a manner to be adjacent to the region overlapping with the gate electrode 112. In addition, in the second oxide semiconductor film 108, a channel region 108a is formed in a region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b is formed in a manner to be adjacent to the region overlapping with the gate electrode 112.

[0255] In addition, the high-resistance region 106a formed outside the second oxide semiconductor film 108 functions as a separation layer between transistors. This is because, for example, when a structure in which the high-resistance region 106a is not provided outside the second oxide semiconductor film 108 is employed, adjacent transistors are electrically connected.

[0256] In addition, an insulating film 113 formed over a region overlapping with the gate electrode 112, a sidewall insulating film 115 formed on side surfaces of the gate electrode 112 and the insulating film 113 in a cross section in a channel length direction, a source electrode 118a and a drain electrode 118b which are in contact with the sidewall insulating film 115 and are electrically connected to the second oxide semiconductor film 108, a protective insulating film 114 and an interlayer insulating film 116 formed at least over the source electrode 118a and the drain electrode 118b, an insulating film 120 formed over the interlayer insulating film 116, a wiring 119a and a wiring 119b which are electrically connected to the source electrode 118a and the drain electrode 118b through an opening portion provided in the insulating film 120, the interlayer insulating film 116, and the protective insulating film 114 can be included. In addition, since the source electrode 118a and the drain electrode 118b are in contact with the pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0257] The structure of the semiconductor device of this embodiment is different from that of the semiconductor device of Embodiment 1 in that the insulating film 113 over the gate electrode 112, the sidewall insulating film 115 provided on side surfaces of the gate electrode 112, the source electrode 118a and the drain electrode 118b formed in contact with the sidewall insulating film 115, and the insulating film 120 are included in the structure of the semiconductor device of this embodiment.

[0258] Further, in the semiconductor device of this embodiment, the source electrode 118a and the drain electrode 118b are formed by performing planarization processing (also referred to as polishing processing) on the conductive film after forming the conductive film serving as the source electrode 118a and the drain electrode 118b over the insulating film 113 and the sidewall insulating film 115, and removing a part of the conductive film. Thus, when the source electrode 118a and the drain electrode 118b are formed, it is not necessary to use a photolithography process, and thus the source electrode 118a and the drain electrode 118b can be formed without being affected by the precision of an exposure machine or misalignment of a photomask. Thus, the semiconductor device of this embodiment has a structure suitable for miniaturization.

[0259] Note that the details of each component of the semiconductor device of this embodiment are the same as those of the structures described in Embodiment 1 and Embodiment 2, and thus the description thereof is omitted. Hereinafter, structures not used in Embodiment 1 and Embodiment 2 are described.

[0260] [Detailed description of insulating film and sidewall insulating film]

[0261] As the insulating film 113, the sidewall insulating film 115, and the insulating film 120, an inorganic insulating film is preferably used, and a single layer or a stack of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, and a silicon nitride oxide film can be used. There is no particular limitation on a method for forming the insulating film 113, the sidewall insulating film 115, and the insulating film 120, and for example, a sputtering method, an MBE method, a PE-CVD method, a pulse laser deposition method, an ALD method, or the like can be appropriately used.

[0262] Further, in the manufacturing method 3 of the semiconductor device described later, the details of other components are described with reference to FIG. 8A to FIG. 8D , FIG. 9A to FIG. 9C, FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12C .

[0263] [Manufacturing method 3 of semiconductor device]

[0264] Next, one example of the manufacturing method of the semiconductor device of this embodiment is described with reference to FIG. 8A to FIG. 8D , FIG. 9A to FIG. 9C, FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12C . FIG. 7A to FIG. 7C

[0265] First, the semiconductor device in the state shown in Embodiment 1 can be manufactured with reference to the manufacturing method shown in Embodiment 1. Note that the cross section shown in Embodiment 1 is the same as the cross section shown in Embodiment 2. FIG. 8A FIG. 8A FIG. 2B ​​​​

[0266] Next, the insulating film 113a is formed over the conductive film 111 (see FIG. 1B). FIG. 8B ).

[0267] Next, the resist mask is formed over the insulating film 113a by a photolithography process, and the insulating film 113a and the conductive film 111 are selectively etched, whereby the insulating film 113 and the gate electrode 112 are formed (see FIG. 1C). FIG. 8C ).

[0268] Next, the resist mask 134 is formed over the gate insulating film 110 and the insulating film 113 (see FIG. 1D). FIG. 8D ).

[0269] Next, the resist mask 134a or the resist mask 134b is formed by selectively performing exposure and development on the resist mask 134 by a photolithography process. Then, the dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 with the gate electrode 112, the insulating film 113, and the resist mask (the resist mask 134a or the resist mask 134b) as masks. By the introduction of the dopant 142, the high-resistance region 106a and the pair of low-resistance regions 106b adjacent to a region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and the channel region 108a and the pair of low-resistance regions 108b adjacent to a region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see FIG. 1E). FIG. 9B and FIG. 10B ).

[0270] Note that, in this embodiment mode, in order to clearly show the positions where the low-resistance regions 106b and the low-resistance regions 108b are formed by the introduction of the dopant 142, cross-sectional views and plan views are used for description in FIG. 9A to FIG. 9C and FIG. 10A to FIG. 10C .

[0271] FIG. 9A is a plan view, FIG. 9B corresponds to a cross-sectional view along X3-Y3 in FIG. 9A , and FIG. 9C corresponds to a cross-sectional view along V3-W3 in FIG. 9A . Note that, in FIG. 9A , part of the components of the semiconductor device (e.g., the gate insulating film 110) is omitted in order to avoid complexity. In addition, FIG. 10A is a plan view, FIG. 10B corresponds to a cross-sectional view along X3-Y3 in FIG. 10A , and FIG. 10C corresponds to a cross-sectional view along V3-W3 in FIG. 10A . Note that, in FIG. 10AIn the present embodiment, in order to avoid complication, a part of the constituent elements of the semiconductor device (e.g., the gate insulating film 110 and the like) is omitted.

[0272] Further, with reference to FIG. 9A to FIG. 9C and FIG. 10A FIG. 10C The positions where the low-resistance regions 106b and 108b are formed are described for the two manufacturing methods. Note that, FIG. 9A to FIG. 9C the manufacturing method described with reference to FIG. 10A to FIG. 10C Both the manufacturing methods described with reference to

[0273] The following describes FIG. 9A to FIG. 9C the manufacturing method described with reference to FIG. 10A to FIG. 10C the manufacturing method described with reference to

[0274] In FIG. 9A to FIG. 9C the manufacturing method described with reference to FIG. 9A to FIG. 9C .

[0275] On the other hand, in FIG. 10A to FIG. 10C the manufacturing method described with reference to FIG. 10A to FIG. 10C .

[0276] In FIG. 9A to FIG. 9C the manufacturing method described with reference to FIG. 10A to FIG. 10C , the entire region other than the channel region 108a becomes the low-resistance region 108b, so the contact area of the source electrode 118a and the drain electrode 118b formed later can be enlarged. On the other hand, in

[0277] As described above, by changing the shape of the resist mask 134a and the resist mask 134b, a semiconductor device with different effects can be manufactured.

[0278] Next, the resist mask (the resist mask 134a or the resist mask 134b) is removed to form the insulating film 115a over the gate insulating film 110 and the insulating film 113 (see FIG. 11A ).

[0279] Next, a side wall insulating film 115 is formed by etching the insulating film 115a. The side wall insulating film 115 is formed self-aligned by performing an etching process with high anisotropy on the insulating film 115a. For example, dry etching is preferably used as the etching method. As the etching gas for dry etching, for example, fluorine-containing gas such as trifluoromethane, octafluorocyclobutane, tetrafluoromethane, or the like can be given. A rare gas or hydrogen can be added to the etching gas. Dry etching is preferably reactive ion etching (RIE method) in which a high-frequency voltage is applied to a substrate. After the side wall insulating film 115 is formed, the gate insulating film 110 is processed with the gate electrode 112, the insulating film 113, and the side wall insulating film 115 as masks and the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are exposed (see FIG. 1C). FIG. 11B Further, the gate insulating film 110 can be processed when the side wall insulating film 115 is formed.

[0280] In this embodiment mode, the dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 immediately after the gate electrode 112 and the insulating film 113 are formed with the gate electrode 112, the insulating film 113, and the resist mask (the resist mask 134a or the resist mask 134b) as masks, but the dopant 142 can be introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 after the side wall insulating film 115 is formed with the gate electrode 112, the insulating film 113, the side wall insulating film 115, and the resist mask as masks. By employing the above steps, a region of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 overlapping with the side wall insulating film 115 can be included in the high-resistance region.

[0281] Next, a conductive film is formed so as to cover the first oxide semiconductor film 106, the second oxide semiconductor film 108, the insulating film 113, and the side wall insulating film 115, and the conductive film is subjected to a photolithography process and an etching process to form a conductive film 118 (see FIG. 1D). FIG. 11C

[0282] Next, an insulating film 114a and an insulating film 116a are formed over the first oxide semiconductor film 106 and the conductive film 118 (see FIG. 1E). FIG. 11D

[0283] ​​Next, CMP processing is performed on insulating films 114a, 116a, and 118 to remove conductive film 118 disposed on insulating film 113 (at least the area overlapping with gate electrode 112), thereby dividing insulating films 114a, 116a, and 118, thereby forming protective insulating film 114, interlayer insulating film 116, source electrode 118a, and drain electrode 118b while gate electrode 112 is sandwiched (see reference). FIG. 12A ).

[0284] In addition, FIG. 12A Although the surfaces of the source electrode 118a and drain electrode 118b are on the same plane as the surfaces of the insulating film 113 and the interlayer insulating film 116, when polishing the surfaces of the source electrode 118a and drain electrode 118b, the insulating film 113, and the interlayer insulating film 116 using a CMP apparatus, sometimes the surfaces of the source electrode 118a and drain electrode 118b are at different heights from the surfaces of the insulating film 113 or the interlayer insulating film 116, resulting in steps. For example, sometimes the surfaces of the source electrode 118a and drain electrode 118b are lower than the surface of the insulating film 113 (becoming concave). Additionally, depending on the CMP processing conditions, the sidewall insulating film 115 may also be polished.

[0285] Note that the CMP treatment here can refer to the CMP treatment of the conductive film 118 described in Embodiment 2.

[0286] Next, an insulating film 120 is formed on the protective insulating film 114, the interlayer insulating film 116, the source electrode 118a, and the drain electrode 118b (see reference). FIG. 12B ).

[0287] Next, a photoresist mask is formed on the insulating film 120 using a photolithography process. The protective insulating film 114, the interlayer insulating film 116, and the insulating film 120 are selectively etched to form openings reaching the source electrode 118a and the drain electrode 118b. The photoresist mask is then removed. A conductive film is then formed covering these openings. A photoresist mask is formed on this conductive film using a photolithography process. The conductive film is then selectively etched to form wirings 119a and 119b (see reference). FIG. 12C ).

[0288] Through the above processes, it is possible to manufacture FIG. 7A to FIG. 7C The semiconductor device shown.

[0289] As illustrated in this embodiment, the technical idea of the present application is as follows: by the first oxide semiconductor film formed by layering over the oxide film and the second oxide semiconductor film formed over the first oxide semiconductor film, at least at the time of forming the second oxide semiconductor film, the release of oxygen from the oxide film is suppressed, and furthermore, the first oxide semiconductor film is used as a base film of the second oxide semiconductor film, and thus the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film, oxygen defects of the second oxide semiconductor film are suppressed, and thus a transistor having stable electrical characteristics can be provided.

[0290] The structure, method, and the like illustrated in this embodiment can be used in appropriate combination with the structures, methods, and the like illustrated in other embodiments.

[0291] Embodiment 4

[0292] In this embodiment, a modification example of the semiconductor device illustrated in Embodiments 1 to 3 and a manufacturing method different from the manufacturing method of the semiconductor device illustrated in Embodiments 1 to 3 will be described with reference to FIG. 13A to FIG. 13C , FIG. 14A to FIG. 14D , FIG. 15A to FIG. 15D , FIG. 16A to FIG. 16D , and FIG. 17A to FIG. 17B . Note that the same symbols are used for the same portions as those illustrated in FIG. 1A to FIG. 1C , FIG. 2A to FIG. 2D , FIG. 3A to FIG. 3D , FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5D , FIG. 6A to FIG. 6C , FIG. 7A to FIG. 7C , Figures 8A-8D , Figure 9A to FIG. 9 C, Figures 10A-10C , Figures 11A-11D , and Figures 12A-12C , and repetitive description thereof is omitted.

[0293] <Structure Example 4 of Semiconductor Device>

[0294] Figures 13A-13C A plan view and cross-sectional views of a transistor having a top gate structure are illustrated as one example of a semiconductor device. Figure 13A is a plan view, Figure 13B corresponds to a cross-sectional view along X4-Y4 in Figure 13A , and Figure 13C corresponds to a cross-sectional view along V4-W4 in Figure 13A . Note that in Figure 13A , part of the components of the semiconductor device (e.g., the gate insulating film 110 and the like) is omitted in order to avoid complexity.

[0295] Figures 13A-13C ​The illustrated semiconductor device includes an oxide film 104, a first oxide semiconductor film 106 formed over the oxide film 104, a second oxide semiconductor film 108 formed over the first oxide semiconductor film 106, a gate insulating film 110 formed over the second oxide semiconductor film 108, and a gate electrode 112 formed in a region which is in contact with the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0296] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium, and zinc, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108.

[0297] In addition, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. In addition, the content of indium in the second oxide semiconductor film 108 is higher than that of gallium. By increasing the content of indium in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be increased.

[0298] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the composition of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0299] In addition, the second oxide semiconductor film 108 is formed over the first oxide semiconductor film 106 formed using the same kind of material, so that an oxide semiconductor film having a crystal portion from the interface with the first oxide semiconductor film 106 can be formed.

[0300] That is, the first oxide semiconductor film 106 suppresses oxygen released from the oxide film 104 at least when the second oxide semiconductor film 108 is formed and serves as a base film for the second oxide semiconductor film 108, so that the crystallinity of the second oxide semiconductor film 108 can be increased. In addition, after the second oxide semiconductor film 108 is formed, heat treatment or the like can be performed to release oxygen from the oxide film 104 and supply the oxygen to the second oxide semiconductor film 108 through the first oxide semiconductor film 106.

[0301] As described above, with the structure in which the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, the excellent effects of suppressing oxygen defects in the second oxide semiconductor film 108 and increasing the crystallinity of the second oxide semiconductor film 108 can be obtained.

[0302] In addition, in the first oxide semiconductor film 106, a high-resistance region 106a is formed in a region overlapping with the gate electrode 112 and outside the second oxide semiconductor film 108, and a pair of low-resistance regions 106b is formed adjacent to the region overlapping with the gate electrode 112. In addition, in the second oxide semiconductor film 108, a channel region 108a is formed in a region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b is formed adjacent to the region overlapping with the gate electrode 112.

[0303] In addition, the high-resistance region 106a formed outside the second oxide semiconductor film 108 serves as a separation layer between transistors. This is because, for example, when a structure in which the high-resistance region 106a is not provided outside the second oxide semiconductor film 108 is employed, adjacent transistors are electrically connected.

[0304] In addition, a source electrode 118a which contacts one side surface of the second oxide semiconductor film 108, a drain electrode 118b which contacts the other side surface of the second oxide semiconductor film 108, a first conductive film 121a which is formed in one side surface of the gate electrode 112, a second conductive film 121b which is formed in the other side surface of the gate electrode 112, a side wall insulating film 115 which is formed in side surfaces of the first conductive film 121a and the second conductive film 121b, a protective insulating film 114 which is formed over the first oxide semiconductor film 106, the source electrode 118a, the drain electrode 118b, the side wall insulating film 115, and the gate electrode 112, an interlayer insulating film 116 which is formed over the protective insulating film 114, and a wiring 119a and a wiring 119b which are electrically connected to the source electrode 118a and the drain electrode 118b, respectively, can be included. In addition, since the source electrode 118a and the drain electrode 118b contact the pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, contact resistance can be reduced.

[0305] The structure of the semiconductor device of this embodiment differs from that of the semiconductor device of Embodiment 1 in that, in the structure of the semiconductor device of this embodiment, the first conductive film 121a, the second conductive film 121b, and the side wall insulating film 115 are formed in both side surfaces of the gate electrode 112, and the source electrode 118a which contacts one side surface of the second oxide semiconductor film 108 and the drain electrode 118b which contacts the other side surface are formed in a cross section in the channel length direction of the second oxide semiconductor film 108.

[0306] In addition, in the semiconductor device of this embodiment, at least a part of the first conductive film 121a formed on one side of the gate electrode 112 is formed on the source electrode 118a with the gate insulating film 110 interposed therebetween, and at least a part of the second conductive film 121b formed on the other side of the gate electrode 112 is formed on the drain electrode 118b with the gate insulating film 110 interposed therebetween. Thus, a region in which a part of the gate electrode 112 (specifically, the gate electrode 112, the first conductive film 121a, and the second conductive film 121b) overlaps with the source electrode 118a and the drain electrode 118b with the gate insulating film 110 interposed therebetween (also referred to as a Lov region) can be provided. Thus, the semiconductor device of this embodiment has a structure suitable for miniaturization, and the semiconductor device of this embodiment has a structure suitable for suppression of a decrease in on-current that occurs with miniaturization.

[0307] Note that the details of each of the components of the semiconductor device of this embodiment are the same as those of the structures described in Embodiments 1 to 3, and thus the description thereof is omitted. The structures not used in Embodiments 1 to 3 are described below.

[0308] [Detailed description of first conductive film and second conductive film]

[0309] The first conductive film 121a and the second conductive film 121b have conductivity, and for example, a metal film of tungsten, titanium, or the like or a silicon film containing an impurity element such as phosphorus or boron can be processed to form the first conductive film 121a and the second conductive film 121b. Alternatively, a polysilicon film can be formed over the gate electrode 112, etching can be performed on the polysilicon film to form a conductive film in contact with the gate electrode 112, and the conductive film can be doped with an impurity element such as phosphorus or boron, followed by heat treatment to form the first conductive film 121a and the second conductive film 121b having conductivity.

[0310] In addition, in the semiconductor device manufacturing method 4 described later, the details of other components are described with reference to Figures 14A-14D , Figures 15A-15D , Figures 16A-16D , and Figures 17A-17B .

[0311] [Semiconductor device manufacturing method 4]

[0312] One example of the semiconductor device manufacturing method of this embodiment is described below with reference to Figures 14A-14D , Figures 15A-15D , Figures 16A-16D , and Figures 17A-17B . Figures 13A-13C

[0313] First, the semiconductor device can be manufactured by the manufacturing method described in Embodiment 1.​Figure 14A The semiconductor device shown in FIG. 1A is described in detail below. Note that the semiconductor device shown in FIG. 1A is different from the semiconductor device shown in FIG. 1B only in that the area of the second oxide semiconductor film 108 is different from that of the second oxide semiconductor film 108. Figure 14A The cross section shown in FIG. 1B is Figure 2B The semiconductor device shown in FIG. 1B is described in detail below. Note that the semiconductor device shown in FIG. 1B is different from the semiconductor device shown in FIG. 1A only in that the area of the second oxide semiconductor film 108 is different from that of the second oxide semiconductor film 108.

[0314] Next, a conductive film is formed over the first oxide semiconductor film 106 and the second oxide semiconductor film 108, a resist mask is formed over the conductive film by a photolithography process, and etching treatment is performed on the conductive film selectively, whereby a conductive film 118 is formed (see FIG. 1C). Figure 14B ).

[0315] Next, CMP treatment is performed on the conductive film 118, and part of the conductive film 118 is removed to expose the second oxide semiconductor film 108. By performing the CMP treatment, the conductive film 118 in the region overlapping with the second oxide semiconductor film 108 is removed, whereby a source electrode 118a and a drain electrode 118b are formed (see FIG. 1D). Figure 14C ).

[0316] Note that the CMP treatment here can be performed in the same manner as the CMP treatment performed on the conductive film 118 described in Embodiment 2.

[0317] Next, a gate insulating film 110 and a conductive film 111 are formed over the first oxide semiconductor film 106, the second oxide semiconductor film 108, the source electrode 118a, and the drain electrode 118b (see FIG. 1E). Figure 14D ).

[0318] Next, a resist mask is formed over the conductive film 111 by a photolithography process, and etching is performed on the conductive film 111 selectively, whereby a gate electrode 112 is formed (see FIG. 1F). Figure 15A ).

[0319] Next, a resist mask 136 is formed over the gate insulating film 110 and the gate electrode 112 (see FIG. 1G). Figure 15B ).

[0320] Next, exposure and development are performed on the resist mask 136 selectively by a photolithography process, whereby a resist mask 136a is formed. Then, a dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 with the gate electrode 112 and the resist mask 136a as masks. By the introduction of the dopant 142, a high-resistance region 106a and a pair of low-resistance regions 106b adjacent to a region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and a channel region 108a and a pair of low-resistance regions 108b adjacent to a region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see FIG. 1H). Figure 15C ).

[0321] Note that in this embodiment, the structure in which the dopant 142 is introduced into the first oxide semiconductor film 106 through the source electrode 118a and the drain electrode 118b to form a low-resistance region 106b is described, but the structure is not limited thereto. The impurity concentration of the first oxide semiconductor film 106 in a region overlapping with the source electrode 118a and the drain electrode 118b can be the same as that of the high-resistance region 106a.

[0322] Next, the resist mask 136a is removed, and a conductive film 121 is formed over the gate insulating film 110 and the gate electrode 112 (see FIG 1C). Figure 15D ).

[0323] Next, an insulating film 115a is formed over the conductive film 121 (see FIG 1D). Figure 16A

[0324] Next, a side wall insulating film 115 is formed by etching the insulating film 115a. The side wall insulating film 115 can be formed self-aligned by etching the insulating film 115a with high anisotropy. For example, dry etching is preferably used as the etching method. As an etching gas used for dry etching, a fluorine-containing gas such as trifluoromethane, octafluorocyclobutane, or tetrafluoromethane can be used, for example. A rare gas or hydrogen can be added to the etching gas. Dry etching is preferably performed by a reactive ion etching method (RIE method) in which a high-frequency voltage is applied to a substrate. After the side wall insulating film 115 is formed, the conductive film 121 and the gate insulating film 110 are processed with the gate electrode 112 and the side wall insulating film 115 as masks, and the first oxide semiconductor film 106, the source electrode 118a, and the drain electrode 118b are exposed (see FIG 1E). Figure 16B In addition, the conductive film 121 and the gate insulating film 110 can be processed when the side wall insulating film 115 is formed. In this embodiment, the conductive film 121 is divided into a first conductive film 121a and a second conductive film 121b, part of the gate insulating film 110 is removed, and part of the surfaces of the source electrode 118a and the drain electrode 118b is exposed.

[0325] Next, a protective insulating film 114 and an interlayer insulating film 116 are formed so as to cover the first oxide semiconductor film 106, the gate electrode 112, the side wall insulating film 115, the first conductive film 121a, the second conductive film 121b, the source electrode 118a, and the drain electrode 118b (see FIG 1F). Figure 16C

[0326] Next, a resist mask is formed on the interlayer insulating film 116 by a photolithography process, and the protective insulating film 114 and the interlayer insulating film 116 are selectively etched, so that an opening portion reaching the source electrode 118a and the drain electrode 118b is formed, and the resist mask is removed (see FIG 1G).​​Figure 16D ).

[0327] Next, a conductive film 119 is formed on the interlayer insulating film 116 in a manner that fills the opening (see reference). Figure 17A ).

[0328] Next, a photoresist mask is formed on the conductive film 119 using a photolithography process, and the conductive film 119 is selectively etched to form wirings 119a and 119b (see reference). Figure 17B ).

[0329] Through the above processes, it is possible to manufacture Figures 13A-13C The semiconductor device shown.

[0330] As shown in this embodiment, the technical concept of the present invention is as follows: By stacking a first oxide semiconductor film on an oxide film and a second oxide semiconductor film on the first oxide semiconductor film, oxygen release from the oxide film is suppressed, at least during the formation of the second oxide semiconductor film. Furthermore, by using the first oxide semiconductor film as the substrate film of the second oxide semiconductor film, the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film and suppressing oxygen defects in the second oxide semiconductor film, a transistor with stable electrical characteristics can be provided.

[0331] The structures and methods shown in this embodiment can be appropriately combined with the structures and methods shown in other embodiments.

[0332] Implementation Method 5

[0333] In this embodiment, refer to Figures 18A-18C , Figures 19A-19D , Figures 20A-20D as well as Figures 21A-21C Modified examples of the semiconductor devices shown in Embodiments 1 to 4, and manufacturing methods different from those used in Embodiments 1 to 4, will be described. Furthermore, methods using... Figures 1A-1C , Figures 2A-2D , Figures 3A-3D , Figures 4A-4C , Figures 5A-5D , Figures 6A-6C , Figures 7A-7C , Figures 8A-8D , Figure 9A To Figure 9 C, Figures 10A-10C , Figures 11A-11D , Figures 12A-12C , Figures 13A-13C , Figures 14A-14D , Figures 15A-15D , Figures 16A-16D as well as Figures 17A-17B The symbols shown are the same as those shown, and their repeated descriptions are omitted.

[0334] <Structure Example 5 of Semiconductor Device>

[0335] Figures 18A-18C A plan view and a cross-sectional view of a transistor having a top gate structure are shown as one example of a semiconductor device. Figure 18A is a plan view, Figure 18B corresponds to a cross-sectional view along Figure 18A in X5-Y5, Figure 18C corresponds to a cross-sectional view along Figure 18A in V5-W5. Note that in Figure 18A , part of the components of the semiconductor device (e.g., a gate insulating film 110 and the like) is omitted in order to avoid complexity.

[0336] Figures 18A-18C The semiconductor device illustrated in FIG. 5A includes an oxide film 104, a first oxide semiconductor film 106 formed over the oxide film 104, a second oxide semiconductor film 108 formed over the first oxide semiconductor film 106, a gate insulating film 110 formed over the second oxide semiconductor film 108, and a gate electrode 112 formed in a region which is in contact with the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0337] In addition, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films each containing at least indium, gallium, and zinc, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108.

[0338] In addition, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. In addition, the content of indium in the second oxide semiconductor film 108 is higher than that of gallium. By increasing the content of indium in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be increased.

[0339] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the compositions of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are different. In addition, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0340] In addition, the second oxide semiconductor film 108 is formed over the first oxide semiconductor film 106 formed using the same kind of material, so that an oxide semiconductor film having a crystal portion at the interface with the first oxide semiconductor film 106 can be formed.

[0341] That is, the first oxide semiconductor film 106 inhibits release of oxygen from the oxide film 104 at least when the second oxide semiconductor film 108 is formed and serves as a base film of the second oxide semiconductor film 108, so that the crystallinity of the second oxide semiconductor film 108 can be improved. Further, after the second oxide semiconductor film 108 is formed, heat treatment or the like can be performed to release oxygen from the oxide film 104 and supply the oxygen to the second oxide semiconductor film 108 through the first oxide semiconductor film 106.

[0342] As described above, the use of the structure in which the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked has an excellent effect of inhibiting oxygen vacancies in the second oxide semiconductor film 108 and improving the crystallinity of the second oxide semiconductor film 108.

[0343] Further, in the first oxide semiconductor film 106, a high-resistance region 106a is formed in a region overlapping with the gate electrode 112 and outside the second oxide semiconductor film 108, and a pair of low-resistance regions 106b is formed so as to be adjacent to the region overlapping with the gate electrode 112. Further, in the second oxide semiconductor film 108, a channel region 108a is formed in a region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b is formed so as to be adjacent to the region overlapping with the gate electrode 112.

[0344] Further, the high-resistance region 106a formed outside the second oxide semiconductor film 108 serves as a separation layer between transistors. This is because, for example, when a structure in which the high-resistance region 106a is not provided outside the second oxide semiconductor film 108 is employed, adjacent transistors are prevented from being electrically connected.

[0345] Further, a protective insulating film 114 formed over the gate electrode 112, an interlayer insulating film 116 formed over the protective insulating film 114, a source electrode 118a and a drain electrode 118b which are in contact with a side surface of the second oxide semiconductor film 108 in an opening portion passing through the interlayer insulating film 116, the protective insulating film 114, the gate insulating film 110, and the second oxide semiconductor film 108 in a cross section in a channel length direction, a wiring 119a electrically connected to the source electrode 118a, and a wiring 119b electrically connected to the drain electrode 118b can be included. Further, since the source electrode 118a and the drain electrode 118b are in contact with the pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, contact resistance can be reduced.

[0346] The structure of the semiconductor device of this embodiment differs from the structure of the semiconductor device of Embodiment 1 in that, in the structure of the semiconductor device of this embodiment, the source electrode 118a and the drain electrode 118b which are filled in the opening portions of the gate insulating film 110, the protective insulating film 114, the interlayer insulating film 116, and the second oxide semiconductor film 108, and the wiring 119a and the wiring 119b which are electrically connected to the source electrode 118a and the drain electrode 118b are formed.

[0347] Further, the structure of the semiconductor device of this embodiment differs from the structure of the semiconductor device of Embodiment 1 in the shape of the second oxide semiconductor film 108 and the shapes of the gate insulating film 110 and the gate electrode 112 which cover the top surface and the side surface of the channel region 108a of the second oxide semiconductor film 108.

[0348] Further, in the semiconductor device of this embodiment, a channel is formed in the top surface and the side surface of the second oxide semiconductor film 108 (specifically, the channel region 108a).

[0349] In the semiconductor device of this embodiment, thus, a thick (so-called plate-shaped) second oxide semiconductor film 108 is formed, the gate insulating film 110 is formed so as to cover the top surface and the side surface of the second oxide semiconductor film 108, and the gate electrode 112 is formed thereover. Thus, since the channel width becomes the sum of the top surface length and the side surface length of the second oxide semiconductor film 108 (specifically, the channel region 108a), the actual channel width can be increased without increasing the width of the top surface of the second oxide semiconductor film 108. By increasing the channel width, the decrease in on-state current or the unevenness in electrical characteristics of the transistor can be suppressed.

[0350] Note that the details of each component of the semiconductor device of this embodiment are the same as those of the structures of Embodiments 1 to 4, and thus the description thereof is omitted. The structures not used in Embodiments 1 to 4 are described below.

[0351] [Detailed Description of Second Oxide Semiconductor Film]

[0352] As the second oxide semiconductor film 108, the same structure as that of Embodiment 1 can be employed, but the thickness thereof differs from that of Embodiment 1. The thickness of the second oxide semiconductor film 108 of this embodiment is greater than 5 nm and less than or equal to 500 nm, preferably greater than or equal to 100 nm and less than or equal to 300 nm.

[0353] In addition, in the manufacturing method 5 of the semiconductor device described later, the details of each component of the semiconductor device are the same as those of the structures of Embodiments 1 to 4, and thus the description thereof is omitted. The structures not used in Embodiments 1 to 4 are described below. Figures 19A-19D , Figures 20A-20C and Figures 21A-21CDetails of other components are described.

[0354] <Manufacturing method of semiconductor device 5>

[0355] Next, one example of a manufacturing method of a semiconductor device shown in Figures 19A-19D , Figures 20A-20C and Figures 21A-21C of the present embodiment will be described with reference to Figures 18A-18C .

[0356] First, a semiconductor device in the state shown in Figure 19A can be manufactured with reference to the manufacturing method shown in Embodiment 1. Note that the cross section shown in Figure 19A is a modification example of the semiconductor device shown in Figure 2A , and the difference between the two is only that the thicknesses of the second oxide semiconductor films 108 are different from each other.

[0357] Next, a gate insulating film 110 and a conductive film 111 are formed over the first oxide semiconductor film 106 and the second oxide semiconductor film 108 (see Figure 19B ).

[0358] Next, a resist mask is formed over the conductive film 111 by a photolithography process, and the conductive film 111 is selectively etched to form a gate electrode 112 (see Figure 19C ).

[0359] Next, a resist mask 138 is formed over the gate insulating film 110 and the gate electrode 112 (see Figure 19D ).

[0360] Next, the resist mask 138 is selectively exposed and developed by a photolithography process to form a resist mask 138a. Then, a dopant 142 is introduced into the first oxide semiconductor film 106 and the second oxide semiconductor film 108 with the gate electrode 112 and the resist mask 138a as masks. By the introduction of the dopant 142, a high-resistance region 106a and a pair of low-resistance regions 106b adjacent to a region overlapping with the gate electrode 112 are formed in the first oxide semiconductor film 106, and a channel region 108a and a pair of low-resistance regions 108b adjacent to a region overlapping with the gate electrode 112 are formed in the second oxide semiconductor film 108 (see Figure 20A ).

[0361] Note that, in the present embodiment, a structure in which the dopant 142 is introduced into the first oxide semiconductor film 106 through the second oxide semiconductor film 108 to form the low-resistance regions 106b is described, but the structure is not limited thereto. The impurity concentration of the first oxide semiconductor film 106 in the region overlapping with the second oxide semiconductor film 108 can be the same as that of the high-resistance region 106a.

[0362] Next, the resist mask 138a is removed to form a protective insulating film 114 and an interlayer insulating film 116 over the gate insulating film 110 and the gate electrode 112 (see Figure 20B ).

[0363] Next, a resist mask is formed over the interlayer insulating film 116 by a photolithography process, and the interlayer insulating film 116, the protective insulating film 114, and the second oxide semiconductor film 108 are selectively etched to form an opening portion 153a reaching the first oxide semiconductor film 106, and the resist mask is removed (see Figure 20C ).

[0364] Next, a resist mask is formed over the opening portion 153a and the interlayer insulating film 116 by a photolithography process, and the interlayer insulating film 116, the protective insulating film 114, and the second oxide semiconductor film 108 are selectively etched to form an opening portion 153b reaching the first oxide semiconductor film 106, and the resist mask is removed (see Figure 20D ). Thus, a pair of opening portions is formed with the gate electrode 112 and the channel region 108a interposed therebetween.

[0365] Note that in this embodiment, the opening portion 153a and the opening portion 153b are formed so as to reach the first oxide semiconductor film 106, but the present embodiment is not limited to this. For example, the opening portion 153a and the opening portion 153b can be formed so as to reach the gate insulating film 104.

[0366] In the manufacturing method described in this embodiment, as in the manufacturing method described in Embodiment 2, the opening portion 153a and the opening portion 153b are formed using two masks, and thus the position of the opening portion can be freely set without depending on the resolution limit of an exposure device. Thus, for example, the distance between the source-side contact region or the drain-side contact region and the gate electrode 112 can be reduced to 0.05 μm or more and 0.1 μm or less. By reducing the distance between the source-side contact region or the drain-side contact region and the gate electrode 112, the resistance between the source and the drain can be reduced, and thus the electrical characteristics of the semiconductor device (e.g., the on-state current characteristics of the transistor) can be improved.

[0367] Next, a conductive film 118 is formed over the interlayer insulating film 116 so as to fill the opening portion 153a and the opening portion 153b (see Figure 21A ).

[0368] Next, the conductive film 118 is subjected to CMP treatment so that the conductive film 118 provided over the interlayer insulating film 116 (at least a region overlapping with the gate electrode 112) is removed, and a source electrode 118a and a drain electrode 118b which fill the opening portion 153a and the opening portion 153b are formed (seeFigure 21B ).

[0369] In addition, in this embodiment mode, the contact regions of the source electrode 118a and the drain electrode 118b with the second oxide semiconductor film 108 are side surfaces of the second oxide semiconductor film 108 in the opening portions through the interlayer insulating film 116, the protective insulating film 114, the gate insulating film 110, and the second oxide semiconductor film 108.

[0370] Next, a conductive film is formed over the interlayer insulating film 116, the source electrode 118a, and the drain electrode 118b, and a resist mask is formed over the conductive film by a photolithography process, whereby a wiring 119a electrically connected to the source electrode 118a and a wiring 119b electrically connected to the drain electrode 118b are formed (see FIG. 1C). Figure 21C ).

[0371] By the above process, the semiconductor device illustrated in FIG. 1A can be manufactured. Figures 18A-18C

[0372] As described in this embodiment mode, the technical idea of the present application is as follows: by the first oxide semiconductor film formed by stacking over the oxide film and the second oxide semiconductor film formed over the first oxide semiconductor film, oxygen released from the oxide film is suppressed at least when the second oxide semiconductor film is formed, and further, the first oxide semiconductor film is used as a base film of the second oxide semiconductor film, so that the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film, oxygen defects in the second oxide semiconductor film are suppressed, so that a transistor with stable electrical characteristics can be provided.

[0373] The structure, method, and the like described in this embodiment mode can be used in appropriate combination with the structures, methods, and the like described in other embodiment modes.

[0374] Embodiment 6

[0375] In this embodiment mode, one example of a structure of a semiconductor device which can retain stored content even in the absence of power supply and has no limit on the number of times of writing is described with reference to drawings.

[0376] Figures 22A-22C is one example of a structure of a semiconductor device. Figure 22A shows a cross-sectional view of a semiconductor device, Figure 22B shows a plan view of a semiconductor device, Figure 22C shows a circuit diagram of a semiconductor device. Here, Figure 22A corresponds to a cross section along C1-C2 and D1-D2 in Figure 22B

[0377] Figure 22A and Figure 22B ​​The semiconductor device illustrated has a transistor 260 using a first semiconductor material in its lower portion, and a transistor 300 using a second semiconductor material in its upper portion. As the transistor 300 using the second semiconductor material, the structure of the semiconductor device illustrated in Embodiment Mode 3 can be employed. Further, although not described in this embodiment mode, the structures of the semiconductor devices used in Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 4, and Embodiment Mode 5 can be applied.

[0378] Here, the first semiconductor material and the second semiconductor material are preferably materials having different band gaps. For example, a semiconductor material other than an oxide semiconductor (crystalline silicon or the like) can be used for the first semiconductor material, and an oxide semiconductor can be used for the second semiconductor material. A transistor using crystalline silicon as a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can hold a charge for a long time by its characteristics.

[0379] Further, although the transistors described above are n-channel transistors, p-channel transistors can of course be used.

[0380] Figure 22A The transistor 260 in FIG. 2A includes a channel formation region 216 provided in a substrate 200 including a semiconductor material (e.g., crystalline silicon or the like), an impurity region 220 provided so as to sandwich the channel formation region 216, an intermetallic compound region 224 in contact with the impurity region 220, a gate insulating film 208 provided over the channel formation region 216, and a gate electrode 210 provided over the gate insulating film 208. Note that although a source electrode or a drain electrode of a transistor is not illustrated in some drawings, such a state is also referred to as a transistor for convenience. Further, in this case, in order to describe the connection relation of the transistor, a source region or a drain region is also referred to as a source electrode or a drain electrode. That is, in this specification, a source electrode can include a source region.

[0381] Further, an element isolation insulating film 206 is provided over the substrate 200 so as to surround the transistor 260, and an insulating film 228 and an oxide film 230 are provided so as to cover the transistor 260. Further, in order to achieve high integration, as Figure 22A As illustrated in FIG. 2A, it is preferable to employ a structure in which the transistor 260 does not have a sidewall insulating film. However, in the case where the characteristics of the transistor 260 are valued, a sidewall insulating film can be provided on the side surface of the gate electrode 210, and an impurity region 220 including a region having different impurity concentration can be provided.

[0382] The transistor 260 using a crystalline silicon substrate can operate at high speed. Thus, by using the transistor as a transistor for reading out, reading out of information can be performed at high speed. An insulating film and an oxide film are formed so as to cover the transistor 260. As a process before the transistor 300 and the capacitor element 264 are formed, the insulating film and the oxide film are subjected to CMP treatment to form a planarized insulating film 228 and an oxide film 230, and the upper surface of the gate electrode 210 is exposed.

[0383] As the insulating film 228, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride film can be used. The oxide film 230 can be formed using a silicon oxide film, a silicon oxynitride film, or a silicon oxynitride film. The insulating film 228 and the oxide film 230 can be formed by a plasma CVD method or a sputtering method.

[0384] In addition, the insulating film 228 can be formed using an organic material such as a polyimide-based resin, an acrylic-based resin, or a benzocyclobutene-based resin. In addition to the above-described organic material, a low-k material or the like can be used. In the case of using an organic material, the insulating film 228 can be formed by a wet process such as a spin coating method or a printing method.

[0385] In this embodiment, a silicon nitride film is used as the insulating film 228 and a silicon oxide film is used as the oxide film 230.

[0386] The first oxide semiconductor film 106 and the second oxide semiconductor film 108 are formed over the oxide film 230 which is sufficiently planarized by polishing treatment (e.g., CMP treatment). The average surface roughness of the surface of the oxide film 230 is preferably less than or equal to 0.15 nm.

[0387] Figure 22A The transistor 300 illustrated in the drawing is a transistor in which an oxide semiconductor is used for a channel formation region. Here, the second oxide semiconductor film 108 included in the transistor 300 is preferably an oxide semiconductor film which is highly purified. By using an oxide semiconductor which is highly purified, a transistor 300 with extremely excellent off-state current characteristics can be obtained.

[0388] The off-state current of the transistor 300 is small, and thus the content of storage can be kept for a long time by using such a transistor. In other words, since refresh operation is not needed or the frequency of refresh operation can be extremely low, power consumption can be sufficiently reduced.

[0389] A single-layer or stacked insulating film 302 and an insulating film 304 are provided on the transistor 300. In this embodiment, a stack of silicon oxide film and aluminum oxide film stacked from one side of the transistor 300 is used as the insulating film 302 and the insulating film 304. Furthermore, the aluminum oxide film is set to a high density (e.g., a film density of 3.2 g / cm³). 3 The above, preferably 3.6 g / cm³ 3 The above can impart stable electrical characteristics to transistor 300, so it is preferred.

[0390] Furthermore, a conductive film 306 is provided in the area where it overlaps with the wiring 119a connected to the source electrode 118a of the transistor 300, separated by the insulating film 302. The wiring 119a, the insulating film 302, and the conductive film 306 constitute a capacitor element 364. In other words, the source electrode 118a of the transistor 300 serves as one electrode of the capacitor element 364, and the conductive film 306 serves as the other electrode of the capacitor element 364. Alternatively, when a capacitor is not required, a structure without the capacitor element 364 can be used. Furthermore, the capacitor element 364 can also be separately disposed above the transistor 300.

[0391] An insulating film 304 is provided on the transistor 300 and the capacitor element 364. Furthermore, wiring 308 for connecting the transistor 300 to other transistors is provided on the insulating film 304. The wiring 308 is formed in such a way that it fills the openings formed in the insulating film 302, the insulating film 304, etc., and is electrically connected to the drain electrode 118b.

[0392] In addition, Figure 22A and Figure 22B Preferably, transistors 260 and 300 are arranged in a manner that overlaps at least partially, and the source or drain region of transistor 260 and the second oxide semiconductor film 108 are arranged in a manner that overlaps partially. Additionally, transistor 300 and capacitor element 364 are arranged in a manner that overlaps at least partially with transistor 260. For example, the conductive film 306 of capacitor element 364 is arranged in a manner that overlaps at least partially with the gate electrode 210 of transistor 260. By adopting this planar layout, the footprint of the semiconductor device can be reduced, thereby achieving high integration.

[0393] then, Figure 22C Showing the corresponding Figure 22A and 22B An example of a circuit structure.

[0394] exist Figure 22CIn this case, one of the source and drain electrodes of the transistor 260 is electrically connected to the first wiring (first line), and the other of the source and drain electrodes of the transistor 260 is electrically connected to the second wiring (second line). In addition, one of the source and drain electrodes of the transistor 300 is electrically connected to the third wiring (third line), and the gate electrode of the transistor 300 is electrically connected to the fourth wiring (fourth line). Further, the gate electrode of the transistor 260 and the other of the source and drain electrodes of the transistor 300 are electrically connected to one of the electrodes of the capacitor element 364, and the fifth wiring (second line) is electrically connected to the other of the electrodes of the capacitor element 364.

[0395] In Figure 22C the semiconductor device illustrated in FIG. 1, by effectively utilizing the characteristics that the potential of the gate electrode of the transistor 260 can be held, writing, holding, and reading of information can be performed as follows.

[0396] Writing and holding of information are described. First, the potential of the fourth wiring is set to a potential at which the transistor 300 is in an on state, and the transistor 300 is in an on state. Thus, the potential of the third wiring is applied to the gate electrode of the transistor 260 and the capacitor element 364. That is, a predetermined charge is applied to the gate electrode of the transistor 260 (writing). Here, either of charges (hereinafter referred to as a Low-level charge and a High-level charge) which are given different potential levels is applied. Then, by setting the potential of the fourth wiring to a potential at which the transistor 300 is in an off state, the transistor 300 is in an off state, and the charge applied to the gate electrode of the transistor 260 is held (holding).

[0397] Since the off current of the transistor 300 is small, the charge of the gate electrode of the transistor 260 is held for a long time.

[0398] Next, reading of information is described. When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring has different potentials depending on the amount of charge held in the gate electrode of the transistor 260. This is because, in general, in the case where the transistor 260 is n-channel type, the apparent threshold value V th_H of the transistor 260 when the High-level charge is applied to the gate electrode of the transistor 260 is lower than the apparent threshold value V th_L of the transistor 260 when the Low-level charge is applied to the gate electrode of the transistor 260. Here, the apparent threshold voltage refers to the potential of the fifth wiring which is necessary for the transistor 260 to be in an on state. Thus, by setting the potential of the fifth wiring to V th_H and V th_LThe potential V0 between the fifth wiring and the gate electrode of the transistor 260 can be distinguished from the potential V0 between the fifth wiring and the gate electrode of the transistor 260. For example, in writing, when a High-level charge is supplied, the transistor 260 becomes an "on state" if the potential of the fifth wiring is V0 (> V th_H ), and the transistor 260 maintains an "off state" even if the potential of the fifth wiring is V0 (< V th_L ). Thus, the held information can be read depending on the potential of the second wiring.

[0399] Note that when the storage units are arranged in an array, it is necessary to read out information from only the desired storage unit. In this case, a potential that makes the transistor 260 an "off state" regardless of the state of the gate electrode, that is, a potential lower than V th_H , is applied to the fifth wiring without reading out information. Alternatively, a potential that makes the transistor 260 an "on state" regardless of the state of the gate electrode, that is, a potential higher than V th_L , is applied to the fifth wiring.

[0400] In the semiconductor device described in this embodiment, the storage content can be held for a long period of time by using a transistor whose off-state current is small because an oxide semiconductor is used for a channel formation region thereof. That is, power consumption can be sufficiently reduced because there is no need to perform refresh operation or the frequency of refresh operation can be reduced to be extremely low. Further, the storage content can be held for a long period of time even when no power supply is provided (preferably, the potential is fixed).

[0401] Further, in the semiconductor device described in this embodiment, information can be written without high voltage and there is no problem of element deterioration. For example, unlike in the case of a conventional nonvolatile memory, there is no need to inject or extract an electron to or from a floating gate, so there is no problem such as deterioration of a gate insulating layer. That is, in the semiconductor device according to the disclosed application, there is no limitation on the number of times of rewriting, which is a problem of a conventional nonvolatile memory, and thus the reliability is significantly improved. Furthermore, information is written depending on the on state or off state of a transistor, so high-speed operation can be easily achieved.

[0402] The transistor 300 includes a first oxide semiconductor film 106 formed over the oxide film 230, a second oxide semiconductor film 108 formed over the first oxide semiconductor film 106, a gate insulating film 110 formed over the second oxide semiconductor film 108, and a gate electrode 112 formed in a region where the gate insulating film 110 is in contact with the second oxide semiconductor film 108.

[0403] Further, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium, and zinc, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108.

[0404] Further, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. Further, the content of indium in the second oxide semiconductor film 108 is higher than that of gallium. Thus, by increasing the content of indium in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be increased.

[0405] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the composition of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is different. Further, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0406] Further, the second oxide semiconductor film 108 is formed over the first oxide semiconductor film 106 formed using the same kind of material, so that an oxide semiconductor film having a crystal portion from the interface with the first oxide semiconductor film 106 can be formed.

[0407] That is, the first oxide semiconductor film 106 suppresses oxygen released from the oxide film 104 at least when the second oxide semiconductor film 108 is formed and serves as a base film of the second oxide semiconductor film 108, so that the crystallinity of the second oxide semiconductor film 108 can be increased. Further, after the second oxide semiconductor film 108 is formed, heat treatment or the like can be performed to release oxygen from the oxide film 104 and supply the oxygen to the second oxide semiconductor film 108 through the first oxide semiconductor film 106.

[0408] As described above, with the structure in which the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, the excellent effects of suppressing oxygen vacancies in the second oxide semiconductor film 108 and increasing the crystallinity of the second oxide semiconductor film 108 can be obtained.

[0409] As described in this embodiment, the technical idea of the present application is as follows: by stacking a first oxide semiconductor film formed over an oxide film and a second oxide semiconductor film formed over the first oxide semiconductor film, oxygen released from the oxide film is suppressed at least when the second oxide semiconductor film is formed, and further, the first oxide semiconductor film is used as a base film of the second oxide semiconductor film, so that the crystallinity of the second oxide semiconductor film can be increased. By increasing the crystallinity of the second oxide semiconductor film, oxygen vacancies in the second oxide semiconductor film are suppressed, so that a transistor with stable electrical characteristics can be provided.

[0410] The structure, method, and the like described in this embodiment can be used in appropriate combination with the structures, methods, and the like described in the other embodiments.

[0411] Embodiment 7

[0412] In this embodiment, the structure using the semiconductor device described in Embodiments 1 to 5 is described with reference to Figures 23A-23B and Figures 24A-24B A structure different from that described in Embodiment 6 is described. This structure can hold stored content even without power supply and has no limit on the number of times of writing.

[0413] Figure 23A One example of a circuit structure of a semiconductor device is shown, Figure 23B is a schematic view showing one example of a semiconductor device. First, a semiconductor device shown in Figure 23A is described, and then a semiconductor device shown in Figure 23B is described.

[0414] In the semiconductor device shown in Figure 23A , the bit line BL is electrically connected to the source or drain of the transistor 300, the word line WL is electrically connected to the gate of the transistor 300, and the source or drain of the transistor 300 is electrically connected to the first terminal of the capacitor element 354.

[0415] The transistor 300 using an oxide semiconductor has a characteristic of having extremely small off-state current. Thus, by making the transistor 300 an off state, the potential of the first terminal of the capacitor element 354 (or the charge accumulated in the capacitor element 354) can be held for a long time.

[0416] Next, a case where information is written to and held in the semiconductor device (storage unit 350) shown in Figure 23A is described.

[0417] First, the transistor 300 is made an on state by setting the potential of the word line WL to a potential at which the transistor 300 is made an on state. Thus, the potential of the bit line BL is applied to the first terminal of the capacitor element 354 (writing). Then, the transistor 300 is made an off state by setting the potential of the word line WL to a potential at which the transistor 300 is made an off state, whereby the potential of the first terminal of the capacitor element 354 is held (holding).

[0418] Since the off-state current of the transistor 300 is extremely small, the potential of the first terminal of the capacitor element 354 (or the charge accumulated in the capacitor element) can be held for a long time.

[0419] Next, the readout of information is described. When the transistor 300 becomes in an on state, the bit line BL in a floating state is connected to the capacitor element 354, and thus, the charge is redistributed between the bit line BL and the capacitor element 354. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL takes a different value depending on the potential of the first terminal of the capacitor element 354 (or the charge accumulated in the capacitor element 354).

[0420] For example, when V represents the potential of the first terminal of the capacitor element 354, C represents the capacity of the capacitor element 354, CB represents the capacitive component possessed by the bit line BL (hereinafter also referred to as bit line capacitance), and VB0 represents the potential of the bit line BL before the charge is redistributed, the potential of the bit line BL after the charge is redistributed becomes (CB*VB0+C*V) / (CB+C). Thus, as the state of the memory cell 350, when the potential of the first terminal of the capacitor element 354 is in two states of VI and V0 (VI>V0), the potential of the bit line BL when the potential VI is held (= (CB*VB0+C*VI) / (CB+C)) is higher than the potential of the bit line BL when the potential V0 is held (= (CB*VB0+C*V0) / (CB+C)).

[0421] Further, by comparing the potential of the bit line BL with a prescribed potential, the information can be read out.

[0422] Thus, Figure 23A The semiconductor device illustrated in FIG. 1 can use the characteristic that the off-state current of the transistor 300 is extremely small to hold the charge accumulated in the capacitor element 354 for a long period of time. In other words, since the refresh operation is not needed, or the frequency of the refresh operation can be extremely low, the power consumption can be sufficiently reduced. In addition, the storage content can be held for a long period of time even in the absence of power supply.

[0423] Next, the semiconductor device illustrated in FIG. 1 is described. Figure 23B

[0424] Figure 23B The semiconductor device illustrated in FIG. 1 has, in an upper portion thereof, a memory cell array 351a and a memory cell array 351b which have a plurality of memory cells 350. Figure 23A The semiconductor device illustrated in FIG. 1 has, in an upper portion thereof, a memory cell array 351a and a memory cell array 351b which have a plurality of memory cells 350. Figure 23B The semiconductor device illustrated in FIG. 1 has, in a lower portion thereof, a peripheral circuit 353 for operating the memory cell array 351a and the memory cell array 351b. In addition, the peripheral circuit 353 is electrically connected to the memory cell array 351a and the memory cell array 351b.

[0425] By employing the semiconductor device illustrated in FIG. 1, Figure 23B ​The structure shown allows the peripheral circuit 353 to be positioned directly below the memory cell arrays 351a and 351b, thereby enabling the miniaturization of the semiconductor device.

[0426] The transistor disposed in the peripheral circuit 353 is preferably made of a semiconductor material different from that of the transistor 300. For example, silicon, germanium, silicon-germanium, silicon carbide, or gallium arsenide can be used, and single-crystal semiconductors are preferred. In addition, organic semiconductor materials can also be used. Transistors using such semiconductor materials can operate at sufficiently high speeds. Thus, by utilizing this transistor, various circuits (logic circuits, drive circuits, etc.) that require high-speed operation can be successfully implemented.

[0427] in addition, Figure 23B The semiconductor device shown illustrates a structure with two stacked memory cell arrays (memory cell array 351a and memory cell array 351b), but the number of stacked memory cell arrays is not limited to this. A structure with three or more stacked memory cell arrays can also be used.

[0428] Next, refer to Figure 24A and Figure 24B right Figure 23A The specific structure of the storage unit 350 shown will be explained.

[0429] Figure 24A and Figure 24B An example of the structure of storage unit 350 is shown. Figure 24A This is a cross-sectional view showing the storage cell 350. Figure 24B This is a plan view showing storage cell 350. Here, Figure 24A Equivalent to along Figure 24B Cross-sectional views of F1-F2 and G1-G2.

[0430] Figure 24A and Figure 24B The transistor 300 shown can have the same structure as that shown in Embodiment 3 or Embodiment 6. However, it can also have the structure of the transistor shown in other embodiments.

[0431] The transistor 300 includes: a first oxide semiconductor film 106 formed on an oxide film 274; a second oxide semiconductor film 108 formed on the first oxide semiconductor film 106; a gate insulating film 110 formed on the second oxide semiconductor film 108; and a gate electrode 112 formed in a region that contacts the gate insulating film 110 and overlaps with the second oxide semiconductor film 108.

[0432] Further, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are oxide films containing at least indium, gallium, and zinc, and the content of gallium in the first oxide semiconductor film 106 is higher than that in the second oxide semiconductor film 108.

[0433] Further, the content of gallium in the first oxide semiconductor film 106 is equal to or higher than that of indium. Further, the content of indium in the second oxide semiconductor film 108 is higher than that of gallium. Thus, by increasing the content of indium in the second oxide semiconductor film 108, the crystallinity of the second oxide semiconductor film 108 can be increased.

[0434] Thus, the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, and the composition of the first oxide semiconductor film 106 and the second oxide semiconductor film 108 is different. Further, the first oxide semiconductor film 106 can suppress oxygen released from the oxide film 104 when the second oxide semiconductor film 108 is formed.

[0435] Further, the second oxide semiconductor film 108 is formed over the first oxide semiconductor film 106 formed using the same kind of material, so that an oxide semiconductor film having a crystal portion from the interface with the first oxide semiconductor film 106 can be formed.

[0436] That is, the first oxide semiconductor film 106 suppresses oxygen released from the oxide film 104 at least when the second oxide semiconductor film 108 is formed and serves as a base film of the second oxide semiconductor film 108, so that the crystallinity of the second oxide semiconductor film 108 can be increased. Further, after the second oxide semiconductor film 108 is formed, heat treatment or the like can be performed to release oxygen from the oxide film 104 and supply the oxygen to the second oxide semiconductor film 108 through the first oxide semiconductor film 106.

[0437] As described above, with the structure in which the first oxide semiconductor film 106 and the second oxide semiconductor film 108 are stacked, the excellent effects of suppressing oxygen defects in the second oxide semiconductor film 108 and increasing the crystallinity of the second oxide semiconductor film 108 can be obtained.

[0438] Further, in the first oxide semiconductor film 106, a high-resistance region 106a is formed in a region overlapping with the gate electrode 112 and outside the second oxide semiconductor film 108, and a pair of low-resistance regions 106b is formed adjacent to the region overlapping with the gate electrode 112. Further, in the second oxide semiconductor film 108, a channel region 108a is formed in a region overlapping with the gate electrode 112, and a pair of low-resistance regions 108b is formed adjacent to the region overlapping with the gate electrode 112.

[0439] Furthermore, the high-resistivity region 106a formed on the outer side of the second oxide semiconductor film 108 serves as a separation layer between the transistors. This is to prevent electrical connection between adjacent transistors, for example, when a structure is adopted in which the high-resistivity region 106a is not provided on the outer side of the second oxide semiconductor film 108.

[0440] Additionally, it may include: an insulating film 113 disposed in the region overlapping with the gate electrode 112; a sidewall insulating film 115 formed on the sidewalls of the gate electrode 112 and the insulating film 113; a source electrode 118a and a drain electrode 118b electrically connected to the second oxide semiconductor film 108; an insulating film 120 formed on the interlayer insulating film 116; and wiring 119a and wiring 119b electrically connected to the source electrode 118a and the drain electrode 118b through openings disposed in the insulating film 120, the interlayer insulating film 116, and the protective insulating film 114. Furthermore, since the source electrode 118a and the drain electrode 118b are in contact with a pair of low-resistance regions 108b formed in the second oxide semiconductor film 108, the contact resistance can be reduced.

[0441] Furthermore, an insulating film 258 is formed on the transistor 300, and a conductive film 262 is disposed in the region where the insulating film 258 overlaps with the wiring 119a connected to the source electrode 118a of the transistor 300. The wiring 119a, the insulating film 258, and the conductive film 262 constitute a capacitor element 354. In other words, the source electrode 118a of the transistor 300 serves as one electrode of the capacitor element 354, and the conductive film 262 serves as the other electrode of the capacitor element 354.

[0442] Furthermore, a single-layer or multi-layer insulating film 256 is provided on the transistor 300 and the capacitor element 354. A wiring 272 for connecting to adjacent memory cells is also provided on the insulating film 256. The wiring 272 is electrically connected to the drain electrode 118b of the transistor 300 through openings and wiring 119b formed in the insulating films 256 and 258. However, the wiring 272 and the drain electrode 118b can also be directly connected. Additionally, the wiring 272 is equivalent to... Figure 23A The bit line BL in the circuit diagram.

[0443] exist Figure 24A and Figure 24B In this context, the drain electrode 118b of transistor 300 can also be used as the source electrode of a transistor included in an adjacent memory cell.

[0444] Thus, by adopting Figure 24B The planar layout shown can reduce the footprint of semiconductor devices, thereby enabling high integration.

[0445] As described above, the plurality of memory cells which are stacked are formed using transistors using an oxide semiconductor. Since the off-state current of the transistor using an oxide semiconductor is small, the content of memory can be held for a long period by using such a transistor. In other words, since the frequency of refresh operation can be made extremely low, power consumption can be sufficiently reduced.

[0446] As described above, by integrating the peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of sufficiently high-speed operation) and the memory circuit using a transistor using an oxide semiconductor (more generally, a transistor having extremely small off-state current), a semiconductor device having novel features can be achieved. In addition, by employing a stacked structure of the peripheral circuit and the memory circuit, integration of the semiconductor device can be achieved.

[0447] As described above, a semiconductor device in which miniaturization and high integration are achieved and high electric characteristics are given and a method for manufacturing the semiconductor device can be provided.

[0448] As described in this embodiment, the technical idea of the present application is as follows: by a first oxide semiconductor film formed over an oxide film and a second oxide semiconductor film formed over the first oxide semiconductor film, at least at the time of forming the second oxide semiconductor film, release of oxygen from the oxide film is suppressed, and further, the first oxide semiconductor film is used as a base film of the second oxide semiconductor film, and thus the crystallinity of the second oxide semiconductor film can be improved. By improving the crystallinity of the second oxide semiconductor film, oxygen defects of the second oxide semiconductor film are suppressed, and thus a transistor having stable electric characteristics can be provided.

[0449] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

[0450] Embodiment 8

[0451] In this embodiment, examples in which the semiconductor device described in the above embodiment is applied to a portable device such as a mobile phone, a smartphone, an e-book reader, and the like are described with reference to Figures 25A-25B , Figure 26 , Figure 27 and Figure 28

[0452] In a portable device such as a mobile phone, a smartphone, an e-book reader, and the like, an SRAM or a DRAM is used for temporary storage of image data. An SRAM or a DRAM is used because a flash memory is slow in response and is not suitable for processing of an image. On the other hand, when an SRAM or a DRAM is used for temporary storage of image data, the following features are obtained.

[0453] As Figure 25A ​As shown, in a general SRAM, one memory cell is composed of six transistors of transistors 801 to 806, and the transistors 801 to 806 are driven by an X decoder 807 and a Y decoder 808. The transistors 803 and 805 and the transistors 804 and 806 constitute inverters, which enable high-speed driving. However, since one memory cell is composed of six transistors, there is a disadvantage that the memory cell area is large. In a case where the minimum size of a design rule is set to F, the memory cell area of the SRAM is generally 100 to 150 F 2 . Therefore, the unit price of each bit of the SRAM is the highest among various memories.

[0454] On the other hand, in a DRAM, as shown, Figure 25B , a memory cell is composed of a transistor 811 and a storage capacitor 812, and the transistor 811 and the storage capacitor 812 are driven by an X decoder 813 and a Y decoder 814. Since one cell is composed of one transistor and one capacitor, the area occupied is small. The memory area of the DRAM is generally 10 F 2 below. Note that the DRAM needs to perform a refresh operation all the time, and thus consumes power even in a case where rewriting is not performed.

[0455] In relation to this, the memory cell area of the semiconductor device described in the above-described embodiment is 10 F 2 or less, and a frequent refresh operation is not needed. Thus, it is possible to reduce the memory cell area, and it is also possible to reduce the power consumption.

[0456] Next, Figure 26 a block diagram of a portable device is shown. Figure 26 The portable device shown has an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, a touch sensor 919, an audio circuit 917, and a keyboard 918, and the like. The display 913 has a display portion 914, a source driver 915, and a gate driver 916. The application processor 906 has a CPU (Central Processing Unit) 907, a DSP (Digital Signal Processor) 908, and an IF 909. The memory circuit 912 is generally composed of an SRAM or a DRAM, and by using the semiconductor device described in the above-described embodiment for this portion, it is possible to perform writing and reading of information at high speed, to maintain the storage contents for a long period of time, and to sufficiently reduce the power consumption.

[0457] Next,Figure 27 An example of a storage circuit 950 using the semiconductor device described in the above embodiment for a display is shown. Figure 27 The storage circuit 950 shown has a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. In addition, the storage circuit is connected to a display controller 956 for reading out and controlling image data (input image data) input from a signal line and data (storage image data) stored in the memory 952 and the memory 953, and a display 957 that performs display in accordance with a signal from the display controller 956.

[0458] First, an image data (input image data A) is formed by an application processor (not shown). The input image data A is stored in the memory 952 through the switch 954. Then, the image data (storage image data A) stored in the memory 952 is sent to the display 957 through the switch 955 and the display controller 956 to perform display.

[0459] When the input image data A does not change, the storage image data A is generally read out from the memory 952 by the display controller 956 through the switch 955 at a cycle of about 30 to 60 Hz.

[0460] In addition, for example, when the user performs an operation to rewrite the screen (that is, when the input image data A changes), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 through the switch 954. During this period, the storage image data A is also continuously read out from the memory 952 through the switch 955 at regular intervals. When the new image (storage image data B) is stored in the memory 953, the reading out of the storage image data B is started from the next frame of the display 957, and the storage image data B is sent to the display 957 through the switch 955 and the display controller 956 to perform display. This reading out continues until the next new image data is stored in the memory 952.

[0461] As described above, the display of the display 957 is performed by alternately performing the writing of the image data and the reading out of the image data by the memory 952 and the memory 953. In addition, the memory 952 and the memory 953 are not limited to two different memories, and one memory can be divided and used. By using the semiconductor device described in the above embodiment for the memory 952 and the memory 953, the writing and the reading out of information can be performed at high speed, the storage contents can be maintained for a long period of time, and the power consumption can be sufficiently reduced.

[0462] Next, Figure 28 A block diagram of an electronic book reader is shown. Figure 28The illustrated electronic book viewer has a battery 1001, a power supply circuit 1002, a microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a storage circuit 1007, a touch screen 1008, a display 1009, and a display controller 1010.

[0463] In this case, the semiconductor device described in the above embodiment can be used for the storage circuit 1007 of the electronic book viewer. Figure 28 The storage circuit 1007 has a function of temporarily holding the contents of a book. As an example of this function, there is a case where a user uses a highlight function. When the user is reading an electronic book viewer, the user sometimes needs to mark a certain part. This marking function is called a highlight function, that is, by changing the display color, underlining, changing the font to bold, changing the font of the text, and the like, the part is highlighted from the surrounding. The highlight function is a function of storing and holding the information of the part designated by the user. When the information is held for a long time, the information can be copied to the flash memory 1004. Even in this case, by using the semiconductor device described in the above embodiment, the writing and reading of the information can be performed at high speed, the storage contents can be held for a long time, and the power consumption can be sufficiently reduced.

[0464] As described above, the portable device according to the present embodiment is provided with the semiconductor device according to the above embodiment. Therefore, a portable device that can perform reading of information at high speed, hold storage contents for a long time, and sufficiently reduce power consumption can be realized.

[0465] The structure and method and the like according to the present embodiment can be appropriately combined with the structure and method and the like according to the other embodiments.

[0466] Explanation of Symbols

[0467] 102: substrate, 104: oxide film, 106: first oxide semiconductor film, 106a: high-resistance region, 106b: low-resistance region, 108: second oxide semiconductor film, 108a: channel region, 108b: low-resistance region, 110: gate insulating film, 111: conductive film, 112: gate electrode, 113: insulating film, 113a: insulating film, 114: protective insulating film, 114a: insulating film, 115: sidewall insulating film, 115a: insulating film, 116: interlayer insulating film, 116a: insulating film, 118: conductive film, 118a: source electrode, 118b: drain electrode, 119: conductive film, 119a: wiring, 119b: wiring, 120: insulating film, 121: conductive film, 121a: first conductive film, 121b: second conductive film, 132: resist mask, 132a: resist mask, 134: resist mask, 134a: resist mask, 134b: resist mask, 136: resist mask, 136a: resist mask, 138: resist mask, 138a: resist mask, 142: dopant, 151a: first opening portion, 151b: second opening portion, 153a: opening portion, 153b: opening portion, 200: substrate, 206: element separation insulating film, 208: gate insulating film, 210: gate electrode, 216: channel formation region, 220: impurity region, 224: intermetallic compound region, 228: insulating film, 230: oxide film, 256: insulating film, 258: insulating film, 260: transistor, 262: conductive film, 264: capacitive element, 272: wiring, 274: oxide film, 300: transistor, 302: insulating film, 304: insulating film, 306: conductive film, 308: wiring, 350: memory cell, 351a: memory cell array, 351b: memory cell array, 353: peripheral circuit, 354: capacitive element, 364: capacitive element, 801: transistor, 802: transistor, 803: transistor, 804: transistor, 805: transistor, 806: transistor, 807: X decoder, 808: Y decoder, 811: transistor, 812: storage capacitor, 813: X decoder, 814: Y decoder, 901: RF circuit, 902: analog baseband circuit, 903: digital baseband circuit, 904: battery, 905: power supply circuit, 906: application processor, 907: CPU, 908: DSP, 909: IF, 910: flash memory, 911: display controller, 912: storage circuit, 913: display, 914: display portion, 915: source driver, 916: gate driver, 917: audio circuit, 918: keyboard, 919: touch sensor, 950: storage circuit, 951: memory controller, 952: memory, 953: memory, 954: switch, 955: switch, 956: display controller, 957: display1001: battery, 1002: power supply circuit, 1003: microprocessor, 1004: flash memory, 1005: audio circuit, 1006: keyboard, 1007: storage circuit, 1008: touch screen, 1009: display, 1010: display controller.

[0468] This application is based on Japanese Patent Application No. 2011-282509 filed on December 23, 2011 with the Japan Patent Office, the entire contents of which are hereby incorporated by reference.

Claims

1. A semiconductor device, comprising: The first oxide semiconductor film on the oxide film; The second oxide semiconductor film on the first oxide semiconductor film; The first insulating film on the second oxide semiconductor film; The gate electrode on the first insulating film has a region that overlaps with the second oxide semiconductor film; The second insulating film has a region that contacts the top surface of the gate electrode; The third insulating film on the second insulating film; as well as A first conductive film electrically connected to the second oxide semiconductor film; Wherein, the first oxide semiconductor film and the second oxide semiconductor film are oxide films containing at least indium, gallium, and zinc. The indium content in the first oxide semiconductor film is less than the indium content in the second oxide semiconductor film. The gallium content in the first oxide semiconductor film is greater than the gallium content in the second oxide semiconductor film. The gallium content in the first oxide semiconductor film is greater than the indium content in the first oxide semiconductor film. The proportion of indium in the second oxide semiconductor film is greater than the proportion of gallium in the second oxide semiconductor film. The second oxide semiconductor film includes a crystalline portion. The second insulating film contains aluminum oxide. The first conductive film is a metal film or a metal nitride film containing elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The first insulating film, the second insulating film, and the third insulating film each have openings. The first conductive film is disposed in the opening. Furthermore, the hydrogen concentration in the first insulating film is less than 7.2 × 10⁻⁶. 20 atoms / cm 3 .

2. A semiconductor device, comprising: The first oxide semiconductor film on the oxide film; The second oxide semiconductor film on the first oxide semiconductor film; The first insulating film on the second oxide semiconductor film; The gate electrode on the first insulating film has a region that overlaps with the second oxide semiconductor film; The second insulating film has a region that contacts the top surface of the gate electrode; The third insulating film on the second insulating film; as well as A first conductive film electrically connected to the second oxide semiconductor film; Wherein, the first oxide semiconductor film and the second oxide semiconductor film are oxide films containing at least indium, gallium, and zinc. The indium content in the first oxide semiconductor film is less than the indium content in the second oxide semiconductor film. The gallium content in the first oxide semiconductor film is greater than the gallium content in the second oxide semiconductor film. The gallium content in the first oxide semiconductor film is greater than the indium content in the first oxide semiconductor film. The proportion of indium in the second oxide semiconductor film is greater than the proportion of gallium in the second oxide semiconductor film. The second oxide semiconductor film is crystalline. The second insulating film contains aluminum oxide. The first conductive film is a metal film or a metal nitride film containing elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The first insulating film, the second insulating film, and the third insulating film each have openings. The first conductive film is disposed in the opening. Furthermore, the hydrogen concentration in the first insulating film is less than 7.2 × 10⁻⁶. 20 atoms / cm 3 .

3. A semiconductor device, comprising: The first oxide semiconductor film on the oxide film; The second oxide semiconductor film on the first oxide semiconductor film; The first insulating film on the second oxide semiconductor film; The gate electrode on the first insulating film has a region that overlaps with the second oxide semiconductor film; The second insulating film has a region that contacts the top surface of the gate electrode; The third insulating film on the second insulating film; as well as A first conductive film electrically connected to the second oxide semiconductor film; Wherein, the first oxide semiconductor film and the second oxide semiconductor film are oxide films containing at least indium, gallium, and zinc. The indium content in the first oxide semiconductor film is less than the indium content in the second oxide semiconductor film. The gallium content in the first oxide semiconductor film is greater than the gallium content in the second oxide semiconductor film. The gallium content in the first oxide semiconductor film is greater than the indium content in the first oxide semiconductor film. The proportion of indium in the second oxide semiconductor film is greater than the proportion of gallium in the second oxide semiconductor film. The second oxide semiconductor film comprises c-axis oriented crystals. The second insulating film comprises aluminum oxide or silicon oxide. The first conductive film is a metal film or a metal nitride film containing elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The first insulating film, the second insulating film, and the third insulating film each have openings. The first conductive film is disposed in the opening. Furthermore, the hydrogen concentration in the first insulating film is less than 7.2 × 10⁻⁶. 20 atoms / cm 3 .

4. The semiconductor device according to any one of claims 1 to 3, wherein, The top surface of the first insulating film is aligned with the top surface of the third insulating film.

5. A semiconductor device, comprising: First oxide semiconductor film; The second oxide semiconductor film on the first oxide semiconductor film; as well as The insulating film on the second oxide semiconductor film, The hydrogen concentration in the insulating film is less than 7.2 × 10⁻⁶. 20 atoms / cm 3 , Both the first oxide semiconductor film and the second oxide semiconductor film contain indium, gallium, and zinc. Furthermore, the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, while the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

6. A semiconductor device, comprising: First oxide semiconductor film; A second oxide semiconductor film, wherein the first oxide semiconductor film and the second oxide semiconductor film overlap each other; as well as An insulating film adjacent to the second oxide semiconductor film, wherein the hydrogen concentration in the insulating film is less than 7.2 × 10⁻⁶. 20 atoms / cm 3 , Both the first oxide semiconductor film and the second oxide semiconductor film contain indium, gallium, and zinc. Furthermore, the indium content in the first oxide semiconductor film is lower than that in the second oxide semiconductor film, while the gallium content in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

7. The semiconductor device according to claim 5 or 6, wherein, The carrier concentration in the second oxide semiconductor film is less than 1×10⁻⁶. 14 / cm 3 .

8. The semiconductor device according to claim 5 or 6, wherein, The copper concentration in the second oxide semiconductor film is 1×10⁻⁶. 18 atoms / cm 3 the following.

9. The semiconductor device according to claim 5 or 6, wherein, The aluminum concentration in the second oxide semiconductor film is 1×10⁻⁶. 18 atoms / cm 3 the following.

10. The semiconductor device according to claim 5 or 6, wherein, The chlorine concentration in the second oxide semiconductor film is 2×10 18 atoms / cm 3 the following.

11. The semiconductor device according to claim 5 or 6, wherein, The hydrogen concentration in the second oxide semiconductor film is 5 × 10⁻⁶. 19 atoms / cm 3 the following.

12. The semiconductor device according to claim 5 or 6, wherein, The insulating film contains an oxygen content that exceeds the oxygen content in the stoichiometric composition of the insulating film.

13. The semiconductor device according to claim 5 or 6, wherein, The second oxide semiconductor film includes a crystalline portion.

14. The semiconductor device according to claim 5 or 6, wherein, The first oxide semiconductor film includes a low-resistance region and a high-resistance region, wherein the high-resistance region is located outside the second oxide semiconductor film.

15. The semiconductor device according to claim 5 or 6, wherein, The second oxide semiconductor film includes a channel region and a pair of low-resistance regions in contact with the channel region.

16. The semiconductor device according to claim 5 or 6, wherein, Each end of the second oxide semiconductor film in the channel width direction includes a high-resistance region.

17. The semiconductor device according to claim 5 or 6, wherein, The gallium content in the first oxide semiconductor film is greater than or equal to the indium content.

18. The semiconductor device according to claim 5 or 6, wherein, The indium content in the second oxide semiconductor film is greater than the gallium content.

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