Magnetic memory device and method of forming the same

Abstract

Embodiments of the present disclosure generally relate to a memory device. More specifically, embodiments described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side with and in contact with a SOT layer. The side-by-side magnetic storage layer and the SOT layer can achieve switching of the magnetic storage layer by reversing the direction of a current flowing through the SOT layer without any additional conditions.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a memory device. More specifically, the embodiments described herein generally relate to a spin-orbit torque magnetoresistive random-access memory (SOT-MRAM). Background Art

[0002] Magnetoresistive random access memory (MRAM) is a memory device containing an array of MRAM cells that use their resistance values ​​rather than charge to store data. Typically, each MRAM cell includes a magnetic tunnel junction (MTJ) structure having at least one magnetic storage layer (free layer) and a magnetic reference layer (pinned layer). The MTJ structure can have an adjustable resistance to represent a logic state "0" or "1" by switching the magnetic moment of the magnetic storage layer from a parallel direction relative to the magnetic moment of the magnetic reference layer to an anti-parallel direction relative to the magnetic moment of the magnetic reference layer. MRAM can take various forms, such as spin transfer torque MRAM (STT-MRAM) or SOT-MRAM.

[0003] Traditionally, in SOT-MRAM, the magnetic storage layer is set on the spin-orbit torque (SOT) layer. Due to the strong spin-orbit coupling of the SOT layer, the current flowing along the SOT layer will produce SOT. The magnetic storage of the MRAM cell is usually made of a perpendicular magnetic anisotropy (PMA) material with a magnetic moment perpendicular to the substrate plane. The spin polarization generated in the magnetic storage layer by spin-orbit coupling is orthogonal to the magnetic moment of the PMA magnetic storage layer. Therefore, due to the symmetric switching (the amount of spin current used to switch the magnetic moment of the magnetic storage layer from a parallel state to an antiparallel state is equal to the amount of spin current used to switch from an antiparallel state to a parallel state), the SOT generated by the SOT layer cannot switch the magnetic moment of the PMA magnetic storage layer. One or more additional conditions (such as an external magnetic field or a spin transfer torque from an additional structure) are required to break the symmetry and switch the magnetic moment of the magnetic storage layer.

[0004] Therefore, there is a need for improved SOT-MRAM. Summary of the invention

[0005] Embodiments of the present disclosure generally relate to a memory device. More specifically, the embodiments described herein generally relate to SOT-MRAM. In one embodiment, a memory device includes: a SOT-MRAM cell array, the SOT-MRAM cell array having a magnetic storage layer and a first lead disposed side by side with the magnetic storage layer and contacting the magnetic storage layer.

[0006] In another embodiment, a memory device includes: a SOT-MRAM cell array, the SOT-MRAM cell array having a contact; a magnetic reference layer disposed on the contact; a barrier layer disposed on the magnetic reference layer; a magnetic storage layer disposed on the barrier layer; and a lead disposed side by side with and contacting the magnetic storage layer.

[0007] In another embodiment, a memory device includes: a SOT-MRAM cell array having a first lead; a magnetic storage layer arranged side by side with and contacting the first lead; a barrier layer arranged on the first lead and the magnetic storage layer; a magnetic reference layer arranged on the barrier layer; and a second lead arranged on the magnetic reference layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order that the features of the present disclosure described above may be understood in detail, a more specific description of the present disclosure briefly summarized above may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, and the present disclosure may allow other equally effective embodiments.

[0009] Figure 1 is a schematic diagram of a memory cell array.

[0010] FIG. 2 is a schematic perspective view of a conventional memory cell.

[0011] Figure 3 is a schematic perspective view of a memory cell.

[0012] Figure 4A yes Figure 3 A schematic top view of a portion of a memory cell is shown.

[0013] Figure 4B yes Figure 4A A schematic cross-sectional side view of the portion of a memory cell is shown.

[0014] Figure 5A is a schematic top view of a memory cell.

[0015] Figure 5B yes Figure 5AA schematic cross-sectional side view of a memory cell is shown.

[0016] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0017] Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to SOT-MRAM. SOT-MRAM includes a memory cell having a magnetic storage layer, which is arranged side by side with a SOT layer and contacts the SOT layer. The side-by-side magnetic storage layer and the SOT layer can achieve switching of the magnetic storage layer by reversing the direction of the current flowing through the SOT layer without any additional conditions.

[0018] Figure 1 is a schematic diagram of a memory cell array 100. The memory cell array 100 may be part of a SOT-MRAM cell and chip architecture. The memory cell array 100 includes a plurality of first leads 104, a plurality of second leads 106, and a plurality of memory cells 102. The plurality of first leads 104 may be substantially parallel to each other, the plurality of second leads 106 may be substantially parallel to each other, and each first lead 104 may be substantially perpendicular to each second lead 106. The plurality of first leads 104 may be disposed above the plurality of second leads 106. The plurality of first leads 104 may be bit lines, and the plurality of second leads 106 may be word lines. Figure 1 Four first leads 104 and four second leads 106 are shown in FIG. 1 , but the memory cell array 100 may include more than four first leads 104 and second leads 106 .

[0019] FIG2 is a schematic perspective view of a conventional memory cell 202. As shown in FIG2, the conventional memory cell 202 is disposed between a first lead 204 and a second lead 206. The conventional memory cell 202 includes a magnetic storage layer 208 disposed on the second lead 206.

[0020] Figure 3 is a schematic perspective view of the memory unit 102. Figure 3As shown, the memory cell 102 is in contact with the first lead 301 and the second lead 303. The second lead 303 is made of a material with strong spin-orbit coupling (such as a metal or a metal alloy). In one example, the second lead 303 is made of platinum, tantalum, tungsten, palladium or iridium. In another example, the second lead 303 is made of a metal alloy containing one or more metals (such as platinum, tantalum, tungsten, palladium, molybdenum, copper, gold, silver, ruthenium, iridium, manganese, bismuth, antimony, tellurium, hafnium, magnesium or selenium). In one example, the second lead 303 is a SOT layer and the memory cell 102 is a SOT-MRAM cell. The first lead 301 is made of a conductive material (such as tantalum nitride, titanium nitride, tungsten nitride or other suitable material). In one example, the first lead 301 is made of a metal. The first lead 301 is made of a material different from the material of the second lead 303. In one example, the first lead 301 is Figure 1 The first lead 104 is shown, and the second lead 303 is Figure 1 A second lead 106 is shown.

[0021] The memory cell 102 may include a magnetic storage layer 302, a barrier layer 304, and a magnetic reference layer 306. The magnetic storage layer 302, the barrier layer 304, and the magnetic reference layer 306 form an MTJ. The magnetic storage layer 302 and the magnetic reference layer 306 are made of a ferromagnetic material such as a metal alloy with a dopant such as a boron dopant, an oxygen dopant, or other suitable material. The metal alloy may contain nickel (Ni), platinum (Pt), ruthenium (Ru), cobalt (Co), iron (Fe), tantalum (Ta), or palladium (Pd). Suitable examples of ferromagnetic materials include Ru, Ta, Co, Pt, TaN, NiFeOx, NiFeB, CoFeOxB, CoFeB, CoFe, NiOxB, CoBOx, FeBOx, CoFeNiB, CoPt, CoPd, TaOx, and the like. In one example, the magnetic storage layer 302 and the magnetic reference layer 306 are made of Co, Fe, Ni, or alloys thereof. The barrier layer 304 may be made of a dielectric material for a tunnel junction magnetoresistance (TMR) sensor, or a conductive material for a giant magnetoresistance (GMR) sensor. If the memory cell 102 is a TMR sensor, the barrier layer 304 is made of MgO, HfO2, TiO2, Ta2O5, Al2O3, or other suitable materials. If the memory cell 102 is a GMR sensor, the barrier layer 304 is made of copper, silver, or other suitable materials.

[0022] like Figure 3As shown, the magnetic storage layer 302 is arranged side by side with the second lead 303 and contacts the second lead 303. The second lead 303 has a first surface 308 facing the first lead 301 and a second surface 310 connected to the first surface 308. In one example, the second surface 310 is substantially perpendicular to the first surface 308. The magnetic storage layer 302 has a first surface 312 in contact with the second surface 310 of the second lead 303. In one example, the second surface 310 corresponds to the thickness dimension of the second lead 303, and the second lead 303 is deposited or grown with the thickness dimension. Figure 3 As shown, at least two surfaces 308, 310 of the second lead 303 are in contact with the memory cell 102. In one example, the memory cell 102 is a three-terminal SOT-MRAM memory cell and the leads 301, 303 are connected to an access transistor or to an access transistor and a diode.

[0023] Figure 4A yes Figure 3 A schematic top view of a portion of a memory cell 102 is shown, and Figure 4B It is along Figure 4A 4A and 4B, the second lead 303 and the magnetic storage layer 302 are arranged side by side and in contact with each other on the substrate 402. The substrate 402 may include one or more transistors formed thereon, and the second lead 303 and the magnetic storage layer 302 may be arranged on a dielectric material (such as an oxide, for example, silicon oxide). The second lead 303 and the magnetic storage layer 302 may be manufactured by any suitable method. In one example, a blanket layer is formed on the substrate 402. The blanket layer is made of the same material as the magnetic storage layer 302. The blanket layer is then patterned to form the magnetic storage layer 302. The second lead 303 is then deposited on the substrate 402. In another example, a blanket layer is formed on the substrate 402. The blanket layer is made of the same material as the second lead 303. The blanket layer is then patterned to form the second lead 303. The magnetic storage layer 302 is then deposited on the substrate 402 .

[0024] The second lead 303 includes a first surface 308 and a second surface 310 substantially perpendicular to the first surface 308. The magnetic storage layer 302 includes a first surface 312 in contact with the second surface 310 of the second lead 303. The magnetic storage layer 302 also includes a second surface 404 connected to the first surface 312, such as Figure 4B In one example, the second surface 404 is substantially perpendicular to the first surface 312. The second surface 404 may face the first lead 301. In one example, the second surface 404 is substantially coplanar with the first surface 308 of the second lead 303, and the barrier layer 304 (such as Figure 3 The layers shown in FIG. 4A and FIG. 4B may be arranged on both surfaces 308 and 404. With the magnetic storage layer 302 and the second lead 303 (SOT layer) arranged side by side, the magnetic moments of the SOT and the magnetic storage layer 302 generated by the second lead 303 are both perpendicular to the substrate 402, which can achieve switching of the magnetic storage layer 302 by reversing the direction of the current flowing through the second lead 303 without any additional conditions.

[0025] Figure 5A is a schematic top view of a portion of a memory cell 102 according to another embodiment, and Figure 5B It is along Figure 5A 5A and 5B, the second lead 303 and the magnetic storage layer 302 are arranged side by side and in contact with each other. The magnetic storage layer 302 includes a portion 504 extending below the second lead 303. The first surface 308 of the second lead 303 is disposed on and in contact with the portion 504 of the magnetic storage layer 302. The second surface 310 of the second lead 303 is in contact with the first surface 312 of the magnetic storage layer 302. The second surface 310 of the second lead 303 forms an angle A with respect to the first surface 308 of the second lead 303. In one example, the angle A is about 90 degrees. In another example, the angle A is an acute angle. In yet another example, the angle A is an obtuse angle.

[0026] The magnetic storage layer 302 and the second lead 303 are disposed on the barrier layer 304. Figure 5B The second surface 404 of the magnetic storage layer 302 may contact the barrier layer 304. The barrier layer 304 is disposed on the magnetic reference layer 306, and the magnetic reference layer 306 is disposed on the contact 502. In one example, the contact 502 is the first lead 301.

[0027] With the magnetic storage layer and the SOT layer side by side, the magnetic moments of the SOT generated by the SOT layer and the magnetic storage layer are parallel to each other, which can achieve switching of the magnetic storage layer by reversing the direction of the current flowing through the SOT layer without any additional conditions.

[0028] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof and the scope of the disclosure is determined by the claims that follow.

Claims

1. A memory device, comprising: A spin-orbit torque magnetoresistive random access memory cell comprising: A first lead, the first lead being disposed on the magnetic reference layer; a barrier layer disposed under the magnetic reference layer and contacting the magnetic reference layer; a magnetic storage layer disposed below and in contact with the barrier layer; A second lead, the second lead is disposed under the barrier layer and contacts the barrier layer, the second lead is disposed side by side with the magnetic storage layer and contacts the magnetic storage layer; and a substrate disposed below and in contact with each of the magnetic storage layer and the second lead, The switching of the magnetic storage layer is achieved by reversing the direction of the current flowing along the second lead. 2 . The memory device of claim 1 , wherein the magnetic storage layer comprises Co, Fe, Ni or a combination thereof.

3. The memory device of claim 1 , wherein the second lead comprises platinum, tantalum, tungsten, palladium, iridium, or a metal alloy comprising platinum, tantalum, tungsten, palladium, molybdenum, copper, gold, silver, ruthenium, iridium, manganese, bismuth, antimony, tellurium, hafnium, magnesium, or selenium. 4 . The memory device of claim 1 , wherein the second lead includes a first surface and a second surface substantially perpendicular to the first surface, and the first surface is configured to face the first lead. 5 . The memory device of claim 4 , wherein the magnetic storage layer comprises a first surface and a second surface substantially perpendicular to the first surface. 6 . The memory device according to claim 5 , wherein the first surface of the magnetic storage layer contacts the second surface of the second lead, and the second surface is configured to face the first lead.

7. A memory device comprising: A spin-orbit torque magnetoresistive random access memory cell comprising: contact; a magnetic reference layer disposed on the contact; a barrier layer having a bottom surface contacting the magnetic reference layer; a magnetic storage layer disposed on the barrier layer; a lead disposed side by side with and in contact with the magnetic storage layer, wherein the bottom surface of the barrier layer contacts the lead; and A substrate is disposed below and in contact with each of the magnetic storage layer and the lead, wherein switching of the magnetic storage layer is achieved by reversing the direction of a current flowing along the lead. 8 . The memory device of claim 7 , wherein the magnetic storage layer and the magnetic reference layer each comprise Co, Fe, Ni, or a combination thereof.

9. The memory device of claim 7, wherein the lead comprises platinum, tantalum, tungsten, palladium, iridium, or a metal alloy comprising platinum, tantalum, tungsten, palladium, molybdenum, copper, gold, silver, ruthenium, iridium, manganese, bismuth, antimony, tellurium, hafnium, magnesium, or selenium.

10. The memory device of claim 7, wherein the barrier layer comprises MgO, HfO2, TiO2, Ta2O5 or Al2O3. The memory device of claim 7 , wherein the barrier layer comprises copper or silver.

12. The memory device of claim 7, wherein the lead comprises a first surface facing the contact and a second surface connected to the first surface. 13 . The memory device of claim 12 , wherein the magnetic storage layer comprises a first surface facing the contact and a second surface connected to the first surface. The memory device of claim 13 , wherein the second surface of the magnetic storage layer contacts the second surface of the lead. 15 . The memory device of claim 1 , wherein the magnetic storage layer and the magnetic reference layer each comprise Co, Fe, Ni, or a combination thereof.

16. The memory device of claim 1, wherein the barrier layer comprises MgO, HfO2, TiO2, Ta2O5 or Al2O3.

17. The memory device of claim 1, wherein the barrier layer comprises copper or silver.

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