A test system for supercapacitor circuits

Abstract

The application relates to a test system of a super capacitor circuit, which comprises a super capacitor circuit and a test tool, wherein at least one test point is arranged at the voltage input end and the voltage output end of a charging circuit in the super capacitor circuit, a test point is arranged at the position where the voltage level of a voltage equalizing circuit changes after the voltage equalizing circuit is activated, at least one test point is arranged at the voltage input end and the voltage output end of a voltage boosting circuit, and at least one test point is arranged at the voltage input end and the voltage output end of a discharging circuit; the output voltage of the first test voltage output end of the test tool is higher than the sum of the nominal voltages of all super capacitors in the charging and discharging circuit, and the output voltage of the second test voltage output end is higher than the detection voltage of any power supply monitoring chip in the charging and discharging circuit and is smaller than the target voltage output by the voltage boosting circuit. The test system can complete the super capacitor circuit test before the production of the super capacitor circuit product, and avoids the complex process of product repair after assembly.

Description

Technical Field

[0001] This invention relates to the field of supercapacitor circuits, and more particularly to a testing system for supercapacitor circuits. Background Technology

[0002] With the operation of various power terminal equipment in the power grid, new requirements have been put forward for the operation standards of power terminal equipment. That is, in the event of a power outage, the supercapacitor circuit in the power terminal equipment needs to be able to provide power for at least 3 minutes to ensure that the power terminal equipment can complete the necessary operations.

[0003] To meet the discharge time requirements of the supercapacitor circuits within the power terminal equipment, accurate testing must be conducted on the supercapacitor's charging and discharging circuits, as well as its boost and buck circuits. This ensures that problems can be identified and resolved before the power terminal equipment is manufactured, preventing high back-end maintenance costs after production begins.

[0004] Current testing methods for supercapacitor circuits merely calculate the supercapacitor's charging and discharging performance by determining the power supply time after a power outage has occurred. This approach is not only inefficient but also fails to assess the performance of the supercapacitor's boost / buck circuitry. This leaves potential faults for the normal operation of the power terminal equipment after it leaves the factory, increasing the cost of subsequent maintenance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a testing system for supercapacitor circuits in light of the above-mentioned prior art.

[0006] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a testing system for supercapacitor circuits, characterized in that it includes a supercapacitor circuit and testing fixtures; wherein, the supercapacitor circuit includes:

[0007] The charging circuit has a charging circuit voltage input terminal, at least two supercapacitors connected in series, at least two power monitoring chips, and a charging circuit voltage output terminal. The charging circuit voltage input terminal is provided with at least one test point, and the charging circuit voltage output terminal is provided with at least one test point.

[0008] The voltage equalization circuit has test points set at the locations where the voltage level changes after it is activated.

[0009] A boost circuit has a boost circuit voltage input terminal and a boost circuit voltage output terminal, and each of the boost circuit voltage input terminal and the boost circuit voltage output terminal is provided with at least one test point;

[0010] The discharge circuit has a discharge circuit voltage input terminal and a discharge circuit voltage output terminal. The discharge circuit voltage input terminal is provided with at least one test point, and the discharge circuit voltage output terminal is provided with at least one test point.

[0011] The test fixture has a test voltage output terminal group and a test voltage input terminal group. The test voltage output terminal group includes at least a first test voltage output terminal and a second test voltage output terminal, and the test voltage input terminal group includes at least one test voltage input terminal.

[0012] In the testing fixture, the output voltage of the first test voltage output terminal is higher than the sum of the nominal voltages of all supercapacitors in the charging and discharging circuit, and the output voltage of the second test voltage output terminal is higher than the detection voltage of any power monitoring chip in the charging and discharging circuit but lower than the target voltage output by the boost circuit.

[0013] Furthermore, in the test system for the supercapacitor circuit, the test fixture has a display and a grounding terminal.

[0014] Improvedly, in the test system for the supercapacitor circuit, the charging circuit includes:

[0015] Resistor R218, the first end of which is connected to the first voltage output interface of the test fixture;

[0016] Resistor R541, the first end of which is connected to the second end of resistor R218;

[0017] The emitter of transistor V106 is connected to the second terminal of resistor R218 and the first terminal of resistor R541, respectively.

[0018] Diode VD332, its positive terminal is connected to the collector of transistor V106;

[0019] Transistor V109 has its emitter connected to the first voltage output interface of the test fixture, its base connected to the second terminal of resistor R541, and its collector connected to the base of transistor V106.

[0020] Resistor R539, its first end is connected to the collector of transistor V109;

[0021] The collector of transistor V103 is connected to the second terminal of resistor R539.

[0022] Resistor R214, its second end is connected to the base of transistor V103;

[0023] Resistor R236, its first end is connected to the second end of resistor R214, and its second end and the emitter of transistor V103 are respectively connected to ground GND;

[0024] Among them, the first terminal of resistor R218 is provided with test point TP6, the negative terminal of diode VD332 is provided with test point TP1, and the emitter of transistor V103 is provided with test point TP5.

[0025] Further, in the test system for the supercapacitor circuit, the voltage equalization circuit includes:

[0026] Supercapacitor C207;

[0027] The positive terminal of supercapacitor C225 is connected to the negative terminal of supercapacitor C207 through a shorting point S101, and its negative terminal is connected to the ground terminal GND through another shorting point S100.

[0028] The power monitoring chip N109 has one pin connected to the positive terminal of the supercapacitor C207;

[0029] Resistor R294, its first end is connected to the positive terminal of supercapacitor C207;

[0030] Resistor R306 has its first end connected to power monitoring chip N109, and its second end connected to the second end of resistor R294 through MOSFET M102.

[0031] Resistor R307, its first end is connected to the second end of resistor R306, and its second end is connected to the ground terminal GND and the shorting point S100 of power monitoring chip N109 respectively.

[0032] The power monitoring chip N110 has a ground terminal. One pin of the power monitoring chip N110 is connected to the shorting point S100 and the ground terminal GND of the power monitoring chip N109.

[0033] Resistor R316 has its first end connected to one end of power monitoring chip N110, and its second end connected to the second end of resistor R311 through MOSFET M101. The first end of resistor R311 is connected to the second end of resistor R307.

[0034] Resistor R317, its first end is connected to the second end of resistor R316, and its second end is connected to the ground terminal GND of power monitoring chip N110.

[0035] Specifically, the test point TP1 is set between the positive terminal of supercapacitor C207 and the first end of resistor R294; the test point TP2 is set between the second end of resistor R294 and MOSFET M102; the test point TP3 is set between the second end of resistor R307 and the ground terminal GND of power monitoring chip N109; the test point TP4 is set between the second end of resistor R311 and MOSFET M101; and the test point TP5 is set between the second end of resistor R317 and the ground terminal GND of power monitoring chip N110.

[0036] In a further improvement, in the test system for the supercapacitor circuit, the boost circuit includes:

[0037] Voltage conversion chip N106;

[0038] The series resistor group includes resistors R301, R302 and R303 connected in series. The first end of resistor R310 is grounded and the second end of resistor R310 is connected to resistor R302. The feedback terminal FB of voltage conversion chip N106 is connected between resistor 301 and resistor R302.

[0039] Resistor R304 has its first end connected to the positive terminal of supercapacitor C207, and its second end connected to the collector of transistor V104. The emitter of transistor V104 is connected to ground GND and one end of resistor R257. The other end of resistor R257 is connected to the base of transistor V104 and one end of resistor R210. The second end of resistor R304 is connected to the enable terminal EN of voltage converter chip N106. The power supply terminal VDD of voltage converter chip N106 is connected to ground GND through capacitor C243. The input voltage terminal VIN of voltage converter chip N106 is connected to ground GND through capacitor C246. The SW terminal of voltage converter chip N106 is connected to the input voltage terminal VIN of voltage converter chip N106 through inductor L107. The BST terminal of voltage converter chip N106 is connected to the SW terminal of voltage converter chip N106 through capacitor C244.

[0040] The parallel capacitor bank includes capacitors C247 and C245 connected in parallel. The first parallel terminal of the parallel capacitor bank is connected to the output voltage terminal VOUT of the voltage conversion chip N106, and the second parallel terminal of the parallel capacitor bank is connected to the ground terminal GND.

[0041] The voltage conversion chip N106 has a test point TP1 between its input voltage terminal VIN and capacitor C246, the parallel capacitor bank has a test point TP5 at its second parallel terminal, and the parallel capacitor bank has a test point TP6 at its first parallel terminal.

[0042] For example, in this invention, the voltage conversion chip N106 is a DC-DC voltage conversion chip.

[0043] Furthermore, in the supercapacitor circuit testing system, the output voltage of the first test voltage output terminal in the testing fixture is 5.4V, the output voltage of the second test voltage output terminal is 2.7V, and the detection voltage of the chip N109 is 2.6V.

[0044] Furthermore, in the test system for the supercapacitor circuit, both the power monitoring chip N109 and the power monitoring chip N110 are model SGM809B.

[0045] Furthermore, in the testing system for the supercapacitor circuit, the chip N106 is model MP3437GJ.

[0046] Furthermore, in the test system of the supercapacitor circuit, the capacitance values ​​of capacitor C207 and capacitor C225 are both 150F.

[0047] Compared with the prior art, the advantages of the present invention are as follows: In the supercapacitor circuit testing system of the present invention, the testing fixture can test the voltage equalization circuit, charging circuit and boost circuit of the supercapacitor circuit at the production front end of the product equipped with supercapacitor circuit, avoiding the complex process of rework after product assembly, and reducing time and maintenance costs; secondly, the testing system of the present invention can simply and quickly complete the performance test of the supercapacitor circuit, and realize the synchronous test of the supercapacitor circuit in multiple products. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the test fixture in an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of the charging circuit in a supercapacitor circuit.

[0050] Figure 3 This is a schematic diagram of the voltage equalization circuit in a supercapacitor circuit.

[0051] Figure 4 This is a schematic diagram of the boost discharge circuit in a supercapacitor circuit. Detailed Implementation

[0052] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0053] This embodiment provides a testing system for supercapacitor circuits. Specifically, see... Figures 1-4 As shown, the test system for the supercapacitor circuit in this embodiment includes:

[0054] The charging circuit has a charging circuit voltage input terminal, at least two supercapacitors connected in series, at least two power monitoring chips, and a charging circuit voltage output terminal. The charging circuit voltage input terminal is provided with at least one test point, and the charging circuit voltage output terminal is provided with at least one test point.

[0055] The voltage equalization circuit has test points set at the locations where the voltage level changes after it is activated.

[0056] A boost circuit has a boost circuit voltage input terminal and a boost circuit voltage output terminal, and each of the boost circuit voltage input terminal and the boost circuit voltage output terminal is provided with at least one test point;

[0057] The discharge circuit has a discharge circuit voltage input terminal and a discharge circuit voltage output terminal. The discharge circuit voltage input terminal is provided with at least one test point, and the discharge circuit voltage output terminal is provided with at least one test point.

[0058] The testing fixture includes a test voltage output terminal group and a test voltage input terminal group. The test voltage output terminal group includes a first test voltage output terminal, a second test voltage output terminal, and a third test voltage output terminal. The test voltage input terminal group includes at least one test voltage input terminal. Each voltage output terminal in the test voltage output terminal group is responsible for providing the test voltage to the supercapacitor circuit, and the voltage input terminal in the test voltage input terminal group is responsible for acquiring the voltage at the corresponding test point within the supercapacitor circuit. For example... Figure 1 The test fixture has test voltage input terminals T1, T2, T3, and T4. The first test voltage output terminal outputs 5.4V, and the second test voltage output terminal outputs 2.7V. Furthermore, the test fixture includes a display and a ground terminal GND. The display allows the test fixture to show the voltages at the test points acquired from the test voltage input terminals via a visual interface.

[0059] In the testing fixture, the output voltage of the first test voltage output terminal is higher than the sum of the nominal voltages of all supercapacitors in the charging and discharging circuit, and the output voltage of the second test voltage output terminal is higher than the detection voltage of any power monitoring chip in the charging and discharging circuit but lower than the target voltage output by the boost circuit.

[0060] Specifically, in this embodiment, see Figure 2 As shown, the charging circuit includes:

[0061] Resistor R218, the first end of which is connected to the first voltage output interface of the test fixture;

[0062] Resistor R541, the first end of which is connected to the second end of resistor R218;

[0063] The emitter of transistor V106 is connected to the second terminal of resistor R218 and the first terminal of resistor R541, respectively.

[0064] Diode VD332, its positive terminal is connected to the collector of transistor V106;

[0065] Transistor V109 has its emitter connected to the first voltage output interface of the test fixture, its base connected to the second terminal of resistor R541, and its collector connected to the base of transistor V106.

[0066] Resistor R539, its first end is connected to the collector of transistor V109;

[0067] The collector of transistor V103 is connected to the second terminal of resistor R539.

[0068] Resistor R214, its second end is connected to the base of transistor V103;

[0069] Resistor R236, its first end is connected to the second end of resistor R214, and its second end and the emitter of transistor V103 are respectively connected to ground GND;

[0070] Among them, the first terminal of resistor R218 is provided with test point TP6, the negative terminal of diode VD332 is provided with test point TP1, and the emitter of transistor V103 is provided with test point TP5.

[0071] See Figure 3 As shown, the voltage equalization circuit includes:

[0072] The supercapacitor C207 has a capacitance of 150F;

[0073] The positive terminal of supercapacitor C225 is connected to the negative terminal of supercapacitor C207 through a shorting point S101, and its negative terminal is connected to the ground terminal GND through another shorting point S100. The capacitance value of supercapacitor C225 is also 150F.

[0074] The power monitoring chip N109 has one pin connected to the positive terminal of the supercapacitor C207. The model of the power monitoring chip N109 is SGM809B, and the detection voltage of the power monitoring chip N109 is 2.6V.

[0075] Resistor R294, its first end is connected to the positive terminal of supercapacitor C207;

[0076] Resistor R306 has its first end connected to power monitoring chip N109, and its second end connected to the second end of resistor R294 through MOSFET M102.

[0077] Resistor R307, its first end is connected to the second end of resistor R306, and its second end is connected to the ground terminal GND and the shorting point S100 of power monitoring chip N109 respectively.

[0078] The power monitoring chip N110 has a ground terminal. One pin of the power monitoring chip N110 is connected to the shorting point S100 and the ground terminal GND of the power monitoring chip N109 respectively. The model of the power monitoring chip N110 is also SGM809B.

[0079] Resistor R316 has its first end connected to one end of power monitoring chip N110, and its second end connected to the second end of resistor R311 through MOSFET M101. The first end of resistor R311 is connected to the second end of resistor R307.

[0080] Resistor R317, its first end is connected to the second end of resistor R316, and its second end is connected to the ground terminal GND of power monitoring chip N110.

[0081] Specifically, the test point TP1 is set between the positive terminal of supercapacitor C207 and the first end of resistor R294; the test point TP2 is set between the second end of resistor R294 and MOSFET M102; the test point TP3 is set between the second end of resistor R307 and the ground terminal GND of power monitoring chip N109; the test point TP4 is set between the second end of resistor R311 and MOSFET M101; and the test point TP5 is set between the second end of resistor R317 and the ground terminal GND of power monitoring chip N110.

[0082] See Figure 4 As shown, the boost circuit includes:

[0083] The N106 voltage conversion chip is a DC-DC voltage conversion chip.

[0084] The series resistor group includes resistors R301, R302 and R303 connected in series. The first end of resistor R310 is grounded and the second end of resistor R310 is connected to resistor R302. The feedback terminal FB of voltage conversion chip N106 is connected between resistor 301 and resistor R302.

[0085] Resistor R304 has its first end connected to the positive terminal of supercapacitor C207, and its second end connected to the collector of transistor V104. The emitter of transistor V104 is connected to ground GND and one end of resistor R257. The other end of resistor R257 is connected to the base of transistor V104 and one end of resistor R210. The second end of resistor R304 is connected to the enable terminal EN of voltage converter chip N106. The power supply terminal VDD of voltage converter chip N106 is connected to ground GND through capacitor C243. The input voltage terminal VIN of voltage converter chip N106 is connected to ground GND through capacitor C246. The SW terminal of voltage converter chip N106 is connected to the input voltage terminal VIN of voltage converter chip N106 through inductor L107. The BST terminal of voltage converter chip N106 is connected to the SW terminal of voltage converter chip N106 through capacitor C244.

[0086] The parallel capacitor bank includes capacitors C247 and C245 connected in parallel. The first parallel terminal of the parallel capacitor bank is connected to the output voltage terminal VOUT of the voltage conversion chip N106, and the second parallel terminal of the parallel capacitor bank is connected to the ground terminal GND.

[0087] The voltage conversion chip N106 has a test point TP1 between its input voltage terminal VIN and capacitor C246, the second parallel terminal of the parallel capacitor bank has a test point TP5, and the first parallel terminal of the parallel capacitor bank has a test point TP6.

[0088] The following combination Figures 1-4 The testing process of the test system for the supercapacitor circuit in this embodiment is described below:

[0089] (I) Charging Circuit Test Scheme

[0090] Connect the +5.4V output voltage of the test fixture to test point TP6 and the ground terminal GND of the test fixture to test point TP5. Connect the test voltage input interface T1 of the test fixture to test point TP1 and the test voltage input interface T2 to test point TP5. Short-circuit points S100 and S101, and then power on the test fixture. When a rising edge of voltage is detected between test points TP1 and TP5, it indicates that the charging circuit is working normally after testing.

[0091] (II) Voltage Equalization Circuit Test Scheme

[0092] Connect the three output interfaces (i.e., the three test voltage output terminals) of the test fixture to... Figure 3 Connect test points TP1, TP3, and TP5, then connect the input interfaces of the test fixture to test points TP1, TP2, TP3, and TP4 respectively, and disconnect shorting points S100 and S101. Then power on the test fixture.

[0093] When the voltage equalization circuit is working, a square wave with a period of 280ms will appear between test points TP1 and TP2, and between test points TP3 and TP4. This indicates that the voltage equalization circuit has been tested and is working normally, ensuring that the circuit can perform voltage equalization when there is a voltage difference between the two supercapacitors C207 and C225 under actual operating conditions.

[0094] After the test fixture is powered on, the input voltage of the power monitoring chip N110 is 2.7V. The nRESET pin of the power monitoring chip N110 outputs a high level, turning on the MOSFET M101. At this time, the voltage drop across MOSFET M101 is close to 0V, so the voltage drop between test points TP3 and TP4 is close to 2.7V. Due to the sudden connection of resistor R311, the input voltage of the power monitoring chip N110 fluctuates and drops below 2.6V. When this drops, the nRESET pin of the power monitoring chip N110 immediately outputs a low level, turning off MOSFET M101. At this point, the voltage drop between test points TP3 and TP4 is close to 0V. The input voltage of the power monitoring chip N110 gradually rises as the load decreases. When the input voltage exceeds 2.6V, due to the delay of the power monitoring chip N110, the nRESET pin will output a high level after 140ms, and this cycle repeats. The working principle of the power monitoring chip N109 is the same as that of the power monitoring chip N110.

[0095] (III) Test Scheme for Boost Circuit

[0096] Connect the +2.7V test voltage output terminal of the test fixture to... Figure 4 Test point TP1 and the grounding terminal GND of the test fixture are connected to test point TP5, then disconnected. Figure 3 Shorting points S100 and S101 are connected, and the test voltage input interface T1 of the test fixture is connected. Figure 3 Test point TP6 is connected to the test voltage input interface T2 of the test fixture. Figure 3 Test point TP5 is then used to power on the test fixture.

[0097] When the voltage difference between test point TP6 and test point TP5 is detected to be 5.2V, it indicates that the boost circuit is working normally. The boost circuit will not work when the input voltage is higher than the output voltage. Therefore, the boost circuit is tested by ensuring the input voltage is lower than the output voltage.

[0098] Although preferred embodiments of the present invention have been described in detail above, it should be clearly understood that various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A testing system for a supercapacitor circuit, characterized in that, Includes supercapacitor circuitry and testing fixtures; the supercapacitor circuitry includes: A charging circuit has a charging circuit voltage input terminal and a charging circuit voltage output terminal. The charging circuit voltage input terminal is provided with at least one test point, and the charging circuit voltage output terminal is provided with at least one test point. The voltage equalization circuit has test points set at the locations where the voltage level changes after it is activated; the voltage equalization circuit has at least two supercapacitors connected in series and at least two power monitoring chips. A boost circuit has a boost circuit voltage input terminal and a boost circuit voltage output terminal, and each of the boost circuit voltage input terminal and the boost circuit voltage output terminal is provided with at least one test point; The discharge circuit has a discharge circuit voltage input terminal and a discharge circuit voltage output terminal. The discharge circuit voltage input terminal is provided with at least one test point, and the discharge circuit voltage output terminal is provided with at least one test point. The test fixture has a test voltage output terminal group and a test voltage input terminal group. The test voltage output terminal group includes at least a first test voltage output terminal and a second test voltage output terminal, and the test voltage input terminal group includes at least one test voltage input terminal. In the test fixture, the output voltage of the first test voltage output terminal is higher than the sum of the nominal voltages of all supercapacitors in the voltage equalization circuit, and the output voltage of the second test voltage output terminal is higher than the detection voltage of any power monitoring chip in the voltage equalization circuit but lower than the target voltage output by the boost circuit; where: The test fixture has a display and a grounding terminal; The charging circuit includes: Resistor R218, the first end of which is connected to the first voltage output interface of the test fixture; Resistor R541, the first end of which is connected to the second end of resistor R218; The emitter of transistor V106 is connected to the second terminal of resistor R218 and the first terminal of resistor R541, respectively. Diode VD332, its positive terminal is connected to the collector of transistor V106; Transistor V109 has its emitter connected to the first voltage output interface of the test fixture, its base connected to the second terminal of resistor R541, and its collector connected to the base of transistor V106. Resistor R539, its first end is connected to the collector of transistor V109; The collector of transistor V103 is connected to the second terminal of resistor R539. Resistor R214, its second end is connected to the base of transistor V103; Resistor R236, its first end is connected to the second end of resistor R214, and its second end and the emitter of transistor V103 are respectively connected to ground GND; Among them, the first terminal of resistor R218 is provided with test point TP6, the negative terminal of diode VD332 is provided with test point TP1, and the emitter of transistor V103 is provided with test point TP5. The voltage equalization circuit includes: Supercapacitor C207; The positive terminal of supercapacitor C225 is connected to the negative terminal of supercapacitor C207 through a shorting point S101, and its negative terminal is connected to the ground terminal GND through another shorting point S100. The power monitoring chip N109 has one pin connected to the positive terminal of the supercapacitor C207; Resistor R294, its first end is connected to the positive terminal of supercapacitor C207; Resistor R306 has its first end connected to power monitoring chip N109, and its second end connected to the second end of resistor R294 through MOSFET M102. Resistor R307, its first end is connected to the second end of resistor R306, and its second end is connected to the ground terminal GND and the shorting point S100 of power monitoring chip N109 respectively. The power monitoring chip N110 has a ground terminal. One pin of the power monitoring chip N110 is connected to the shorting point S100 and the ground terminal GND of the power monitoring chip N109. Resistor R316 has its first end connected to one end of power monitoring chip N110, and its second end connected to the second end of resistor R311 through MOSFET M101. The first end of resistor R311 is connected to the second end of resistor R307. Resistor R317, its first end is connected to the second end of resistor R316, and its second end is connected to the ground terminal GND of power monitoring chip N110. Specifically, the test point TP1 is set between the positive terminal of supercapacitor C207 and the first end of resistor R294; the test point TP2 is set between the second end of resistor R294 and MOSFET M102; the test point TP3 is set between the second end of resistor R307 and the ground terminal GND of power monitoring chip N109; the test point TP4 is set between the second end of resistor R311 and MOSFET M101; and the test point TP5 is set between the second end of resistor R317 and the ground terminal GND of power monitoring chip N110.

2. The testing system for supercapacitor circuits according to claim 1, characterized in that, The boost circuit includes: Voltage conversion chip N106; The series resistor group includes resistors R301, R302 and R303 connected in series. The first end of resistor R310 is grounded and the second end of resistor R310 is connected to resistor R302. The feedback terminal FB of voltage conversion chip N106 is connected between resistor 301 and resistor R302. Resistor R304 has its first end connected to the positive terminal of supercapacitor C207, and its second end connected to the collector of transistor V104. The emitter of transistor V104 is connected to ground GND and one end of resistor R257. The other end of resistor R257 is connected to the base of transistor V104 and one end of resistor R210. The second end of resistor R304 is connected to the enable terminal EN of voltage converter chip N106. The power supply terminal VDD of voltage converter chip N106 is connected to ground GND through capacitor C243. The input voltage terminal VIN of voltage converter chip N106 is connected to ground GND through capacitor C246. The SW terminal of voltage converter chip N106 is connected to the input voltage terminal VIN of voltage converter chip N106 through inductor L107. The BST terminal of voltage converter chip N106 is connected to the SW terminal of voltage converter chip N106 through capacitor C244. The parallel capacitor bank includes capacitors C247 and C245 connected in parallel. The first parallel terminal of the parallel capacitor bank is connected to the output voltage terminal VOUT of the voltage conversion chip N106, and the second parallel terminal of the parallel capacitor bank is connected to the ground terminal GND. The voltage conversion chip N106 has a test point TP1 between its input voltage terminal VIN and capacitor C246, the parallel capacitor bank has a test point TP5 at its second parallel terminal, and the parallel capacitor bank has a test point TP6 at its first parallel terminal.

3. The testing system for supercapacitor circuits according to claim 2, characterized in that, The first test voltage output terminal of the test fixture has an output voltage of 5.4V, the second test voltage output terminal has an output voltage of 2.7V, and the detection voltage of the power monitoring chip N109 is 2.6V.

4. The testing system for supercapacitor circuits according to claim 3, characterized in that, The power monitoring chip N109 and the power monitoring chip N110 are both model SGM809B.

5. The testing system for supercapacitor circuits according to claim 4, characterized in that, The chip N106 is model MP3437GJ.

6. The testing system for supercapacitor circuits according to claim 2, characterized in that, The capacitance values ​​of both supercapacitor C207 and supercapacitor C225 are 150F.

7. The testing system for supercapacitor circuits according to claim 2, characterized in that, The voltage conversion chip N106 is a DC-DC voltage conversion chip.

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