Interrupt Signal Transmission for Directed Interrupt Virtualization

Abstract

The present invention relates to a method for providing an interrupt signal to a guest operating system. A bus-attached device receives an interrupt signal having an interrupt target ID from a bus connection module, and the interrupt target ID is to be assigned to a processor identifier used by the guest operating system as a target processor for processing the interrupt signal. The bus-attached device forwards the interrupt signal to the target processor for processing. The conversion of the interrupt target ID to the logical processor ID of the target processor is used to directly address the target processor. In addition, the bus-attached device updates a directed interrupt signal indicator of a directed interrupt signal vector assigned to the target processor to indicate that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

Description

BACKGROUND OF THE DISCLOSURE

[0001] The present disclosure generally relates to interrupt handling within a computer system, and more particularly to handling interrupts generated by a bus-connected module in a multi-processor computer system.

[0002] Interrupts are used to signal to a processor that an event requires the processor's attention. For example, a hardware device (e.g., a hardware device connected to the processor via a bus) uses an interrupt to convey that it requires attention from the operating system. In the case where the receiving processor is currently performing some activity, the receiving processor may suspend its current activity, save its state, and handle the interrupt, e.g., by executing an interrupt handler, in response to receiving the interrupt signal. The interruption of the processor's current activity due to the reception is only temporary. After handling the interrupt, the processor may resume its suspended activity. Thus, interrupts can allow for performance improvements by eliminating the processor's ineffective waiting time in a polling loop waiting for external events.

[0003] In a multi-processor computer system, interrupt routing efficiency issues may arise. The challenge is to forward an interrupt signal sent by a hardware device (e.g., a bus-connected module) to a processor among multiple processors assigned for use by the operating system in an efficient manner. This can be particularly challenging in the case where interrupts are used to communicate with a guest operating system on a virtual machine. A hypervisor or virtual machine monitor (VMM) creates and runs one or more virtual machines, i.e., guest machines. The virtual machine provides a virtual operating platform to the guest operating system executing thereon while hiding the physical characteristics of the underlying platform. Using multiple virtual machines allows multiple operating systems to run in parallel. Since it is executed on a virtual operating platform, the view of the guest operating system of the processor Figure 1 generally may be different from the underlying (e.g., physical) view of the processor. The guest operating system uses a virtual processor ID to identify the processor, which typically does not match the underlying logical processor ID. The hypervisor that manages the execution of the guest operating system defines a mapping between the underlying logical processor ID and the virtual processor ID used by the guest operating system. However, this mapping and the selection of the processor scheduled for use by the guest operating system are not static, but can be changed by the hypervisor at runtime without the knowledge of the guest operating system.

[0004] Generally, this challenge is addressed by using broadcast to forward the interrupt signal. When using broadcast, the interrupt signal is continuously forwarded among multiple processors until a processor suitable for handling the interrupt signal is encountered. However, in the case of a multi-processor, the probability that the processor that first receives the broadcast interrupt signal is actually suitable for handling the interrupt signal may be quite low. In addition, being suitable for handling the interrupt signal does not necessarily mean that the corresponding processor is the best choice for handling the interrupt. Summary of the Invention

[0005] Various embodiments provide a method, a computer system, and a computer program product for providing an interrupt signal to a guest operating system, where the interrupt signal is executed using one or more of a plurality of processors of a computer system that are allocated for use by the guest operating system. Advantageous embodiments are described in the dependent claims. If the embodiments of the present invention are not mutually exclusive, they can be freely combined with each other.

[0006] In one aspect, the present invention relates to a method for providing an interrupt signal to a guest operating system, where the interrupt signal is executed using one or more of a plurality of processors of a computer system that are allocated for use by the guest operating system. The computer system further includes one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices. The computer system further includes a memory operably connected to the bus-attached devices. Each of the plurality of processors is assigned a logical processor ID used by the bus-attached devices to address the corresponding processor. Each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID used by the operating system and one or more bus connection modules to address the corresponding processor. The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID. Each directed interrupt signal vector includes a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module. Each directed interrupt signal vector indicates whether there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed. The method includes: receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus connection modules, where the interrupt target ID identifies one of the processors allocated for use by the guest operating system as the target processor for processing the interrupt signal; selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed; selecting, by the bus-attached device, in the selected directed interrupt signal vector, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal; updating, by the bus-attached device, the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed; and forwarding, by the bus-attached device, the interrupt signal to the target processor.

[0007] In another aspect, the present invention relates to a computer system for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of the computer system that are allocated for use by the guest operating system. The computer system further includes one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices. The computer system further includes a memory operably connected to the bus-attached devices. Each of the plurality of processors is assigned a logical processor ID used by the bus-attached devices to address the corresponding processor. Each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID used by the operating system and one or more bus connection modules to address the corresponding processor. The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID. Each directed interrupt signal vector includes a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module. Each directed interrupt signal vector indicates whether an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed. The computer system is configured to execute a method that includes: receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus connection modules, the interrupt target ID identifying one of the processors allocated for use by the guest operating system as the target processor for processing the interrupt signal; selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed; selecting, by the bus-attached device, in the selected directed interrupt signal vector, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal; updating the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed; and forwarding, by the bus-attached device, the interrupt signal to the target processor.

[0008] In another aspect, the present invention relates to a computer program product for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of a computer system that are allocated for use by the guest operating system. The computer system further includes one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices. The computer system further includes a memory operably connected to the bus-attached devices. Each of the plurality of processors is assigned a logical processor ID used by the bus-attached devices to address the corresponding processor. Each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID used by the operating system and one or more bus connection modules to address the corresponding processor. The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID. Each directed interrupt signal vector includes a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module. Each directed interrupt signal vector indicates whether an interrupt signal issued by the corresponding bus-attached device and addressed to the corresponding interrupt target ID is waiting to be processed. The computer program product includes a computer-readable non-transitory medium readable by a processing circuit and storing instructions for execution by the processing circuit to perform a method, the method including: receiving, by a bus-attached device, an interrupt signal having an interrupt target ID from one of the bus connection modules, the interrupt target ID identifying one of the processors allocated for use by the guest operating system as a target processor for processing the interrupt signal; selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed; selecting, by the bus-attached device, in the selected directed interrupt signal vector, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal; updating the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed; and forwarding, by the bus-attached device, the interrupt signal to the target processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments of the present invention are explained in more detail below only by way of example, with reference to the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of an exemplary computer system is depicted,

[0011] Figure 2 A schematic diagram of an exemplary virtualization scheme is depicted,

[0012] Figure 3 A schematic diagram of an exemplary virtualization scheme is depicted,

[0013] Figure 4 Shows a schematic diagram of an exemplary virtualization solution,

[0014] Figure 5 Shows a schematic diagram of an exemplary computer system,

[0015] Figure 6 Shows a schematic diagram of an exemplary vector structure,

[0016] Figure 7 shows a schematic diagram of an exemplary vector structure,

[0017] Figure 8 Shows a schematic diagram of an exemplary computer system,

[0018] Figure 9 Shows a schematic flowchart of an exemplary method,

[0019] Figure 10 Shows a schematic flowchart of an exemplary method,

[0020] Figure 11 Shows a schematic flowchart of an exemplary method,

[0021] Figure 12 Shows a schematic diagram of an exemplary computer system,

[0022] Figure 13 shows a schematic flowchart of an exemplary method,

[0023] Figure 14 Shows a schematic flowchart of an exemplary method,

[0024] Figure 15 Shows a schematic flowchart of an exemplary method,

[0025] Figure 16 Shows a schematic flowchart of an exemplary method,

[0026] Figure 17 Shows a schematic flowchart of an exemplary method,

[0027] Figure 18 Shows a schematic diagram of an exemplary data structure,

[0028] Figure 19 shows a schematic flowchart of an exemplary method,

[0029] Figure 20 Shows a schematic diagram of an exemplary computer system,

[0030] Figure 21 Shows a schematic diagram of an exemplary computer system,

[0031] Figure 22 Shows a schematic diagram of an exemplary computer system,

[0032] Figure 23 depicts a schematic diagram of an exemplary computer system,

[0033] FIG. 24 depicts a schematic diagram of an exemplary unit, and

[0034] Figure 25 depicts a schematic diagram of an exemplary computer system. DETAILED DESCRIPTION

[0035] The description of various embodiments of the present invention will be presented for purposes of illustration but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application or technical improvement of technologies found in the marketplace, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

[0036] Embodiments can have the beneficial effect of enabling a bus-attached device to directly address a target processor. Thus, by issuing a bus connection module to select a target processor ID, an interrupt signal can be targeted to a specific processor (i.e., the target processor) of a multiprocessor computer system. For example, a processor can be selected as the target processor of an interrupt signal that has previously performed activities related to the interrupt. Processing the interrupt signal as a corresponding activity by the same processor can result in performance advantages because, in the case where the same processor also processes the interrupt signal, all data in the context of that interrupt may already be available to the processor and / or stored in a local cache, enabling quick access to the corresponding processor without a large amount of cache traffic.

[0037] Therefore, broadcasting of the interrupt signal can be avoided, for which, from a performance perspective, such as minimizing cache traffic, it cannot be guaranteed that the processor that will finally process the interrupt is the most suitable for the task. Instead of providing the interrupt signal to all processors, where each processor attempts to process it and one processor wins, the interrupt signal can be directly provided to the target processor, thereby improving the efficiency of interrupt signal processing.

[0038] The interrupt mechanism can be implemented using directed interrupts. When a bus-attached device forwards an interrupt signal for processing to a target processor defined by the issuing bus connection module, the bus-attached device can be enabled to directly address the target processor using the logical processor ID of the target processor. Converting the interrupt target ID to a logical processor ID by the bus connection device can further ensure that from the perspective of the guest operating system, the same processor is always addressed, even if the mapping between the interrupt target ID and the logical processor ID or the selection of the processor to be scheduled for use by the guest operating system can be changed by the hypervisor.

[0039] The directed interrupt signal vectors are sorted according to the target processor ID, i.e., are optimized to track directed interrupts. In other words, the main ordering criterion is the target processor ID rather than the requester ID identifying the issuing bus connection module. Depending on the number of bus connection modules, each directed interrupt signal vector can include one or more directed interrupt signal indicators.

[0040] Accordingly, sorting of interrupt signal indicators (e.g., in the form of interrupt signaling bits) indicating that individual interrupt signals (e.g., in the form of MSI-X messages) have been sequentially received within consecutive memory regions (e.g., cache lines) for individual bus connection modules (e.g., PCIe functions) can be avoided. Enabling and / or disabling the interrupt signal indicators, e.g., by setting and / or resetting the interrupt signaling bits, requires corresponding consecutive memory regions to be moved to one processor to correspondingly change the respective interrupt signal indicators.

[0041] From the perspective of the guest operating system, it can be expected that a processor processes all indicators it is responsible for, i.e., especially all indicators assigned to the respective processor. This can achieve performance advantages since in the case where each processor is processing all data assigned to it, the likelihood that the data required in this context is provided to the processor and / or stored in the local cache may be high, enabling fast access to the respective data for the processor without a large amount of cache traffic.

[0042] However, each processor attempting to process all indicators it is responsible for may still result in high cache traffic between processors since each processor needs to write all cache lines for all functions. Since the indicators assigned to each individual processor can be distributed across all consecutive regions (e.g., cache lines).

[0043] The interrupt signaling indicators can be reordered in the form of a directed interrupt signaling vector such that all interrupt signaling indicators assigned to the same interrupt target ID are grouped in the same contiguous memory region (e.g., cache line). Thus, a processor expecting to process the indicators assigned to a corresponding processor (i.e., interrupt target ID) may only need to load a single contiguous memory region. Therefore, contiguous regions per interrupt target ID are used instead of contiguous regions per bus-connected module. For all interrupt signals received from all available bus-connected modules targeted at a particular processor that is the target processor identified by the interrupt target ID, each processor may only need to scan and update a single contiguous memory region, e.g., cache line.

[0044] According to an embodiment, an offset may be applied by a hypervisor to a guest operating system to align bits to a different offset.

[0045] According to an embodiment, interrupt signals are received in the form of message signaled interrupts (MSIs), which include the interrupt target ID of the target processor. Using message signaled interrupts (MSIs) is a method by which a bus-connected module (such as a Peripheral Component Interconnect (PCI) or a Peripheral Component Interconnect Express (PCIe) function) generates a Central Processing Unit (CPU) interrupt to notify a guest operating system using the corresponding central processing unit of the occurrence of an event or the existence of a certain state. MSI provides an in-band method of signaling interrupts using special in-band messages, thus avoiding the need for a dedicated path separate from the main data path to send such control information, such as dedicated interrupt pins on each device. MSI relies more on the exchange of special messages indicating interrupts over the main data path. When a bus-connected module is configured to use MSI, the corresponding module requests an interrupt by performing an MSI write operation of a specified number of bytes of data to a special address. The combination of this special address (i.e., MSI address) and a unique data value (i.e., MSI data) is called an MSI vector.

[0046] Modern PCIe standard adapters have the ability to present multiple interrupts. For example, MSI-X allows a bus-connected module to allocate up to 2048 interrupts. Thus, it is possible to direct individual interrupts to different processors, such as in high-speed network applications that rely on multi-processor systems. MSI-X allows the allocation of multiple interrupts, each with a separate MSI address and MSI data value.

[0047] To send an interrupt signal, an MSI-X message can be used. The required content of the MSI-X message can be determined using an MSI-X data table. The MSI-X data table local to the bus attachment module (i.e., PCIe adapter / function) can be indexed by the number assigned to each interrupt signal (also known as interrupt request (IRQ)). The MSI-X data table content is under the control of the guest operating system and can be set into the operating system through hardware and / or firmware boot. A single PCIe adapter can include multiple PCIe functions, and each PCIe function can have an independent MSI-X data table. This can be the case, for example, for single root input / output virtualization (SR-IOV) or multi-function devices.

[0048] The interrupt target ID (e.g., virtual processor ID) can be directly encoded as part of a message (e.g., MSI-X message) sent by the bus attachment module that includes the interrupt signal. The message (e.g., MSI-X message) can include a requester ID (i.e., the ID of the bus attachment module), the above-mentioned interrupt target ID, DIBV or AIBV index, MSI address, and MSI data. The MSI-X message can provide 64 bits for the MSI address and 32 bits for the data. The bus attachment module can use an MSI request interrupt by performing an MSI write operation of a specific MSI data value to a special MSI address.

[0049] The device table is a shared table that can be fully indexed by the requester ID (RID) of the interrupt requester (i.e., the bus attachment module). The bus-attached device remaps and issues an interrupt, i.e., the bus-attached device translates the interrupt target ID and uses it to directly address the target processor.

[0050] The guest operating system can use the virtual processor ID to identify processors in a multi-processor computer system. Thus, the view of the processors by the guest operating system can be different from the view of the underlying system that uses logical processor IDs. The bus attachment module that provides resources used by the guest operating system can use the virtual processor ID as a resource for communicating with the guest operating system. For example, the MSI-X data table can be under the control of the guest operating system. As an alternative to the virtual processor ID, any other ID can be defined for the bus attachment module to address the processor.

[0051] Interrupts are presented to the guest operating system or other software executing thereon, such as other programs, etc. As used herein, the term "operating system" includes operating system device drivers.

[0052] As used herein, the term "bus connection module" may include any type of bus connection module. According to an embodiment, the module may be a hardware module, such as a storage function, a processing module, a network module, an encryption module, a PCI / PCIe adapter, other types of input / output modules, etc. According to other embodiments, the module may be a software module, i.e., a function, such as a storage function, a processing function, a network function, an encryption function, a PCI / PCIe function, other types of input / output functions, etc. Thus, in the examples given herein, unless otherwise stated, the module may be used interchangeably with a function (such as a PCI / PCIe function) and an adapter (such as a PCI / PCIe function).

[0053] Embodiments may have the following benefits: providing an interrupt signal routing mechanism, such as an MSI-X message routing mechanism, which allows it to keep the bus connection modules (such as PCIe adapters and functions) and the device drivers for operating or controlling the bus connection modules unchanged. In addition, the hypervisor can be prevented from intercepting the underlying architecture for implementing the communication between the bus connection module and the guest operating system, such as the PCIe MSI-X architecture. In other words, the change to the interrupt signal routing mechanism can be implemented outside the hypervisor and the bus connection module.

[0054] According to an embodiment, the interrupt signal indicators assigned to the same bus connection module all include the same offset within the directed interrupt signal vector including the corresponding interrupt signal indicator. Embodiments may have the beneficial effect of providing a simplified check of the interrupt signal indicators for a particular bus connection module. According to an embodiment, the directed interrupt signal vectors are all implemented as contiguous regions in memory. Embodiments may have the following beneficial effects: providing an interrupt summary vector in a form that minimizes memory space and can be processed quickly and efficiently. The contiguous region may be, for example, a cache line. According to an embodiment, the directed interrupt signal indicators are all implemented as a single bit. Embodiments may have the following beneficial effects: providing the directed interrupt signal indicators in a form that minimizes memory space and can be processed quickly and efficiently.

[0055] According to an embodiment, the method further includes the bus-attached device retrieving a copy of the interrupt table entry assigned to the received interrupt target ID from the interrupt table stored in memory, the interrupt table entry including a directed interrupt signal vector address indicator indicating the memory address of the directed interrupt signal vector to which the received interrupt signal is addressed, and the bus-attached device using the memory address of the corresponding directed interrupt signal vector to select the directed interrupt signal vector to which the received interrupt signal is addressed for the received interrupt target ID.

[0056] According to an embodiment, the method further includes a bus-attached device retrieving a copy of a device table entry from a device table stored in a memory, the device table entry including an interrupt table address indicator indicating a memory address of an interrupt table, and the bus-attached device using the memory address of the interrupt table to retrieve a first copy of an interrupt table entry.

[0057] According to an embodiment, the device table entry further includes a directed interrupt signal offset indicator indicating an offset of a directed interrupt signal indicator assigned to a bus connection module that issues the received interrupt signal.

[0058] According to an embodiment, the memory further includes a directed interrupt summary vector having a directed interrupt summary indicator for each interrupt target ID, each directed interrupt summary indicator being assigned to an interrupt target ID and indicating whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed, and wherein the method further includes: the bus-attached device selecting a directed interrupt summary indicator assigned to a target processor ID to which the received interrupt signal is addressed; and the bus-attached device updating the selected directed interrupt summary indicator such that the selected directed interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0059] When an interrupt cannot be directly delivered, for example because the hypervisor has not yet scheduled the target processor, the guest operating system can benefit from delivering the interrupt with the originally expected affinity (i.e., information about which processor the interrupt was expected for) using a broadcast. In this case, the bus-attached device can set a bit specifying the target processor in the DISB after setting the DIBV and before delivering the broadcast interrupt request to the guest operating system. If the guest operating system receives the broadcast interrupt request, it can thus identify which target processors have interrupt signals pending to be signaled in the DIBV by scanning and disabling the direct interrupt summary indicators in the DISB (e.g., scanning and resetting the direct interrupt summary bits). Thus, the guest operating system can be enabled to decide whether the interrupt signal is to be processed by the current processor that received the broadcast or further forwarded to the original target processor.

[0060] According to an embodiment, the directed interrupt summary vector is implemented as a contiguous region in the memory. Embodiments can have the beneficial effect of providing the directed interrupt summary vector in a form that minimizes memory space and can be processed quickly and efficiently. The contiguous region can be, for example, a single cache line. According to an embodiment, each of the directed interrupt summary indicators is implemented as a single bit. Embodiments can have the beneficial effect of providing the directed interrupt summary indicators in a form that minimizes memory space and can be processed quickly and efficiently.

[0061] According to an embodiment, the interrupt table entry further includes a directed interrupt summary vector address indicator indicating the memory address of the directed interrupt summary vector, wherein the bus-attached device uses the memory address of the directed interrupt summary vector to select a directed interrupt summary indicator assigned to the target processor ID to which the received interrupt signal is addressed.

[0062] According to an embodiment, the interrupt table entry further includes a directed interrupt summary offset indicator indicating an offset of the directed interrupt summary indicator assigned to the target processor ID within the directed interrupt summary vector.

[0063] According to an embodiment, the method further includes: when forwarding an interrupt signal to a target processor, converting, by the bus-attached device, the interrupt target ID of the target processor received together with the interrupt signal into a logical processor ID of the target processor, and using the logical processor ID of the target processor to address the target processor as the target of the interrupt signal.

[0064] According to an embodiment, the method further includes retrieving, by the bus-attached device, a copy of the interrupt table entry assigned to the interrupt target ID from an interrupt table stored in a memory, wherein the copy of the interrupt table entry further includes a current mapping of the interrupt target ID to a first logical processor ID, and the bus-attached device uses the copy of the interrupt table entry to convert the interrupt target ID of the target processor received together with the interrupt signal.

[0065] Embodiments can have the beneficial effect of providing an interrupt table (IRT) including interrupt table entries (IRTEs), each interrupt table entry providing a mapping of an interrupt target ID to a logical processor ID. Thus, the entries can define a unique assignment of each interrupt target ID to a logical processor ID. According to an embodiment, the interrupt target ID can be provided in the form of a virtual processor ID. According to an embodiment, the interrupt target ID can be any other ID used by a guest operating system to identify a separate processor being used.

[0066] According to an embodiment, the IRT is provided in a memory for use by the bus-attached device to map the interrupt target ID to the logical processor ID. According to an embodiment, the IRT is provided in a single location. An address indicator indicating the memory address of the IRT can be provided, such as a pointer. The address indicator can be provided, for example, by an entry in a device table retrieved by the bus-attached device from the memory. Embodiments can have the beneficial effect of not having to store a large mapping table in the bus-attached device. If needed, the interrupt table for mapping can be stored in the memory and accessed by the bus-attached device. Thus, the bus-attached device can only have to process a working copy of one or more interrupt table entries for each interrupt signal to be forwarded. The number of interrupt table entries can preferably be small, such as one.

[0067] According to an embodiment, the IRT or individual IRTEs may be updated upon rescheduling of a processor. According to an embodiment, the IRT may be stored in an internal section of the memory (i.e., the HSA).

[0068] According to an embodiment, a copy of a device table entry further includes a direct signaling indicator indicating whether a target processor is to be directly addressed, the direct signaling indicator indicating that direct forwarding of an interrupt signal is a requirement to perform forwarding of the interrupt signal by directly addressing the target processor using the logical processor ID of the target processor, otherwise, the forwarding is performed using broadcast.

[0069] Embodiments may have the beneficial effect of controlling whether an interrupt signal is forwarded using direct addressing or broadcast with a direct signaling indicator. Using a direct signaling indicator for each bus connection module can provide a separate predefined selection as to whether direct addressing or broadcast is to be performed for an interrupt signal received from that bus connection module.

[0070] According to an embodiment, a double fetch of an IRTE may be performed to prevent an interrupt signal from being sent to a processor that has been deactivated, for example, during that time. According to an embodiment, after forwarding an interrupt signal to a processor identified by a logical processor ID obtained from a translation of an interrupt target ID using a first copy of the IRTE, a second copy of the same IRTE may be fetched to check whether any change to the IRTE has occurred during that time. In the case where the IRTE has been updated during that time, there is a risk that the interrupt signal has been forwarded to a deactivated processor. Therefore, the second copy of the IRTE may be used to translate the interrupt target ID again and forward the interrupt signal to a processor identified by the logical processor ID resulting from the second translation. According to an alternative embodiment, in the case where the second copy of the IRTE does not match the first copy, the complete method starting from fetching the first copy of the IRTE may be repeated. For example, a third copy of the IRTE may be fetched in place of the first copy of the IRTE, or the second copy of the IRTE may be in place of the first copy of the IRTE and a third copy of the IRTE may be fetched to also repeat the double fetch scheme for parts of the method. The scheme may be repeated until a match is achieved. According to another alternative embodiment, in the case where the second copy of the IRTE does not match the first copy, the interrupt signal may be forwarded using broadcast. According to an embodiment, a bus-attached device participates in a memory-cache coherence protocol and detects replacement of the IRTE through the same mechanism, such as cache snooping. The CPU may detect cache line replacement.

[0071] Embodiments may have the beneficial effect of avoiding cache flushing that may have inefficient scaling. The double fetch may be global or specific to the IRTE, i.e., the entire entry may be subject to the double fetch or limited to specific information included by the corresponding entry.

[0072] According to an embodiment, a race condition can be detected by check logic for checking whether a receiving processor is still the correct target processor with respect to a CPU, the race condition being caused by the time required to convert an interrupt target ID and forward an interrupt signal to the target processor until it reaches the processor. For this check, the interrupt target ID and / or the logical partition ID received together with the interrupt request can be compared with the current interrupt target ID and / or the logical partition ID assigned to the receiving processor as a reference. In the case of a match, the receiving processor directly addressed using the logical processor ID obtained from the conversion using a copy of the IRTE is actually the correct target processor. Thus, the information provided by the copy of the IRTE is already up-to-date. In the case of a mismatch, the copy of the IRTE is not yet up-to-date, and the receiving processor is no longer the target processor. In the case of a mismatch, the interrupt signal can be forwarded to the target operating system using, for example, a broadcast.

[0073] According to an embodiment, three entities can operate in parallel, namely, a bus-attached device, a target processor that processes an interrupt signal, and a hypervisor that can change the assignment between an interrupt target ID and a logical processor ID. According to an embodiment, in a physically distributed system, there may be no central synchronization point that provides a virtual appearance of such a system at the cost of latency, other than the memory. An embodiment using a secondary acquisition scheme can have the beneficial effect of providing a method optimized for speed against secondary delivery or even misses of interrupt requests.

[0074] In view of the interrupt signal, the following actions can be performed: A1) reading a first copy of the IRTE, A2) sending an interrupt request to the directly addressed processor, and A3) reading a second copy of the IRTE. At the same time, the following sequence of changes in the assignment between the interrupt target ID and the logical processor ID can occur: B1) activating an additional processor with an additional logical processor ID and deactivating a previous processor with a previous logical processor ID, and B2) updating the IRTE with the additional logical processor ID, that is, replacing the previous logical processor ID with the additional logical processor ID.

[0075] In certain error situations, a processor (such as the target processor) can be reset to a checkpoint and lose intermediate information. To regain the lost information, the processor can scan all IRTE entries for that particular processor, that is, all IRTE entries for the logical processor ID assigned to it, and deliver direct interrupt requests as indicated by pending direct interrupt indicators (such as, for example, the dPIA bit) present in the memory that are not affected by the processor recovery.

[0076] If an interrupt signal is to be presented, the outstanding direct interrupt indicator (e.g., the IRTE.dPIA bit) included by the IRTE can be used as the master copy, i.e., the single point of truth. To simplify processor recovery, the outstanding direct interrupt indicator in the processor can be used as a shadow copy of, for example, the IRTE.dPIA bit to keep the direct interrupt outstanding on the processor.

[0077] In the case where the memory has the property of strict ordering, given steps A1, A2, and B1, only the following sequences are possible: Alternative 1 is A1 → A3 → B1, and Alternative 2 is A1 → B1 → A3. In the case of Alternative 1, the first and second copies of the IRTE can match. Thus, the interrupt signal can be forwarded to the previous processor instead of the current target processor. The previous processor can see the mismatch regarding the interrupt target ID and / or the logical partition ID and initiate the broadcast of the received interrupt signal. In the case of Alternative 2, the bus-attached device can see the mismatch between the first and second copies of the IRTE. In response to this mismatch, the bus-attached device can broadcast the interrupt signal. Due to the broadcast, the interrupt signal can be received by additional processors that see the hit and directly process the received interrupt request. An embodiment can have the beneficial effect of closing the timing window by an over-initiative-approach.

[0078] According to an embodiment, the copy of the interrupt table entry further includes a copy of a run indicator that indicates whether the target processor identified by the interrupt target ID is scheduled to be used by the guest operating system. The target processor being scheduled to be used by the guest operating system is another requirement for using the logical processor ID of the target processor to directly address the target processor to forward the interrupt signal. Otherwise, the interrupt signal is forwarded to the first operating system for processing using a broadcast.

[0079] An embodiment can have the beneficial effect of preventing an interrupt from targeting a processor that is not running (i.e., not scheduled to be used by the guest operating system). An embodiment can have the beneficial effect of supporting the hypervisor to reschedule the processor.

[0080] The run indicator indicates whether the target processor identified by the interrupt target ID received together with the interrupt signal is scheduled for use by the guest operating system. The run indicator may be implemented, for example, in the form of a run bit, i.e., the run bit is a single bit that indicates whether the processor to which the corresponding bit is assigned is running (i.e., is scheduled for use by the guest operating system). Thus, an enabled run bit can tell the bus-attached device that the target processor is currently scheduled, while a disabled run bit can tell the bus-attached device that the target processor is not currently scheduled. In the case where the target processor is not running, the bus-attached device can send a fallback broadcast interrupt request in the correct manner without attempting to directly address one of the processors.

[0081] According to an embodiment, a copy of the interrupt table entry further includes an interrupt block indicator that indicates whether the target processor identified by the interrupt target ID is currently blocked from receiving the interrupt signal. The target processor not being blocked is another requirement for using the logical processor ID of the target processor to directly address the target processor to perform forwarding of the interrupt signal. Otherwise, the interrupt signal is forwarded to the first operating system using a broadcast for processing.

[0082] According to an embodiment, a direct interrupt block indicator is introduced in the interrupt entry of the interrupt table in the memory. The direct interrupt block indicator may be implemented in the form of a single bit (i.e., the dIBPIA bit).

[0083] According to an embodiment, the IRTE is fetched from the memory and the run indicator is checked to determine whether the target processor is scheduled. In the case where the target processor is scheduled, the direct interrupt block indicator is enabled to prevent the target processor from receiving another interrupt signal while processing the current interrupt signal. Otherwise, another interrupt signal may interfere with the processing of the current interrupt signal. To ensure that the target processor has not been rescheduled during this period, the IRTE is refetched and the current run indicator is checked again to determine whether the target processor is still scheduled. In the case where the target processor is still scheduled, the logical processor ID of the target processor can be used to directly address the target processor to forward the interrupt signal to the target processor. In addition, it can be checked whether the logical processor ID of the target processor provided by the IRTE for the received interrupt target ID is still the same.

[0084] According to an embodiment, the device table entry further includes a logical partition ID that identifies the logical partition to which the guest operating system is assigned, and forwarding the interrupt signal by the bus-attached device further includes forwarding the logical partition ID together with the interrupt signal. The embodiment can have the beneficial effect of enabling the receiving processor to check which target processor the interrupt signal is addressed to.

[0085] According to an embodiment, the method further includes a bus-attached device retrieving an interrupt subclass ID to which the received interrupt signal is assigned, and forwarding the interrupt signal by the bus-attached device further includes forwarding the interrupt subclass ID together with the interrupt signal.

[0086] According to an embodiment, instructions provided on a computer-readable non-transitory medium for execution by a processing circuit are configured to perform any of the embodiments of the method for providing an interrupt signal to a guest operating system as described herein.

[0087] According to an embodiment, the computer system is further configured to perform any of the embodiments of the method for providing an interrupt signal to a guest operating system as described herein.

[0088] Figure 1 An exemplary computer system 100 for providing an interrupt signal to a guest operating system is depicted. The computer system 100 includes a plurality of processors 130 for executing a guest operating system. The computer system 100 further includes a memory 140, also referred to as a storage memory or main memory. The memory 140 may provide a memory space, i.e., a memory segment, which is allocated for use by the hardware, firmware, and software components included in the computer system 100. The memory 140 may be used by the hardware and firmware of the computer system 100 as well as by software (e.g., a hypervisor, host / guest operating systems, applications, etc.). One or more bus connection modules 120 are operably connected to the plurality of processors 130 and the memory 140 via a bus 102 and a bus-attached device 110. The bus-attached device 110 manages the communication between the bus connection module 120 and the processor 130 on one hand, and the communication between the bus connection module 120 and the memory 140 on the other hand. The bus connection module 120 may be connected to the bus 102 directly or via one or more intermediate components (e.g., a switch 104).

[0089] The bus connection module 120 may be provided, for example, in the form of a high-speed peripheral component interconnect (PCIe) module, also referred to as a PCIe adapter or PCIe functions provided by a PCIe adapter. The PCIe functions 120 may issue a request, which is sent to the bus-attached device 110, e.g., a PCI host bridge (PHB), also referred to as a PCI bridge unit (PBU). The bus-attached device 110 receives the request from the bus connection module 120. The request may include, for example, an input / output address for a direct memory access (DMA) to the memory 140 to be performed by the bus-attached device 110 or an input / output address indicating an interrupt signal (e.g., a message signal interrupt (MSI)).

[0090] Figure 2Depicts an exemplary virtual machine support provided by computer system 100. Computer system 100 may include one or more virtual machines 202 and at least one hypervisor 200. The virtual machine support can provide the ability to operate a large number of virtual machines, each of which is capable of executing a guest operating system 204, such as z / Linux. Each virtual machine 201 can function as a separate system. Thus, each virtual machine can be reset independently, execute a guest operating system, and run different programs, such as applications. The operating system or application running in the virtual machine may appear to have access to a complete computer system. However, in reality, only a portion of the available resources of the computer system are available for use by the corresponding operating system or application.

[0091] The virtual machine can use the V=V model, where the memory allocated to the virtual machine is supported by virtual memory rather than real memory. Thus, each virtual machine has a virtual linear memory space. The physical resources are owned by a hypervisor 200, such as a VM hypervisor, and the shared physical resources are dispatched by the hypervisor to the guest operating systems as needed to meet their processing requirements. The V=V virtual machine model assumes that the interaction between the guest operating system and the physical shared machine resources is controlled by the VM hypervisor because a large number of clients may prevent the hypervisor from simply partitioning the hardware resources and allocating the hardware resources to the configured clients.

[0092] The processor 120 can be allocated by the hypervisor 200 to the virtual machine 202. The virtual machine 202 can be allocated, for example, one or more logical processors. Each logical processor can represent all or a share of the physical processor 120 that can be dynamically allocated by the hypervisor 200 to the virtual machine 202. The virtual machine 202 is managed by the hypervisor 200. The hypervisor 200 can be implemented, for example, in the firmware running on the processor 120, or can be a part of the operating system executing on the computer system 100. The hypervisor 200 can be, for example, a VM hypervisor, such as that provided by International Business Machines Corporation of Armonk, New York

[0093] Figure 3 Depicts an exemplary multi-level virtual machine support provided by computer system 100. In addition to Figure 2 the first-level virtualization, a second-level virtualization is provided, where a second hypervisor 210 executes on a first-level guest operating system that serves as the host operating system for the second hypervisor 210 in the first-level guest operating system. The second hypervisor 210 can manage one or more second-level virtual machines 212, each of which is capable of executing a second-level guest operating system 212.

[0094] Figure 4Illustrates an exemplary pattern for using different types of IDs to identify processors at different architectural levels of a computer system 100. The underlying firmware 220 may provide a logical processor ID ICPU 222 to identify the processor 130 of the computer system 100. The first-level hypervisor 200 uses the logical processor ID ICPU 222 to communicate with the processor 130. The first-level hypervisor may provide a first virtual processor ID vCPU 224 for use by the guest operating system 204 or the second-level hypervisor 219 executing on a virtual machine managed by the first-level hypervisor 200. The hypervisor 200 may group the first virtual processor IDs vCPU 224 to provide logical partitions (also known as zones) to the guest operating system 204 and / or the hypervisor 210. The first virtual processor ID vCPU 224 is mapped by the first-level hypervisor 200 to the logical processor ID ICPU 222. One or more of the first virtual processor IDs vCPU 224 provided by the first-level hypervisor 200 may be assigned to each guest operating system 204 or hypervisor 210 executing using the first-level hypervisor 200. The second-level hypervisor 210 executing on the first-level hypervisor 200 may provide one or more virtual machine execution software, such as other guest operating systems 214. To this end, the second-level hypervisor manages a second virtual processor ID vCPU 226 for use by the second-level guest operating system 214 executing on the virtual machine of the first-level hypervisor 200. The second virtual processor ID vCPU 226 is mapped by the second-level hypervisor 200 to the first virtual processor ID vCPU 224.

[0095] The bus connection module 120 that addresses the processor 130 used by the first / second-level guest operating system 204 may use a target processor ID in the form of the first / second virtual processor IDs vCPU 224, 226 or a replacement ID derived from the first / second virtual processor IDs vCPU 224, 226.

[0096] Figure 5Depicts a simplified schematic setup of a computer system 100, which shows the main parties involved in a method for providing an interrupt signal to a guest operating system executing on the computer system 100. For illustrative purposes, the simplified setup includes a bus connection module (BCM) 120, which sends an interrupt signal to a guest operating system executing on one or more processors (CPUs) 130. The interrupt signal is sent to a bus-attached device 110 together with an interrupt target ID (IT_ID) that identifies one of the processors 130 as the target processor. The bus-attached device 110 is an intermediate device that manages the communication between the bus connection module 120, the processors 130, and the memory 140 of the computer system 100. The bus-attached device 110 receives the interrupt signal and uses the interrupt target ID to identify the logical processor ID of the target processor in order to directly address the corresponding target processor. The directed forwarding to the target processor can improve the efficiency of data processing, for example, by reducing cache traffic.

[0097] Figure 6 Depicts the schematic structure of a DISB 160 and multiple DIBVs 162. The DISB 160 can be provided in the form of a contiguous memory section (e.g., a cache line), which includes an entry 161 (e.g., a bit) for each interrupt target ID. Each entry indicates whether there is an interrupt request (IRQ) to be processed by the corresponding processor identified by the interrupt target ID. For each interrupt target ID, i.e., the entry of the DISB 160, a DIBV 162 is provided. Each DIBV 162 is assigned to a specific interrupt target ID and includes one or more entries 163MN A, MN B for each bus connection module. Each of the DIBVs 162 can be provided in the form of a contiguous memory section (e.g., a cache line), which includes the entries 163 assigned to the same interrupt target ID. The entries of different bus connection modules can be sorted using different offsets DIBVO per bus connection module.

[0098] Figure 7 depicts an exemplary DIBV 162. The offset (DIBVO) within the DIBV assigned to an interrupt target ID identifies the start of a segment or an entry of the vector assigned to a specific bus connection module. An interrupt signal (e.g., an MSI-X message) can provide a DIBV-Idx, which is added to the DIBVO to identify a specific entry of the vector assigned to the bus connection module, to identify the bit 163 assigned to the corresponding bus connection module, and if the bit 163 is set, it indicates the existence of an interrupt signal address from the bus connection module identified by the bit 163 to the corresponding interrupt target ID. The directed interrupt number (NOI) defines the maximum number of bits reserved for a corresponding bus connection module in the DIBV.

[0099] Figure 8 DepictsFigure 5 A computer system 100. The bus-attached device 110 is configured to perform a status update of the state of the bus connection module 120 in a module-specific area (MSA) 149 of the memory 140. Such a status update can be performed in response to receiving a direct memory access (DMA) write from the bus connection module specifying the status update to be written to the memory 140.

[0100] The memory also includes a device table (DT) 144, where there is a device table entry (DTE) 146 for each bus connection module 120. After receiving an interrupt signal (e.g., an MSI-X write message) having an interrupt target ID identifying the target processor for the interrupt request and a requester ID identifying the origin of the interrupt request in the form of the bus connection module 120, the bus-attached device 110 fetches the DTE 146 assigned to the requesting bus connection module 120. The DTE 146 can indicate, for example, using the dIRQ bit whether directed addressing of the target processor is enabled for the requesting bus connection module 120. The bus-attached device updates the entries of the directed interrupt signal vector (DIBV) 162 and the directed interrupt summary vector (DISB) 160 to track which processor 130 the interrupt signal has been received for. The DISB 160 can include one entry per interrupt target ID, which indicates whether there is an interrupt signal from any bus connection module 120 to be processed for that processor 130. Each DIBV 162 is assigned to one of the interrupt target IDs (i.e., the processors 130) and can include one or more entries. Each entry is assigned to one of the bus connection modules 120. Thus, the DIBV indicates from which bus connection modules there is an interrupt signal to be processed for a particular processor 130. This can have the advantage that in order to check whether there are any interrupt signals to be processed or from which bus connection module 120 there is an interrupt signal for a particular processor, only the signal entries (e.g., bits) or signal vectors (e.g., bit vectors) need to be read from the memory 140.

[0101] The bus-attached device 110 uses a mapping table 112 provided on the bus connection module 110 to convert the interrupt target ID (IT_ID) to a logical processor ID (ICPU) and uses the logical processor ID to directly address the target processor to forward the received interrupt signal to the target processor. Each processor includes firmware (e.g., millicode 132) for receiving and processing direct interrupt signals. The firmware can also include, for example, the microcode and / or macrocode of the processor 130. It can include hardware-level instructions and / or data structures used in the implementation of higher-level machine code. According to an embodiment, it can include proprietary code that can be passed as microcode, which includes trusted software or microcode specific to the underlying hardware and controls the operating system's access to the system hardware.

[0102] The firmware of the processor 130 includes check logic 134 for checking whether the receiving processor is the same as the target processor according to the interrupt target ID forwarded by the bus-attached device 110 to the receiving processor 130. In the case where the receiving processor 130 is not the target processor, that is, in the case where the received interrupt target ID does not match the reference interrupt target ID of the receiving processor 130, the interrupt signal is broadcast to the logical partitions to find a processor for processing the interrupt signal.

[0103] Figure 9 FIG. is a flowchart of an exemplary method for performing a status update of the bus connection module 120 via the bus-attached device 110 using a DMA write request. In step 300, the bus connection module may decide to update its status and trigger an interrupt, for example, to indicate signal completion. In step 310, the bus connection module initiates a direct memory access (DMA) write to a section of memory (i.e., main memory) assigned to the host running on the computer system via the bus-attached device to update the status of the bus connection module. DMA is a hardware mechanism that allows the peripheral components of a computer system to directly transfer their I / O data to and from the main memory without involving the system processor. To perform DMA, the bus connection module sends a DMA write request to the bus-attached device, for example, in the form of an MSI-X message. In the case of PCIe, the bus connection module may refer to, for example, the PCIe function provided on the PCIe adapter. In step 320, the bus connection module receives the DMA write request with the status update of the bus connection module and updates the memory using the received update. The update may be performed in the area of the host memory reserved for the corresponding bus connection module.

[0104] Figure 10 is for using Figure 8Flowchart of an exemplary method by which a computer system 100 provides an interrupt signal to a guest operating system. At step 330, a bus-attached device receives an interrupt signal, such as in the form of an MSI-X write message, sent by a bus connection module. This transmission of the interrupt signal can be performed in accordance with the specifications of the PCI architecture. The MSI-X write message includes an interrupt target ID that identifies the target processor of the interrupt. The interrupt target ID can be, for example, a virtual processor ID used by the guest operating system to identify a processor in a multi-processor computer system. According to an embodiment, the interrupt target ID can be any other ID agreed upon by the guest operating system and the bus connection module in order to be able to identify the processor. Such another ID can be, for example, the result of a mapping of the virtual processor ID. Additionally, the MSI-X write message can also include an interrupt requester ID (RID) (i.e., the ID of the PCIe function that issued the interrupt request), a vector index that defines the offset of the vector entry within the vector, an MSI address (e.g., a 64-bit address), and MSI data (e.g., 32-bit data). The MSI address and MSI data can indicate that the corresponding write message is actually an interrupt request in the form of an MSI message.

[0105] In step 340, the bus-attached device fetches a copy of an entry of a device table stored in memory. The device table entry (DTE) provides an address indicator for one or more vectors or vector entries to be updated to indicate that an interrupt signal for the target processor has been received. The address indicator of the vector entry can include, for example, the address of the vector in memory and the offset within the vector. Additionally, the DTE can provide a direct signaling indicator that indicates whether the target processor is to be directly addressed by the bus-attached device using the interrupt target ID provided with the interrupt signal. Additionally, the DTE can provide a logical partition ID (also known as a region ID) and an interrupt subclass ID. The corresponding copy of the device table entry can be fetched from a cache or from memory.

[0106] In step 350, the bus-attached device updates the vectors specified in the DTE. In step 360, the bus-attached device checks the direct signaling indicator provided with the interrupt signal. In the case where the direct signaling indicator indicates no direct signaling, the bus-attached device forwards the interrupt signal by broadcasting using the region identifier and the interrupt subclass identifier in order to provide the interrupt signal to the processors used by the guest operating system.

[0107] In the case where the direct signaling indicator indicates no direct signaling, in step 370, the interrupt signal is forwarded to the processor via broadcast. The broadcast message includes the region ID and / or the interrupt subclass ID. When received by the processor, if the interrupt request is enabled for the region, the status bit is atomically set, for example, according to the nested communication protocol. In addition, the firmware (e.g., microcode) on the processor interrupts its activity, such as program execution, and switches to execute the interrupt handler of the guest operating system.

[0108] In the case where the direct signaling indicator indicates direct signaling, in step 380, the bus-attached device converts the interrupt target ID provided with the interrupt signal into the logical processor ID of the processor assigned to be used by the guest operating system. For this conversion, the bus-attached device can use the mapping table included by the bus-attached device. The bus-attached device can include a mapping table or sub-table for each zone (i.e., logical partition).

[0109] In step 390, the bus-attached device uses the logical processor ID to directly address the corresponding processor to forward the interrupt signal to the target processor, that is, to send a direct message. The direct message includes the interrupt target IS. The direct message can also include the region ID and / or the interrupt subclass ID. The receiving processor includes interrupt target ID checking logic. In the case where the interrupt target ID is unique per logical partition only, the checking logic can also consider the logical partition ID.

[0110] In step 392, the checking logic checks whether the received interrupt target ID and / or logical partition ID match the interrupt target ID and / or logical partition currently assigned to the receiving processor and accessible to the checking logic. In the case of a mismatch, in step 394, the receiving firmware initiates a broadcast and uses the logical partition ID and / or interrupt subclass ID to broadcast the received interrupt request to the remaining processors to identify a valid target processor for handling the interrupt. In the case of a match, in step 396, the receiving firmware (e.g., millicode) of the target processor accepts the directly addressed interrupt for presentation to the guest operating system. In response, the firmware can interrupt its activity, such as program execution, and switch to execute the interrupt handler of the guest operating system. The interrupt can be presented to the guest operating system with a direct signaling indication.

[0111] Figure 11 is further shown Figure 8Additional flowchart of the method. In step 400, an interrupt message is sent to the bus-attached device. In step 402, the interrupt message is received. In step 404, it is checked whether the DTE assigned to the interrupt requester (i.e., the bus connection module) is cached in the local cache operably connected to the bus-attached device. In the case where the DTE is not cached, in step 406, the corresponding DTE is fetched from the memory by the bus-attached device. In step 408, the vector address indicator provided by the DTE is used to set vector bits in the memory. In step 410, the direct signaling indicator provided by the DTE is used to check whether the target processor is to be directly addressed by the bus-attached device using the interrupt target ID provided together with the interrupt signal. In the case where the target processor is not to be directly targeted, the method continues in step 412 to broadcast an interrupt request to the processors. In the case where the target processor is to be directly targeted, the method continues in step 414 to convert the interrupt target ID into a logical processor ID, and in step 416 to send a message forwarding the interrupt signal to the target processor. The logical processor ID is used to directly address the target processor. The message includes the interrupt target ID, the logical partition ID, and the interrupt subclass ID. In step 418, the processor receives the message. In step 419, the processor checks whether the interrupt target ID and / or the logical partition ID match the current interrupt target ID and / or the logical partition ID provided as a reference for the check. In the case of a match, in step 420, the processor presents the interrupt request to the guest operating system. In the case of a mismatch, in step 422, the processor broadcasts the interrupt request to other processors. Then, the processor continues its activity until the next interrupt message is received.

[0112] Figure 12 depicts Figure 5Another embodiment of computer system 100. Instead of using the mapping table 112 stored on the bus-attached device 110, the bus-attached device 110 instead retrieves a copy 114 of an entry (IRTE) 152 of an interrupt table (IRT) 150 stored in the memory 140. The copy can be retrieved from the local cache or from the memory 140 using the address (IRT@) of the interrupt table 150 provided by the copy of the DTE 146. The IRTE 152 provides a mapping of interrupt target IDs to logical processor IDs, which the bus-attached device 110 uses to directly address the target processor in the case of directed interrupt forwarding. The IRTE 152 may additionally provide a run indicator 154 and / or a block indicator 146, where the run indicator 154 indicates whether the target processor identified by the interrupt target ID is fully scheduled (i.e., running), and the block indicator 146 indicates whether the target processor is currently blocked from receiving interrupt signals. In the case where the target processor is not scheduled or is temporarily blocked, broadcasting can be initiated to enable timely interrupt handling.

[0113] FIG. 13 is a flowchart of an exemplary method for providing an interrupt signal to a guest operating system using the computer system 100 of FIG. 100. Figure 11 The method in Figure 8 continues with step 342 after step 340. In step 342, the bus-attached device retrieves a copy of the IRTE from the memory using the interrupt target ID received with the interrupt signal and the address indicator indicating the memory of the IRT provided by the DTE. In step 350, the bus-attached device updates the vector specified in the DTE.

[0114] In step 360, the bus-attached device checks the direct signaling indicator provided with the interrupt signal. In the case where the direct signaling indicator indicates no direct signaling, in step 370, the bus-attached device forwards the interrupt signal by broadcasting using the region identifier and the interrupt subclass identifier to provide the interrupt signal to the processors used by the guest operating system. In the case where the direct signaling indicator indicates direct signaling, in step 362, the bus-attached device further checks whether the run indicator included in the copy of the IRTE indicates that the target processor identified by the interrupt target ID is running.

[0115] In the case where the target processor is not running, in step 364, the bus-attached device uses, for example, a logical partition ID and / or an interrupt subclass ID to identify a processor suitable for handling the interrupt and sends a broadcast interrupt as a fallback. In the case where no suitable processor matching the logical partition ID and / or the interrupt subclass ID is found, the hypervisor (i.e., the processor assigned to be used by the hypervisor) rather than the processor assigned to the guest operating system may receive the interrupt request. If one or more processors assigned to the guest operating system are scheduled, the hypervisor may decide to broadcast the interrupt request again. For the entry of the processor assigned to the operating system, the hypervisor may check the direct interrupt pending indicator to be presented to the incoming processor, such as the dPIA bit. According to an embodiment, the hypervisor may, for example, selectively reschedule (i.e., wake up) the target processor.

[0116] In the case where the target processor is running, in step 366, it is checked whether the direct interrupt block indicator (e.g., the dIBPIA bit) is enabled. An enabled direct interrupt block indicator indicates that interrupt delivery is not currently desired by the guest operating system interrupt handler. Thus, in the case where the direct interrupt block indicator is enabled, in step 368, an interrupt signal may be broadcast.

[0117] If the direct interrupt block indicator is disabled to indicate that the target processor is not currently blocked, in step 380, the delivery of the current interrupt signal is continued by translating the received interrupt target ID so as to directly forward the interrupt to the target processor using the logical processor ID provided by the IRTE for the received interrupt target ID.

[0118] In step 380, the bus-attached device translates the interrupt target ID provided together with the interrupt signal into the logical processor ID of the processor assigned to be used by the guest operating system. For this translation, the bus-attached device may use a mapping table included by the bus-attached device. The bus-attached device may include a mapping table or a sub-table for each zone (i.e., logical partition).

[0119] In step 390, the bus-attached device uses the logical processor ID to directly address the corresponding processor to forward the interrupt signal to the target processor, i.e., send a direct message. The direct message includes the interrupt target IS. The direct message may further include a zone ID and / or an interrupt subclass ID. The receiving processor includes interrupt target ID checking logic. In the case where the interrupt target ID is unique per logical partition only, the checking logic may also consider the logical partition ID.

[0120] In step 392, the check logic checks whether the received interrupt target ID and / or logical partition ID match the interrupt target ID and / or logical partition that is currently assigned to the receiving processor and is accessible to the check logic. In the case of a mismatch, in step 394, the receiving firmware initiates a broadcast and uses the logical partition ID and / or interrupt subclass ID to identify a valid target processor for handling the interrupt to broadcast the received interrupt request to the remaining processors. In the case of a match, in step 396, the receiving firmware (e.g., microcode) of the target processor accepts the interrupt that is directly addressed for presentation to the guest operating system. In response, the firmware may interrupt its activity, such as program execution, and switch to execute the interrupt handler of the guest operating system. The interrupt may be presented to the guest operating system with a direct signaling indication.

[0121] Figure 14 is further shown Figure 11 an additional flowchart of the method. If the target processor is to be directly targeted, then Figure 12 the method shown in Figure 9 continues after step 410. The method continues in step 413 by fetching a copy of the IRTE that is assigned to the received interrupt target ID from memory. In step 413a, it is checked whether the run indicator included by the IRTE is enabled. In the case where the run indicator is disabled, in step 413b, the interrupt signal may be forwarded by the bus-attached device using a broadcast. In the case where the run indicator is enabled, the bus-attached device continues in step 413c to check whether the directed block indicator is enabled. In the case where the directed block indicator is not enabled, the bus-attached device continues in step 414 to convert the interrupt target ID into a logical processor ID using the fetched copy of the IRTE. Otherwise, the interrupt signal may be suppressed in step 413d.

[0122] Figure 15Describes a method for performing an exemplary secondary fetch scheme to ensure that the IRTEs used are up-to-date. In step 500, an interrupt signal (e.g., an MSI-X message) is sent from a bus connection module 120 (e.g., a PCIe adapter or a PCIe function on a PCIe adapter) to a bus-attached device 110 (e.g., a PCIe host bridge (PHB)). In step 502, the bus-attached device 110 requests from a memory 140 a first copy of the IRTE assigned to the interrupt target ID provided together with the interrupt signal. In step 504, the memory 140 sends a copy of the IRTE in response to the request. The time point at which the copy of the IRTE is sent marks the last time point at which the IRTE was indeed up-to-date. At this time point, a time window starts, during which the IRTE can be updated and the data provided by the first copy of the IRTE can become obsolete. The time window ends when the interrupt is processed by the target processor 130. From this time point on, any changes to the IRTE no longer affect the processing of the received interrupt signal. In step 506, the bus-attached device 110 sends a request to the IRTE to enable the directed pending interrupt indicator, e.g., set the directed pending interrupt array (dPIA) bit. The enabled directed pending interrupt indicator indicates that a directed interrupt is waiting for the interrupt target ID. In step 508, the setting of the directed pending interrupt indicator is acknowledged by the memory 140. In step 510, the interrupt signal is forwarded in the form of a directed interrupt request using direct addressing to the target processor 130 identified by the logical processor ID obtained by translating the interrupt target ID using the IRTE. As the target processor 130 receives the directed interrupt request, the time window is closed. In step 512, after the time window is closed, the bus-attached device 110 reads a second copy of the IRTE from the IRTE provided in the memory 140. In step 514, after receiving the requested second copy of the IRTE, the bus-attached device 110 checks whether the second copy of the IRTE matches the first copy of the IRTE, i.e., whether the IRTE, particularly the mapping of the interrupt target ID, has changed. In the case of a match, the method ends with the target processor 130 resetting the directed pending interrupt indicator in the IRTE after the interrupt request has been presented to and processed by the guest operating system. In the case of a mismatch, the method may continue with step 502. Alternatively, the method may continue with the bus-attached device 110 broadcasting the received interrupt signal.

[0123] Figure 16Depicts another method for performing a secondary fetch of the IRTE to ensure that the information provided by the IRTE is up-to-date. In step 600, an interrupt signal (e.g., an MSI-X message) is sent from the bus connection module 120 (e.g., a PCIe adapter or a PCIe function on a PCIe adapter) to the bus-attached device 110 (e.g., a PCIe host bridge (PHB)). In step 602, the bus-attached device 110 requests a copy of the IRTE assigned to the interrupt target ID provided together with the interrupt signal from the memory 140. In step 604, the memory 140 sends a first copy of the IRTE in response to the request. The first copy includes a run indicator (e.g., run bit R = 1) indicating that the target processor is scheduled, a directed interrupt block indicator (e.g., directed block bit dIBPIA = 0) indicating that the target processor is not currently blocked from receiving the interrupt signal, and a logical processor ID ICPU. The logical processor ID ICPU is used by the bus-attached device 110 to directly address the target processor 130. Since the run indicator indicates that the target processor 130 is running, in step 606, the bus-attached device 110 enables the directed interrupt pending indicator in the IRTE, e.g., sets dPIA = 1, and blocks the target processor from receiving other interrupts, e.g., sets dIBPIA = 1. To check that the content of the IRTE has not been changed during this time, e.g., the target processor 130 has been deactivated, in step 608, the critical time window is closed by requesting a re-read of the IRTE. In step 610, the memory 140 sends a second current copy of the IRTE in response to the request. The second copy includes a run indicator (e.g., run bit R = 1) indicating that the target processor 130 is still scheduled, a directed interrupt block indicator enabled by the bus-attached device, and the same logical processor ID ICPU as the ICPU provided by the first copy of the IRTE. Since the run indicator and the ICPU have not changed, the method continues in step 612 to use the ICPU to send an interrupt request directly addressed to the target processor 130. The target processor 130 presents the interrupt to the guest operating system and processes the interrupt. When the processing of the interrupt ends, the target processor 130 disables the directed interrupt pending indicator (e.g., resets dPIA = 0) and the directed interrupt block indicator (e.g., resets dIBPIA = 0).

[0124] Figure 17 Depicts Figure 14Alternative flowchart of the method, which shows the situation where the information included in the IRTE changes during this period. In step 600, an interrupt signal (e.g., an MSI-X message) is sent from the bus connection module 120 (e.g., a PCIe adapter or a PCIe function on a PCIe adapter) to the bus-attached device 110 (e.g., a PCIe primary bridge (PHB)). In step 602, the bus-attached device 110 requests a copy of the IRTE assigned to the interrupt target ID provided together with the interrupt signal from the memory 140. In step 604, the memory 140 sends a first copy of the IRTE in response to this request. The first copy includes a run indicator (e.g., run bit R = 1) indicating that the target processor 130 is scheduled and the logical processor ID ICPU. The logical processor ID ICPU is used by the bus-attached device 110 to directly address the target processor 130. Since the run indicator indicates that the target processor 130 is running, in step 606, the bus-attached device 110 enables the directed interrupt pending indicator in the IRTE, e.g., sets dPIA = 1, and blocks the target processor from receiving other interrupts, e.g., sets dIBPIA = 1. To check that the content of the IRTE has not changed during this period, e.g., the target processor 130 has been deactivated, the critical time window is closed by requesting a re-read of the IRTE in step 608. In step 610, the memory 140 sends a second current copy of the IRTE in response to this request. In this example, the target processor 130 has been deactivated for the guest operating system during this period. Therefore, the second copy includes a run indicator indicating that the target processor 130 is no longer scheduled, e.g., run bit R = 0. The logical processor ID ICPU may or may not be the same as the ICPU provided by the first copy of the IRTE. The directed interrupt block indicator remains enabled by the bus-attached device. Since the run indicator and / or the ICPU have changed, the method continues to use broadcasting to send an interrupt request to the processors in step 612.

[0125] Figure 18 Depicts an exemplary DTE 146, which includes the memory address IRT@ of the IRT, the logical partition ID (region), and the offset (DIBVO) within the DIBV assigned to the interrupt target ID. The DIBVO identifies the start of a segment or entry of the vector assigned to a particular bus connection module. The interrupt signal (e.g., an MSI-X message) may provide a DIBV-Idx, which is added to the DIBVO to identify a particular entry of the vector assigned to the bus connection module. In addition, a directed interrupt number (NOI) is provided, which defines the maximum number of bits reserved in the DIBV for the corresponding bus connection module. Further details of the DIBV are shown in Figure 19A shown. In the case of the AIBV, the DTE may provide the corresponding AIBV-specific parameters as shown in Figure 19B shown.

[0126] In addition, an exemplary IRTE 152 is depicted. The IRTE 152 may include a logical partition ID (region), an interrupt subclass ID (DISC), the memory address DISB@ of DISB, the offset DISBO within DISB, and the memory address DIBV of DIBV that is the interrupt target ID assigned to the target processor.

[0127] Figure 19A and 19B An exemplary method for providing an interrupt signal to a guest operating system is shown. In step 704, a bus connection module (BCM) (e.g., a virtual function on a PCI adapter, i.e., a PCI adapter (VF)) sends an interrupt signal. The interrupt signal may be sent, for example, in the form of an MSI-X message MSI-X(VF, vCPU, DIBV-Idx), which includes an identifier of the virtual function VF, an interrupt target ID in the form of a virtual processor ID vCPU, for example, and an offset (e.g., DIBV-Idx) within the directed interrupt signal vector that identifies an entry (e.g., a bit) included by the vector. In step 706, a bus attached device (BAD) (e.g., a PCI host bridge (PHB), also referred to as a PCI bridge unit (PBU)) receives the interrupt signal.

[0128] In step 708, the PBU reads an entry of the device table (DT) assigned to the VF. The entry of the DT stored in the hardware system area (HSA) of the memory is illustrated as a row of the table. The entry of the DT may include the address of the interrupt table (IRT@) and a directed signaling bit (S) indicating whether directed signaling is to be performed. The PBU uses IRT@ to fetch an entry of the IRT assigned to the vCPU from the HSA, which includes a running bit (R) indicating whether the vCPU is running, a directed interrupt block bit (dIBPIA) indicating whether the vCPU is blocked from receiving an interrupt, and a directed interrupt pending bit (dPIA) indicating whether an interrupt directed to the vCPU is pending. In step 700, at an earlier time point, a start interpret execution instruction (SIE-Entry) that initiates a state change of the target processor from the hypervisor mode to the guest mode has been issued. In step 701, R is set to 1 in the IRTE assigned to the target processor, and the logical processor ID (TrgtPU#) of the target processor is provided. Then, the method ends at 702. For firmware and hardware, TrgtPU# refers to the physical ID of the processing unit (1 physical PU), while for zOS and logical partitions (LPARs), TrgtPU# refers to the logical ID of the processing unit (logical PU).

[0129] In step 710, the PBU uses the DIBV-Idx from MSI-X to set the bits in the DIBV that are assigned to the vCPU to indicate the presence of an interrupt signal targeted at the vCPU from the VF. In step 712, the PBU checks whether the IRTE is blocked, i.e., IRTE.dIBIA == 1. In the case of the IRTE assigned to the vCPU being blocked from receiving other interrupts by the vCPU, the method ends in step 714. In the case of the IRTE not being blocked, the method continues to step 716, where the PBU checks whether the vCPU is running, i.e., whether R is set in the IRTE.

[0130] If R is set, the method continues to step 718 to perform directed addressing. In step 718, dlBPIA and dPIA are set to 1 in the IRTE, indicating that the vCPU is currently blocked from receiving interrupt signals and that the interrupt addressed to the vCPU is pending. In step 720, it is checked whether the IRTE (more precisely, the status of R and / or TrgtPU# in the IRTE) has changed compared to the IRTE in step 78. Thus, a secondary acquisition scheme of reading the IRTE twice is implemented to ensure that no relevant changes have occurred, for example, due to the SIE entry of another guest as shown in step 722, between the readings.

[0131] In step 722, the SIE entry instruction for another guest is executed on the target processor. In step 724, the other guest reads the IRTE of the previous guest and issues an atomic reset command for R in step 726, i.e., sets R = 0 and indicates that the vCPU is no longer running. Additionally, dPIA is read from the IRTE. In step 728, it is checked whether dPIA is set (IRTE.dPIA == 1), indicating that the interrupt for the vCPU is still pending. If no interrupt is pending, the method ends in step 730. If the interrupt is still pending, then in step 732, the pending interrupt indicator PU.dPIA is reset on the target PU and IRTE.dPIA of the IRTE is reset, and a broadcast for the pending interrupt is initiated. Thus, if a relevant change in the IRTE is determined in step 720, the interrupt is broadcast.

[0132] If no relevant change to the IRTE is determined in step 720, the method proceeds to step 734. In step 734, the interrupt signal (directed PCI interrupt SYSOP) is forwarded to the target PU, which is also referred to as the directed PU. In step 736, the directed PU receives the directed PCI interrupt and, in step 738, sets the pending interrupt indicator PU.dPIA on the directed PU. In step 739, it is checked whether the directed PU is masked, i.e., generally prevented from receiving and executing interrupts. If the directed PU is masked, the method ends with step 740. If the directed PU is not masked, for example due to unmasking as shown in step 742, the method continues with the execution of the interrupt by the firmware (e.g., microcode) (mCode IO-Irpt) of the directed PU in step 744. In step 746, PU.dPIA and IRTE.dPIA are reset to indicate that the interrupt is no longer pending.

[0133] In step 748, the operating system interrupt handler (OS IO-Irpt) is called and, in step 750, the DIBV bit set in step 710 is read and reset. In step 752, a loop is made over all DIBV bits of the DIBV assigned to the target PU (i.e., the directed PU). Thus, all interrupts of the target PU can be processed successively. In the case where all DIBV bits have been processed, in step 754, the target PU is unblocked (SIC.OC17) by resetting IRTE.dIBPIA. Additionally, the DIBV is reread in order to determine in step 756 whether another DIBV bit has been set in the meantime. If this is the case, the corresponding interrupt is processed, otherwise the method ends with step 758.

[0134] If the result of the check in step 716 is that R is not set, the method proceeds to step 760 to perform a broadcast as a fallback. In step 760, the directed interrupt summary indicator is enabled in the directed interrupt summary vector, for example by setting a bit. Each bit of the interrupt summary vector is assigned to a CPU, indicating whether there are any interrupts to be processed by the corresponding CPU. In step 764, the interrupt is broadcast (SIGI.enq.IBPIA), and in step 766 it is received by any PU. In step 768, the block bit is set in the IBPIA for the corresponding PU, indicating that the PU is currently blocked from receiving interrupts. In step 770, it is checked whether the IBPIA has been changed by setting the block bit, i.e., whether the IBPIA is 0→1. If the IBPIA has not been changed, i.e., it has been blocked, the method ends in step 772. If the IBPIA has been changed, then in step 774, the pending bit is set in the PIA for the corresponding PU. In step 776, it is checked whether the PU is masked, i.e., generally blocked from receiving and executing interrupts. If the PU is masked, the method ends in step 778. If the PU is not masked, for example due to unmasking as shown in step 780, the method proceeds to step 782 where the interrupt is executed by the firmware of the PU (e.g., microcode) (mCode IO-Irpt). In step 784, the pending bit in the PIA is reset to indicate that the interrupt is no longer pending.

[0135] In step 786, the operating system interrupt handler (OS IO-Irpt) is called, and in step 788 the DISB bit set in step 760 is read and reset. In steps 790 and 792, the corresponding directed PU is signaled that the interrupt has been processed. In step 794, a loop is made over all the DISB bits in the DISB array, each bit being assigned to another PU. DISB summarizes all the interrupts to be processed by broadcast. The interrupts are sorted according to the PU they are directed to. Thus, all the interrupts to be processed by broadcast can be processed successively by the PUs. In the case where all the DISB bits have been processed, in step 796 the PU is unblocked (SIC.OC1) by resetting the IBPIA. In addition, DISB is reread in order to determine in step 798 whether another DISB bit has been set in the meantime. If this is the case, the corresponding interrupt is processed, otherwise the method ends in step 799.

[0136] The guest operating system can be implemented, for example, using a paged storage mode guest. For example in, the paged guest can be interpretively executed at interpretive level 2 via the start interpret execution (SIE) instruction. For example, the logical partition (LPAR) hypervisor executes the SIE instruction to start a logical partition in physical fixed memory. The operating system in this logical partition (e.g., ) It can issue SIE instructions to execute its guest (virtual) machines in its virtual storage devices. Thus, the LPAR hypervisor can use level 1 SIE, while the hypervisor can use level 2 SIE.

[0137] According to an embodiment, the computer system is a server provided by International Business Machines Corporation. server. is based on that provided by International Business Machines Corporation Regarding the details of which are described in the publication titled “z / Architecture Principles of Operation” ( publication number SA22 - 7832 - 11, August 25, 2017), which is hereby incorporated by reference in its entirety into this text. and are registered trademarks of International Business Machines Corporation in Armonk, New York. Other names used herein may be registered trademarks, trademarks, or product names of International Business Machines Corporation or other companies.

[0138] According to an embodiment, computer systems of other architectures can implement and use one or more aspects of the present invention. As an example, servers other than servers (such as Power Systems servers provided by International Business Machines Corporation or other servers) or servers of other companies implement, use, and / or benefit from one or more aspects of the present invention. Further, although in the examples herein, the bus connection module and the bus - attached device are considered part of the server, in other embodiments, they are not necessarily considered part of the server and can be considered only as being coupled to the system memory and / or other components of the computer system. The computer system does not need to be a server. Further, although the bus connection module can be PCIe, one or more aspects of the present invention can use other bus connection modules. PCIe adapters and PCIe functions are just examples. Further, one or more aspects of the present invention can be applicable to interrupt schemes other than PCI MSI and PCI MSI - X. Further, although examples in which bits are set are described, in other embodiments, bytes or other types of indicators can be set. Additionally, the DTE and other structures can include more, fewer, or different information.

[0139] Further, other types of computer systems may benefit from one or more aspects of the present invention. By way of example, a data processing system suitable for storing and / or executing program code is available, which includes at least two processors directly or indirectly coupled to memory elements via a system bus. The memory elements include, for example, local memory employed during actual execution of the program code, mass storage devices, and cache memory that provides temporary storage of at least some program code to reduce the number of times code must be retrieved from the mass storage device during execution.

[0140] Input / output or I / O devices include, but are not limited to, keyboards, displays, pointing devices, DASD, tapes, CDs, DVDs, thumb drives, and other storage media, etc., which may be coupled to the system directly or via an intermediate I / O controller. A network adapter may also be coupled to the system to enable the data processing system to be coupled to other data processing systems or remote printers or storage devices via an intermediate private or public network. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.

[0141] Reference Figure 20, depicts representative components of a host computer system 800 for implementing one or more aspects of the present invention. The representative host computer 800 includes one or more processors (e.g., CPU 801) in communication with computer memory 802 and an I / O interface to a storage media device 811 and a network 810 for communicating with other computers or a SAN, etc. The CPU 801 complies with an architecture having an architectural instruction set and architectural functions. The CPU 801 may have a dynamic address translation (DAT) 803 for converting a program address, a virtual address into a real address of the memory. The DAT may include a translation lookaside buffer (TLB) 807 for caching the translation, so that later access to a block of the computer memory 802 does not require the latency of address translation. A cache 809 may be used between the computer memory 802 and the CPU 801. The cache 809 may be hierarchical, providing a large high-level cache available to more than one CPU and smaller, faster, lower-level caches between the high-level cache and each CPU. In some implementations, the lower-level cache may be split to provide separate low-level caches for instruction fetch and data access. According to an embodiment, instructions may be fetched from the memory 802 via the cache 809 by an instruction fetch unit 804. The instructions may be decoded in an instruction decode unit 806 and, in some embodiments, dispatched to one or more instruction execution units 808 together with other instructions. A number of execution units 808 may be employed, such as arithmetic execution units, floating-point execution units, and branch instruction execution units. The instructions are executed by the execution units, accessing operands from registers or memory specified by the instructions as needed. If an operand is to be accessed from the memory 802, e.g., loaded or stored, the load / store unit 805 may handle the access under the control of the instruction being executed. The instructions may be executed in hardware circuitry or in internal microcode (i.e., firmware), or by a combination of both.

[0142] A computer system may include information in local or main memory, as well as addressing, protection, and reference and change records. Some aspects of addressing include address formats, the concept of address space, various types of addresses, and the way one type of address is converted to another type of address. Some main memories include permanently allocated storage locations. Main memory provides direct addressable fast access storage of data to the system. Data and programs will be loaded into main memory, e.g., from an input device, before they can be processed.

[0143] Main memory may include one or more smaller and faster accessed buffer memories, sometimes referred to as caches. The cache may be physically associated with the CPU or an I / O processor. The effects of the physical construction (other than on performance) and the use of different storage media are generally not observable by the executing program.

[0144] Separate caches can be maintained for instruction and data operands. Information within a cache can be maintained in consecutive bytes on integer boundaries, known as cache blocks or cache lines. The model can provide an EXTRACT CACHE ATTRIBUTE instruction that returns the size of a cache line in bytes. The model can also provide PREFETCH DATA and PREFETCH DATA RELATIVE LONG instructions that implement prefetching of stores into the data or instruction cache or freeing data from the cache.

[0145] Memory can be viewed as a long horizontal string of bits. For most operations, access to memory can be made in a left-to-right order. The bit string is subdivided into eight-bit units. An eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte location in a memory device can be identified by a unique non-negative integer, which is the address of that byte location, also called the byte address. Adjacent byte locations can have consecutive addresses, starting from 0 on the left and proceeding in a left-to-right order. Addresses are unsigned binary integers and can be, for example, 24, 31, or 64 bits.

[0146] Information is transferred between memory and the CPU one byte or a group of bytes at a time. Unless otherwise specified, for example, in , a group of bytes in memory is addressed by the leftmost byte of the group. The number of bytes in a group is implied or explicitly specified by the operation to be performed. When used in CPU operations, a group of bytes is called a field. Within each group of bytes, for example, in , the bits are numbered in a left-to-right order. In In it, the leftmost bit is sometimes called the "high-order" bit, and the rightmost bit is called the "low-order" bit. However, the number of bits is not the storage address. Only bytes are addressable. To operate on the individual bits of a byte in storage, the entire byte can be accessed. In, for example, z / Architecture, the bits in a byte can be numbered from 0 to 7 from left to right. The bits in an address can be numbered 8 - 31 or 40 - 63 for a 24-bit address, or 1 - 31 or 33 - 63 for a 31-bit address; for a 64-bit address, they are numbered 0 - 63. In any other fixed-length format of multiple bytes, the bits making up the format can be numbered consecutively starting from 0. For error detection and preferably for correction, one or more check bits can be sent along with each byte or group of bytes. Such check bits are automatically generated by the machine and cannot be directly controlled by a program. Storage capacity is expressed in terms of the number of bytes. When the length of a storage operand field is implied by the opcode of an instruction, the field is said to have a fixed length, which can be one, two, four, eight, or sixteen bytes. For some instructions, a larger field can be implied. When the length of a storage operand field is not implied but is explicitly specified, the field is said to have a variable length. A variable-length operand can vary in length by an increment of one byte or in multiples of two bytes or other multiples with certain instructions. When information is placed in a storage device, only the contents of the byte positions included in the specified field are replaced, even if the width of the physical path to the storage device may be greater than the length of the field being stored.

[0147] Certain information units will be stored on integer boundaries. When the storage address of an information unit is a multiple of the byte length of that unit, the boundary is called an integer for that information unit. Special names are given to fields of 2, 4, 8, and 16 bytes on integer boundaries. A halfword is a group of two consecutive bytes on a two-byte boundary and is a basic building block of an instruction. A word is a group of four consecutive bytes on a four-byte boundary. A doubleword is a group of eight consecutive bytes on an eight-byte boundary. A quadword is a group of sixteen consecutive bytes on a 16-byte boundary. When the storage address specifies a halfword, word, doubleword, and quadword, the binary representation of the address contains one, two, three, or four rightmost zero bits respectively. Instructions are to be on a two-byte integer boundary. Most instructions' storage operands have no boundary alignment requirement.

[0148] On a device that implements separate caches for instructions and data operands, if a program stores into a cache line from which an instruction is subsequently fetched, significant latency may be experienced, regardless of whether the store changes the instruction that is subsequently fetched.

[0149] In one embodiment, the present invention can be implemented by software, which is sometimes called licensed in-code, firmware, microcode, nano-code, pico-code, etc., any of which conforms to the present invention. Refer toFigure 20 The software program code embodying the present invention can be accessed from a long-term storage medium device 811 such as a CD-ROM drive, a tape drive, or a hard disk drive. The software program code can be embodied on any of a variety of known media used with a data processing system, such as a disk, a hard disk drive, or a CD-ROM. The code can be distributed on such media or can be distributed from a computer memory 802 to a user or from the storage device of one computer system to other computer systems via a network 810 for use by users of such other systems.

[0150] The software program code can include an operating system that controls the functions and interactions of various computer components and one or more application programs. The program code can be paged from the storage medium device 811 to a relatively high-speed computer storage device 802 in which it is available for processing by a processor 801. Known techniques and methods can be used for embodying software program code in memory, on a physical medium, and / or for distributing software code via a network. The program code can be referred to as a "computer program product" when it is created and stored on a tangible medium, which includes but is not limited to an electronic memory module (RAM), a flash memory, an optical disc (CD), a DVD, or a magnetic tape. The computer program product medium can be read by a processing circuit, preferably in a computer system, for execution by the processing circuit.

[0151] Figure 21 A representative workstation or server hardware system is shown in which embodiments of the present invention can be implemented. Figure 21 The system 820 includes a representative underlying computer system 821, such as a personal computer, a workstation, or a server, which includes optional peripheral devices. The underlying computer system 821 includes one or more processors 826 and a bus that is used to connect the (one or more) processors 826 to other components of the system 821 and to enable communication therebetween according to known techniques. The bus connects the processor 826 to a memory 825 and a long-term storage device 827, and the long-term storage device 827 can include, for example, a hard disk drive (e.g., including any one of magnetic media, CD, DVD, and flash memory) or a tape drive. The system 821 can also include a user interface adapter that connects the microprocessor 826 via the bus to one or more interface devices, such as a keyboard 824, a mouse 823, a printer / scanner 830, and / or other interface devices (which can be any user interface device, such as a touch-sensitive screen, a digitizing tablet, etc.). The bus also connects a display device 822, such as an LCD screen or a monitor, to the microprocessor 826 via a display adapter.

[0152] System 821 can communicate with other computers or computer networks through a network adapter capable of communicating 828 with network 829. Example network adapters are communication channels, token rings, Ethernet, or modems. Alternatively, system 821 can communicate using a wireless interface (such as a Cellular Digital Packet Data (CDPD) card). System 821 can be associated with these other computers in a local area network (LAN) or wide area network (WAN), or system 821 can be a client in a client / server arrangement with another computer, etc.

[0153] Figure 22 Data processing network 840 is shown in which embodiments of the present invention can be implemented. Data processing network 840 can include multiple separate networks, such as wireless networks and wired networks, and each network can include multiple separate workstations 841, 842, 843, 844. Additionally, as will be understood by those skilled in the art, one or more LANs can be included, where a LAN can include multiple intelligent workstations coupled to a host processor.

[0154] Still referring to Figure 22 , the network can also include mainframe computers or servers, such as gateway computers (e.g., client server 846) or application servers (e.g., remote server 848), which can access data repositories and can also be accessed directly from workstation 845. Gateway computer 846 can serve as an entry point into each separate network. A gateway may be required when connecting one network protocol to another. Preferably, gateway 846 can be coupled to another network, such as the Internet 847, through a communication link. Gateway 846 can also be directly coupled to one or more of workstations 841, 842, 843, 844 using a communication link. The gateway computer can be implemented using an IBM eServer TM server provided by International Business Machines Corporation.

[0155] Also referring to Figure 21 and Figure 22 , the software programming code embodying the present invention can be accessed by the processor 826 of system 820 from a long-term storage medium 827 such as a CD-ROM drive or a hard disk drive. The software programming code can be included on any of a variety of known media used with a data processing system, such as a disk, a hard disk drive, or a CD-ROM. The code can be distributed on such media, or can be distributed from the memory or storage device of one computer system to users 850, 851 over a network to other computer systems for use by users of such other systems.

[0156] Alternatively, programming code can be included in the memory 825 and accessed by the processor 826 using the processor bus. Such programming code can include an operating system that controls the functions and interactions of various computer components and one or more application programs 832. The program code can be paged from the storage medium 827 into the high-speed memory 825, where it is available for processing by the processor 826. Well-known techniques and methods can be used for including software programming code in the memory, on a physical medium, and / or distributing software code via a network.

[0157] The cache that is most readily available to the processor (i.e., the cache that is faster and smaller than other caches of the processor) is the lowest-level cache, also known as L1 or first-level cache, while the main memory is the highest-level cache, also known as Ln (e.g., L3) if there are n (e.g., n = 3) levels. The lowest-level cache can be divided into an instruction cache and a data cache, where the instruction cache is also known as the I cache, which holds machine-readable instructions to be executed, and the data cache is also known as the D cache, which holds data operands.

[0158] See Figure 23 , which depicts an exemplary processor embodiment of the processor 826. One or more levels of cache 853 can be employed to buffer memory blocks in order to improve processor performance. The cache 853 is a buffer of cache lines that hold memory data that may be used. A cache line can be, for example, 64, 128, or 256 bytes of memory data. Separate caches can be employed to cache instructions and cache data. Cache coherence (i.e., synchronization of copies of lines in the memory and the cache) can be provided by various suitable algorithms, such as the "snoop" algorithm. The main memory device 825 of the processor system can be referred to as a cache. In a processor system having four levels of cache 853, the main storage device 825 is sometimes referred to as a fifth-level (L5) cache because it can be faster and holds only a portion of the non-volatile storage available to the computer system. The main storage device 825 "caches" data pages that are paged into and out of the main storage device 825 by the operating system.

[0159] The program counter (instruction counter) 861 keeps track of the address of the current instruction to be executed. The program counter in the processor is 64 bits and can be truncated to 31 or 24 bits to support previous addressing limitations. The program counter can be embodied in the computer's program status word (PSW) so that it persists during a context switch. Thus, an ongoing program with a program counter value can be interrupted, for example, by the operating system, resulting in a context switch from the program environment to the operating system environment. When the program is inactive, the PSW of the program maintains the program counter value, and when the operating system is executing, the program counter in the operating system's PSW is used. The program counter can be incremented by an amount equal to the number of bytes of the current instruction. Reduced Instruction Set Computing (RISC) instructions can be of fixed length, while Complex Instruction Set Computing (CISC) instructions can be of variable length. IBM 's instructions are CISC instructions that are 2, 4, or 6 bytes in length. The program counter 861 can be modified, for example, by a context switch operation or a branch taken operation of a branch instruction. In a context switch operation, the current program counter value along with other state information about the program being executed (such as condition codes) is saved in the program status word, and a new program counter value is loaded, pointing to the instruction of the new program module to be executed. A branch taken operation can be executed to allow the program to make decisions or loop within the program by loading the result of the branch instruction into the program counter 861.

[0160] An instruction fetch unit 855 can be employed to fetch instructions on behalf of the processor 826. The fetch unit fetches the "next sequential instruction", the target instruction of a branch taken instruction, or the first instruction of a program after a context switch. Modern instruction fetch units can employ prefetch techniques to speculatively prefetch instructions based on the likelihood of the prefetch instructions being used. For example, the fetch unit can fetch 16 bytes of instructions, which includes the next sequential instruction and additional bytes of other sequential instructions.

[0161] Then, the fetched instruction(s) can be executed by the processor 826. According to an embodiment, the fetched instruction(s) can be passed to the dispatch unit 856 of the fetch unit. The dispatch unit decodes the instruction(s) and forwards information about the decoded instruction(s) to the appropriate units 857, 858, 860. The execution unit 857 can receive information about the decoded arithmetic instruction from the instruction fetch unit 855 and can perform arithmetic operations on the operands according to the opcode of the instruction. The operands can preferably be provided to the execution unit 857 from the memory 825, the architectural registers 859, or the immediate field of the instruction being executed. The result of the execution can be stored in the memory 825, the register 859, or other machine hardware (such as control registers, PSW registers, etc.) when it is stored.

[0162] Processor 826 may include one or more units 857, 858, 860 for performing instruction functions. Refer to Figure 24A , execution unit 857 may communicate with architectural general registers 859, decode / dispatch unit 856, load / store unit 860, and other processor units 865 through interface logic 871. Execution unit 857 may employ a number of register circuits 867, 868, 869 to hold information for operation by arithmetic logic unit (ALU) 866. The ALU performs arithmetic operations (such as addition, subtraction, multiplication, and division) and logical functions (such as AND, OR, exclusive OR (XOR), circular shift). Preferably, the ALU may support design-related dedicated operations. Other circuits may provide other architectural facilities 872, such as including condition code and recovery support logic. The result of the ALU operation may be held in output register circuit 870 configured to forward the result to various other processing functions. There are many arrangements of processor units, and this description is only intended to provide a representative understanding of one embodiment.

[0163] The ADD instruction, for example, may be executed in execution unit 857 having arithmetic and logical functions, while floating-point instructions, for example, would be executed in a floating-point execution having dedicated floating-point capabilities. Preferably, the execution unit operates on the operands identified by the instruction by performing the function defined by the opcode on the operands. For example, the ADD instruction may be executed by execution unit 857 on the operands found in two registers 859 identified by the register fields of the instruction.

[0164] Execution unit 857 performs arithmetic addition on two operands and stores the result in a third operand, where the third operand may be a third register or one of the two source registers. The execution unit preferably utilizes arithmetic logic unit (ALU) 866, which is capable of performing various logical functions (such as shift, rotate, AND, OR, and XOR) and various algebraic functions (including any of addition, subtraction, multiplication, division). Some ALUs 866 are designed for scalar operations and some for floating-point operations. Data may be in big-endian mode (where the least significant byte is at the highest byte address) or little-endian mode (where the least significant byte is at the lowest byte address), depending on the architecture. IBM is big-endian. The signed field may be sign and magnitude, one's complement, or two's complement, depending on the architecture. Two's complement may be advantageous because the ALU does not need to be designed with subtraction capabilities since negative or positive values in two's complement only require addition within the ALU. Numbers may be described in shorthand, for example, a 12-bit field defines the address of a 4,096-byte block and is described as a 4K byte (kilobyte) block.

[0165] Refer to Figure 24BBranch instruction information for executing branch instructions can be sent to the branch unit 858, which typically employs a branch prediction algorithm (such as the branch history table 882) to predict the outcome of a branch before other conditional operations are completed. The target of the current branch instruction will be fetched and speculatively executed before the conditional operation is completed. When the conditional operation is completed, based on the condition of the conditional operation and the speculative result, the speculatively executed branch instruction is either completed or discarded. The branch instruction can test the condition code, and if the condition code meets the branch requirement of the branch instruction, it branches to the target address, which can be calculated based on several numbers including, for example, numbers found in a register field or an immediate field of the instruction. The branch unit 858 can employ an ALU 874 having multiple input register circuits 875, 876, 877 and an output register circuit 880. The branch unit 858 can communicate with, for example, the general-purpose register 859, the decode dispatch unit 856, or other circuits 873.

[0166] The execution of a set of instructions can be interrupted for various reasons, such as a context switch initiated by the operating system, a program exception or error that causes a context switch, an I / O interrupt signal that causes a context switch, or multi-threaded activity of multiple programs in a multi-threaded environment. Preferably, the context switch action saves the state information about the currently executing program and then loads the state information about another program being called. The state information can be saved in, for example, hardware registers or memory. The state information preferably includes the program counter value pointing to the next instruction to be executed, the condition code, the memory translation information, and the architecture register content. The context switch activity can be implemented by hardware circuits, application programs, operating system programs, or firmware code (such as microcode, pico-code, or license internal code (LIC)) individually or in combination.

[0167] The processor accesses operands according to an instruction definition method. The instruction can use a value of a part of the instruction to provide an immediate operand, and can provide one or more register fields that explicitly point to a general-purpose register or a special-purpose register (such as a floating-point register). The instruction can utilize an implied register identified by an opcode field as an operand. The instruction can use a memory location for an operand. The memory location of the operand can be provided by a register, an immediate field, or a combination of a register and an immediate field, as illustrated by a long displacement tool, where the instruction defines a base register, an index register, and an immediate field, i.e., a displacement field, which are added together to provide, for example, the address of the operand in memory. Unless otherwise indicated, a location herein can mean a location in the main memory.

[0168] Reference Figure 24C, the processor uses the load / store unit 860 to access memory. The load / store unit 860 can perform a load operation by obtaining the address of the target operand in the memory 853 and loading the operand into the register 859 or another memory 853 location, or can perform a store operation by obtaining the address of the target operand in the memory 853 and storing the data obtained from the register 859 or another memory 853 location at the target operand location in the memory 853. The load / store unit 860 can be speculative and can access memory in a sequence that is out of order with respect to the instruction sequence. However, the load / store unit 860 gives the appearance that the program instructions are being executed in order. The load / store unit 860 can communicate with the general-purpose register 859, the decode / dispatch unit 856, the cache / memory interface 853, or other elements 883, and includes various register circuits, an ALU 885, and control logic 890 to calculate the memory address and provide pipeline ordering to keep the operations in order. Some operations can be out of order, but the load / store unit provides the function of making the out-of-order operations appear to the program as if they have been executed in order.

[0169] Preferably, the addresses "seen" by an application program are typically referred to as virtual addresses. Virtual addresses are sometimes also referred to as "logical addresses" and "effective addresses". These virtual addresses are virtual because they are redirected to physical memory locations through one of various dynamic address translation (DAT) techniques, which include but are not limited to prefixing the virtual address with only an offset value, converting the virtual address via one or more translation tables, which preferably include at least a segment table and a page table either separately or in combination, and preferably, the segment table has entries pointing to the page table. In , a translation hierarchy is provided, which includes a region first table, a region second table, a region third table, a segment table, and an optional page table. The performance of address translation is typically improved by utilizing a translation lookaside buffer (TLB), which includes entries that map virtual addresses to associated physical memory locations. These entries are created when the DAT uses the translation table to translate the virtual address. Then, subsequent uses of the virtual address can utilize the entries in the fast TLB instead of slow sequential translation table access. The TLB content can be managed by various replacement algorithms including least recently used (LRU).

[0170] Each processor in a multiprocessor system is responsible for keeping shared resources such as I / O, caches, TLBs, and memory interlocked for consistency. So-called "snooping" techniques can be utilized in maintaining cache consistency. In a snooping environment, each cache line can be marked as being in any one of a shared state, an exclusive state, a modified state, an invalid state, etc., for sharing purposes.

[0171] The I / O unit 854 can provide the processor with means for attaching to peripheral devices such as including tape, disk, printer, display, and network. The I / O unit is typically presented to computer programs by software drivers. In a host (such as from of ), channel adapters and open system adapters are the host's I / O units, which provide communication between the operating system and peripheral devices.

[0172] Furthermore, other types of computer systems can benefit from one or more aspects of the present invention. As an example, a computer system can include an emulator, such as software or other emulation mechanisms, where a specific architecture including, for example, instruction execution, architectural functions (such as address translation), and architectural registers is emulated, or a subset thereof is emulated, for example, on a native system having a processor and memory. In such an environment, one or more emulation functions of the emulator can implement one or more aspects of the present invention, even if the computer on which the emulator is executed may have an architecture different from the emulated capabilities. For example, in emulation mode, a specific instruction or operation being emulated can be decoded, and appropriate emulation functions can be constructed to implement the individual instruction or operation.

[0173] In an emulation environment, a host computer can include, for example, a memory for storing instructions and data, an instruction fetch unit for fetching instructions from the memory and optionally providing local buffering for the fetched instructions, an instruction decoding unit for receiving the fetched instructions and determining the type of the fetched instructions, and an instruction execution unit for executing the instructions. Execution can include: loading data from the memory into registers, storing data from the registers back into the memory, and / or performing a certain type of arithmetic or logical operation, as determined by the decoding unit. For example, each unit can be implemented in software. The operations performed by these units can be implemented as one or more subroutines within the emulator software.

[0174] More specifically, in a mainframe, architecture machine instructions are used by programmers, such as "C" programmers, for example, through a compiler application. These instructions stored in a storage medium can be executed locally in a server, or alternatively, executed in a machine with a different architecture. They can be executed in existing and future mainframe servers and in other servers (such as Power Systems servers and servers) being emulated. They can be executed in machines running Linux on various machines using hardware manufactured by AMD TM etc. In addition to being in In addition to being executed on such hardware, Linux and machines emulating Hercules, UMX, or FSI (Fundamental Software, Inc) can also be used, where the execution is typically in emulation mode. In emulation mode, the emulation software is executed by the native processor to emulate the architecture of the processor being emulated.

[0175] The native processor can execute emulation software including firmware or the native operating system to perform the emulation of the processor being emulated. The emulation software is responsible for fetching and executing the instructions of the architecture of the processor being emulated. The emulation software maintains the emulated program counter to track the instruction boundaries. The emulation software can fetch one or more emulated machine instructions at a time and convert one or more emulated machine instructions into a corresponding set of native machine instructions to be executed by the native processor. These converted instructions can be cached to enable faster conversion. However, the emulation software has to maintain the architectural rules of the architecture of the processor being emulated to ensure that the operating systems and applications written for the processor being emulated work correctly. In addition, the emulation software has to provide the resources recognized by the architecture of the processor being emulated, including but not limited to control registers, general-purpose registers, floating-point registers, dynamic address translation functions including, for example, segment tables and page tables, interrupt mechanisms, context switching mechanisms, a calendar (TOD) clock, and an architectural interface to the I / O subsystem, so that an operating system or application designed to run on the processor being emulated can run on the native processor with the emulation software.

[0176] The particular instruction being emulated is decoded and subroutines are called to perform the functions of the individual instructions. The emulation software functions for emulating the functions of the processor being emulated are implemented, for example, in "C" subroutines or drivers or in some other way that provides drivers for the particular hardware.

[0177] In Figure 25In [the description], an example of the emulation host computer system 892 of the host computer system 800' with an emulated host architecture is provided. In the emulation host computer system 892, the host processor (i.e., CPU) 891 is an emulation host processor or a virtual host processor, and includes an emulation processor 893 having a native instruction set architecture different from that of the processor 891 of the host computer 800'. The emulation host computer system 892 has a memory 894 accessible by the emulation processor 893. In an example embodiment, the memory 894 is partitioned into a host computer memory 896 portion and an emulation routine 897 portion. According to the host computer architecture, the host computer memory 896 can be used for programs of the emulation host computer 892. The emulation processor 893 executes native instructions of an architecture instruction set different from that of the emulation processor 891, where the native instructions are obtained from the emulation routine memory 897 and can access host instructions from a program in the host computer memory 896 for execution by employing one or more instructions obtained in a sequence and access / decoding routine, where the sequence and access / decoding routine can decode the accessed host instructions to determine a native instruction execution routine for emulating the function of the accessed host instructions. Other tools defined for the host computer system 800' architecture can be emulated by an architecture tool routine, including tools such as general-purpose registers, control registers, dynamic address translation, and I / O subsystem support, as well as processor caches. The emulation routine can also utilize functions available in the emulation processor 893 (such as general-purpose registers and dynamic translation of virtual addresses) to improve the performance of the emulation routine. Specialized hardware and offload engines can also be provided to assist the processor 893 in emulating the functions of the host computer 800'.

[0178] It should be understood that one or more of the above embodiments of the present invention can be combined as long as the combined embodiments are not mutually exclusive. Ordinal numbers, such as "first" and "second", are used herein to indicate different elements assigned the same name, but do not necessarily establish any order of the corresponding elements.

[0179] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0180] The present invention can be a system, a method, and / or a computer program product. The computer program product can include one or more computer-readable storage media having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention.

[0181] A computer-readable storage medium can be a tangible device that is capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, by way of example and not limitation, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punched card or raised structures in a groove having instructions recorded thereon, and any appropriate combination of the foregoing. As used herein, a computer-readable storage medium should not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0182] The computer-readable program instructions described herein can be downloaded to a respective computing / processing device from a computer-readable storage medium or downloaded to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network can include a copper transmission cable, an optical transmission fiber, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0183] The computer-readable program instructions for performing the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages (such as Smalltalk, C++, etc.) and conventional procedural programming languages (such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a computer of the user's computer system, partially on a computer of the user's computer system (as a stand-alone software package), partially on a computer of the user's computer system and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the computer of the user's computer system through any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., using an Internet service provider via the Internet). In some embodiments, in order to perform aspects of the present invention, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0184] Aspects of the present invention are described herein with reference to the flowchart and / or block diagram of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It will be understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram, can be implemented by computer-readable program instructions.

[0185] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create a means for implementing the functions / acts specified in the flowchart and / or one or more block diagram blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium, which may direct a computer, a programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored comprises an article of manufacture that includes instructions for implementing aspects of the functions / acts specified in the flowchart and / or one or more block diagram blocks.

[0186] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices so that a series of operational steps are performed on the computer, other programmable apparatus, or other devices to produce a computer-implemented process such that the instructions executed on the computer, other programmable apparatus, or other devices implement the functions / acts specified in the flowchart and / or one or more block diagram blocks.

[0187] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially in parallel, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or combinations of special purpose hardware and computer instructions.

[0188] Possible combinations of the above features may be as follows:

[0189] 1. A method for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of a computer system that are allocated for use by the guest operating system, the computer system further including one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices, the computer system further including a memory operably connected to the bus-attached devices,

[0190] Each of the plurality of processors is assigned a logical processor ID that is used by the bus-attached device to address the corresponding processor,

[0191] Each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID for use by the operating system and one or more bus connection modules to address the corresponding processor,

[0192] The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID, each directed interrupt signal vector including a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module, each directed interrupt signal vector indicating whether there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed,

[0193] The method includes:

[0194] Receiving, by a bus-attached device, an interrupt signal having an interrupt target ID from one of bus connection modules, the interrupt target ID being assigned to identify, in one of processors used by a guest operating system, a target processor for processing the interrupt signal,

[0195] Selecting, by the bus-attached device, a directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed,

[0196] Selecting, by the bus-attached device, in the selected directed interrupt signal vector, a directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal,

[0197] Updating, by the bus-attached device, the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed,

[0198] Forwarding, by the bus-attached device, the interrupt signal to the target processor.

[0199] 2. The method according to item 1, wherein the interrupt signal indicators assigned to the same bus connection module each include the same offset within a directed interrupt signal vector including the corresponding interrupt signal indicator.

[0200] 3. The method according to any one of the preceding items, wherein each directed interrupt signal vector is implemented as a contiguous region in a memory.

[0201] 4. The method according to any one of the preceding items, wherein each directed interrupt signal indicator is implemented as a single bit.

[0202] 5. The method according to any one of the preceding items, the method further includes: retrieving, by the bus-attached device, a copy of an interrupt table entry assigned to the received interrupt target ID from an interrupt table stored in a memory, the interrupt table entry including a directed interrupt signal vector address indicator indicating a memory address of a directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed, and the bus-attached device using the memory address of the corresponding directed interrupt signal vector to select the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed.

[0203] 6. The method according to item 5, the method further includes: retrieving, by the bus-attached device, a copy of a device table entry from a device table stored in a memory, the device table entry including an interrupt table address indicator indicating a memory address of the interrupt table, and the bus-attached device using the memory address of the interrupt table to retrieve a first copy of the interrupt table entry.

[0204] 7. The method according to item 6, wherein the device table entry further includes a directed interrupt signal offset indicator indicating an offset of a directed interrupt signal indicator that indicates a bus connection module assigned to issue the received interrupt signal.

[0205] 8. The method according to any one of the preceding items, wherein the memory further includes a directed interrupt summary vector having a directed interrupt summary indicator per interrupt target ID, each directed interrupt summary indicator being assigned to an interrupt target ID for indicating whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0206] The method further includes:

[0207] selecting, by a bus-attached device, a directed interrupt summary indicator assigned to a target processor ID to which the received interrupt signal is addressed, and

[0208] updating, by the bus-attached device, the selected directed interrupt summary indicator such that the selected directed interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

[0209] 9. The method according to item 8, wherein the directed interrupt summary vector is implemented as a contiguous region in the memory.

[0210] 10. The method according to any one of items 8 to 9, wherein each of the directed interrupt summary indicators is implemented as a single bit.

[0211] 11. The method according to any one of items 8 to 10, wherein the interrupt table entry further includes a directed interrupt summary vector address indicator indicating a memory address of the directed interrupt summary vector, and the bus-attached device uses the memory address of the directed interrupt summary vector to select a directed interrupt summary indicator assigned to a target processor ID to which the received interrupt signal is addressed.

[0212] 12. The method according to any one of items 8 to 11, wherein the interrupt table entry further includes a directed interrupt summary offset indicator indicating an offset of the directed interrupt summary indicator assigned to the target processor ID within the directed interrupt summary vector.

[0213] 13. The method according to any one of the preceding claims, the method further includes: when forwarding the interrupt signal to the target processor, converting, by the bus-attached device, the interrupt target ID of the target processor received together with the interrupt signal into a logical processor ID of the target processor, and using the logical processor ID of the target processor to address the target processor as the target of the interrupt signal.

[0214] 14. The method according to any one of items 11 to 13, the method further comprising: retrieving, by a bus-attached device, a copy of an interrupt table entry assigned to an interrupt target ID from an interrupt table stored in a memory, the copy of the interrupt table entry further including a current mapping of the interrupt target ID to a first logical processor ID, and the bus-attached device using the copy of the interrupt table entry to translate the interrupt target ID of a target processor received together with an interrupt signal.

[0215] 15. The method according to any one of the preceding items, the copy of the device table entry further including a direct signaling indicator indicating whether the target processor is to be directly addressed, the direct signaling indicator indicating that direct forwarding of the interrupt signal is a requirement to directly address the target processor using the logical processor ID of the target processor to perform forwarding of the interrupt signal, otherwise using broadcast to perform the forwarding.

[0216] 16. The method according to any one of the preceding items, the copy of the interrupt table entry further including a copy of a run indicator indicating whether the target processor identified by the interrupt target ID is scheduled to be used by a guest operating system, the target processor being scheduled to be used by the guest operating system being another requirement to directly address the target processor using the logical processor ID of the target processor to perform forwarding of the interrupt signal, otherwise forwarding the interrupt signal to a first operating system using broadcast for processing.

[0217] 17. The method according to any one of the preceding items, the copy of the interrupt table entry further including an interrupt block indicator indicating whether the target processor identified by the interrupt target ID is currently blocked from receiving the interrupt signal, the target processor not being blocked being another requirement to directly address the target processor using the logical processor ID of the target processor to perform forwarding of the interrupt signal, otherwise forwarding the interrupt signal to a first operating system using broadcast for processing.

[0218] 18. The method according to any one of the preceding items, the device table entry further including a logical partition ID identifying a logical partition to which the guest operating system is assigned, and forwarding the interrupt signal by the bus-attached device further includes forwarding the logical partition ID together with the interrupt signal.

[0219] 19. The method according to any one of the preceding items, the method further comprising: retrieving, by the bus-attached device, an interrupt subclass ID identifying an interrupt subclass to which the received interrupt signal is assigned, and forwarding the interrupt signal by the bus-attached device further includes forwarding the interrupt subclass ID together with the interrupt signal.

[0220] 20. A computer system for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of the computer system that are allocated for use by the guest operating system. The computer system further includes one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices. The computer system further includes a memory operably connected to the bus-attached devices.

[0221] Each of the plurality of processors is assigned a logical processor ID that is used by the bus-attached device to address the corresponding processor.

[0222] Each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID that is used by the operating system and one or more bus connection modules to address the corresponding processor.

[0223] The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID. Each directed interrupt signal vector includes a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module. Each directed interrupt signal vector indicates whether an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed.

[0224] The computer system is configured to execute a method that includes:

[0225] Receiving, by the bus-attached device, from one of the bus connection modules, an interrupt signal having an interrupt target ID that identifies one of the processors allocated for use by the guest operating system as a target processor for processing the interrupt signal.

[0226] Selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed.

[0227] Selecting, by the bus-attached device, in the selected directed interrupt signal vector, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal.

[0228] Updating the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed.

[0229] Forwarding the interrupt signal to the target processor.

[0230] 21. A computer program product for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of a computer system that are allocated for use by the guest operating system. The computer system further includes one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices. The computer system further includes a memory operably connected to the bus-attached devices.

[0231] Each of the plurality of processors is assigned a logical processor ID that is used by the bus-attached device to address the corresponding processor.

[0232] Each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID that is used by the operating system and one or more bus connection modules to address the corresponding processor.

[0233] The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID. Each directed interrupt signal vector includes a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module. Each directed interrupt signal vector indicates whether an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed.

[0234] The computer program product includes a computer-readable non-transitory medium that can be read by a processing circuit and stores instructions for execution by the processing circuit to perform a method. The method includes:

[0235] Receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus connection modules, the interrupt target ID identifying one of the processors allocated for use by the guest operating system as the target processor for processing the interrupt signal.

[0236] Selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed.

[0237] Selecting, by the bus-attached device, in the selected directed interrupt signal vector, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal.

[0238] Updating the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed.

[0239] Forwarding the interrupt signal to the target processor.

Claims

1. A method for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of a computer system that are allocated for use by the guest operating system, the computer system further including one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices, the computer system further including a memory operably connected to the bus-attached devices, each of the plurality of processors is assigned a logical processor ID that is used by the bus-attached device to address the corresponding processor, each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID for use by the operating system and one or more bus connection modules to address the corresponding processor, the memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID, each directed interrupt signal vector including a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module, each directed interrupt signal vector indicating whether there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed, the method comprises: receiving, by the bus-attached device, from one of the bus connection modules an interrupt signal having an interrupt target ID that identifies one of the processors allocated for use by the guest operating system as a target processor for processing the interrupt signal, selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed, selecting, by the bus-attached device, in the selected directed interrupt signal vector, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal, updating, by the bus-attached device, the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that there is an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID to be processed, forwarding, by the bus-attached device, the interrupt signal to the target processor.

2. The method according to claim 1, wherein each of the interrupt signal indicators assigned to the same bus connection module includes the same offset within the directed interrupt signal vector that includes the corresponding interrupt signal indicator.

3. The method according to claim 1, wherein each of the directed interrupt signal vectors is implemented as a contiguous region in the memory.

4. The method according to claim 1, wherein each of the directed interrupt signal indicators is implemented as a single bit.

5. The method according to claim 1, the method further comprises: The bus-attached device retrieves a copy of the interrupt table entry assigned to the received interrupt target ID from the interrupt table stored in the memory. The interrupt table entry includes a directed interrupt signal vector address indicator indicating the memory address of the directed interrupt signal vector of the directed interrupt signal assigned to the interrupt target ID to which the received interrupt signal is addressed. The bus-attached device uses the memory address of the corresponding directed interrupt signal vector to select the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed.

6. The method according to claim 5, the method further comprises: The bus-attached device retrieves a copy of the device table entry from the device table stored in the memory. The device table entry includes an interrupt table address indicator indicating the memory address of the interrupt table. The bus-attached device uses the memory address of the interrupt table to retrieve a first copy of the interrupt table entry.

7. The method according to claim 6, wherein, the device table entry further includes a directed interrupt signal offset indicator indicating the offset of the directed interrupt signal indicator assigned to the bus connection module that issues the received interrupt signal.

8. The method according to claim 1, wherein, the memory further includes a directed interrupt summary vector having a directed interrupt summary indicator for each interrupt target ID. Each directed interrupt summary indicator is assigned to an interrupt target ID and is used to indicate whether there is an interrupt signal addressed to the corresponding interrupt target ID to be processed. The method further includes: The bus-attached device selects the directed interrupt summary indicator assigned to the target processor ID to which the received interrupt signal is addressed, and The bus-attached device updates the selected directed interrupt summary indicator such that the selected directed interrupt summary indicator indicates that there is an interrupt signal addressed to the corresponding interrupt target ID to be processed.

9. The method according to claim 8, wherein, the directed interrupt summary vector is implemented as a contiguous region in the memory.

10. The method according to claim 8, wherein, each of the directed interrupt summary indicators is implemented as a single bit.

11. The method according to claim 8, wherein, the interrupt table entry further includes a directed interrupt summary vector address indicator indicating the memory address of the directed interrupt summary vector. The bus-attached device uses the memory address of the directed interrupt summary vector to select the directed interrupt summary indicator assigned to the target processor ID to which the received interrupt signal is addressed.

12. The method according to claim 8, wherein, the interrupt table entry further includes a directed interrupt summary offset indicator indicating the offset of the directed interrupt summary indicator assigned to the target processor ID within the directed interrupt summary vector.

13. The method according to claim 1, the method further comprises: When forwarding the interrupt signal to the target processor, the bus-attached device converts the interrupt target ID of the target processor received together with the interrupt signal into the logical processor ID of the target processor, and uses the logical processor ID of the target processor to address the target processor that is the target of the interrupt signal.

14. The method according to claim 11, the method further comprises: The bus-attached device retrieves a copy of the interrupt table entry assigned to the interrupt target ID from the interrupt table stored in the memory, the copy of the interrupt table entry further includes the current mapping of the interrupt target ID to the first logical processor ID, and the bus-attached device uses the copy of the interrupt table entry to convert the interrupt target ID of the target processor received together with the interrupt signal.

15. The method according to claim 1, wherein, The copy of the device table entry further includes a direct signaling indicator indicating whether the target processor is to be directly addressed, and the direct signaling indicator indicates that the direct forwarding of the interrupt signal is a requirement to execute the forwarding of the interrupt signal by directly addressing the target processor using the logical processor ID of the target processor, otherwise, the forwarding is performed using broadcast.

16. The method according to claim 1, wherein, The copy of the interrupt table entry further includes a copy of a run indicator, and the run indicator indicates whether the target processor identified by the interrupt target ID is scheduled to be used by the guest operating system. The target processor being scheduled to be used by the guest operating system is another requirement to execute the forwarding of the interrupt signal by directly addressing the target processor using the logical processor ID of the target processor, otherwise, the interrupt signal is forwarded to the first operating system using broadcast for processing.

17. The method according to claim 1, wherein, The copy of the interrupt table entry further includes an interrupt blocking indicator, and the interrupt blocking indicator indicates whether the target processor identified by the interrupt target ID is currently blocked from receiving interrupt signals. The target processor not being blocked is another requirement to execute the forwarding of the interrupt signal by directly addressing the target processor using the logical processor ID of the target processor, otherwise, the interrupt signal is forwarded to the first operating system using broadcast for processing.

18. The method according to claim 1, wherein, The device table entry further includes a logical partition ID identifying the logical partition to which the guest operating system is assigned, and forwarding the interrupt signal by the bus-attached device further includes forwarding the logical partition ID together with the interrupt signal.

19. The method according to claim 1, the method further comprises: The bus-attached device retrieves an interrupt subclass ID identifying the interrupt subclass to which the received interrupt signal is assigned, and forwarding the interrupt signal by the bus-attached device further includes forwarding the interrupt subclass ID together with the interrupt signal.

20. A computer system for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of the computer system that are allocated for use by the guest operating system. The computer system further includes one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices. The computer system further includes a memory operably connected to the bus-attached devices. Each of the plurality of processors is assigned a logical processor ID, which is used by the bus-attached devices to address the corresponding processor. Each of the plurality of processors allocated for use by the guest operating system is further assigned an interrupt target ID, which is used by the operating system and the one or more bus connection modules to address the corresponding processor. The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID. Each directed interrupt signal vector includes a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module. Each directed interrupt signal vector indicates whether an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed. The computer system is configured to execute a method that includes: receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus connection modules, the interrupt target ID identifying one of the processors allocated for use by the guest operating system as a target processor for processing the interrupt signal; selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed; selecting, by the bus-attached device, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal in the selected directed interrupt signal vector; updating the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed; forwarding the interrupt signal to the target processor.

21. A computer program product for providing an interrupt signal to a guest operating system, the interrupt signal being executed using one or more of a plurality of processors of a computer system that are allocated for use by the guest operating system. The computer system further includes one or more bus connection modules operably connected to the plurality of processors via a bus and bus-attached devices. The computer system further includes a memory operably connected to the bus-attached devices. Each of the plurality of processors is assigned a logical processor ID, which is used by the bus-attached devices to address the corresponding processor. Each of the plurality of processors allocated for use by the guest operating system is also allocated an interrupt target ID, which is used by the operating system and one or more bus connection modules to address the corresponding processor. The memory includes a per-interrupt target ID directed interrupt signal vector assigned to the corresponding interrupt target ID. Each directed interrupt signal vector includes a per-bus connection module directed interrupt signal indicator assigned to the corresponding bus connection module. Each directed interrupt signal vector indicates whether an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed. The computer program product includes a computer-readable non-transitory medium that can be read by a processing circuit and stores instructions for execution by the processing circuit to perform a method, the method comprising: receiving, by the bus-attached device, an interrupt signal having an interrupt target ID from one of the bus connection modules, the interrupt target ID identifying one of the processors allocated for use by the guest operating system as the target processor for processing the interrupt signal; selecting, by the bus-attached device, the directed interrupt signal vector assigned to the interrupt target ID to which the received interrupt signal is addressed; selecting, by the bus-attached device, in the selected directed interrupt signal vector, the directed interrupt signal indicator assigned to the bus connection module that issued the received interrupt signal; updating the selected directed interrupt signal indicator such that the corresponding directed interrupt signal indicator indicates that an interrupt signal issued by the corresponding bus connection module and addressed to the corresponding interrupt target ID is waiting to be processed; forwarding the interrupt signal to the target processor.

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