Memory with variable access granularity

Abstract

The integrated circuit memory component receives a first column access command identifying a first amount of data and a second column read command identifying a second amount of data as part of a respective first memory read transaction and a second memory read transaction, the second amount of data consisting of no more than half of the data bits of the first amount of data. In response to receiving the first column access command, the integrated circuit memory component transmits the first amount of data as N parallel bit serial data signals over N external signaling links. In response to receiving the second column access command, the integrated circuit memory component transmits the second amount of data as M parallel bit serial data signals over M of the N external signaling links, where M is less than N.

Description

Technical Field

[0001] The present disclosure relates generally to data processing and, more particularly, to memory systems and components thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Various embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals represent similar elements and in which:

[0003] Figure 1 An embodiment of a dual channel memory component that can be accessed in either of at least two transaction modes having different access granularities is shown;

[0004] Figure 2 More details about switching between volume and parsing modes of operation are shown;

[0005] Figure 3 shows that it can be used to implement Figure 2 An embodiment of a sub-column decoder of the sub-column decoder shown;

[0006] Figure 4 Exemplary row and column command packets are shown that may be used to specify sub-row activation and sub-column access, respectively, during parse mode access;

[0007] Figure 5 shows exemplary configuration registers that may be programmed in response to memory controller instructions and configuration data to configure an operating mode of a variable access granularity memory component;

[0008] Figure 6 Shown with reference Figures 1 to 4 An exemplary timing diagram comparing the described volume and analytical mode operations;

[0009] Figure 7 An exemplary memory channel having a memory bank organized in a memory array mat is shown;

[0010] Figure 8 Shows the available Figure 7 A more detailed embodiment of a memory cell pad implementing a pad in a pad-based bulk architecture of; and

[0011] Fig. 9 An alternative embodiment of a dual channel, variable granularity memory component having circuitry to support merge bank operations is shown. DETAILED DESCRIPTION

[0012] In various embodiments herein, the memory controller and the memory component exchange data of varying granularity according to programming settings and / or granularity-specified commands. In multiple embodiments, a memory component having a native read / write data transfer granularity includes a circuit that supports partial data transfer (i.e., a data amount that is a small portion of the native size data amount), thereby achieving improved access efficiency (e.g., higher access energy / bit) in applications that require access to relatively small, positionally different data amounts. In other embodiments, two or more groups of memory banks accessed via respective / separate memory channels are accessed via shared channels-in effect, logically merging these separate memory banks into a larger unified group, and thus correspondingly reducing the amount of data that must be retrieved in each memory bank access to maintain peak data throughput. These and other features and embodiments will be discussed in more detail below.

[0013] Figure 1 An embodiment of a dual-channel memory component 100 is shown, which can be accessed using any of at least two transaction modes with different access granularities: volume mode access with relatively coarse local granularity and resolution mode access with relatively fine (smaller volume data) granularity. In the described example, the memory component 100 includes two identically implemented and independently operable / configurable memory channels 101 and 103 (channels A and B, which can be essentially two memory components implemented in a single integrated circuit die or in corresponding dies of a multi-die integrated circuit package, respectively), so that, for example, transactions described for channel A are also applicable to channel B. In other embodiments, particularly where the two memory channels can operate in a merge mode (i.e., increasing the effective bank count and thus reducing the data transfer granularity required in sequential bank accesses to maintain peak data throughput), the memory channels 101 and 103 can be implemented in a decentralized manner.

[0014] exist Figure 1 In the example of FIG. 1 , each memory channel 101, 103 includes 16 memory banks 105, each bank 2 14 Memory cells of row (107), 2 per row 6 Columns of memory cells, 2 per column 8 memory units and a bidirectional 16-bit data signaling interface 109. During data mode data transmission, the data signaling interface 109 ("data interface" or "DQ interface") simultaneously (in parallel) outputs / receives 16 bits via 16 external data links (DQ) during each half cycle of the data clock signal DCK, and can therefore output / receive a full 256-bit data train over a "burst interval" of 8 DCK cycles - two bits per link per DCK cycle times 8 DCK cycles times 16 DQ links.

[0015] The command interface 111 samples the command / address (CA) bits transmitted on the CA signaling path in response to successive rising / falling or falling / rising edges of the system clock signal (CK), thereby receiving a 22-bit command / address packet per CK cycle in the 11-bit wide example shown. Figure 1 In the embodiment of the present invention, the system clock period is four times the data clock period (t CK =4t DCK ), so that every 8t DCK The data burst interval of the high-speed mode can receive two command / address packets.

[0016] The memory cells that make up the storage row 107 are single-bit dynamic random access memory cells that are accessed in two phases - a row activation phase (responsive to a row activation CA packet) in which the data stored in the address-specified row of memory cells or "data page" is transferred to the sense amplifier body 113, and a column access phase (responsive to a column access CA packet) in which the address-selected data column within the sense amplifier body 113 is output via the data signaling interface 109 (column read operation, outputting "read" data) or overwritten with a similar amount of "write" data received via the data signaling interface 109. Because the data page remains resident and accessible within the sense amplifier body 113 (or "page buffer") until the sense amplifier body is precharged (i.e., refreshed or "unlocked" in preparation for a subsequent row activation), the principles of spatial and temporal locality can be exploited to perform multiple column access operations per row activation.

[0017] All of the above implementation details—number of banks, rows, and columns, data and CA interface sizes, data burst sizes, CA packet sizes, relative data and system clock rates, etc.—as well as those discussed below regarding resource timing constraints, clock frequencies, time intervals, etc., are presented herein for purposes of example only. In alternative embodiments, any or all of these implementation details may vary. Furthermore, while it is assumed herein that the memory component 100 (and the alternative embodiments discussed below) has a DRAM core, in alternative variable access granularity memory embodiments, various other core memory technologies (e.g., flash memory, static random access memory, phase change memory, magnetoresistive memory, etc.) may be deployed in place of or in addition to DRAM.

[0018] Still reference Figure 1 , the system and data clock frequencies associated with various resource timing constraints imply control sequences for sustained peak data throughput (i.e., maximum memory bandwidth). For example, repeated row activation operations directed to the same memory bank are limited by the row cycle time (t RC ), assuming the best case loop body access, the row cycle time means tRC The active data transfer interval per time is divided by the memory bank count. In a 16-bank memory channel 101, for example, 32 nS t RC The interval allows 2nS for data to be read from each memory bank, so assuming 0.125nS t DCK (data clock period) and each t DCK Double data rate transfer of two bits per link provides time for two 16-bit data transfers on each DQ link per bank; time for two 256-bit data transfers on the 16-bit wide data interface 109, and therefore an average of two column access operations per bank (i.e., each open page (activated row) within the bank). Said another way, peak data throughput with balanced bank accesses (i.e., no idle time on the DQ links, and all banks are accessed at substantially the same rate) requires that 512 bits (64 bytes (64B)) of data be transferred to / from a given memory channel per row activation - i.e., 64-byte data granularity per row activation and 32-byte data granularity per column read / write operation.

[0019] Still reference Figure 1 , volume mode operation reflects the relatively coarse access granularity described above, with each column access transferring a full 32-byte volume of data (64 bytes per row activation, 32 bytes per column access), and an average of one 64-byte volume per row activation (two column operations per row activation). In applications where relatively frequent access is required to smaller, less localized units of data (i.e., smaller amounts of data that may be dispersed among different rows of a given memory bank), the coarse volume mode access granularity results in a significant energy / bit penalty because a major (or at least substantial) share of the read / write data is unnecessarily retrieved (memory reads) or overwritten (writes). In these cases, the memory component 100 or either or both of its memory channels may be converted to a resolution mode - either dynamically in response to an input command or programmatically in response to a register setting - to achieve finer-grained data access, thereby avoiding wasteful retrieval and overwriting of unnecessary data. In the particular embodiment shown, parsing mode data accesses are scaled in both row activation and column access operations, as shown at 121 (e.g., from 16Kb to 4Kb), reducing the amount of activated data (and therefore the effective data page size) by a factor of 4, and also reducing column read / write data accesses by a factor of 4, as shown at 123 (e.g., from 256 bits to 64 bits). These 4:1 scaling factors are carried forward in many of the embodiments described herein - in all cases, scaling factors of larger or smaller granularity may be applied, and the memory components and control components may support multiple mode programmed and / or command specified scaling factors. Figure 1In embodiments, the resolution mode column data volume is reduced (i.e., by a factor of 4 in the depicted example) in part by scaling the width of the data interface 109 as shown at 125. Where the transition between volume and resolution modes is performed dynamically (i.e., on the fly via command codes, for example), in the illustrated 4:1 volume reduction example, a proportional number of signaling links and corresponding signaling circuits within the DQ interface are unused / disabled - 12 of the 16 links and signaling circuits.

[0020] Figure 2 The transition between the quantitative and analytical modes of operation is described in detail. In the described example, the sub-column enable signal (sce) is de-asserted (sce=0) during quantitative mode memory access and is asserted (sce=1) during analytical mode access. Referring first to the quantitative mode details at 151, a complete data row (containing 2 8 2 of the data units 6 Column, so 2 14 The column decode logic 153 is a block of 64 sense amplifiers (c00-c63) that transmits a row of 256 data bits (row 'n') to a sense amplifier block (SA block) and then selects a single 256-bit column of data in a column access operation. More specifically, the column decode logic 153 performs a 64:1 multiplexing operation to transmit an entire 256-bit column of data between 64 sense amplifier banks (c00-c63) and a selected one of 256 column input / output (I / O) lines 155, wherein data is multiplexed from the selected sense amplifier bank onto the column I / O line 155 in a column read operation and demultiplexed from the column I / O line 155 to the selected sense amplifier bank in a column write operation. Within the data interface 157, each of the sixteen 16-bit subgroups of the column I / O lines is coupled to a corresponding serialization / deserialization circuit 159, which serializes the outbound (read) data for transmission as a stream of 16 sequential bits via the corresponding DQ pads 161 (and external DQ signaling links), and conversely, deserializes the inbound stream of 16 write data bits (i.e., arriving via the corresponding DQ links / DQ pads) into parallel 16-bit values ​​on the subject column I / O lines.

[0021] Turning now to the resolution mode operation shown at 181, a two-bit sub-row address "SR[1:0]" is applied during a row activation operation to more finely resolve the activated memory cell into one of four sub-rows within the row specified by the row address. In one embodiment, for example, the sub-row address is applied (i) in combination with the row address to select (and enable latching from) one of four sub-rows of memory cells within the row of memory cells specified by the row address, and (ii) to the sense amplifier body (SA body) to enable latching of data in one of four groups of sense amplifiers (one of four "sub-pages") corresponding to the sub-row selected for data transfer. By this operation, the contents of the three unselected sub-rows of memory cells are not disturbed, and the three unselected sub-pages within the sense amplifier body remain in a standby state and do not require pre-charging - "sub-row activation", which substantially reduces the energy consumption consumed by activating an entire row of memory cells.

[0022] In one embodiment, the sub-row organization is layered above the column organization within the memory cell array such that activation of a given sub-row constitutes activation of a corresponding portion (e.g., one of four) of each column of data within the address selection memory row. Still referring to Figure 2 , for example, resolution mode activation results in activation of cell groups 0, 1, 2, or 3 in each of the 64 columns of memory cells in the target memory row (activation of cell group 1 is shown by shading), and transfers the contents of the activated cell group in each column to the corresponding sense amplifier group. Since any of the four cell groups can be activated in each column (according to the sub-row address SR[1:0]), the data from the activated cell groups is referred to herein as a "sub-column" of data - in this case a total of 64 bits (one quarter of a 256-bit mode data column).

[0023] Because the sense amplifiers corresponding to the unselected subcolumns remain unlatched (ready for subsequent activation) during a subrow activation, column access following a subrow activation is limited to the activated data subcolumns. Thus, the subcolumn address value (SC[1:0]) provided for column decoding to resolve to a particular one of the 64 activated data subcolumns has a one-to-one correspondence with (e.g., matches or uniquely maps to) the subrow address value. As described below, this correspondence has an effect on the subcolumn address source, enabling the subcolumn address to be derived from the subrow address within the memory component (e.g., a copy of the subrow address is stored with the subrow activation and subsequently provided to the column decode logic 153 as the subcolumn address value), or provided by the memory control component in a correspondence required with the subrow activation. In either case, when the sub-column enable signal is asserted (sce=1), the sub-column address is applied within the sub-column decoder 187 (i.e., within the column decode logic 153) to enable 4:1 decoding of the entire 256-bit data column output by the 64:1 column decoder 185. In the example shown, the column address selects a 64-bit data sub-column (i.e., sub-column '1') within the data column to be passed to four enabled I / O circuits 159 within the DQ interface 157. Those enabled I / O circuits (i.e., the shaded examples) output corresponding 16-bit portions of the 64-bit data sub-column as a serial bit stream via corresponding DQ pads 161 (i.e., the pads labeled DQ0, DQ1, DQ2, and DQ3 in the example shown).

[0024] Figure 3 shows that it can be used to implement Figure 21 and 2. An embodiment of a 4:1 sub-column decoder 201 of the sub-column decoder 187 of FIG. As shown, selector circuits 203 are coupled between corresponding groups of column I / O lines 155 and data I / O circuits 159 - in this example, four selector circuits, each selector 203 is coupled between corresponding groups of 64 column I / O lines (four groups of 16 column I / O lines per selector) and one of the four I / O circuits 159 coupled to pads DQ0-DQ3. Referring to the detailed view 209 of the selector circuit 203 (other selector circuits may be implemented similarly), the sub-column enable signal (SCE) is matched with the sub-column address bits SC[0] and SC[1] in gates 211 and 213, respectively, to transmit a two-bit select signal 214 to the multiplexer 215, which in response switches one of four groups of 16 column I / O lines (out of a total of 64 column I / O lines coupled to the selector) to 16 lines (217) extending between the selector and the corresponding data I / O circuits. With this arrangement, when the sub-column enable signal is asserted, the selector 203 couples one of the four groups of 16 column I / O lines to a corresponding one of the data I / O circuits 159 according to the sub-column address, thereby routing the sub-column read data to the data I / O circuit for bit serial transmission on the corresponding signaling link, and routing the sub-column write data received / parallelized by the data I / O circuit to the sub-column address specified portion of the data sub-page (i.e., overwriting the data within the sense amplifier containing the data sub-page). When the sub-column enable signal is de-asserted (e.g., logic low), the select signal 214 is driven low (i.e., '00') by gates 211 and 213 to select the 16 column I / O lines that constitute the corresponding I / O circuits 159 of the assembly dedicated to the 256 column I / O lines in the full volume mode access. As shown, the remaining three groups of 16 column I / O lines are directly coupled to corresponding I / O circuits 159 to conduct read data thereto and write data therefrom during data mode access.

[0025] Figure 4Exemplary row and column command packets 251 and 253 are shown, which can be used to specify sub-row activation and sub-column access during resolution mode access, respectively. In one embodiment, the command signaling interface is widened by one or more bits (e.g., from 10 bits to 11 bits, as shown or 12 bits) relative to conventional implementations to transmit additional address bits that allow sub-row activation and sub-column decoding. In other embodiments, unused bits in a pre-existing command packet protocol can be requisitioned to transmit additional address bits, avoiding CA width expansion. In implementations that support distinguishing between quantitative mode and resolution mode operation of commands (i.e., specifying between quantitative mode and resolution mode accesses by command encoding), the increased CA interface width and / or unused bits within the pre-existing command protocol can provide headroom (additional command codes) for such distinction. For example, the memory control component can drive other unused bits within the row activation command packet (or additional bits delivered by the interface width increase) high or low to distinguish between resolution and quantitative mode accesses.

[0026] Still reference Figure 4 , each command / address packet (251 or 253) is sampled in response to two consecutive system clock edges (e.g., rising first and then falling or vice versa), thus, in the 11-bit CA interface width example, containing 22 command / address bits. Assuming Figure 1 The example memory configuration shown (2 per channel) 4 Individual, each individual 2 14 Rows, 2 per row 6 Column), each activation command packet 251 conveys a 1-bit or 2-bit activation command code, a 4-bit bank address and a 14-bit row address, as well as a 2-bit sub-row address. In cases where a single bit is sufficient to encode the activation command (e.g., asserting a predetermined bit within the command packet is sufficient, where the activation command constitutes a unique bank-specific row command), the address and command bits total 21 of the 22 available CA packet bits, leaving spare bits that can be used to convey additional sub-row address or bank address information (e.g., to indicate a merged bank / channel operation as described below) or to distinguish between quantitative mode and analytical mode row activation.

[0027] A multi-bit column command code (specifying the column to be read in the example shown) is accompanied by a 4-bit group address, a 6-bit column address, and a 2-bit sub-column address in column command packet 253. The relatively small address bit count (12 bits, rather than 20 bits in the row command packet) leaves room to encode a relatively large number of column commands (e.g., read and write commands distinguished by various precharge options and bit masking options) as well as one or more bits to specify whether a given read or write access is performed in volume mode or in resolution mode.

[0028] As described above, in resolution mode accesses, the sub-row and sub-column addresses can be the same (or have a one-to-one correspondence) so that in at least some embodiments, the sub-row address provided in a resolution mode row activation CA packet can be temporarily stored and then applied as a sub-column address value (or used to derive a sub-column address value) during a subsequent column access - this action avoids transmitting the sub-column address bits within the column CA packet, freeing up clean space for additional command distinction or address information (including more decisive column address information). Figure 4 This sub-row storage method is conceptually illustrated. As shown, command decoder 271 asserts the sub-address storage signal in response to decoding a parsing mode row activation command (e.g., command 251), thereby strobing the accompanying sub-row address bits into sub-column address register (SC register) 273. When a parsing mode column read or write command directed to an activated sub-row is received (e.g., command 253 does not have sub-column address bits), the contents of sub-column address register 273 are used to decode (select) a data sub-column.

[0029] Figure 5 An exemplary configuration register 281 (e.g., configuration data memory, mode register, etc.) is shown that can be programmed in response to memory controller instructions and configuration data to configure the operating mode of the variable access granularity memory component. In the described embodiment, the configuration register 281 includes a bit field for programmatically selecting between quantity mode and resolution mode operation (i.e., full data quantity per coarse granularity of memory access vs. partial data quantity per fine granularity of memory access), for specifying the source of sub-column address information, and for enabling or disabling body-merging operations. In one implementation, specification of quantity mode operation within the configuration register 281 (e.g., setting bit "V / R" to '0') allows for command-based selection of resolution mode operation (i.e., the command code indicates whether a given memory transaction is to be performed in quantity mode or resolution mode), while resolution mode specification (V / R=1) triggers full-time resolution mode operation. In the case where the data link between the memory component and the controller is limited to the resolution mode data width (e.g., in Figures 1 to 3 ), resolution mode operation may be specified at system initialization (i.e., programmed in register 281) so that all memory access commands received thereafter (e.g., row activation, column read / write) are executed at resolution mode granularity, avoiding the need to specify / distinguish resolution mode operation in command code. In alternative embodiments, particularly in the case of DQ link count adapted quantity mode operation, dynamic granularity switching (i.e., command-based selection between quantity mode and resolution mode operation) may be enabled in resolution mode rather than quantity mode (e.g., unless register 281 is programmed to resolution mode, all memory access commands are executed in quantity mode).

[0030] Still reference Figure 5The sub-column address (SCA) setting in configuration register 281 indicates the source of the sub-column address bits to be applied during the resolution mode column read and write operations - the sub-row address bits received in the previous row activation command (e.g., Figure 4 The sub-row address bits stored in the main memory component are reapplied as sub-column address bits, or the sub-column address bits are received with a separate column access command. The channel merge setting (CHM) in the configuration register 281 indicates the respective memory channels (e.g., Figure 1 ) are operated individually (i.e., each as an N-bank memory device) or logically combined to double the effective bank count. In the latter case (doubling the (2N) bank count), data written to or read from either of the two sets of N memory banks is transmitted over a shared set of signaling links. In various embodiments, channel merging (or bank-merging) mode is implemented in conjunction with resolution mode operation to further reduce the granularity of transactions per row activation required for peak data throughput (i.e., as described below). Optionally, bank-merging mode can be implemented in conjunction with volume mode operation to reduce the number of column access operations required for each row activation without compromising data throughput.

[0031] Figure 6 Shown is a comparative reference Figures 1 to 4 1 and 2 are exemplary timing diagrams of the described quantitative and analytical modes of operation. In the example shown, CA packets are sent on the multilink command / address path (CA) and are sampled in response to the rising and falling edges of the system clock signal (i.e., each CA link per system clock cycle, t CK ), while data is transmitted on the multi-link data path (DQ) and is sampled / transmitted in response to the rising and falling edges of the data clock signal (i.e., each DQ link is sampled / transmitted every t DCK As discussed above and Figure 6 As shown, in resolution mode, wider command / address packets may be transmitted on the command / address path than in granularity mode (i.e., more bits transmitted in parallel, more specifically 11 bits instead of 10 bits in the example shown) to accommodate the additional sub-row and sub-column address bits and / or additional command code bits required to specify resolution mode operation. In alternative embodiments, the command / address packet width may be consistent across different granularity modes.

[0032] refer to Figure 6 In the exemplary timing of the quantitative mode shown, the row activation command received at 305 is activated after a predetermined time (ie, RAS to CAS delay, t RCD ) is followed by a column access command 307 directed to the activated row, which in this example is itself executed after a predetermined read latency (t RL) and then triggers burst data output 309 via the DQ path. Note that, like the shading of the activate command 305, the read command 307 and the data burst 309 indicate that they correspond to the same memory bank, while the unshaded activate command, read command, and data transfer refer to transactions in other memory banks. Assuming the 32-byte mode column access granularity discussed above, transferring a data column on a 16DQ link consumes 8t DCK Burst interval (16 bit interval (16t BIT ), each interval has 0.5t DCK duration), thus consuming 2t CK Interval - Assume 0.5nS t CK Interval (0.125nS t DCK 1nS data burst interval. With 32nS line cycle time (t RC ) constrained per-channel-16-bank arrangement means a 2nS data transfer window per row activation (i.e., for peak data throughput without resource contention), so on average two column access operations per row activation. This transaction arrangement is shown by the activate command at 305, the two corresponding column read commands 307 and 311, and the two back-to-back read data bursts at 309, 313 - overall, a data granularity of 64B per row activation.

[0033] In resolver mode operation, the same general timing applies (32nS t RC , 0.5nS CA receive interval, 1nS column data burst), but the amount of activation and sent / received data is reduced by a factor of 4. That is, instead of 32-byte column access granularity and 64-byte average granularity per row activation 325, each column access 327, 331 (through four links instead of 16 links) transmits 8 bytes (329, 331), with an average of 16 bytes per row activation.

[0034] Figure 7 An exemplary memory channel 365 is shown having memory banks 367 organized in an array of memory "mats" 369. More specifically, each 256Mb bank (2 14 Memory rows, 2 per memory row 14 1024 (32 rows and 32 columns) memory pads 369, each pad including a 512b×512b cell array, a 512-bit sense amplifier bank, sub-row decoding logic, and sub-column decoding logic. In the particular memory bank shown, the one-hot sub-row enable value “EN SR[3:0]" (e.g., one of four sub-row enable signals asserted in accordance with decoding of a two-bit sub-row address value) is applied to each of eight groups of four pads across each row of the memory bank. With this arrangement, a parsed mode memory transaction will allow row activation of one quarter of the pads 369 within an address selected pad row (i.e., a pad row containing a row of memory cells specified by the row address), with the activated pads being offset a maximum of one another within the row (i.e., every four pads activated). The one-hot sub-row enable value "EN SC [3:0]" (i.e., one of four sub-column enable signals asserted in accordance with decoding of a two-bit sub-column address field) is likewise applied to each of the eight groups of four pads making up the address select row to enable column data to be output therefrom. For bulk mode access, all four sub-row enable signals and all four sub-column enable signals are asserted to enable full bulk access (rather than fine-grained access) within the memory bank.

[0035] Figure 8 Shows the available Figure 7 A more detailed embodiment of a memory cell pad 401 implementing pad 369 within a pad-based body architecture is shown - in this case, in the context of a DRAM memory cell 403, each memory cell having an access transistor 405 and a capacitive storage element 407, although other core storage technologies may be used in alternative embodiments. As shown, the four decoded (one-hot) sub-rows enable signals (E SR [0]-EN SR [3]) is coupled to row decoding circuitry 411 within pad 401 (the other three sub-row enable signals are also coupled to row decoding circuitry 411 within pads of corresponding row distributions) and applied to row selection logic therein (conceptually depicted as logic AND gate 415 and row driver 417). Therefore, if the sub-row address provided in the resolution mode row activation corresponds to the sub-row enable signal coupled to row decoding circuitry 411 in memory cell pad 401 (i.e., is decoded to produce an assertion), and the row address is also decoded to a cell row in the pad, then the word line in pad 401 coupled to the gate of access transistor 405 in the subject memory cell row will be turned on, thereby enabling the contents of capacitive storage element 407 to drive column bit line 420. As shown, the sub-row enable signal also enables operation of sense amplifier 421 within pad 401 (which operation is also conditioned on the row address selection of the cell row within the pad) so that the sense amplifier is enabled within a portion (one of four) of the pads within a given row during row activation.

[0036] Still reference Figure 8 , four decoded sub-column enable signals (EN SC [0]-EN SC[3]) is coupled to column decode logic (multiplexing logic) within the pad to enable selective data output from the sense amplifier body via pass-gate transistor 423. More specifically, if the sub-column address provided in the resolved mode column access (including the sub-column address captured for later use as a sub-column select) corresponds to the subject memory cell pad, and the row address is also decoded to a cell row within the pad, gate 425 will assert the column enable signal at the gate of transistor 423, thereby enabling the subject sense amplifier body (i.e., the sense amplifier body within the memory cell pad selected by the sub-column address) to drive data signals onto column data I / O line 427 and receive data from column data I / O line 427 - transferring the read data from sense amplifier 421 to the data I / O interface, and enabling data to be written from the data I / O interface to overwrite the contents of sense amplifier 21 (and drive that data back to the activated memory cell row 403).

[0037] Fig. 9 An alternative embodiment of a dual-channel variable-granularity memory component 450 is shown with circuitry supporting merge-bank operations. Figure 1 In an embodiment, each of memory channels A and B includes 15 memory banks organized in rows and columns (e.g., same size row and column counts are shown) and data and command / address signaling interfaces. To simplify the explanation of bank-merging operations, the data interface 451 within each channel (A and B) is shown as having a 4-bit data width accessed according to the resolution mode - additional I / O circuitry sufficient to support the volume mode data transfer (e.g., 16 bits per channel) may be present within each data interface.

[0038] Still reference Fig. 9 , a channel multiplexer 455 is provided in one or both memory channels (shown only in channel A in the described embodiment) to enable read / write data transmitted via an external data path coupled to channel A to be routed to / from either of the channel A / B data interfaces - in effect enabling access to each of the two memory channels via a single data interface 451, and thus enabling a logical merger of two 16-bank memory channels into a single 32-bank memory channel. In one embodiment, by programming (e.g., as described in reference Figure 5) to enable such "bank-merge" operation so that the two memory channels can operate in bank-merge mode or independently (in which case the channel multiplexer 455 statically passes data between the external data link and the channel A data interface). In other embodiments, for example, bank-merge operation may be dynamically selected by a command specification (i.e., a command code indicating whether a given transaction or sequence of transactions is to be performed in bank-merge mode). In any case, additional memory bank address bits may be provided within the input command / address packet (e.g., widening the CA path to 12 bits to accommodate the additional address bits, if desired) to support bank-merge operation - the additional bits selecting between the 16 banks of channel A or the 16 banks of channel B, while the remaining 4 bank address bits are decoded within a given channel to perform row activation and column access operations. The added bank address bits, referred to herein as channel select bits, are also provided to the channel multiplexer to route data to / from a selected memory channel during a column access operation.

[0039] In one embodiment, the replicated command / address packets are sent simultaneously to the CA interface in each of the two memory channels with the channel select bits inverted, thereby implementing command transactions (e.g., row activation or column read or write) in one or the other memory channel. In an alternative embodiment, the two channel interfaces can be switchably coupled together during bank-merging operations, and the bank-merging enable bit (e.g., in a programmable register or command transmission) can flip the state of the channel select signal sent to the channel B command / address interface, thereby enabling one channel or the other channel to respond to the other shared command.

[0040] In one embodiment, Fig. 9 As shown in the timing details 471, the memory component 450 is subject to the 32nS row cycle constraint discussed above and operates at the same system and data clock rates (i.e., 2GHz system clock, 8GHz data clock). Assuming a 4-bit resolution mode data interface width, each resolution mode column access command is followed by a corresponding 8-byte read or write data burst (16t BIT When bank-merging operation is enabled, the number of banks accessible through a given memory channel is doubled from 16 to 32, and peak data throughput can be achieved with a single 8B column access in each row activation across the 32 banks (i.e., no idle time on the data path) - avoiding the need for multiple column access operations per row activation, thereby further reducing access granularity (8B per row activation instead of 16B) and improving access efficiency (e.g., reducing access energy / bit).

[0041] It should be noted that the various circuits disclosed herein may be described using computer-aided design tools and represented (or represented) as data and / or instructions contained in various computer-readable media in terms of their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics. The formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats that support behavioral languages ​​such as C, Verilog, and VHDL, formats that support register-level description languages ​​such as RTL, and formats that support geometric description languages ​​such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. Computer-readable media in which such formatted data and / or instructions may be contained may include, but are not limited to, various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media, whether independently distributed in this manner or stored "in situ" in an operating system).

[0042] When received within a computer system via one or more computer-readable media, such data and / or instruction-based representations of the circuits described above may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs, including but not limited to netlist generation programs, placement and routing programs, etc., to generate a representation or image of the physical manifestation of such circuits. Such a representation or image may thereafter be used in device fabrication, for example, by allowing the generation of one or more masks used to form various components of the circuit in a device fabrication process.

[0043] In the foregoing description and accompanying drawings, specific terms and figure symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terms and symbols may imply specific details that are not required to practice those embodiments. For example, any of the specific number of bits, signal path width, signaling or operating frequency, etc. may be different from those described above in alternative embodiments. In addition, the links or other interconnections between the integrated circuit device or internal circuit elements or blocks may be shown as buses or single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be a bus. Signals and signaling links, no matter how they are shown or described, can be single-ended or differential. Integrated circuit device "programming" may include, for example, but not limited to, responding to host instructions (and thus controlling the operating aspects of the device and / or establishing the device configuration) or by a one-time programming operation (e.g., blowing fuses within the configuration circuit during device production) to load control values ​​into registers or other storage circuits within the integrated circuit device, and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also referred to as a strap) to establish a specific device configuration or operating aspect of the device. When a signal driver circuit asserts (or asserts, if explicitly stated or indicated by the context) a signal on a signal line coupled between the signal driver circuit and the signal receiving circuit, the signal driver circuit is said to "output" a signal to the signal receiving circuit. The term "coupled" is used herein to represent a direct connection as well as a connection through one or more intermediate circuits or structures. The terms "exemplary" and "embodiment" are used to represent examples, not preferences or requirements. In addition, the terms "may" and "can" are used interchangeably to represent optional (permitted) subject matter. The absence of any one term should not be interpreted as requiring a given functionality or technique.

[0044] Various modifications and changes may be made to the embodiments presented herein without departing from the broader spirit and scope of the present disclosure. For example, the features or aspects of any embodiment may be applied in combination with any other embodiment, or in place of the corresponding features or aspects thereof. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. An integrated circuit memory component, comprising: a first data interface for transmitting up to N bit serial data signals in parallel via N external signaling links; Control circuit device: receiving a first column read command as part of a first memory read transaction executed during a first interval in which the integrated circuit memory component remains continuously operable, the first column read command having a first command code specifying a first amount of data; enabling the first data interface to transmit the first amount of data as N parallel bit serial data signals over the N external signaling links in response to the first column read command; receiving a second column read command as part of a second memory read transaction executed during the first interval, the second column read command having a second command code that is different from the first command code and specifies a second amount of data, the second amount of data consisting of no more than half of the data bits of the first amount of data; as well as In response to the second column read command, the first data interface is enabled to send the second amount of data as M parallel bit serial data signals over M of the N external signaling links, where M is less than N.

2. An integrated circuit memory component according to claim 1, wherein the first amount of data consists of a first number (Q1) of bits and the second amount of data consists of a second number (Q2) of bits, where Q2=Q1 / (N / M), where ' / ' represents division.

3. The integrated circuit memory component of claim 1 further comprising a sense amplifier body, and wherein the control circuitry that receives the first column read command and the second column read command comprises a command / address interface to: receiving a first column address value as part of the first column read command, the first column address value uniquely identifying a location of the first amount of data within the sense amplifier, and A second column address value is received as part of the second column read command, the second column address value uniquely identifying a location of the second amount of data within the sense amplifier body, the second column address value having more constituent bits than the first column address value.

4. The integrated circuit memory component of claim 3, wherein the second column address comprises log2(N / M) more bits than the first column address. 5 . The integrated circuit memory component of claim 3 , wherein states of one or more constituent bits of the first column read command code and the second column read command code are different from each other.

6. An integrated circuit memory component according to claim 5, wherein the state of the one or more constituent bits within the second column read command code indicates that the second column address will have more bits than indicated by a different state of the one or more constituent bits within the second column read command code.

7. The integrated circuit memory component according to claim 1 further includes a second data interface to send up to N bit serial data signals in parallel via N external signaling links, which are different from the N external signaling links on which the first data interface sends up to N bit serial data signals.

8. The integrated circuit memory component of claim 1 , wherein the control circuitry that receives the first column read command and the second column read command and enables the first data interface to transmit the first amount of data and the second amount of data comprises: first command / address circuit means, the integrated circuit memory component further comprising a second command / address circuit means for: receiving a third column read command as part of a third memory read transaction, the third column read command identifying a third amount of data; in response to the third column read command, enabling the second data interface to transmit the third amount of data as N parallel bit serial data signals over the N external signaling links to which the second data interface is to be coupled; as well as receiving a fourth column read command as part of a fourth memory read transaction, the fourth column read command identifying a fourth amount of data, the fourth amount of data consisting of no more than half of the data bits of the third amount of data; as well as In response to the fourth column read command, the second data interface is enabled to transmit the fourth amount of data as M parallel bit serial data signals over the N external signaling links to which the second data interface is to be coupled.

9. The integrated circuit memory component of claim 8 further comprising a first core memory array and a second core memory array, each core memory array being organized into a respective plurality of memory banks, and wherein the first command / address circuitry comprises: circuit means for retrieving the first amount of data and the second amount of data from the first core memory array as part of the first memory read transaction and as part of the second memory read transaction, respectively, and the second command / address circuit means includes: circuit means for retrieving the third amount of data and the fourth amount of data from the second core memory array as part of the third memory read transaction and as part of the fourth memory read transaction, respectively.

10. The integrated circuit memory component of claim 9, further comprising multiplexing circuitry coupled to the first data interface and the second data interface, and wherein the control circuitry further: receiving a fifth column read command as part of a fifth memory read transaction, the fifth column read command identifying a fifth amount of data within either the first core memory array or the second core memory array; and In response to the fifth column read command, the first data interface is enabled to transmit the fifth amount of data as a plurality of parallel bit serial data signals over a plurality of the N external signaling links to be coupled to the first data interface.

11. A method of operating in an integrated circuit memory component, the method comprising: receiving a first column read command as part of a first memory read transaction executed during a first interval in which the integrated circuit memory component remains continuously operable, the first column read command having a first command code identifying a first amount of data; in response to receiving the first column read command, enabling the first data interface to transmit the first amount of data as N parallel bit serial data signals over N external signaling links; as well as receiving a second column read command as part of a second memory read transaction executed during the first interval, the second column read command having a second command code that is different from the first command code and specifies a second amount of data, the second amount of data consisting of no more than half of the data bits of the first amount of data; as well as In response to receiving the second column read command, the first data interface is enabled to send the second amount of data as M parallel bit serial data signals over M of the N external signaling links, where M is less than N.

12. The method of claim 11, wherein the first amount of data consists of a first number (Q1) of bits and the second amount of data consists of a second number (Q2) of bits, wherein Q2 = Q1 / (N / M), wherein ' / ' indicates division.

13. The method of claim 11 , wherein receiving the first column read command and the second column read command comprises: receiving a first column address value as part of the first column read command, the first column address value uniquely identifying a location of the first amount of data within a sense amplifier of the integrated circuit memory component, and A second column address value is received as part of the second column read command, the second column address value uniquely identifying a location of the second amount of data within the sense amplifier body, the second column address value having more constituent bits than the first column address value. 14 . The method of claim 13 , wherein the second column address comprises log 2 (N / M) more bits than the first column address. 15 . The method according to claim 13 , wherein states of one or more constituent bits of the first column read command code and the second column read command code are different from each other.

16. The method of claim 15, wherein the state of the one or more constituent bits within the second column read command code indicates that the second column address will have more bits than indicated by a different state of the one or more constituent bits within the second column read command code.

17. The method according to claim 11, further comprising: The second data interface is enabled to transmit up to N bit serial data signals in parallel via N external signaling links different from the N external signaling links over which the first amount of data and the second amount of data are transmitted as part of a third memory access transaction.

18. The method according to claim 11, further comprising: receiving a third column read command as part of a third memory read transaction, the third column read command identifying a third amount of data; in response to the third column read command, enabling the second data interface to transmit the third amount of data as N parallel bit serial data signals over the N external signaling links to which the second data interface is coupled; as well as receiving a fourth column read command as part of a fourth memory read transaction, the fourth column read command identifying a fourth amount of data, the fourth amount of data consisting of no more than half of the data bits of the third amount of data; as well as In response to the fourth column read command, the second data interface is enabled to transmit the fourth amount of data as M parallel bit serial data signals over M of the N external signaling links to which the second data interface is to be coupled.

19. The method according to claim 18, further comprising: retrieving the first amount of data and the second amount of data from a first core memory array as part of the first memory read transaction and as part of the second memory read transaction, respectively; and retrieving the third amount of data and the fourth amount of data from a second core memory array as part of the third memory read transaction and as part of the fourth memory read transaction, respectively.

20. The method according to claim 19, further comprising: receiving a fifth column read command as part of a fifth memory read transaction, the fifth column read command identifying a fifth amount of data within either the first core memory array or the second core memory array; as well as In response to the fifth column read command, the first data interface is enabled to transmit the fifth amount of data as a plurality of parallel bit serial data signals over a plurality of the N external signaling links coupled to the first data interface.

21. An integrated circuit memory component comprising: Data storage device; means for receiving, as part of a first memory read transaction executed during a first interval in which the integrated circuit memory component remains continuously operable, a first column read command having a first command code specifying a first amount of data within the data storage device, receiving, as part of a second memory read transaction executed during the first interval, a second column read command having a second command code different from the first command code and specifying a second amount of data within the data storage device, the second amount of data consisting of no more than half of the data bits of the first amount of data; and A device for sending the first amount of data as N parallel bit serial data signals through N external signaling links in response to the first column read command, and a device for sending the second amount of data as M parallel bit serial data signals through M of the N external signaling links in response to the second column read command, wherein M is less than N.

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