Package and method of manufacturing the same

Abstract

The method includes forming a first photonic package, wherein forming the first photonic package includes: patterning a silicon layer to form a first waveguide, wherein the silicon layer is located on an oxide layer, and wherein the oxide layer is located on a substrate; forming a through hole extending into the substrate; forming a first redistribution structure over the first waveguide and the through hole, wherein the first redistribution structure is electrically connected to the through hole; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first groove, wherein the first groove exposes the oxide layer; and filling the first groove with a first dielectric material to form a first dielectric region. Embodiments of the present application also relate to packages and methods for manufacturing the same.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of manufacturing the same. Background Art

[0002] Electrical signaling and processing is a technology used for signal transmission and processing. In recent years, optical signaling and processing has been used in an increasing number of applications, especially due to the use of optical fiber related applications for signal transmission.

[0003] Optical signals and processing are often combined with electrical signals and processing to provide sophisticated applications. For example, optical fibers can be used for long-range signal transmission, and electrical signals can be used for short-range signal transmission and processing and control. Thus, devices integrating optical components and electronic components are formed for conversion between optical and electrical signals and processing of optical and electrical signals. Thus, a package can include both an optical (photonic) die containing an optical device and an electronic die containing an electronic device. Summary of the invention

[0004] Some embodiments of the present application provide a method for manufacturing a package, comprising: forming a first photonic package, wherein forming the first photonic package comprises: patterning a silicon layer to form a first waveguide, wherein the silicon layer is located on an oxide layer, and wherein the oxide layer is located on a substrate; forming a through hole extending into the substrate; forming a first redistribution structure above the first waveguide and the through hole, wherein the first redistribution structure is electrically connected to the through hole; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first groove, wherein the first groove exposes the oxide layer; and filling the first groove with a first dielectric material to form a first dielectric region.

[0005] Other embodiments of the present application provide a method for manufacturing a package, comprising: forming a first waveguide on a first side of an oxide layer, wherein the first waveguide includes a first waveguide material, wherein the oxide layer is located on a substrate; forming a first redistribution structure above the first waveguide; bonding an electronic tube die to the first redistribution structure; removing the substrate to expose a second side of the oxide layer; and forming a second waveguide on the second side of the oxide layer, wherein the second waveguide includes a second waveguide material different from the first waveguide material.

[0006] Still other embodiments of the present application provide a package, comprising: a substrate comprising a first material; a first dielectric region adjacent to the substrate, wherein the first dielectric region comprises a second material different from the first material, wherein a first sidewall of the first dielectric region physically contacts a sidewall of the substrate; a first dielectric layer extending over the substrate and over the first dielectric region, wherein a second sidewall of the first dielectric region and a sidewall of the first dielectric layer are coplanar; a waveguide located on the first dielectric layer; an edge coupler located on the first dielectric layer, wherein the edge coupler is optically coupled to the waveguide, wherein the edge coupler and the first dielectric region are vertically aligned; a redistribution structure located above the waveguide; and an electronic die bonded to the redistribution structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figures 1 to 14 Cross-sectional views are shown of intermediate steps in forming a photonic package according to some embodiments.

[0009] Fig.15 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0010] Fig.16 Cross-sectional views are shown of intermediate steps in forming a photonic package according to some embodiments.

[0011] Fig.17 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0012] Figures 18 to 23 Cross-sectional views are shown of intermediate steps in forming a photonic package according to some embodiments.

[0013] Fig.24 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0014] Fig.25 Cross-sectional views are shown of intermediate steps in forming a photonic package according to some embodiments.

[0015] Fig.26 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0016] Figures 27 to 42 Cross-sectional views are shown of intermediate steps in forming a photonic package according to some embodiments.

[0017] Fig.43 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0018] Fig.44 A cross-sectional view of a photonic structure according to some embodiments is shown.

[0019] Figures 45 to 50 Cross-sectional views showing intermediate steps in forming a photonic system according to some embodiments.

[0020] Fig.51 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0021] Figure 52 to Figure 55 Cross-sectional views showing intermediate steps in forming a photonic system according to some embodiments.

[0022] Fig.56 A cross-sectional view of a photonic package is shown in accordance with some embodiments.

[0023] Figure 57 to Figure 63 Cross-sectional views showing intermediate steps in forming a photonic system according to some embodiments.

[0024] Fig.64 A cross-sectional view of a photonic system is shown in accordance with some embodiments.

[0025] Figure 65 to Figure 67 A cross-sectional view showing an intermediate step in forming a waveguide structure according to some embodiments.

[0026] Figures 68 to 74 Cross-sectional views showing intermediate steps in forming a photonic system according to some embodiments.

[0027] Fig.75 A cross-sectional view of a photonic system is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0029] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0030] In the present invention, various aspects of packages and their formation are described. According to some embodiments, a three-dimensional (3D) package including an optical device and an electronic device and a method for forming the same are provided. In particular, a photonic package including a waveguide is formed on a substrate, wherein a portion of the substrate is replaced by a dielectric material such as silicon oxide. In some embodiments, replacing the portion of the substrate with a dielectric material can reduce the loss from the edge-mounted optical fiber coupled to the waveguide. In some embodiments, the dielectric material allows optical communication with a grating coupler formed in the waveguide. Replacing a portion of the substrate with a dielectric material can also provide thermal benefits. In some embodiments, a photonic system may include several photonic packages attached to a photonic interconnect structure, wherein the photonic package is optically coupled to a group of waveguides formed in the photonic interconnect structure. In this way, the photonic package can communicate using an optical signal transmitted by the waveguide of the photonic interconnect structure. Using photonic packages and optical communications in this way can provide reduced optical loss, improved efficiency, and improved high-speed communication of the photonic system. According to some embodiments, an intermediate stage of forming a package is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements.

[0031] Figures 1 to 14 The photonic package 100 (see FIG. Fig.14 ). In some embodiments, the photonic package 100 is used as an input / output (I / O) interface between optical signals and electrical signals in a photonic system. For example, one or more photonic packages 100 may be used in a photonic system such as the photonic system 200 (see Fig.15 ) or another photon system.

[0032] First go to Figure 1According to some embodiments, a buried oxide ("BOX") substrate 102 is provided. The BOX substrate 102 includes an oxide layer 102B formed on a substrate 102C and a silicon layer 102A formed on the oxide layer 102B. The substrate 102C may be, for example, a material such as glass, ceramic, dielectric, semiconductor, etc., or a combination thereof. In some embodiments, the substrate 102C may be a semiconductor substrate that may be doped (e.g., with a p-type or n-type dopant) or undoped, such as a bulk semiconductor, etc. The substrate 102C may be a wafer, such as a silicon wafer (e.g., a 12-inch silicon wafer). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 102C may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. The oxide layer 102B may be, for example, silicon oxide, etc. In some embodiments, the oxide layer 102B may have a thickness between about 0.5 μm and about 4 μm. In some embodiments, the silicon layer 102A may have a thickness between about 0.1 μm and about 1.5 μm. The BOX substrate 102 may be referred to as having a front side or a front surface (e.g., Figure 1 the upward-facing side) and the dorsal or back side (e.g. Figure 1 the side facing downward).

[0033] exist Figure 2 In some embodiments, the silicon layer 102A is patterned to form silicon regions for the waveguide 104, the photonic component 106, and / or the coupler 107. The silicon layer 102A can be patterned using suitable photolithography and etching techniques. For example, in some embodiments, a hard mask layer (e.g., a nitride layer or other dielectric material, Figure 2). The pattern of the hard mask layer may then be transferred to the silicon layer 102A using one or more etching techniques, such as dry etching and / or wet etching techniques. For example, the silicon layer 102A may be etched to form a groove that defines the waveguide 104, while the sidewalls of the remaining unrecessed portion define the sidewalls of the waveguide 104. In some embodiments, more than one photolithography and etching sequence may be used to pattern the silicon layer 102A. One waveguide 104 or multiple waveguides 104 may be patterned from the silicon layer 102A. If multiple waveguides 104 are formed, the multiple waveguides 104 may be independent different waveguides 104 or connected as a single continuous structure. In some embodiments, one or more of the waveguides 104 form a continuous ring. Other configurations or arrangements of the waveguide 104, the photonic component 106, or the coupler 107 are also possible. In some cases, the waveguide 104, the photonic component 106, and the coupler 107 may be collectively referred to as a "photonic layer."

[0034] The photonic component 106 may be integrated with the waveguide 104 and may be formed with the silicon waveguide 104. The photonic component 106 may be optically coupled to the waveguide 104 to interact with the optical signal within the waveguide 104. The photonic component 106 may include, for example, a photodetector and / or a modulator. For example, the photodetector may be optically coupled to the waveguide 104 to detect the optical signal within the waveguide 104 and generate an electrical signal corresponding to the optical signal. The modulator may be optically coupled to the waveguide 104 to receive the electrical signal and generate a corresponding optical signal within the waveguide 104 by modulating the optical power within the waveguide 104. In this way, the photonic component 106 facilitates the input / output (I / O) of the optical signal to and from the waveguide 104. In other embodiments, the photonic component may include other active or passive components, such as a laser diode, an optical signal splitter, or other types of photonic structures or devices. The optical power may be provided by, for example, an optical fiber 150 (see FIG. 1 ) coupled to an external light source. Figure 16 to Figure 17 ) is provided to the waveguide 104, or the optical power can be generated by a photonic component within the photonic package 100, such as a laser diode (not shown).

[0035] In some embodiments, the photodetector may be formed by, for example, partially etching an area of ​​the waveguide 104 and growing an epitaxial material on the remaining silicon in the etched area. The waveguide 104 may be etched using acceptable photolithography and etching techniques. The epitaxial material may include, for example, a semiconductor material that may be doped or undoped, such as germanium (Ge). In some embodiments, an implantation process may be performed to introduce dopants into the silicon in the etched area as part of the formation of the photodetector. The silicon in the etched area may be doped with p-type dopants, n-type dopants, or a combination thereof. In some embodiments, the modulator may be formed by, for example, partially etching an area of ​​the waveguide 104 and then implanting appropriate dopants into the remaining silicon in the etched area. The waveguide 104 may be etched using acceptable photolithography and etching techniques. In some embodiments, the etched area for the photodetector and the etched area for the modulator may be formed using one or more of the same photolithography or etching steps. The silicon in the etched area may be doped with p-type dopants, n-type dopants, or a combination thereof. In some embodiments, the etched area for the photodetector and the etched area for the modulator may be implanted using one or more of the same implantation steps.

[0036] In some embodiments, one or more couplers 107 may be integrated with the waveguide 104 and may be formed together with the waveguide 104. The edge coupler 106D may be continuous with the waveguide 104 and may be formed in the same processing step as the waveguide 104 or other photonic components 106. The coupler 107 is a photonic structure that allows optical signals and / or optical power to be transmitted between the waveguide 104 and a photonic component such as an optical fiber 150 or a waveguide of another photonic system. The coupler 107 may include one or more edge couplers, such as Figure 2 The edge coupler allows optical signals and / or optical power to be transmitted between the waveguide 104 and a photonic component that is “edge mounted” near a sidewall of the photonic package 100 . Fig.15 An embodiment of a coupler 107 including an edge coupler for coupling an optical signal between the photonic package 100 and the optical fiber 150 is shown and will be described in more detail below.

[0037] In some embodiments, the coupler 107 includes a grating coupler that allows optical signals and / or optical power to be transmitted between the waveguide 104 and a photonic component mounted vertically above the photonic package 100 . Fig.63 An embodiment of a grating coupler 1107C is shown for coupling optical power between the optical fiber 150C and the waveguide 1106. This will be described in more detail below. Fig.63In some embodiments, the photonic package 100 may include a single coupler 107, multiple couplers 107, or multiple types of couplers 107. The coupler 107 may be formed using acceptable photolithography and etching techniques. In some embodiments, the coupler 107 is formed using the same photolithography or etching steps as the waveguide 104 and / or the photonic component 106. In other embodiments, the coupler 107 is formed after the waveguide 104 and / or the photonic component 106 are formed. In some embodiments, the photonic package 100 or other photonic packages described herein may include one or more reflectors 109 for Fig.56 Embodiments of the present invention will be shown and described in more detail.

[0038] exist Figure 3 In some embodiments, a dielectric layer 108 is formed on the front side of the BOX substrate 102 to form a photonic wiring structure 110. The dielectric layer 108 is formed above the waveguide 104, the photonic component 106, the coupler 107, and the oxide layer 102B. The dielectric layer 108 may be formed of one or more layers of silicon oxide, silicon nitride, combinations thereof, and the like, and may be formed by CVD, PVD, atomic layer deposition (ALD), a spin-on dielectric process, or the like, or a combination thereof. In some embodiments, the dielectric layer 108 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert it to another material, such as an oxide), or the like, or a combination thereof. Other dielectric materials formed by any acceptable process may be used. In some embodiments, a planarization process such as a CMP process, a grinding process, or the like is then used to planarize the dielectric layer 108. In some embodiments, dielectric layer 108 may be formed to have a thickness between about 50 nm and about 500 nm over oxide layer 102B, or may be formed to have a thickness between about 10 nm and about 200 nm over waveguide 104. In some cases, a thinner dielectric layer 108 may allow for more efficient optical coupling between coupler 107 including a grating coupler and a vertically mounted photonic component. Fig.63 and Fig.64 An embodiment is shown in which a coupler 107 comprising a grating coupler is used to couple an optical signal between a photonic package 1101 and a vertically mounted optical fiber 150, as will be described in more detail below.

[0039] Due to the different refractive indices of the materials of the waveguide 104 and the dielectric layer 108, the waveguide 104 has a high internal reflection, so that the light is substantially confined within the waveguide 104, depending on the wavelength of the light and the refractive index of the corresponding materials. In an embodiment, the refractive index of the material of the waveguide 104 is higher than the refractive index of the material of the dielectric layer 108. For example, the waveguide 104 may include silicon, and the dielectric layer 108 may include silicon oxide and / or silicon nitride.

[0040] exist Figure 4 In some embodiments, an opening 111 extending into the substrate 102C is formed. The opening 111 is formed to extend through the dielectric layer 108 and the oxide layer 102B, and may extend partially into the substrate 102C. The opening 111 may be formed by acceptable photolithography and etching techniques, such as by forming and patterning a photoresist and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process.

[0041] exist Figure 5 In some embodiments, a conductive material is formed in the opening 111 to form a through hole 112. In some embodiments, a liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. may be formed in the opening 111 by TaN, Ta, TiN, Ti, CoW, etc., and the liner may be formed using a suitable deposition process such as ALD, etc. In some embodiments, a seed layer (not shown) that may include copper or a copper alloy may then be deposited in the opening 111. A conductive material for forming the through hole 112 in the opening 111 is formed using, for example, ECP or chemical plating. The conductive material may include, for example, a metal or a metal alloy such as copper, silver, gold, tungsten, cobalt, aluminum, or an alloy thereof. A planarization process (e.g., a CMP process or a grinding process) may be implemented to remove excess conductive material along the top surface of the dielectric layer 108 so that the through hole 112 is flush with the top surface of the dielectric layer 108.

[0042] Figure 5 Also shown is the formation of contacts 113 that extend through dielectric layer 108 and are electrically connected to photonic component 106. Contacts 113 allow electrical power or electrical signals to be transmitted to photonic component 106, and allow electrical signals to be transmitted from photonic component 106. In this way, photonic component 106 can transmit electrical signals (e.g., from electronic die 122, see Fig. 9) is converted into an optical signal transmitted by the waveguide 104, and / or the optical signal from the waveguide 104 is converted into an electrical signal (for example, which can be received by the electronic tube core 122). The contact 113 can be formed before or after the formation of the through hole 112, and the formation of the contact 113 and the formation of the through hole 112 can share some steps, such as the deposition and / or planarization of the conductive material. In some embodiments, the contact can be formed by a damascene process, for example, single damascene, dual damascene, etc. For example, in some embodiments, an opening (not shown) for the contact 113 is first formed in the dielectric layer 108 using acceptable photolithography and etching techniques. Then a conductive material can be formed in the opening to form the contact 113. Excess conductive material can be removed using a CMP process or the like. The conductive material of the contact 113 can be formed of a metal or a metal alloy including aluminum, copper, tungsten, etc., which can be the same as the conductive material of the through hole 112. In other embodiments, the contact 113 can be formed using other techniques or materials.

[0043] exist Figure 6 In some embodiments, a redistribution structure 120 is formed over the dielectric layer 108. The redistribution structure 120 includes a dielectric layer 117 and a conductive feature 114 formed in the dielectric layer 117 to provide interconnection and electrical wiring. For example, the redistribution structure 120 may connect the vias 112, the contacts 113, and / or the devices thereon, such as an electronic die 122 (see Fig. 9 ). Dielectric layer 117 may be, for example, an insulating layer or a passivation layer, and may include one or more materials similar to those described above for dielectric layer 108 (such as silicon oxide or silicon nitride), or may include different materials. Dielectric layer 117 and dielectric layer 108 may be transparent or nearly transparent to light in the same wavelength range. Dielectric layer 117 may be formed using techniques similar to those described above for dielectric layer 108 or using different techniques. Conductive features 114 may include conductive lines and vias, and may be formed by a damascene process, such as single damascene, dual damascene, etc. As shown in FIG. Figure 6 As shown, a conductive pad 116 is formed in the topmost layer of the dielectric layer 117. A planarization process (eg, a CMP process, etc.) may be performed after forming the conductive pad 116, so that the surface of the conductive pad 116 and the topmost dielectric layer 117 are substantially coplanar. The redistribution structure 120 may include Figure 6 More or less dielectric layers 117, conductive features 114, or conductive pads 116 are shown. In some embodiments, the redistribution structure 120 may be formed to have a thickness between about 4 μm and about 6 μm. Other thicknesses are also possible.

[0044] exist Figure 7In some embodiments, portions of the redistribution structure 120 are removed and replaced by the dielectric layer 115. For example, portions of the redistribution structure 120 may be removed using acceptable photolithography and etching techniques, such as by forming and patterning a photoresist and then performing an etching process to remove the dielectric layer 117 using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process. The dielectric layer 115 may then be deposited to replace the removed portion of the redistribution structure 120. The dielectric layer 115 may include one or more materials similar to those described above for the dielectric layer 108 (such as silicon oxide or silicon nitride), or may include different materials. In some embodiments, the dielectric layer 115 and the dielectric layer 108 may be transparent or nearly transparent to light in the same wavelength range. The dielectric layer 115 may be formed using techniques similar to those described above for the dielectric layer 108 or using different techniques. In some embodiments, a planarization process (e.g., a CMP or grinding process) is used to remove excess material of the dielectric layer 115. The planarization process may also expose conductive pads 116. After the planarization process is performed, dielectric layer 115, topmost dielectric layer 117, and / or conductive pads 116 may have substantially flush surfaces. In some cases, replacing portions of redistribution structure 120 with dielectric layer 115 may improve optical confinement within waveguide 104 beneath dielectric layer 115. In other embodiments, redistribution structure 120 is not etched, and dielectric layer 115 is not formed.

[0045] exist Figure 8 In some embodiments, one or more electronic dies 122 are bonded to the redistribution structure 120. The electronic dies 122 may be, for example, semiconductor devices, dies, or chips that communicate with the photonic component 106 using electrical signals. Figure 8 1 , one electronic die 122 is shown, but in other embodiments, the photon package 100 may include two or more electronic dies 122. In some cases, multiple electronic dies 122 may be incorporated into a single photon package 100 to reduce processing costs. The electronic die 122 may include a die connector 124, which may be, for example, a conductive pad, a conductive column, etc. In some embodiments, the electronic die 122 may have a thickness between about 10 μm and about 35 μm. Other thicknesses are also possible.

[0046] The electronic die 122 may include an integrated circuit for interfacing with the photonic component 106, such as a circuit for controlling the operation of the photonic component 106. For example, the electronic die 122 may include a controller, a driver, a transimpedance amplifier, etc., or a combination thereof. In some embodiments, the electronic die 122 may also include a CPU. In some embodiments, the electronic die 122 includes a circuit for processing an electrical signal received from the photonic component 106, such as for processing an electrical signal received from the photonic component 106 including a photodetector. In some embodiments, the electronic die 122 may control the high-frequency signal of the photonic component 106 according to an electrical signal (digital or analog) received from another device or die. In some embodiments, the electronic die 122 may be an electronic integrated circuit (EIC) that provides a serializer / deserializer (SerDes) function, etc. In this way, the electronic die 122 may be used as part of an I / O interface between optical signals and electrical signals within the photonic package 100, and the photonic package 100 described herein may be considered a system on a chip (SoC) or a system on an integrated circuit (SoIC) device.

[0047] In some embodiments, the electronic die 122 is bonded to the redistribution structure 120 by dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). In such embodiments, covalent bonds may be formed between oxide layers, such as between the topmost dielectric layer 117 of the electronic die 122 and a surface dielectric layer (not shown). During bonding, metal bonding may also occur between the die connector 124 of the electronic die 122 and the conductive pad 116 of the redistribution structure 120.

[0048] In some embodiments, before the bonding process is performed, the electronic die 122 is subjected to surface treatment. In some embodiments, the top surface of the redistribution structure 120 and / or the electronic die 122 may first be activated using, for example, dry treatment, wet treatment, plasma treatment, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, etc., or a combination thereof. However, any suitable activation process may be used. After the activation process, the redistribution structure 120 and / or the electronic die 122 may be cleaned using, for example, a chemical rinse. Then, the electronic die 122 is aligned with the redistribution structure 120 and placed in physical contact with the redistribution structure 120. For example, the electronic die 122 may be placed on the redistribution structure 120 using a pick-and-place process. Then, the redistribution structure 120 and the electronic die 122 may be subjected to heat treatment and / or pressed against each other (e.g., by applying contact pressure) to bond the redistribution structure 120 and the electronic die 122. For example, the redistribution structure 120 and the electronic die 122 may be subjected to a pressure of about 200 kPa or less and a temperature between about 200° C. and about 400° C. The redistribution structure 120 and the electronic die 122 may then be subjected to a temperature at or above the eutectic point of the materials of the conductive pads 116 and the die connector 124 (e.g., between about 150° C. and about 650° C.) to fuse the conductive pads 116 and the die connector 124. In this manner, the dielectric-to-dielectric bonding and / or metal-to-metal bonding of the redistribution structure 120 and the electronic die 122 forms a bonded structure. In some embodiments, the bonded structure is baked, annealed, pressed, or otherwise treated to enhance or finalize the bond.

[0049] exist Fig. 9 In some embodiments, a dielectric material 126 is formed over the electronic die 122 and the redistribution structure 120. The dielectric material 126 may be formed of silicon oxide, silicon nitride, a polymer, or the like, or a combination thereof. The dielectric material 126 may be formed by CVD, PVD, ALD, a spin-on dielectric process, or the like, or a combination thereof. In some embodiments, the dielectric material 126 may be formed by HDP-CVD, FCVD, or the like, or a combination thereof. In some embodiments, the dielectric material 126 may be a gap filling material, which may include one or more of the above exemplary materials. Other dielectric materials formed by any acceptable process may be used. The dielectric material 126 may be planarized using a planarization process such as a CMP process, a grinding process, or the like. In some embodiments, the planarization process may expose the electronic die 122 so that the surface of the electronic die 122 and the surface of the dielectric material 126 are coplanar.

[0050] exist Fig.10In some embodiments, an optional support 125 is attached to the structure. The support 125 is a rigid structure attached to the structure to provide structural or mechanical stability. The use of the support 125 can reduce warping or bending, which can improve the performance of optical structures such as the waveguide 104 or the photonic component 106. The support 125 can include one or more materials such as silicon (e.g., silicon wafers, bulk silicon, etc.), silicon oxide, a metal, an organic core material, etc., or another type of material. The support 125 can be attached to the structure (e.g., to the dielectric material 126 and / or the electronic tube core 122) using an adhesive layer 127, such as Fig.10 As shown, or the support 125 can be attached using direct bonding or another suitable technique. In some embodiments, the support 125 can have a thickness between about 500 μm and about 700 μm. The support 125 can also have lateral dimensions (e.g., length, width, and / or area) that are greater than, approximately equal to, or less than those of the structure. In other embodiments, during the manufacture of the photonic package 100, the support 125 is attached in a later process step than shown.

[0051] exist Fig.11 In some embodiments, the structure is flipped over and attached to a carrier 140. Carrier 140 may be, for example, a wafer (e.g., a silicon wafer), a panel, a glass substrate, a ceramic substrate, etc. The structure may be attached to carrier 140 using, for example, an adhesive layer or a release layer (not shown). According to some embodiments, the back side of substrate 102C is then thinned to expose through-hole 112. Substrate 102C may be thinned by a CMP process, mechanical grinding, an etching process, etc., or a combination thereof.

[0052] exist Fig.12 In some embodiments, a portion of substrate 102C is removed to form a groove 129 that exposes oxide layer 102B. Groove 129 may extend over waveguide 104 and over coupler 107, and may extend to an edge of photonic package 100, such as Fig.12As shown. In some embodiments, more than one groove 129 is formed. The groove 129 can be formed using suitable photolithography and etching techniques. For example, in some embodiments, a photoresist can be formed and patterned above the structure, wherein the pattern corresponds to the groove 129. The substrate 102C can be etched using the patterned photoresist as an etching mask. The etching can be implemented using one or more suitable techniques, such as a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the etching can be selective, thereby removing the substrate 102C without significantly etching the oxide layer 102B. For example, the etching can be implemented using HNO3, HF, CH3COOH, etc., or a combination thereof. Other etching techniques are also possible. In some embodiments, the groove 129 can have a depth D1 in the range of about 6 μm to about 25 μm, but other depths are also possible. In some embodiments, the sidewalls of the groove 129 are inclined or have small planes, such as Fig.12 As shown, however in other embodiments, the grooves 129 may have vertical sidewalls or sidewalls having a different slope than shown.

[0053] exist Fig.13 In some embodiments, the groove 129 is filled with a dielectric layer 130. The dielectric layer 130 may include one or more materials similar to those described above for the dielectric layer 108 or the dielectric layer 115, such as silicon oxide, etc. In some embodiments, the dielectric layer 130 may be transparent or nearly transparent to light in the same wavelength range. The dielectric layer 130 may be formed using techniques similar to those described above for the dielectric layer 108 or the dielectric layer 115, or may be formed using different techniques. For example, the dielectric layer 130 may be formed by CVD, PVD, HDP-CVD, FCVD, etc. or using different techniques. In some embodiments, a planarization process (e.g., CMP, a grinding process, and / or an etching process) is used to remove excess material from the dielectric layer 130. The planarization process may also expose the through hole 112. After the planarization process is implemented, the dielectric layer 130, the substrate 102C, and the through hole 112 may have substantially flush surfaces.

[0054] In some cases, replacing the portion of substrate 102C above coupler 107 with dielectric layer 130 can improve the performance of edge mounted optical fibers (e.g., Fig.15The dielectric layer 130 can be a material that is transparent to the relevant wavelength of light than the substrate 102C. For example, in some embodiments, the dielectric layer 130 can be silicon oxide and the substrate 102C can be silicon. In some cases, the material of the substrate 102C can reflect or absorb light of the relevant wavelength. By replacing the substrate 102C near the coupler 107 with the dielectric layer 130, less light from the optical fiber can be reflected or absorbed by the substrate 102C before reaching the coupler 107, and more light from the optical fiber can be coupled into the coupler 107. In this way, optical losses can be reduced and the coupling efficiency between the coupler 107 and the edge-mounted optical fiber can be improved. In addition, the formation of the dielectric layer 130 as described herein can avoid difficult process steps such as undercutting and refilling, and can allow the photonic package to have a more robust structure. In other embodiments, more than one groove 129 filled with the dielectric layer 130 can be formed, and one or more dielectric layers 130 can provide similar Fig. 22 The benefits of those described for dielectric layers 330A-330B in .

[0055] exist Fig.14 In some embodiments, a conductive pad 128 is formed on the exposed through hole 112 and the substrate 102C. The conductive pad 128 may be a conductive pad or a conductive column electrically connected to the redistribution structure 120. The conductive pad 128 may be formed of a conductive material such as copper, another metal or a metal alloy, or a combination thereof. The material of the conductive pad 128 may be formed by a suitable process such as plating. For example, in some embodiments, the conductive pad 128 is a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column may be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer (not shown) is formed on the top of the conductive pad 128. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process. In some embodiments, an under-bump metal (UBM, not shown) may be formed above the conductive pad 128. In some embodiments, a passivation layer (not shown) such as silicon oxide or silicon nitride may be formed over the substrate 102C to surround or partially cover the conductive pad 128 .

[0056] Still reference Fig.14According to some embodiments, a conductive connector 132 may be formed on the conductive pad 128 to form the photonic package 100. The conductive connector 132 may be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electroless palladium immersion gold technology (ENEPIG), etc. The conductive connector 132 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 132 is formed by initially forming a solder layer by common methods such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow may be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 132 is a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the conductive connector 132. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process.

[0057] In some embodiments, multiple photon packages 100 may be formed on a single BOX substrate 102 and then singulated to form individual photon packages 100, such as Fig.14 The photonic package 100 shown in FIG. 1 is a photonic package 100. In embodiments such as these, the grooves 129 and the dielectric layer 130 may extend into the scribe line region that is removed during singulation. Singulation may be performed using a suitable technique, such as using a saw, a laser, or the like, or a combination thereof. The photonic package 100 described herein allows for optical communication with the optical fiber 150, as shown below. Fig.15 shown.

[0058] Fig.15 2 shows a photonic system 200 according to some embodiments. The photonic system 200 includes one or more photonic packages 100 and one or more semiconductor devices 250 attached to an interconnect substrate 202. The photonic package 100 may be similar to Fig.14 In some embodiments, the photonic package 100 facilitates optical communication between the semiconductor device 250 and external devices, optical networks, etc. In this way, the photonic system 200 can combine the semiconductor device 250 and the photonic package 100 on a single interconnect substrate 202 that allows for interfacing with one or more optical fibers 150. The optical fibers 150 can be as shown in FIG. Fig.15 Edge mounted as shown.

[0059] The interconnect substrate 202 may be, for example, a glass substrate, a ceramic substrate, a dielectric substrate, an organic substrate (e.g., an organic core), a semiconductor substrate (e.g., a semiconductor wafer), etc., or a combination thereof. In some embodiments, the interconnect substrate 202 includes a conductive pad 204 and conductive wiring (e.g., a wire, a via, a redistribution structure, etc.). In some embodiments, the interconnect substrate 202 may include passive devices or active devices. In some embodiments, the interconnect substrate 202 may be another type of structure, such as an integrated fan-out structure, a redistribution structure, etc. In some embodiments, the interconnect substrate 202 may be similar to the structure for Fig.74 The interconnect substrate 1320 is described. The conductive connector 132 of the photon package 100 can be bonded to the conductive pad 204 of the interconnect substrate 202, thereby forming an electrical connection between the photon package 100 and the interconnect substrate 202. For example, the conductive connector 132 of the photon package 100 can be placed in physical contact with the conductive pad 204, and then a reflow process can be performed to bond the solder material of the conductive connector 132 to the conductive pad 204. In some embodiments, an underfill 210 can be formed between the photon package 100 and the interconnect substrate 202.

[0060] The semiconductor device 250 may be, for example, a chip, a die, a system on chip (SoC) device, a system on integrated circuit (SoIC) device, a package, etc., or a combination thereof. The semiconductor device 250 may include one or more processing devices, such as a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a high performance computing (HPC) die, etc., or a combination thereof. The semiconductor device 250 may include one or more memory devices, which may be volatile memory, such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a high bandwidth memory (HBM), another type of memory, etc. The semiconductor device 250 may be attached to the interconnect substrate 202, and an underfill 210 may be formed between the semiconductor device 250 and the interconnect substrate 202.

[0061] In some embodiments, edge mounted optical fiber 150 can be attached to interconnect substrate 202. Optical fiber 150 can be fixed by optical fiber holder 152 or similar structure, and can be attached to interconnect substrate 202 and / or photonic package 100 by optical glue 212 or the like. In some embodiments, optical fiber 150 can be actively aligned with coupler 107 by adjusting the position of optical fiber 150 while monitoring the signal strength detected by photonic package 100. As previously described, the use of dielectric layer 130 can reduce the optical loss of coupling between optical fiber 150 and coupler 107.

[0062] In some embodiments, the photonic package 100 receives an optical signal from the optical fiber 150 (e.g., at the coupler 107), which is detected using a suitable photonic component 106. One or more electronic dies 122 in the photonic package 100 can then generate corresponding electrical signals based on the optical signal. These electrical signals can then be transmitted to the semiconductor device 250 through the interconnect substrate 202. In some embodiments, the semiconductor device 250 generates electrical signals, which can be transmitted to one or more electronic dies 122 of the photonic package 100 through the interconnect substrate 202. The electronic die 122 can then generate optical signals using a suitable photonic component 106 and couple these optical signals into the optical fiber 150 (e.g., using the coupler 107). In some embodiments, the semiconductor device 250 controls the electronic die 122 of the photonic package 100. In this way, in some embodiments, the photonic package 100 can be considered as an "optical input / output (I / O) module" for the photonic system 200. Use of the photonic package 100 as described herein may reduce the size or cost of the photonic system 200 while providing high-speed optical communications.

[0063] Fig.16 and Fig.17 2 shows a photonic package 100' and a photonic system 200' according to some embodiments. The photonic package 100' may be similar to Fig.14 The photonic package 100 shown, in addition to etching a groove 131 in the support 125 to facilitate the attachment of the optical fiber 150. The groove 131 can be, for example, a V-shaped or U-shaped groove that can have a small facet. In some embodiments, the groove 131 is etched in the support 125 by extending the etching to form the groove 129. In other embodiments, the groove 131 is etched in a different etching step. Controlling the depth and size of the groove 131 can allow passive alignment of the optical fiber 150. For example, the optical fiber 150 can be assembled into the groove 131 so that the optical fiber 150 is optically coupled to the coupler 107. In some cases, passively aligning the optical fiber 150 in this way can reduce assembly time.

[0064] Go to Fig.17 , according to some embodiments, a photonic system 200 ′ including a photonic package 100 ′ having a groove 131 is shown. The photonic system 200 ′ is similar to Fig.15 The photonic system 200 is shown, except that the photonic system 200' includes the photonic package 100'. The optical fiber 150 may be aligned with the groove 131 of the photonic package 100' and then secured using optical glue 212 or the like. In some embodiments, the optical fiber 150 may also be supported by a fiber holder 152.

[0065] Figures 18 to 23An intermediate step in the formation of a photonic package 300 according to some embodiments is shown. Photonic package 300 is similar to photonic package 100, except that a plurality of recesses 329 are formed in substrate 102C and electronic die 122 is attached to via 112 using conductive connectors 132. In some cases, electronic die 122 can be attached to via 112 at a lower cost than attaching electronic die 122 to redistribution structure 120 using direct bonding.

[0066] Fig.18 shows a method similar to that of Figure 7 The structure of the structure shown. For example, Fig.18 The structure shown includes one or more waveguides 104, one or more photonic components 106, one or more couplers 107, vias 112, and redistribution structures 320. The waveguides 104, photonic components 106, couplers 107, and vias 112 may be similar to those previously described with respect to the photonic package 100 and may be formed in a similar manner. The redistribution structures 320 may be similar to those described with respect to Figure 6 to Figure 7 The redistribution structure 320 is similar to the redistribution structure 120 described above and may be formed in a similar manner. The redistribution structure 320 may have a top surface that is substantially flush with the dielectric layer 115. In some embodiments, the redistribution structure 320 includes a layer of conductive features 114 instead of a layer of conductive pads 116.

[0067] exist Fig.19 In the embodiment of the present invention, a support member 125 is attached to the structure. The support member 125 can be similar to the previously described Fig.10 The support 125 described above can be attached in a similar manner. For example, the support 125 can be attached to the redistribution structure 320 and the dielectric layer 115 using an adhesive layer 127. Fig. 20 In some embodiments, the structure is flipped over and attached to a carrier 140. The carrier 140 may be similar to that previously described for Fig.11 Carrier 140 is depicted. The structure may be attached to carrier 140 using, for example, an adhesive layer or a release layer (not shown). According to some embodiments, the back side of substrate 102C is then thinned to expose vias 112. Substrate 102C may be thinned by a CMP process, mechanical grinding, an etching process, etc., or a combination thereof.

[0068] exist Fig.21 In some embodiments, portions of substrate 102C are removed to form a plurality of recesses 329 exposing oxide layer 102B. Fig.21 Two grooves 329A and 329B are shown, but more than two grooves 329 may be formed in other embodiments. The groove 329A may extend over the waveguide 104 and over the coupler 107, and may extend to the edge of the photonic package 300, such as Fig.21As shown. The groove 329B can be formed away from the edge of the photonic package 300, and the remaining portion of the substrate 102C can separate the groove 329A and the groove 329B. The grooves 329A and 329B can have different sizes or shapes, which can be different from each other. Fig.21 Different from those shown.

[0069] The grooves 329A-329B may be formed using suitable photolithography and etching techniques, such as for Fig.12 For example, in some embodiments, a photoresist can be formed and patterned over the structure, and the substrate 102C can then be etched using the patterned photoresist as an etch mask. In some embodiments, the sidewalls of the grooves 329A-329B are sloped or faceted, such as Fig.21 As shown, however in other embodiments, the grooves 329A-329B may have vertical sidewalls or sidewalls with a different slope than shown.

[0070] exist Fig. 22 In some embodiments, the grooves 329A-329B are filled with a dielectric material to form a dielectric layer 330A in the groove 329A and a dielectric layer 330B in the groove 329B. The dielectric material may include a dielectric material similar to that described for Fig.13 The dielectric layer 130 in the embodiment of the present invention may be formed of one or more materials such as those described above for the dielectric layer 130, such as silicon oxide. The dielectric material may be formed using techniques similar to those described above for the dielectric layer 130. In some embodiments, a planarization process (e.g., CMP, a grinding process, and / or an etching process) is used to remove excess dielectric material from the dielectric layers 330A-330B. The planarization process may also expose the via 112. After the planarization process is performed, the dielectric layers 330A-330B, the substrate 102C, and the via 112 may have substantially flush surfaces.

[0071] In some cases, replacing the portion of substrate 102C above coupler 107 with dielectric layer 330A can improve the performance of edge mounted optical fibers (e.g., Fig.24 The optical coupling of the optical fiber 150 in the embodiment of the present invention to the coupler 107 is similar to the previous improvement for Fig.13The improvements described for the dielectric layer 130 in . In some cases, replacing the portion of the substrate 102C located above the coupler 107 with the dielectric layer 330B can improve the electrical isolation and / or thermal isolation of the photonic package 300. For example, in some embodiments, the dielectric layer 330B can be formed above the photonic component 206 or above the redistribution structure 320. In some cases, the dielectric material of the dielectric layer 330B can provide better electrical insulation than the material of the substrate 102C. Therefore, forming the dielectric layer 330B can allow reduced electrical leakage or improved electrical isolation. In addition, in some cases, the dielectric material of the dielectric layer 330B can provide better thermal insulation than the material of the substrate 102C. Therefore, replacing a portion of the substrate 102C with the dielectric layer 330B can allow better thermal isolation of components or structures near the dielectric layer 330B. In some cases, photonic structures such as the photonic component 106, the waveguide 104, or the coupler 107 can have improved performance at high temperatures. Dielectric layer 330B may be formed adjacent such photonic structures to provide improved thermal isolation and improved heating efficiency of the photonic structures, which may improve performance of photonic package 300. In some cases, dielectric layer 330A over coupler 107 may also provide benefits similar to electrical or thermal isolation.

[0072] exist Fig.23 In some embodiments, a conductive pad 128 and a conductive connector 132 are formed on the through hole 112, and the electronic tube die 122 is attached to the conductive connector 132. The conductive pad 128 and the conductive connector 132 can be similar to those previously described for Fig.14 In some embodiments, the conductive pad 128 may include a conductive pad that is subsequently used for wire bonding (see Fig.24 ) of one or more conductive pads, an example of which is Fig.23 It is represented as conductive pad 128'.

[0073] The electronic die 122 may be similar to that previously described with respect to Figure 8 The electronic die 122 described above may be provided, and more than one electronic die 122 may be present. In some embodiments, the electronic die 122 may be bonded to the conductive pad 128, thereby forming an electrical connection between the through hole and the electronic die 122. For example, the connector 124 of the electronic die 122 may be placed in physical contact with the conductive connector 132, and then a reflow process may be performed to bond the solder material of the conductive connector 132 to the connector 124. In some embodiments, an underfill 210 may be formed between the electronic die 122 and the substrate 102C. In some cases, attaching the electronic die 122 using the conductive connector 132 may reduce processing costs. In this way, a photonic package 300 may be formed. In other embodiments, a similar structure may be formed in the photonic package 300. Fig.16Recess 131 is shown. After attaching electronic die 122, carrier 140 may be removed from the structure.

[0074] Fig.24 4 shows a photonic system 400 according to some embodiments. The photonic system 400 includes one or more photonic packages 300 attached to an interconnect substrate 402. The photonic package 300 may be similar to the one for Fig.23 The interconnect substrate 402 may be similar to that described for Fig.15 The interconnect substrate 202 is depicted. For example, the interconnect substrate 402 may include one or more conductive pads 404 similar to the conductive pads 204 of the interconnect substrate 202. In some embodiments, the support 125 of the photonic package 300 is attached to the interconnect substrate 402 using an adhesive layer 410 or another suitable technique.

[0075] In some embodiments, the photon package 300 is electrically connected to the interconnect substrate 402 using one or more wire bonds 420. The wire bonds 420 can be connected to the conductive pads 128' of the photon package 300 and the conductive pads 404 of the interconnect substrate 402. Fig.24 ), an encapsulant, molding compound, etc. may then be deposited over the wire bond 420. One or more edge mounted optical fibers 150 may also be attached to the interconnect substrate 402 and optically coupled to the coupler 107 of the photonic package 300. In some embodiments, similar to the embodiment for Fig.15 One or more semiconductor devices 250 of those described may be connected to an interconnect substrate 402 ( Fig.24 not shown).

[0076] Fig.25 A photonic package 500 is shown according to some embodiments. The photonic package 500 is similar to Fig.23 The photon package 300 is shown, except that the electronic die 122 is not attached to the conductive connector 132, and thus the photon package 500 does not include the electronic die 122. The photon package 500 may include one or more dielectric layers 330A-330B, which may be similar to those described with respect to FIG. Fig.23 The dielectric layers 330A-330B described herein may be directed to Fig.13 A dielectric layer 130 is depicted.

[0077] Fig.26 2 shows a photonic system 550 according to some embodiments. The photonic system 550 includes one or more photonic packages 500 attached to the interconnect substrate 202. The photonic package 500 may be similar to the one described for Fig.25 The interconnect substrate 202 may be similar to that described for Fig.15An interconnect substrate 202 is depicted. For example, the interconnect substrate 202 may include one or more conductive pads 204.

[0078] The conductive connector 132 of the photon package 500 may be bonded to the conductive pad 204 of the interconnect substrate 202, thereby forming an electrical connection between the photon package 500 and the interconnect substrate 202. For example, the conductive connector 132 of the photon package 500 may be placed in physical contact with the conductive pad 204, and then a reflow process may be performed to bond the solder material of the conductive connector 132 to the conductive pad 204. In some embodiments, an underfill 210 may be formed between the photon package 500 and the interconnect substrate 202.

[0079] In some embodiments, one or more electronic dies 122 are connected to the interconnect substrate 202. The electronic dies 122 can be similar to those previously described. The electronic dies 122 can be connected to the conductive pads 204 of the interconnect substrate 202 using, for example, solder bumps. In this way, the electronic dies 122 can be electrically connected to the photonic package 500 through the interconnect substrate 202. In some cases, attaching the electronic dies 122 to the interconnect substrate 202 can allow for greater flexibility in design, thinner photonic systems 550, or reduced processing costs. One or more edge-mounted optical fibers 150 can also be attached to the interconnect substrate 202 and optically coupled to the coupler 107 of the photonic package 500. In some embodiments, similar to the embodiments described for Fig.15 The one or more semiconductor devices 250 described may be connected to the interconnect substrate 202 ( Fig.26 not shown).

[0080] Figures 27 to 42 6 shows an intermediate step in the formation of a photonic package 600 according to some embodiments. The photonic package 600 is similar to the photonic package 100, except that one or more waveguides 604 (see FIG. 1 ) are formed over the waveguide 104 and optically coupled to the waveguide 104. Fig.42 604A-604B in the photonic package 600). Waveguide 604 is formed of a different material than waveguide 104. For example, waveguide 604 may be formed of silicon nitride or a polymer, and waveguide 104 may be formed of silicon. Other materials are also possible. In some cases, waveguide 604 may be formed of a material having less optical loss or less process cost than waveguide 104. In this way, an optical network formed by waveguide 104 and waveguide 604 may be formed in photonic package 600, which may improve the efficiency or performance of photonic package 600.

[0081] Fig. 27 A BOX substrate 102 is shown according to some embodiments. The BOX substrate 102 may be similar to the Figure 1The BOX substrate 102 is described. For example, the BOX substrate may include an oxide layer 102B formed on a substrate 102C and a silicon layer 102A formed on the oxide layer 102B. Fig.28 In some embodiments, the silicon layer 102A is patterned to form silicon regions for the waveguide 104 and / or the photonic component 106. The waveguide 104 or the photonic component 106 may be similar to the silicon regions previously described for the waveguide 104 and / or the photonic component 106. Figure 2 Those described above and can be formed in a similar manner. In some embodiments, one or more couplers 107 ( Fig.28 not shown).

[0082] exist Fig.29 In some embodiments, a dielectric layer 108 is formed on the front side of the BOX substrate 102, and a through hole 612 and a contact 613 are formed in the dielectric layer 108. The dielectric layer 108 is formed over the waveguide 104, the photonic component 106, and the oxide layer 102B. The dielectric layer 108 can be similar to the previous embodiment for Figure 3 A dielectric layer 108 is depicted.

[0083] Vias 612 and contacts 613 may then be formed in the dielectric layer 108. The vias 612 may extend into the dielectric layer 108, and the contacts 613 may extend into the dielectric layer 108 to make electrical contact with the photonic component 106. In some embodiments, the vias 612 or contacts 613 may be formed using a damascene process, such as single damascene, dual damascene, etc. The vias 612 and contacts 613 may be formed, for example, by forming openings in the dielectric layer 108 using acceptable photolithography and etching techniques. In some embodiments, the openings may extend partially or completely through the dielectric layer 108, or may extend partially into the oxide layer 102B. After the openings are formed, a conductive material may be deposited within the openings to form the vias 612 and contacts 613. The conductive material of the vias 612 and / or contacts 613 may be similar to that previously described for the vias 112 or contacts 113 (see Figure 5 ) described herein and can be formed using similar techniques. In other embodiments, the through hole 612 or the contact 613 can be formed using other techniques or materials.

[0084] exist Fig.30 In some embodiments, a redistribution structure 120 is formed over the dielectric layer 108. The redistribution structure 120 may be similar to that for Figure 6 The redistribution structure 120 is described. For example, the redistribution structure 120 may include a dielectric layer 117 and a conductive member 114 formed in the dielectric layer 117 to provide interconnection and electrical wiring. The redistribution structure 120 may connect vias 612, contacts 613, and / or devices such as electronic die 122 (see Fig.32 ).exist Fig.31 In some embodiments, a portion of the redistribution structure 120 is removed and replaced by the dielectric layer 115. The removal of the portion of the redistribution structure 120 and the deposition of the dielectric layer 115 may be similar to the previous description for Figure 7 Process and materials described.

[0085] exist Fig.32 In some embodiments, one or more electronic dies 122 are attached to the redistribution structure 120 and a dielectric material 126 is formed. The electronic dies 122 may be similar to those for Figure 8 The electronic die 122 described above can be attached to the redistribution structure 120 using similar techniques. For example, the electronic die 122 can be attached using direct bonding or the like. The dielectric material 126 can be the same as previously described for Fig. 9 The dielectric material 126 described above is a similar material and can be formed in a similar manner. A planarization process can be performed after forming the dielectric material 126, which can make the top surfaces of the electronic die 122 and the dielectric material 126 substantially coplanar.

[0086] exist Fig.33 In some embodiments, a support 125 is attached to the structure. The support 125 may be similar to the support 125 previously described. Fig.10 The support 125 described above can be attached in a similar manner. For example, the support 125 can be attached using an adhesive layer 127 or the like.

[0087] exist Fig.34 In some embodiments, the structure is flipped over and attached to a carrier 140. The carrier 140 may be similar to that previously described for Fig.11 The carrier 140 is depicted. The structure may be attached to the carrier 140 using, for example, an adhesive layer or a release layer (not shown). According to some embodiments, the back side of the substrate 102C is then removed to expose the oxide layer 102B. The substrate 102C may be removed using a CMP process, mechanical grinding, an etching process (e.g., wet etching, dry etching, or a combination thereof), or the like, or a combination thereof.

[0088] exist Fig.35 In some embodiments, oxide layer 102B is thinned. Oxide layer 102B may be thinned using a CMP process, mechanical grinding, an etching process (e.g., wet etching, dry etching, or a combination thereof), etc., or a combination thereof. In some embodiments, after thinning, oxide layer 102B may have a thickness in a range of about 100 nm to about 400 nm. Other thicknesses are also possible. In some cases, thinning oxide layer 102B may allow waveguide 104 and subsequently formed waveguide 604A (see Fig.37 ) for more efficient optical coupling between them.

[0089] Fig.36 , Fig.37 and Fig.38 FIG. 1 shows an intermediate step of forming a waveguide 604 over the oxide layer 102B according to some embodiments. In some embodiments, the waveguide 604 may include a material such as silicon nitride, a polymer, etc. Fig.36 , Fig.37 and Fig.38 The description is directed to an embodiment in which the waveguide 604 includes silicon nitride, but other materials may be used in other embodiments. The photonic package 600 includes two layers of waveguide 604, which includes a layer of waveguide 604A and a layer of waveguide 604B, but in other embodiments, the photonic package 600 may include more or fewer layers of waveguide 604. In some embodiments, a single layer of waveguide 604 is formed for the photonic package 600, and in other embodiments, three or more layers of waveguide 604 are formed for the photonic package 600. For example, more layers of waveguide 604 may be formed, for example, by repeating some or all of the steps described for forming waveguide 604A or waveguide 604B.

[0090] exist Fig.36 In some embodiments, a silicon nitride layer 602 is deposited over the oxide layer 102B. The silicon nitride layer 602 may be formed using a suitable deposition technique such as CVD, PECVD, LPCVD, PVD, etc. In some embodiments, the silicon nitride layer 602 is formed to have a thickness in a range of about 0.3 μm to about 1.0 μm, but other thicknesses are possible.

[0091] exist Fig.37In some embodiments, the silicon nitride layer 602 is patterned to form a waveguide 604A. The waveguide 604A can be patterned using acceptable photolithography and etching techniques. For example, in some embodiments, a hard mask layer can be formed and patterned above the silicon nitride layer 602. The pattern of the hard mask layer can then be transferred to the silicon nitride layer 602 using an etching process. The etching process can include, for example, a dry etching process and / or a wet etching process. The etching process can be selective to silicon nitride over silicon oxide or other materials. The silicon nitride layer 602 can be etched to form a groove that defines the waveguide 604A, while the sidewalls of the remaining unrecessed portion define the sidewalls of the waveguide 604A. In some embodiments, more than one photolithography and etching sequence can be used to pattern the silicon nitride layer 602. One waveguide 604A or multiple waveguides 604A can be patterned from the silicon nitride layer 602. If multiple waveguides 604A are formed, the multiple waveguides 604A can be independent different waveguides 604A or connected as a single continuous structure. In some embodiments, one or more of the waveguides 604A form a continuous loop. In some embodiments, the waveguide 604A may include a photonic structure such as a grating coupler, an edge coupler, or a coupler (e.g., a mode converter) that allows transmission of optical signals between two waveguides 604A and / or between a waveguide 604A and a waveguide 104. For example, the waveguide 604A may include an edge coupler that allows transmission of optical signals and / or optical power between the waveguide 604A and, for example, an edge-mounted optical fiber 150.

[0092] In some cases, a waveguide formed of silicon nitride (e.g., waveguide 604A) may have advantages over a waveguide formed of silicon (e.g., waveguide 104). For example, silicon nitride has a higher dielectric constant than silicon, and thus a nitride waveguide may have greater internal confinement of light than a silicon waveguide. This may also allow the performance or leakage of a nitride waveguide to be less sensitive to process variations, less sensitive to dimensional uniformity, and less sensitive to surface roughness (e.g., edge roughness or line width roughness). In some cases, the reduced process sensitivity may allow a nitride waveguide to be easier or cheaper to process than a silicon waveguide. These characteristics may allow a nitride waveguide to have lower propagation loss than a silicon waveguide. In some cases, the propagation loss (dB / cm) of a nitride waveguide may be between about 0.1% and about 50% of that of a silicon waveguide. In some cases, a nitride waveguide may also be less sensitive to the temperature of the environment than a silicon waveguide. For example, the sensitivity of a nitride waveguide to temperature may be as little as about 1% of that of a silicon waveguide. In this way, the embodiments described herein can allow for the formation of a photonic package 600 having a nitride waveguide (e.g., waveguide 604A) and a silicon waveguide (e.g., waveguide 104). Multiple sets of waveguides (e.g., 104, 604) in the photonic package 600 can allow for a larger and more efficient optical network within the photonic package 600, which can result in faster and more efficient device performance.

[0093] Go to Fig.38 According to some embodiments, a dielectric layer 605 is formed over the waveguide 604A, and a waveguide 604B may be formed over the dielectric layer 605. The dielectric layer 605 may include one or more materials similar to those described above for the dielectric layer 108 or the dielectric layer 115. For example, the dielectric layer 605 may include silicon oxide, etc. The dielectric layer 605 may be formed using techniques similar to those described above for the dielectric layer 108 or the dielectric layer 115, or may be formed using different techniques. For example, the dielectric layer 605 may be formed by CVD, PVD, HDP-CVD, FCVD, etc. or using different techniques. In some embodiments, a planarization process (e.g., CMP, a grinding process, and / or an etching process) is used to remove excess material of the dielectric layer 605. In some embodiments, after planarization, the dielectric layer 605 may have a thickness between about 0.6 μm and about 1.6 μm. Other thicknesses are also possible. In some cases, a thinner dielectric layer 605 may allow for more efficient optical coupling between waveguide 604A and an overlying waveguide 604B (if present).

[0094] Waveguide 604B may then be formed on dielectric layer 605. Waveguide 604B may be formed using techniques similar to those used to form waveguide 604A. For example, a silicon nitride layer may be deposited and patterned on dielectric layer 605 to form waveguide 604B. Waveguide 604B may include a coupler that allows light signals to be transmitted between two waveguides 604B and / or between waveguide 604B and waveguide 604A, or may include one or more edge couplers. In some embodiments, additional layers of waveguide 604 may be formed above waveguide 604B by, for example, depositing a dielectric layer, thinning the dielectric layer, and then forming additional waveguides in a manner similar to waveguides 604A-604B.

[0095] Go to Fig.39 According to some embodiments, a dielectric layer 608 is formed over the waveguide 604B and over the dielectric layer 605. The dielectric layer 608 may include one or more materials similar to those described above for the dielectric layer 108, the dielectric layer 115, or the dielectric layer 605, and may be formed using similar techniques. For example, the dielectric layer 608 may include silicon oxide, etc. In some embodiments, a planarization process (e.g., CMP, a grinding process, and / or an etching process) is used to remove excess material of the dielectric layer 605. In some embodiments, a planarization process (e.g., CMP or a grinding process) is used to remove excess material of the dielectric layer 608. In some embodiments, after planarization, the dielectric layer 608 may have a thickness between about 6 μm and about 25 μm. Other thicknesses are also possible.

[0096] Fig.40 and Fig.41 The formation of via 616 is described in accordance with some embodiments. Via 616 extends through dielectric layer 608, dielectric layer 605, and oxide layer 102B to electrically contact via 612. Fig.40 In some embodiments, opening 615 is formed to extend through dielectric layer 608, dielectric layer 605, and oxide layer 102B to expose through hole 612. Opening 615 can be formed by acceptable photolithography and etching techniques, such as by forming and patterning a photoresist and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, a dry etching process and / or a wet etching process.

[0097] exist Fig.41 In some embodiments, a conductive material is formed in the opening 615 to form a through hole 616. In some embodiments, a liner (not shown) such as a diffusion barrier layer, an adhesion layer, etc. may be formed in the opening 615 by TaN, Ta, TiN, Ti, CoW, etc., and the liner may be formed using a suitable deposition process such as ALD, etc. In some embodiments, a seed layer (not shown) that may include copper or a copper alloy may then be deposited in the opening 615. A conductive material for forming the through hole 616 in the opening 615 is formed using, for example, ECP or chemical plating. The conductive material may include, for example, a metal or a metal alloy such as copper, silver, gold, tungsten, cobalt, aluminum, or an alloy thereof. A planarization process (e.g., a CMP process or a grinding process) may be implemented to remove excess conductive material along the top surface of the dielectric layer 608 so that the through hole 616 is flush with the top surface of the dielectric layer 608. The through hole 616 allows electrical power or electrical signals to be transmitted to or from the redistribution structure 120.

[0098] exist Fig.42 In some embodiments, a conductive pad 128 and a conductive connector 132 are formed on the through hole 616 to form the photonic package 600. The carrier 140 can be removed from the structure, and then the conductive pad 128 can be formed on the through hole 616. The conductive pad 128 can be similar to the conductive pad 128 for the photonic package 600. Fig.14 Then, a conductive connector 132 may be formed on the conductive pad 128, which may be similar to that described for Fig.14 those described and are formed in a similar manner.

[0099] Fig.43 2 shows a photonic system 700 according to some embodiments. The photonic system 700 may be similar to the Fig.15 The photonic system 200 described herein, except that it uses a method similar to that described for Fig.42The photonic package 600 described. The photonic system 700 includes one or more photonic packages 600 and one or more semiconductor devices 250 attached to an interconnect substrate 202. The interconnect substrate 202 and the semiconductor devices 250 can be similar to those previously described for the photonic system 200. The optical fiber 150 can be attached to the interconnect substrate 202 and coupled into the photonic package 600. For example, the optical fiber 150 can be optically coupled to an edge coupler formed in one or more of the waveguides 604, or can be optically coupled to an edge coupler formed in one or more of the waveguides 104. The use of a photonic package 600 including multiple sets of waveguides (e.g., 104, 604) can allow the photonic system 700 to operate faster and more efficiently.

[0100] Figures 44 to 50 900 according to some embodiments. Fig.50 ) includes a photonic structure 800 incorporated into a photonic package. The photonic structure 800 includes one or more electronic tube cores 122 and a waveguide 104, and the photonic package 900 includes one or more waveguides 920 made of a material different from the waveguide 104. For example, the waveguide 920 can be made of silicon nitride, a polymer, or another material. In some cases, the waveguide 920 can be formed of a material having less optical loss or less processing cost than the waveguide 920. In this way, an optical network formed by the waveguide 104 and the waveguide 920 can be formed in the photonic package 900, which can improve the efficiency or performance of the photonic package 900.

[0101] Fig.44 8 shows a photonic structure 800 according to some embodiments. The photonic structure 800 may be similar to that previously described in Fig.35 The photonic structure 800 may be composed of Fig.35 The photonic structure 800 may be made of similar materials and using similar techniques as the structures shown. For example, the photonic structure 800 may include a waveguide 104 and a photonic component 106 formed above a redistribution structure 120 and one or more electronic dies 122 attached to the redistribution structure 120. In some embodiments, the photonic structure 800 may also include a through hole 612 and an oxide layer 102B that has been thinned. In some embodiments, the photonic structure 800 may also include a support 125.

[0102] exist Fig.45In some embodiments, a through hole 914 is formed above a carrier substrate 901. The carrier substrate 901 may be, for example, a wafer, a glass carrier substrate, a ceramic carrier substrate, etc. In some embodiments, a release layer (not shown) may be formed on the carrier substrate 901. As an example of forming a through hole 914, a seed layer (not shown) may be formed above the carrier substrate 901. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, PVD, etc. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to a conductive through hole. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating (such as electroplating, chemical plating, etc.). The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material form a through hole 914. The through holes 914 may have a different number or arrangement than shown.

[0103] exist Fig.46 In some embodiments, the photonic structure 800 is attached to a carrier substrate 901 and sealed. The photonic structure 800 may be similar to Fig.44 The arrangement of the through holes 914 and the photonic structure 800 may be different from that shown. The photonic structure 800 may be attached to the carrier substrate 901 by, for example, an adhesive layer or the like.

[0104] After attaching the photonic structure 800, a sealant 916 is formed on and around the through hole 914 and the photonic structure 800. The sealant 916 may be a molding compound, an epoxy resin, or the like. The sealant 916 may be applied by compression molding, transfer molding, or the like, and may be formed over the carrier substrate 901 so that the through hole 914 and / or the photonic structure 800 are buried or covered. The sealant 916 may be applied in a liquid or semi-liquid form and then subsequently cured. The sealant 916 may then be subjected to a planarization process to expose the through hole 914. The planarization process may also expose the surface of the photonic structure 800, such as the support 125 of the photonic structure. The top surfaces of the through hole 914, the sealant 916, and / or the photonic structure 800 may be substantially coplanar within process variations after the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. In some embodiments, for example, if the through hole 914 has been exposed, planarization may be omitted.

[0105] exist Fig.47 In the embodiment of the present invention, a redistribution structure 922 is formed over the sealant 916, the through hole 914 and the photonic structure 800. The redistribution structure 922 includes dielectric layers 924, 928, 932 and 936; and metallization patterns 926, 930 and 934. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The redistribution structure 922 is shown as an example having three metallization pattern layers, but more or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 922. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0106] As an example of forming a redistribution structure 922, a dielectric layer 924 is deposited on the sealant 916, the via 914, and the photonic structure 800. In some embodiments, the dielectric layer 924 is formed of a photosensitive material such as PBO, polyimide, BCB, etc., which can be patterned using a photolithographic mask. The dielectric layer 924 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. Then, the dielectric layer 924 is patterned. The patterning forms an opening that exposes a portion of the via 914. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 924 to light and developing it when the dielectric layer 924 is a photosensitive material, or by etching using, for example, anisotropic etching.

[0107] Then form metallization pattern 926.Metallization pattern 926 includes conductive elements extending along the main surface of dielectric layer 924 and extending through dielectric layer 924 to be physically and electrically coupled to through hole 914.As an example of forming metallization pattern 926, a seed layer is formed above dielectric layer 924 and in an opening extending through dielectric layer 924.In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials.In some embodiments, the seed layer includes a copper layer above a titanium layer and a titanium layer.The seed layer can be formed using, for example, PVD, etc. Then form and pattern photoresist on the seed layer.The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning.The pattern of the photoresist corresponds to metallization pattern 926.Patterning forms an opening through the photoresist to expose the seed layer.Then form a conductive material in the opening of the photoresist and on the exposed portion of the seed layer.The conductive material can be formed by plating (such as electroplating, chemical plating, etc.). The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portion of the seed layer forms the metallization pattern 926. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0108] The remaining dielectric layers 928 / 932 / 936 and metallization patterns 930 / 934 may then be formed in a similar manner. For example, dielectric layer 928 is deposited on metallization pattern 926 and dielectric layer 924. Dielectric layer 928 may be formed in a manner similar to dielectric layer 924 and may be formed of a material similar to dielectric layer 924. Metallization pattern 930 is then formed. Metallization pattern 930 includes a portion located on and extending along the main surface of dielectric layer 928. Metallization pattern 930 also includes a portion extending through dielectric layer 928 to physically and electrically couple metallization pattern 926. Metallization pattern 930 may be formed in a manner similar to metallization pattern 926 and of a material similar to metallization pattern 926. In some embodiments, metallization pattern 930 has a different size than metallization pattern 1926. For example, the wires and / or vias of metallization pattern 930 may be wider or thicker than the wires and / or vias of metallization pattern 926. In addition, the metallization pattern 930 may be formed at a larger pitch than the metallization pattern 926 .

[0109] A dielectric layer 932 and a metallization pattern 934 may then be formed in a similar manner. The metallization pattern 934 is the topmost metallization pattern of the redistribution structure 92. Thus, all intermediate metallization patterns of the redistribution structure 922 (e.g., metallization patterns 926 and 930) are disposed between the metallization pattern 934 and the via 914. In some embodiments, the metallization pattern 934 has a different size than the metallization patterns 926 and 930. For example, the wires and / or vias of the metallization pattern 934 may be wider or thicker than the wires and / or vias of the metallization patterns 926 and 930. In addition, the metallization pattern 934 may be formed with a larger pitch than the metallization pattern 930. The dielectric layer 936 is the topmost dielectric layer of the redistribution structure 922.

[0110] exist Fig.48 , the structure is removed from the carrier substrate 901, the structure is flipped over and attached to the carrier substrate 903. According to some embodiments, a conductive connector 918 may also be formed on the via 914 and the via 612. In some embodiments, the carrier substrate 903 may be similar to the carrier substrate 901. The conductive connector 918 is formed to connect to the redistribution structure 120 of the photonic structure 800 and to connect to the via 914. The conductive connector 918 may be formed of, for example, the same material as the metallization pattern of the redistribution structure 922 or the via 914. In some embodiments, an opening in the oxide layer 102B may be formed, wherein the conductive connector 918 extends through the oxide layer 102B to physically and electrically contact the via 612. The opening in the oxide layer 102B may be formed using suitable photolithography and etching techniques.

[0111] exist Fig.49 In some embodiments, one or more waveguides 920 are formed above the oxide layer 102B and the sealant 916. In some embodiments, the waveguides 920 may include materials such as polymers, silicon nitride, etc. For example, the waveguides 920 may include polymers such as PMMA, BCB, etc., although other materials may be used in other embodiments. In some embodiments, one or more of the waveguides 920 may be optically coupled to the waveguide 104 through the oxide layer 102B. In some embodiments, one or more of the waveguides 920 extend above the sealant 916 to the edge of the structure so that edge mounted optical fibers 150 may be coupled into those waveguides 920 (see FIG. 1 ). Fig.51 ). In some embodiments, one or more waveguides 920 may be formed to extend into the scribe line region such that sidewalls of the waveguide 920 are exposed during singulation of the photonic package 900 .

[0112] The waveguide 920 may be formed, for example, by depositing a layer of material of the waveguide 920 (not separately shown in the figure) over the oxide layer 102B and the sealant 916 and then patterning the material layer to form the waveguide 920. The material layer may be deposited using a suitable technique such as a spin coating technique, but other techniques are also possible. In some embodiments, the waveguide 920 is formed to have a thickness in the range of about 3 μm to about 6 μm, but other thicknesses are also possible.

[0113] The waveguide 920 can be patterned using acceptable photolithography and etching techniques. For example, in some embodiments, a hard mask layer can be formed and patterned above the material layer. The pattern of the hard mask layer can then be transferred to the material layer using an etching process. The etching process can include, for example, a dry etching process and / or a wet etching process. The material layer can be etched to form a groove defining the waveguide 920, while the sidewalls of the remaining unrecessed portion define the sidewalls of the waveguide 920. In some embodiments, more than one photolithography and etching sequence can be used to pattern the material layer. One waveguide 920 or multiple waveguides 920 can be patterned from the material layer. If multiple waveguides 920 are formed, the multiple waveguides 920 can be independent different waveguides 920 or connected as a single continuous structure. In some embodiments, one or more of the waveguides 920 form a continuous ring. In some embodiments, the waveguide 920 can include a photonic structure that allows transmission of optical signals between two waveguides 920 and / or between the waveguide 920 and the waveguide 104, such as a grating coupler, an edge coupler, or a coupler (e.g., a mode converter). For example, the waveguide 920 may include an edge coupler that allows for transmission of optical signals and / or optical power between the waveguide 920 and, for example, an edge-mounted optical fiber 150 .

[0114] In some cases, a waveguide formed from a polymer material (e.g., waveguide 920) can have advantages over a waveguide formed from silicon (e.g., waveguide 104). For example, a polymer material can have a higher dielectric constant than silicon, and thus a polymer waveguide can have greater internal confinement of light than a silicon waveguide. This can also allow the performance or leakage of the polymer waveguide to be less sensitive to process variations, less sensitive to dimensional uniformity, and less sensitive to surface roughness (e.g., edge roughness or line width roughness). In some cases, the reduced process sensitivity can allow the polymer waveguide to be easier or cheaper to process than a silicon waveguide. These properties can allow the polymer waveguide to have lower propagation losses than a silicon waveguide. In this way, the embodiments described herein can allow the formation of a photonic package 900 having a polymer waveguide (e.g., waveguide 920) and a silicon waveguide (e.g., waveguide 104). Multiple sets of waveguides (eg, 104, 920) in the photonic package 900 may allow for a larger and more efficient optical network within the photonic package 900, which may result in faster and more efficient device performance.

[0115] exist Fig.50 In the embodiment, a redistribution structure 940 is formed over the conductive connector 918 and the waveguide 920 according to some embodiments. Fig.50 The illustrated redistribution structure 940 includes dielectric layers 942 / 946 and metallization patterns 944. In other embodiments, the redistribution structure 940 may have another number of dielectric layers and metallization patterns than shown. The dielectric layers 942 / 946 and metallization patterns 944 may be similar to the dielectric layers and metallization patterns of the redistribution structure 922 (see FIG. Fig.47 ), and may be formed in a similar manner. The metallization pattern 944 is formed to physically and electrically connect to the conductive connector 918, and thus make electrical connections to the via 914 and / or the photonic structure 800.

[0116] In some embodiments, an under bump metal (UBM) 947 is formed on the redistribution structure 940. The UBM 947 may have a bump portion located on and extending along the main surface of the dielectric layer 946, and may have a via portion extending through the dielectric layer 946 to physically and electrically couple the metallization pattern 944. Thus, the UBM 947 is electrically coupled to the via 914 and the photonic structure 800. The UBM 947 may be formed of the same material as the metallization pattern 944. In some embodiments, the UBM 947 has a different size than the metallization pattern 944.

[0117] In some embodiments, one or more semiconductor devices 250 are connected to the UBM 947. The semiconductor devices 250 can be similar to those previously described. The semiconductor devices 250 can be connected to the UBM 947 through conductive connectors 948, which can be, for example, solder bumps, etc. An underfill 210 can be deposited between the semiconductor devices 250 and the redistribution structure 940. The photonic package 900 can then be removed from the carrier substrate 903, and the UBM 956 and conductive connectors 958 can be formed on the redistribution structure 922 (see FIG. 2 ). Fig.51 ). UBM 956 can be similar to the previously described conductive pad 128 or UBM 947, and conductive connector 958 can be similar to the previously described conductive connector 132.

[0118] Fig.51 9 shows a photonic system 950 according to some embodiments. The photonic system 950 includes one or more photonic packages 900 attached to an interconnect substrate 952. The photonic package 900 may be similar to that described for Fig.50 The interconnect substrate 952 may be similar to that described for Fig.15The interconnect substrate 202 described. For example, the interconnect substrate 952 may include one or more conductive pads 954 similar to the conductive pads 204 of the interconnect substrate 202. The conductive connector 958 of the photon package 900 may be bonded to the conductive pads 954 of the interconnect substrate 952, thereby forming an electrical connection between the photon package 900 and the interconnect substrate 952. For example, the conductive connector 958 of the photon package 900 may be placed in physical contact with the conductive pads 954, and then a reflow process may be performed to bond the solder material of the conductive connector 958 to the conductive pads 954. In some embodiments, an underfill 210 may be formed between the photon package 900 and the interconnect substrate 952. In some embodiments, the optical fiber 150 may be attached to the interconnect substrate 952 and optically coupled to the waveguide 104.

[0119] Figure 52 to Figure 55 1 shows an intermediate step in the formation of a photonic system 1000 according to some embodiments. The photonic system 1000 is similar to Fig.51 Photonic system 950 is shown, except that photonic system 1000 includes multiple photonic structures 800A-800B that interface with semiconductor devices 250A-250B and communicate using optical signals transmitted through an optical network formed by waveguides 920. The optical network of waveguides 920 for intercommunication may allow for improved speed and efficiency of photonic system 1000. Fig.55 A photonic system 1000 is shown having two photonic structures 800A-800B, but in other embodiments, another number of photonic structures 800 may be present.

[0120] Fig.52 A structure including a plurality of photonic structures 800A- 800B and a via 914 formed on a redistribution structure 1022 is shown in accordance with some embodiments. Fig.51 The structure shown is similar to Fig.48 The structure shown, in addition to the plurality of photonic structures 800A-800B. For example, Fig.52 The structure shown includes a through hole 914, which can be similar to Fig.48 A through hole 914 is shown and may be formed in a similar manner. Fig.52 The redistribution structure 1022 shown is similar to Fig.48 The redistribution structure 922 can be formed in a similar manner. Fig.48 In the illustrated structure, vias 914 and photonic structures 800A-800B have been sealed by encapsulant 916, and conductive connectors 918 have been formed on vias 914 and vias 612 of photonic structure 800AB.

[0121] exist Fig.53In the embodiment of the present invention, one or more waveguides 920 are formed above the photonic structures 800A-800B. The waveguides 920 can be similar to those previously described for Fig.49 The waveguide 920 described above can be formed in a similar manner. For example, the waveguide 920 can be formed by a waveguide such as that previously described for Fig.49 The waveguides 920 may be formed of polymer materials such as those described, but other materials are possible. Some of the waveguides 920 may extend over some of the waveguides 104 of the photonic structures 800A-800B, and some of the waveguides 920 may be optically coupled to the waveguides 104. In this way, the waveguides 920 may form an optical network that extends between the photonic structures 800A-800B and communicates optical signals between the photonic structures 800A-800B.

[0122] exist Fig.54 In some embodiments, a redistribution structure 1040 is formed and semiconductor devices 250A-250B are connected to the redistribution structure 1040. The redistribution structure 1040 is similar to Fig.49 The redistribution structure 940 shown in FIG. 1 and may be formed in a similar manner. For example, the redistribution structure 1040 may be made into an electrical connection to the conductive connector 918. The semiconductor devices 250A-250B may be similar to the semiconductor device 250 described previously. The semiconductor devices 250A-250B may be formed in a manner similar to that for Fig.50 The semiconductor devices 250A-250B may be connected to the redistribution structure 1040 in the manner described. For example, the semiconductor devices 250A-250B may be connected to the UBM formed on the redistribution structure 1040 using, for example, solder bumps, etc. In some embodiments, the semiconductor devices 250A-250B may each be connected to the redistribution structure 120 of the corresponding photonic structure 800A-800B. In this manner, the semiconductor devices 250A-250B may communicate with the photonic structure 800A-800B. In some embodiments, the photonic structure 800A-800B may facilitate communication between the semiconductor devices 250A-250B by sending and receiving optical signals over the waveguide 920.

[0123] exist Fig.55 In the embodiment, the redistribution structure 1022 is connected to the interconnect substrate 1002, thereby forming the photonic system 1000. The interconnect substrate 1002 can be similar to the one for Fig.51 The interconnect substrate 952 is described. For example, the interconnect substrate 1002 may include a conductive pad 1004. In some embodiments, a UBM 956 and a conductive connector 958 may be formed on the redistribution structure 1022. The UBM 956 may be connected to the conductive pad 1004 through the conductive connector 958. In this way, a photonic system 1000 may be formed that allows efficient and high-speed optical communication between multiple semiconductor devices 250A-250B using the waveguide 920.

[0124] Figure 56 to Figure 63 1 shows intermediate steps in the formation of a photonic system 1100 according to some embodiments. Fig.63 ) includes attachment to the photonic interconnect structure 1111 (see Fig.59 ) of multiple photon packages 1101 (see Fig.56 or Fig.56 1A-1101B in the photonic package 1101). The photonic interconnect structure 1111 includes a waveguide 1106 optically coupled to the photonic package 1101 and allowing optical communication between the photonic packages 1101. In this way, efficient and high-speed optical communication between the photonic packages 1101 can be achieved. Fig.63 The photonic system 1000 is shown with two photonic packages 1101A- 1101B, but in other embodiments, another number of photonic packages 1101 may be present.

[0125] Fig.56 1 shows a photonic package 1101 according to some embodiments. The photonic package 1101 is similar to Fig.14 The photon package 100 is shown, except that the photon package 1101 includes a contact pad 136 formed in the dielectric layer 134. For example, the photon package 1101 includes the waveguide 104, the grating couplers 107A-107B, the through hole 112 and the dielectric layer 130. The contact pad 136 can be similar to the contact pad 136 for the photon package 1101. Figure 6 The conductive pad 116 described above and the dielectric layer 134 may be similar to that described for Figure 6 Dielectric layer 117 is depicted. For example, dielectric layer 134 may be formed over substrate 102C, via 112, and dielectric layer 130, openings may be patterned in dielectric layer 134, and then conductive material of contact pad 136 may be formed in the openings. Other formation techniques are also possible.

[0126] According to some embodiments, the photonic package 1101 may include optional components, such as a reflector 109 and a coating 123 on a support 125. The reflector 109 may be formed near a corresponding grating coupler 107 to enhance optical coupling between the grating coupler 107 and another component, such as a coupler or an optical fiber. For example, Fig.56 The photonic package 1101 shown includes an optical fiber 150 formed below the grating coupler 107A to enhance the grating coupler 107A and above the grating coupler 107A (see FIG. Fig.63 ) between the reflector 109A and the grating coupler 1107 formed on the grating coupler 107B to enhance the coupling between the grating coupler 107B and the photonic interconnect structure 1111 and located below the grating coupler 107B (see Fig.63) between the reflector 109B. Reflector 109 may include one or more material layers, such as metal (e.g., copper, etc.), titanium nitride, etc., or a combination thereof. In some embodiments, reflector 109 may include a periodic stack of dielectric layers, such as a stack of layers including silicon oxide, silicon nitride, etc. For example, reflector 109A may be formed by depositing a material on oxide layer 102B and then patterning the material, and reflector 109B may be formed by depositing a material on dielectric layer 108A and then patterning the material. Other formation techniques are also possible.

[0127] The optional coating 123 formed on the support 125 may be, for example, an anti-reflective coating. The coating 123 may be formed on the entire surface of the support 125 (eg, Fig.56 ) or formed on a portion of the support 125. For embodiments in which the optical fiber 150 is attached to the support 125 and optical communication is performed through the support 125 (e.g., Fig.63 In the embodiment of the optical fiber 150A-150B in FIG. 1 , the use of the coating 123 can reduce the light loss or reflection between the optical fiber 150 and the support 125. For example, for an embodiment in which the support 125 includes silicon, the coating 123 can include one or more layers of silicon oxide, silicon nitride, polymer, BCB, etc., or a combination thereof. For clarity, Figure 57 to Figure 63 Coating 123 is omitted.

[0128] Fig.57 Waveguide 1106 is shown formed on substrate 1102 according to some embodiments. Substrate 1102 may be similar to Figure 1 For example, in some embodiments, substrate 1102 may be a wafer, such as a silicon wafer (e.g., a 12-inch silicon wafer), another type of semiconductor wafer, a multilayer substrate such as a BOX substrate, etc. A dielectric layer 1104 may be formed over substrate 1102. Dielectric layer 1104 may include a dielectric layer similar to that described for Figure 3 The dielectric layer 108 may be one or more materials of those described for the dielectric layer 108 in , and may be formed in a manner similar to that described for the dielectric layer 108 .

[0129] A waveguide 1106 may be formed on the dielectric layer 1104. The waveguide 1106 may be similar to Figure 2 Waveguide 104, Fig.37 Waveguide 604A or Fig.49The waveguide 1106 of the embodiment of the present invention can be formed by depositing a silicon nitride layer on the dielectric layer 1104 and then patterning the silicon nitride layer to form a waveguide 1106 comprising silicon nitride. Other materials or techniques are also possible. In some embodiments, a grating coupler 1107 can be formed in the waveguide 1106. Fig.57 Three grating couplers 1107A-1107C are shown, but in other embodiments another number of grating couplers 1107 may be formed. After forming the waveguide 1106, a dielectric layer 1108 may be formed over the waveguide 1106 and the dielectric layer 1104. The dielectric layer 1108 may be a material similar to those described for the dielectric layer 108 and may be formed in a similar manner.

[0130] exist Fig.58 In some embodiments, a through hole 1110 is formed. The through hole 1110 may be similar to Figure 5 The via 112 is shown and may be formed in a similar manner. For example, an opening extending into the substrate 1102 may be formed and then a conductive material may be deposited in the opening.

[0131] exist Fig.59 In some embodiments, a redistribution structure 1112 may be formed over the waveguide 1106, the dielectric layer 1108, and the via 1110 to form a photonic interconnect structure 1111. The redistribution structure 1112 may be formed using a similar structure as described for the redistribution structure 120 and in Figure 6 For example, the redistribution structure 1112 may include a plurality of metallization patterns and dielectric layers, and may be electrically connected to the via 1110 .

[0132] Still reference Fig.59 According to some embodiments, a portion of the redistribution structure 1112 may be removed and replaced with a dielectric region 1114. The dielectric region 1114 may be formed on the grating coupler 1107 so that the optical signal may be transmitted to the grating coupler 1107 through the dielectric region 1114. The dielectric region 1114 may include a dielectric similar to that described for the grating coupler 1107. Figure 3 The dielectric region 1114 may be one or more materials of those described for the dielectric layer 108 in FIG. 1 and may be formed in a manner similar to that described for the dielectric layer 108. For example, in some embodiments, the dielectric region 1114 may include silicon oxide or the like, although other materials are possible.

[0133] exist Fig.60 In accordance with some embodiments, one or more photonic packages 1101 , semiconductor devices 250 , and / or dummy devices 1120 are attached to a photonic interconnect structure 1111 . Fig.60The photonic packages 1101A-1101B and the semiconductor device 250 shown may be similar to Fig.56 The photonic package 1101 shown and the semiconductor device 250 described previously. In some embodiments, the dummy device 1120 is subsequently recessed to facilitate the attachment of the optical fiber 150C (see Figure 62 to Figure 63 ) of a dummy die, a material block, etc. For example, in some embodiments, the dummy device 1120 may include silicon, silicon oxide, a polymer, etc., or a combination thereof. Fig.60 Two photonic packages 1101A-1101B, one semiconductor device 250 and one dummy device 1120 are shown, but there may be more or less in other embodiments. For example, in some embodiments, each photonic package 1101 attached to the photonic interconnect structure 1111 has an associated semiconductor device 250 attached to the photonic interconnect structure 1111 .

[0134] The photonic packages 1101A-1101B, the semiconductor device 250, and the dummy device 1120 may be attached using direct bonding, etc. In some embodiments, the dummy device 1120 may be attached using a different technique than the photonic packages 1101A-1101B and / or the semiconductor device 250. In some embodiments, an encapsulant 1122 is formed on and around the photonic packages 1101A-1101B, the semiconductor device 250, and the dummy device 1120. The encapsulant 1122 may be a molding compound, an epoxy resin, etc., and may be similar to the encapsulant 1122 for the photonic packages 1101A-1101B. Fig.46 Sealant 916 as described.

[0135] exist Fig.61 In some embodiments, substrate 1102 is thinned to expose via 1110, and conductive pad 1124 and conductive connector 1126 are formed on exposed via 1110. Substrate 1102 may be thinned using a suitable process such as a CMP process, a grinding process, an etching process, or a combination thereof. Conductive pad 1124 may be similar to that for Fig.14 The conductive pad 128 described above can be formed in a similar manner. The conductive connector 1126 can be similar to the conductive pad 128 described above. Fig.14 Conductive connector 1126 is similar to the conductive connector 132 described above and may be formed in a similar manner. Conductive connector 1126 allows external components to connect to photonic interconnect structure 1111. In this way, external components can transmit electrical signals and / or electrical power to redistribution structure 1112 and thus to photonic packages 1101A-1101B and semiconductor device 250.

[0136] refer to Fig.61 According to some embodiments, a planarization process may be performed on the sealant 1122 .

[0137] The planarization process may expose surfaces of the photonic packages 1101A- 1101B (eg, surfaces of the support 125 or the coating 123 ), surfaces of the semiconductor device 250 , and / or surfaces of the dummy device 1120 .

[0138] The planarization process may include a CMP process, a grinding process, an etching process, etc., or a combination thereof.

[0139] exist Fig.62 In some embodiments, a groove 1140 is formed in the dummy device 1120 . Fig.62 Also shown is a photonic interconnect structure 1111 connected to an interconnect substrate 1130, thereby forming a photonic system 1100. The groove 1140 in the dummy device 1120 can be formed using an etching process such as wet etching, dry etching, or a combination thereof. In some embodiments, the groove 1140 can expose a dielectric region 1114 below the dummy device 1120. Exposing the dielectric region 1114 in this manner allows the optical fiber 150 (e.g., Fig.63 The interconnect substrate 1130 may be similar to that for Fig.51 The interconnect substrate 952 is depicted. For example, the interconnect substrate 1130 may include a conductive pad 1134, and the conductive connector 1126 may be attached to the conductive pad 1134. An underfill 210 may be deposited between the substrate 1102 and the interconnect substrate 1130.

[0140] exist Fig.63 In some embodiments, optical fibers 150A- 150C are attached to the photonic system 1100 . Fig.63 Fiber 150A is shown attached to photon package 1101A, fiber 150B is attached to photon package 1101B, and fiber 150C is attached to groove 1140 of dummy device 1120. In other embodiments, more or fewer optical fibers 150 may be attached to more or fewer photon packages 1101. Optical glue 212 or the like may be used to attach optical fibers 150A-150C.

[0141] In the illustrated embodiment, optical fiber 150A is attached to the support 125 of photon package 1101A and optically coupled to grating coupler 107A of photon package 1101A, and optical fiber 150B is attached to the support 125 of photon package 1101B and optically coupled to grating coupler 107A of photon package 1101B. In some embodiments, optical signals and / or optical power may be transmitted through the support 125 and other dielectric layers of photon packages 1101A-1101B to allow optical communication between grating coupler 107A and optical fiber 150A-150B of photon packages 1101A-1101B. Photon packages 1101A-1101B may include reflectors 109A to facilitate optical coupling between grating coupler 107A and optical fiber 150A-150B.

[0142] According to some embodiments, the optical fiber 150C is attached to the photonic system 1100 within the groove 1140 and optically coupled to the grating coupler 1107C of the waveguide 1106. Optical signals and / or optical power can be transmitted through the dielectric region 1114 to allow optical communication between the grating coupler 1107C and the optical fiber 150C. In this way, the optical fiber 150C can be optically coupled to the waveguide 1106 through the grating coupler 1107C. In some embodiments, the optical fibers 150A-150B attached to the photonic package 1101 are used to communicate optical signals with the photonic system 1100 using the photonic packages 1101A-1101B, and the optical fiber 150C is used to communicate optical power to the photonic system 1100 through the waveguide 1106.

[0143] In some embodiments, the grating coupler 107B of the photonic package 1101A-1101B is optically coupled to the grating coupler 1107A-107B of the waveguide 1106. Optical signals and / or optical power may be transmitted through the dielectric region 1114 to allow optical communication between the grating coupler 1107A-107B and the grating coupler 107B. In this way, the photonic package 1101A-1101B may be optically coupled to the waveguide 1106 through the grating coupler 107B and the grating coupler 1107A-107B. The photonic package 1101A-1101B may include a reflector 109A that facilitates optical coupling between the grating coupler 107B and the grating coupler 1107A-107B.

[0144] In this way, in some embodiments, the photon package 1101 of the photon system 1100 can be electrically connected to the semiconductor device 250 of the photon system 1100 through the redistribution structure 1112. The photon package 1101 can also be optically coupled to the waveguide 1106 of the photon system 1100 to facilitate optical communication between the various semiconductor devices 250 of the photon system 1100. The redistribution structure 1112 and the waveguide 1106 are portions of the photon interconnect structure 1111 of the photon system 1100 that allow electrical and optical communication within the photon system 1100. The photon package 1101 can be optically coupled to the optical fiber 150 to facilitate optical communication between the semiconductor device 250 and external components. The waveguide 1106 can also be optically coupled to one or more optical fibers 150 that provide optical power to the waveguide 1106. In some cases, the waveguide 1106 can transmit a portion of the optical power to the photon package 1101. In this manner, the photonic system 1100 may be formed to allow efficient and high-speed optical communication between multiple semiconductor devices 250 and to external components using the photonic package 1101 and the waveguide 1106 .

[0145] Fig.64 1 shows a photon system 1150 according to some embodiments. The photon system 1150 is similar to Fig.63 The photonic system 1100 is shown, except that the photonic interconnect structure 1151 of the photonic system 1150 includes a waveguide 1106 formed in the same structural layer as the redistribution structure 1112, and except that the photonic packages 1101A-1101B, the semiconductor device 250, and the dummy device 1120 are attached to the photonic interconnect structure 1151 via conductive connectors 1152. Similar to the photonic system 1100, the optical fibers 150A-150B can be optically coupled to the grating couplers 107A of the photonic packages 1101A-1101B, the optical fibers 150C can be optically coupled to the grating couplers 1107C of the waveguide 1106, and the grating couplers 107B of the photonic packages 1101A-1101B can be optically coupled to the grating couplers 1107A-107B of the waveguide 1106.

[0146] In some embodiments, the photonic interconnect structure 1151 of the photonic system 1150 includes a dielectric layer 1104 formed on a substrate 1102, which may be similar to that described for Fig.57 A redistribution structure 1112 may be formed over the dielectric layer 1104 and may be formed using a similar method to that described for Fig.59 After forming the redistribution structure 1112, portions of the redistribution structure 1112 may be removed to expose portions of the dielectric layer 1104. A waveguide 1106 may then be formed on the exposed portions of the dielectric layer 1104. The waveguide 1106 may be formed similarly to the waveguide 1106 described for the redistribution structure 1112 in FIG. Fig.57 The waveguide 1106 described above may be formed in a similar manner. For example, a silicon nitride layer may be deposited and then patterned over the exposed portions of the dielectric layer 1104, but other materials or techniques are possible. The grating couplers 1107A-1107C may be formed in the waveguide 1106 using techniques similar to those previously described. In other embodiments, the waveguide 1106 may be formed prior to the redistribution structure 1112. For example, portions of the redistribution structure 1112 may be formed adjacent to and / or over the waveguide 1106.

[0147] In some embodiments, a dielectric layer 1158 may be formed over the waveguide 1106. The dielectric layer 1158 may be similar to that for Fig.57 The dielectric layer 1108 described above and may be formed using similar techniques. In some embodiments, a planarization process (e.g., CMP, grinding, etching, etc.) is performed so that the surfaces of the redistribution structure 1112 and the dielectric layer 1158 are substantially flush. The dielectric layer 1158 allows optical signals to be coupled from above the grating couplers 1107A-1107C into the grating couplers 1107A-1107C.

[0148] The photonic packages 1101A-1101B, the semiconductor devices 250, and / or the dummy devices 1120 may be attached to the redistribution structure 1112 of the photonic interconnect structure 1151 using conductive connectors 1152. The conductive connectors 1152 may be similar to those for Fig.50 The conductive connector 948 described herein is directed to Fig.61 The conductive connectors 1126 described herein or the conductive connectors described elsewhere herein. An assembly including the photonic packages 1101A-1101C, the semiconductor device 250, and / or the dummy device 1120 can be attached to the redistribution structure 1112 by, for example, forming the conductive connectors 1152 on the redistribution structure 1112 and placing the conductive pads of the assembly in physical contact with the conductive connectors 1152. A reflow process can be performed to bond the solder material of the conductive connectors 1152 to the conductive pads of the assembly. In some cases, using the conductive connectors 1152 to attach the photonic packages 1101A-1101C, the semiconductor device 250, and / or the dummy device 1120 can reduce processing costs or complexity.

[0149] In some embodiments, an optical glue 1154 may be formed between the photonic package 1101A-1101B and the dielectric layer 1158. The optical glue 1154 allows optical signals to be transmitted between the photonic package 1101A-1101B and the grating coupler 1107A-107B. For example, in some embodiments, the optical glue 1154 may be index matched to the dielectric layer 1158 and / or the dielectric layer 130 of the photonic package 1101A-1101B. The optical glue 1154 may be deposited on the photonic interconnect structure 1151 before or after attaching the photonic package 1101A-1101B. In some embodiments, an underfill 210 may be formed between the photonic package 1101A-1101C, the semiconductor device 250 and / or the dummy device 1120, and the photonic interconnect structure 1151.

[0150] Figures 65 to 74 Intermediate steps in the formation of a photonic system 1300 are shown according to some embodiments. Figure 65 to Figure 67 1 shows the formation of a waveguide structure 1200 according to some embodiments. The photonic system 1300 may include one or more waveguide structures 1200. In some embodiments, the photonic system 1300 (see Fig.74 ) includes a plurality of photonic packages 100A-100B and a plurality of semiconductor devices 250A-250B attached to a redistribution structure 1314. The photonic packages 100A-100B may be similar to those previously described with respect to Fig.14 The described photonic package 100, and the semiconductor devices 250A-250B may be similar to those previously described herein. The redistribution structure 1314 is formed over one or more waveguide structures 1200 that are optically coupled to the photonic package 100 and allow optical communication between the photonic packages 100. In this way, efficient and high-speed optical communication between the photonic packages 100 may be achieved. Fig.74 A photonic system 1300 is shown having two photonic packages 100A- 100B and two semiconductor devices 250A- 250B, but in other embodiments, another number of photonic structures 100 or semiconductor devices 250 may be present.

[0151] First go to Fig.65 , according to some embodiments, a BOX substrate 102 is shown. The BOX substrate 102 may be similar to the Figure 1 The BOX substrate 102 is described. For example, the BOX substrate may include an oxide layer 102B formed on a substrate 102C and a silicon layer 102A formed on the oxide layer 102B. Fig.66In some embodiments, the silicon layer 102A is patterned to form silicon regions for the waveguide 1204 and the grating coupler 1207. The waveguide 1204 or the grating coupler 1207 may be similar to the previous embodiments for Figure 2 The waveguides 104 and couplers 107 described elsewhere herein may be formed in a similar manner. One or more waveguides 1204 and one or more grating couplers 1207 may be formed. Fig.67 In some embodiments, a dielectric layer 108 is formed on the front side of the BOX substrate 102. The dielectric layer 108 is formed over the waveguide 1204, the grating coupler 1207, and the oxide layer 102B. The dielectric layer 108 may be similar to that previously described for Figure 3 A dielectric layer 108 is depicted.

[0152] exist Fig.68 In some embodiments, a through hole 1304 is formed over a first carrier substrate 1302. The first carrier substrate 1302 may be, for example, a wafer, a glass carrier substrate, a ceramic carrier substrate, etc. In some embodiments, a release layer (not shown) may be formed on the first carrier substrate 1302. The through hole 1304 may be formed by a similar method to that for Fig.45 The material of the through hole 914 described above can be formed and can be formed using similar techniques. For example, a seed layer can be formed over the first carrier substrate 1302, a photoresist can be formed and patterned over the seed layer, and then a conductive material is deposited over the patterned photoresist. Other techniques are also possible. Fig.68 As shown, according to some embodiments, the waveguide structure 1200 may be attached to a first carrier substrate 1302. The dielectric layer 108 of the waveguide structure 1200 may be attached to the first carrier substrate 1302 using an adhesive layer or the like (not shown). More than one waveguide structure 1200 may be attached to the first carrier substrate 1302, and the waveguide structure 1200 may be attached before or after forming the through hole 1304.

[0153] exist Fig.69 In some embodiments, a sealant 1306 is formed over and around the through hole 1304 and the waveguide structure 1200. The sealant 1306 may be similar to that for Fig.46 or sealants 916 described elsewhere herein and may be formed using similar techniques. Fig.70 According to some embodiments, a planarization process is performed to remove the substrate 102C of the waveguide structure 1200. The planarization process may include, for example, a CMP process, a grinding process, an etching process, etc., or a combination thereof. Fig.70 As shown, the planarization process also thins the encapsulant 1306. After the planarization process is performed, the oxide layer 102B of the waveguide structure 1200 may be exposed, and the via 1304 may be exposed.

[0154] exist Fig.71 In some embodiments, a redistribution structure 1308 is formed over the through hole 1304, the sealant 1306, and the waveguide structure 1200. The redistribution structure 1308 may be similar to that for Fig.47 The redistribution structure 1308 is similar to the redistribution structure 922 described above and can be formed using similar techniques. For example, the redistribution structure 1308 can include multiple dielectric layers and metallization patterns. In other embodiments, the redistribution structure 1308 can have another number of dielectric layers and metallization patterns than shown. The metallization pattern of the redistribution structure 1308 can be physically and electrically connected to the through hole 1304.

[0155] exist Fig.72 13, according to some embodiments, the structure is removed from the first carrier substrate 1302, flipped over and attached to the second carrier substrate 1310. The second carrier substrate 1310 may be similar to the first carrier substrate 1302, and the structure may be attached using a release layer or the like (not shown in the figure). According to some embodiments, a redistribution structure 1314 and a polymer region 1312 may then be formed over the through-holes 1304, the sealant 1306 and the waveguide structure 1200.

[0156] The redistribution structure 1314 can be similar to the redistribution structure 1308 and can be formed in a similar manner. For example, the redistribution structure 1314 can include a dielectric layer and one or more metallization patterns. In other embodiments, the redistribution structure 1314 can have another number of dielectric layers and metallization patterns than shown. The metallization patterns of the redistribution structure 1314 can be physically and electrically connected to the through-hole 1304, and thus the redistribution structure 1314 can be electrically connected to the redistribution structure 1308 through the through-hole 1304.

[0157] In some embodiments, an under bump metallization (UBM) 1316 is formed on the redistribution structure 1314. The UBM 1316 may have a via portion that extends through the dielectric layer of the redistribution structure 1314 to physically and electrically couple the metallization pattern of the redistribution structure 1314. The UBM 1316 may be similar to the Fig.50 The UBM 947 described above may be formed using similar techniques.

[0158] In some embodiments, the portion of the redistribution structure 1314 located above the waveguide structure 1200 is removed, and a polymer region 1312 is formed on the waveguide structure 1200. The polymer region 1312 can be formed above the grating coupler 1207 of the waveguide structure 1200, so that the optical signal can be transmitted to the grating coupler 1207 through the polymer region 1312. The polymer region 1312 can include, for example, PMMA, BCB, etc. or a combination thereof. The material of the polymer region 1312 can be formed using a suitable technique, such as ink drop printing, etc., but other techniques are also possible. In some embodiments, the polymer material can be deposited without significantly damaging the redistribution structure 1314. In other embodiments, the polymer region 1312 can be formed before the redistribution structure 1314.

[0159] In some embodiments, the second carrier substrate 1310 may be removed Fig.72 The structure shown in FIG. 1 and the UBM 1317 and the conductive connection 1318 may be formed on the redistribution structure 1308 (see FIG. 1314 ). Fig.73 ). UBM 1317 can be similar to UBM 1316 described previously, and conductive connector 1318 can be similar to UBM 1316 described previously. Fig.64 Conductive connector 1152 is described.

[0160] exist Fig.73 In some embodiments, the interconnect substrate 1320 is attached to the redistribution structure 1308. The interconnect substrate 1320 may provide electrical wiring and structural stability for the photonic system 1300. In some embodiments, the interconnect substrate 1320 may be, for example, an interposer or a "semi-finished substrate" and may not have active devices. In some embodiments, the interconnect substrate 1320 may include a wiring layer formed on a core substrate 1321. The core substrate 1321 may include materials such as Ajinomoto accumulated film (ABF), pre-impregnated composite fiber ("prepreg") materials, epoxy resins, molding compounds, epoxy molding compounds, glass fiber reinforced resin materials, printed circuit board (PCB) materials, silica fillers, polymer materials, polyimide materials, paper, glass fibers, non-woven glass fiber fabrics, glass, ceramics, other laminates, etc., or combinations thereof. In some embodiments, the core substrate may be a double-sided copper clad laminate (CCL) substrate, etc. The interconnect substrate 1320 may have one or more wiring structures formed on each side of the core substrate 1321 and through holes extending through the core substrate 1321. The wiring structures may each include one or more wiring layers and one or more dielectric layers (not separately labeled in the figures).

[0161] Still reference Fig.73, external connectors 1322 can be formed on the wiring structure of the interconnect substrate 1320. External connectors 1322 can be, for example, contact bumps or solder balls, but any suitable connector can be used. In an embodiment where the external connector 216 is a contact bump, the external connector 1322 can include a material such as tin or other suitable materials such as silver, lead-free tin or copper. In an embodiment where the external connector 1322 is a solder bump, the external connector 1322 can be formed by first forming a solder layer using techniques such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be implemented to shape the material into the desired bump shape of the external connector 1322.

[0162] The interconnect substrate 1320 can be attached to the redistribution structure 1308 by placing the conductive regions of the interconnect substrate 1320 on the corresponding conductive connectors 1318. Once in physical contact, the conductive connectors 1318 can be bonded to the interconnect substrate 1320 using a reflow process. Fig.73 As shown, an underfill 1319 can be deposited between the interconnect substrate 1320 and the redistribution structure 1308. The underfill 1319 can also at least partially surround the conductive connector 1318. The underfill 1319 can be a material such as an encapsulant molding compound, an epoxy, an underfill, a molded underfill (MUF), a resin, etc., which can be similar to the underfills or encapsulants previously described herein.

[0163] exist Fig.74 In some embodiments, the photonic packages 100A-100B and the semiconductor devices 250A-250B are attached to the redistribution structure 1314 to form the photonic system 1300. The photonic packages 100A-100B and the semiconductor devices 250A-250B may be attached to the redistribution structure 1314 in a manner similar to that described for Fig.64 The photonic packages 100A-100B and semiconductor devices 250A-250B may be connected to the redistribution structure 1314 in a manner similar to that described above. Fig.64 The conductive connectors 1152 described elsewhere herein may be connected to the UBM 1316 formed on the redistribution structure 1314. For example, the conductive connectors may be formed on the UBM 1316, and then the photonic packages 100A-100B and the semiconductor devices 250A-250B may be placed on the conductive connectors. A reflow process may be performed to bond the solder material of the conductive connectors to the conductive pads of the photonic packages 100A-100B and the semiconductor devices 250A-250B. Other techniques are also possible.

[0164] In some embodiments, an optical glue 1354 may be formed between the photonic package 100A-100B and the polymer region 1312. The optical glue 1154 allows optical signals to be transmitted between the photonic package 100A-100B and the grating coupler 1207 of the waveguide structure 1200. In some cases, the optical glue 1354 may be similar to the one for Fig.64 The optical glue 1354 is described. The optical glue 1354 can be deposited before or after attaching the photonic packages 100A- 100B. In some embodiments, an underfill 210 can be deposited between the photonic packages 1101A- 1101C or the semiconductor device 250 and the redistribution structure 1314 .

[0165] In this manner, in some embodiments, the photonic packages 100A-100B may be optically coupled to the waveguide 1206 of the waveguide structure 1200 to facilitate optical communication between the semiconductor devices 250A-250B of the photonic system 1300. Fig.75 It is shown in Fig.75 Shows Fig.74 An enlarged view of a portion of the photonic system 1300 is shown. Fig.75 As shown, optical signals can be transmitted between the grating coupler 107 of the photonic package 100A-100B and the grating coupler 1207 of the waveguide structure 1200. Optical signals can also be transmitted within the waveguide 1206 of the waveguide structure 1200. In this way, the waveguide structure 1200 can facilitate optical communication between the photonic packages 100A-100B. In this way, the photonic system 1300 can be formed to allow efficient and high-speed optical communication between multiple semiconductor device 250A-250B components using the photonic package 100A-100B and the waveguide structure 1200.

[0166] Embodiments can achieve advantages. Embodiments described herein allow photonic systems to be formed with lower costs, larger sizes, and improved operations. For example, a photonic package formed on a substrate can replace a portion of the substrate with a dielectric layer that transmits an optical signal. In this way, an optical signal can be transmitted from a grating coupler within the photonic package to an external component, thereby allowing more efficient optical communication between the photonic package and the external component. In some cases, the dielectric layer can also improve the coupling efficiency of an edge coupler formed in the photonic package, thereby allowing more efficient optical communication between the photonic package and, for example, an edge-mounted optical fiber. In some embodiments, a plurality of photonic packages can be attached to a structure including a waveguide, and each photonic package can be optically coupled to the waveguide through a dielectric layer. A photonic system can include a photonic package and a semiconductor device, and the photonic package can be docked with the semiconductor device to facilitate optical communication between the semiconductor devices. In this way, components of a photonic system can communicate using optical signals, which can improve the efficiency and speed of the photonic system. For example, compared with transmitting electrical signals using, for example, wires, the transmitted optical signal has less signal attenuation, lower crosstalk, and less switching noise at high frequencies. Optical communications can allow for lower latency and higher bandwidth communications.

[0167] According to an embodiment, a method includes forming a first photonic package, wherein forming the first photonic package includes: patterning a silicon layer to form a first waveguide, wherein the silicon layer is located on an oxide layer, and wherein the oxide layer is located on a substrate; forming a via extending into the substrate; forming a first redistribution structure over the first waveguide and the via, wherein the first redistribution structure is electrically connected to the via; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region. In an embodiment, the first semiconductor device is bonded to the first redistribution structure using a direct bonding process. In an embodiment, forming the photonic package includes forming a photodetector in the silicon layer, wherein the photodetector is optically coupled to the first waveguide, wherein the photodetector is electrically connected to the first redistribution structure. In an embodiment, forming the photonic package also includes patterning the silicon layer to form a grating coupler, wherein the grating coupler is optically coupled to the first waveguide. In an embodiment, forming the photonic package includes patterning the silicon layer to form an edge coupler, wherein the edge coupler is optically coupled to the first waveguide. In an embodiment, a sidewall of the first dielectric region and a sidewall of the oxide layer are coplanar. In an embodiment, the method includes: removing a second portion of the substrate to form a second recess, wherein the second recess exposes the oxide layer; and filling the second recess with a first dielectric material to form a second dielectric region. In an embodiment, the method includes: attaching a first photonic package and a second photonic package to an interconnect structure, wherein the interconnect structure includes a second waveguide, wherein the second waveguide is optically coupled to a first waveguide of the first photonic package. In an embodiment, the method includes: attaching a support structure to the first semiconductor device.

[0168] According to an embodiment, a method includes: forming a first waveguide on a first side of an oxide layer, wherein the first waveguide includes a first waveguide material, wherein the oxide layer is located on a substrate; forming a first redistribution structure above the first waveguide; bonding an electronic die to the first redistribution structure; removing the substrate to expose a second side of the oxide layer; and forming a second waveguide on the second side of the oxide layer, wherein the second waveguide includes a second waveguide material different from the first waveguide material. In an embodiment, the second waveguide material is silicon nitride. In an embodiment, the second waveguide material is a polymer. In an embodiment, the method includes: forming a third waveguide above the second waveguide, wherein the third waveguide includes the second waveguide material, wherein the third waveguide is optically coupled to the second waveguide. In an embodiment, the method includes: thinning the oxide layer before forming the second waveguide on the second side of the oxide layer. In an embodiment, the method includes: depositing a molding material on a sidewall of the oxide layer, wherein the second waveguide extends on a top surface of the molding material. In an embodiment, the method includes: forming a second redistribution structure extending above the oxide layer and the second waveguide.

[0169] According to an embodiment, a package includes: a substrate including a first material; a first dielectric region adjacent to the substrate, wherein the first dielectric region includes a second material different from the first material, wherein a first sidewall of the first dielectric region physically contacts a sidewall of the substrate; a first dielectric layer extending over the substrate and over the first dielectric region, wherein a second sidewall of the first dielectric region and a sidewall of the first dielectric layer are coplanar; a waveguide located on the first dielectric layer; an edge coupler located on the first dielectric layer, wherein the edge coupler is optically coupled to the waveguide, wherein the edge coupler and the first dielectric region are vertically aligned; a redistribution structure located above the waveguide; and an electronic die bonded to the redistribution structure. In an embodiment, the package includes a photonic device located on the first dielectric layer, wherein the photonic device is optically coupled to the waveguide and electrically connected to the redistribution structure. In an embodiment, the package includes an optical fiber optically coupled to the edge coupler. In an embodiment, the package includes a via extending through the substrate, wherein the via is electrically connected to the redistribution structure.

[0170] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a package, comprising: Forming a first photonic package, wherein forming the first photonic package comprises: patterning a silicon layer to form a first waveguide, wherein the silicon layer is located on an oxide layer, and wherein the oxide layer is located on a substrate; forming a via extending into the substrate; forming a first redistribution structure over the first waveguide and the through hole, wherein the first redistribution structure is electrically connected to the through hole; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and The first groove is filled with a first dielectric material to form a first dielectric region.

2. The method according to claim 1, wherein: The first semiconductor device is bonded to the first redistribution structure using a direct bonding process.

3. The method according to claim 1, wherein: Forming the photonic package further includes forming a photodetector in the silicon layer, wherein the photodetector is optically coupled to the first waveguide, wherein the photodetector is electrically connected to the first redistribution structure.

4. The method according to claim 1, wherein: Forming the photonic package further includes patterning the silicon layer to form a grating coupler, wherein the grating coupler is optically coupled to the first waveguide.

5. The method according to claim 1, wherein: Forming the photonic package further includes patterning the silicon layer to form an edge coupler, wherein the edge coupler is optically coupled to the first waveguide.

6. The method according to claim 1, wherein: A sidewall of the first dielectric region is coplanar with a sidewall of the oxide layer.

7. The method according to claim 1, further comprising: A second portion of the substrate is removed to form a second recess, wherein the second recess exposes the oxide layer; and the second recess is filled with the first dielectric material to form a second dielectric region.

8. The method according to claim 1, further comprising: The first and second photonic packages are attached to an interconnect structure, wherein the interconnect structure includes a second waveguide, wherein the second waveguide is optically coupled to the first waveguide of the first photonic package.

9. The method according to claim 1, further comprising: A support structure is attached to the first semiconductor device.

10. A method for manufacturing a package, comprising: forming a first waveguide on a first side of an oxide layer, wherein the first waveguide comprises a first waveguide material, wherein the oxide layer is located on a substrate; forming a first redistribution structure above the first waveguide; bonding an electronic die to the first redistribution structure; removing the substrate to expose the second side of the oxide layer; and A second waveguide is formed on the second side of the oxide layer, wherein the second waveguide comprises a second waveguide material different from the first waveguide material.

11. The method according to claim 10, wherein: The second waveguide material is silicon nitride.

12. The method according to claim 10, wherein: The second waveguide material is a polymer.

13. The method according to claim 10, further comprising: A third waveguide is formed over the second waveguide, wherein the third waveguide comprises the second waveguide material, wherein the third waveguide is optically coupled to the second waveguide.

14. The method according to claim 10, further comprising: The oxide layer is thinned prior to forming the second waveguide on the second side of the oxide layer.

15. The method according to claim 10, further comprising: A molding material is deposited on sidewalls of the oxide layer, wherein the second waveguide extends on a top surface of the molding material.

16. The method according to claim 10, further comprising: A second redistribution structure is formed extending over the oxide layer and the second waveguide.

17. A package comprising: a substrate comprising a first material; a first dielectric region laterally adjacent to the substrate and having first and second laterally opposing sidewalls, wherein the first dielectric region comprises a second material different than the first material, wherein the first sidewall of the first dielectric region physically contacts a sidewall of the substrate; a first dielectric layer extending on the substrate and on the first dielectric region, wherein a second sidewall of the first dielectric region and a sidewall of the first dielectric layer are coplanar; a waveguide located on the first dielectric layer; an edge coupler disposed on the first dielectric layer, wherein the edge coupler optically couples to the waveguide, wherein the edge coupler and the first dielectric region are vertically aligned; a redistribution structure located above the waveguide; and An electronic die is bonded to the redistribution structure.

18. The package of claim 17, further comprising a photonic device located on the first dielectric layer, wherein: The photonic device is optically coupled to the waveguide and electrically connected to the redistribution structure.

19. The package of claim 17, further comprising an optical fiber optically coupled to the edge coupler.

20. The package of claim 17, further comprising a through hole extending through the substrate, wherein The through-via is electrically connected to the redistribution structure.

Images