WLCSP with a transparent substrate and method for manufacturing the same

Abstract

Embodiments of the present disclosure relate to a WLCSP with a transparent substrate and a method of manufacturing the same. The present disclosure relates to a package, such as a wafer-level chip scale package (WLCSP), having a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to contacts of the die within the package, the contacts extending from the transparent substrate to an active surface of the package. The active surface is used to mount the package within an electronic device or onto a printed circuit board (PCB) accordingly. The package includes a first insulating layer separating the die from the conductive layer and a second insulating layer over the conductive layer.

Description

Technical Field

[0001] The present disclosure relates to a package (such as a wafer-level chip scale package (WLCSP)) and a method of manufacturing the same. Background Art

[0002] Generally, semiconductor device packages (such as chip scale packages or wafer-level chip scale packages (WLCSP)) include dies, such as sensors configured to detect any quantity or quality of an external environment outside the semiconductor device package. For example, the semiconductor device package can detect light, temperature, sound, pressure, or any other quantity or quality of the external environment as needed.

[0003] As the demand increases for providing more semiconductor device packages in electronic devices to perform increasingly complex functions while reducing manufacturing costs, increasing resistance to external stress to reduce the likelihood of failure, and improving the effectiveness of semiconductor devices, there are significant challenges in balancing all of the above preferences. Examples of electronic devices include laptop computers, displays, televisions, smart phones, tablet computers, foldable electronic products, or any other electronic device. Summary of the Invention

[0004] Embodiments of the present disclosure overcome significant challenges associated with packages (such as wafer-level chip scale packages (WLCSP)), such as improving the effectiveness and robustness of light sensors within the WLCSP.

[0005] One significant challenge is to reduce the amount of light escaping from the transparent substrate when the WLCSP is configured as a light sensor. For example, depending on the configuration of the layers and components of the light sensor (such as a glass lens aligned with the light sensor), light emitted from an external light source and entering the WLCSP or package from the external environment may be able to escape from the WLCSP or package before reaching the light sensor completely.

[0006] In the present disclosure, embodiments of a WLCSP configured to detect light include a transparent substrate, a die, a light sensor in the die, a first insulating layer on the die, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and a molded compound layer on a sidewall of the transparent substrate. The molded compound layer is formed of an opaque material on the sidewall of the transparent substrate. This reduces the amount of light escaping from the sidewall of the transparent substrate and increases the amount of light reaching the light sensor of the die. Therefore, it is desirable to have an opaque molded compound layer on the sidewall of the transparent substrate to increase the light reaching the light sensor of the die.

[0007] Another significant challenge is to manufacture WLCSPs with the least amount of highly specialized machinery and the least amount of waste to reduce the cost of manufacturing WLCSPs and to increase the yield of available WLCSPs with a transparent substrate.

[0008] In an embodiment of a method of manufacturing a WLCSP, a 12-inch semiconductor wafer is converted into an 8-inch wafer. A transparent wafer is coupled to the 12-inch semiconductor wafer, which may include active and passive components. The transparent wafer and the 12-inch semiconductor wafer are diced to form a plurality of substrate assemblies, each substrate assembly including a semiconductor substrate and a transparent substrate fixedly attached to each other. The plurality of substrate assemblies are coupled to a carrier substrate (e.g., glass, silicon, etc.). Then, a molding compound is formed over the plurality of substrate assemblies to form an 8-inch wafer, and then the 8-inch wafer is further processed by highly specialized machinery to form a plurality of WLCSPs. Thus, by the above process of converting a 12-inch wafer into an 8-inch wafer, machines that utilize only 8-inch wafers can be used, and no replicas of any highly specialized machinery are required when manufacturing WLCSPs by converting a 12-inch wafer into an 8-inch wafer.

[0009] In this embodiment of the method of manufacturing a WLCSP, a preferably opaque molding compound is formed on and covers the sidewalls of the substrate assemblies on a carrier support. The molding compound fills the spaces or channels between the substrate assemblies, which are coupled to the carrier substrate. A plurality of trenches are formed in the molding compound and in the plurality of semiconductor dies. On the plurality of trenches and on the plurality of substrate assemblies, various layers of materials (e.g., insulating layers, passivation layers, transparent substrates, conductive layers, and various other material layers) are formed. After forming the various layers, the 8-inch wafer is diced to form WLCSPs. The wafer is diced at locations between the plurality of transparent substrates where the molding compound is present. By dicing the wafer at these locations, the likelihood of cracking or breaking the transparent substrates is significantly reduced since the transparent substrates are not diced multiple times. Additionally, by retaining some of the molding compound during this dicing step, a layer of molding compound on the sidewalls of the transparent substrates is formed in the intact package. Thus, this embodiment of the method of manufacturing these WLCSPs reduces the manufacturing cost as the yield of available WLCSPs increases.

[0010] Another significant challenge is to reduce the thickness of the wafer-level chip scale package (WLCSP) while maintaining its functionality. For example, as electronic devices become thinner, more flexible (such as foldable displays or devices, bendable displays or devices, etc.), and more interactive (such as touchscreens, haptic feedback, etc.), the space available to provide semiconductor dies within the electronic device is significantly reduced. It is desirable to make the WLCSP thin so that it can be incorporated into the small space available within the electronic device to provide information to the electronic device to function as needed.

[0011] In this embodiment of the method of manufacturing a WLCSP, a 12-inch semiconductor wafer including active components and passive components is coupled to a transparent wafer. The transparent wafer can be coupled to the 12-inch semiconductor wafer using a transparent die attach film, a transparent adhesive, or an alternative transparent die attach material that allows light to pass through. By coupling the 12-inch semiconductor wafer to the transparent wafer at the beginning of the process, there is no need to apply a lid or lens to the WLCSP to allow light to reach the light sensor, thus reducing the overall thickness of the complete WLCSP. Therefore, this embodiment of the method of manufacturing these WLCSPs reduces the overall thickness of the complete WLCSP. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the drawings, like reference numerals identify similar elements or acts unless the context otherwise indicates. The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale.

[0013] Figure 1A is a top view of an embodiment of a wafer-level chip scale package (WLCSP) that includes a die having a light sensor and a transparent substrate aligned with the light sensor of the die;

[0014] Figure 1B is along Figure 1A is a cross-sectional view of an embodiment of a WLCSP taken along line 1B-1B in

[0015] Figure 1C is Figure 1A and 1B is a bottom plan view of an embodiment of a WLCSP in

[0016] Figure 2 is along a line similar to line 1B-1B in Figure 1A is a cross-sectional view of an alternative embodiment of a WLCSP taken along a line similar to line 1B-1B in

[0017] Figure 3 is along a line similar to line 1B-1B in Figure 1A is a cross-sectional view of an alternative embodiment of a WLCSP taken along a line similar to line 1B-1B in

[0018] Figure 4Ais a flowchart of a method of manufacturing a WLCSP (such as the WLCSP shown in Figures 1A - 1C ) in accordance with one or more embodiments; and

[0019] Figures 4B - 4Q is a cross-sectional view of a method of manufacturing a WLCSP (such as the WLCSP shown in Figure 4A ) as indicated in the flowchart of Figures 1A - 1C and in accordance with one or more embodiments. DETAILED DESCRIPTION

[0020] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments of the present disclosure. However, one skilled in the art will understand that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electrical components and semiconductor fabrication techniques have not been described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0021] Unless the context otherwise requires, throughout the following specification and claims, the word "comprise" and its variations (such as "comprises" and "comprising") shall be construed in an open, inclusive sense, i.e., as "including, but not limited to."

[0022] The use of ordinal numbers such as first, second, and third does not necessarily imply a sense of ordered sequence, but may only distinguish multiple instances of an action or structure.

[0023] Throughout this specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0024] As described below, the terms "left," "right," "top," and "bottom" are used solely for the purpose of discussion of the orientation of components in the context of the figures in the present disclosure. These terms are not limited to the possible positions explicitly disclosed, implicitly disclosed, or inherently disclosed in the present disclosure.

[0025] The term "substantially" is used to clarify that there may be minor differences when manufacturing WLCSPs in the real world, as it is impossible to make anything exactly equal or identical. The term is not restrictive as it is only used to clarify the real-world manufacturing manner of WLCSPs. In other words, substantially means that there may be some minor variations in actual practice as it is impossible to make anything perfect, but rather to keep it within an acceptable tolerance.

[0026] As used in this specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" include plural referents. It should also be noted that unless the context clearly indicates otherwise, the term "or" is generally employed in its inclusive sense of "and / or".

[0027] The present disclosure relates to various embodiments of semiconductor device packages (such as wafer-level chip scale packages (WLCSPs)), each of which includes a semiconductor die and a transparent substrate. The transparent substrate is aligned with a sensor of the die and is configured to expose the sensor of the die to light from an external light source. In some other embodiments, the die may include an LED or a light source that is aligned with the transparent substrate to emit light through the transparent substrate.

[0028] In some embodiments, the transparent substrate includes a central portion having a first height and a peripheral portion surrounding the central portion having a second height. The first height of the central portion is greater than the second height of the peripheral portion surrounding the central portion. The peripheral portion has sidewalls covered by a molded compound layer. The molded compound layer surrounds the transparent substrate and forms a boundary around the transparent substrate. The molded compound is an opaque material that is configured to increase the amount of light reaching the sensor of the die by reducing the amount of light escaping from the sidewalls of the transparent substrate when light passes through the transparent substrate to reach the sensor. During the dicing process in the manufacturing process, the molded compound also protects the transparent substrate of the package as the molded compound is cut instead of the transparent substrate. The die is located on the central portion of the transparent substrate, and the sensor is aligned with the central portion of the transparent substrate.

[0029] Although various embodiments have been shown and described with respect to WLCSPs, it will be readily understood that the embodiments of the present disclosure are not limited thereto. In various embodiments, the structures, devices, methods, etc. described herein may be implemented or otherwise utilized in any suitable type or form of semiconductor package or WLCSP, and any suitable semiconductor packaging technology may be utilized as needed.

[0030] Figure 1Ais a top view of an embodiment of an encapsulation body 100 (such as a WLCSP). The encapsulation body 100 includes an insulating layer 101 having a first surface 102 and a plurality of conductive contacts 104 exposed through openings 106 in the first surface 102. The insulating layer may be a passivation layer, a molding compound layer, an epoxy resin layer, or some other insulating material. The first surface 102 may be referred to as the active or mounting surface of the encapsulation body 100 because the plurality of conductive contacts 104 are configured to be mounted to a printed circuit board (PCB) or mounted within an electronic device through a conductive material. The contacts 104 are coupled to active and passive components within the encapsulation body 100, and these active and passive components will be discussed in more detail relative to Figure 1B below.

[0031] Figure 1B is a cross-sectional side view of the encapsulation body 100 taken along line 1B-1B in Figure 1A , and Figure 1C is Figure 1A and 1B a bottom plan view of the encapsulation body 100 in. Line 1B-1B passes through three of the contacts 104 of the encapsulation body 100.

[0032] The encapsulation body 100 includes a second surface 108 opposite the first surface 102. The second surface 108 may be referred to as a passive surface because the second surface 108 does not include any active components or passive conductive components. Instead, the second surface 108 includes the surface of a transparent substrate 110 and the surface of a molding compound layer 112. The transparent substrate 110 may be a glass material, an acrylic material, a plastic material, or any other transparent material or a combination of transparent materials that allow light to pass through and have a high transmittance. Alternatively, the transparent substrate 110 may be a stacked multi-layer material to increase the transmittance of light through the multi-layers. The surface of the transparent substrate 110 and the surface of the molding compound layer 112 are substantially flush or coplanar.

[0033] The surface of the transparent substrate 110 (which is part of the second surface 108 of the encapsulation body 100) is uncovered. The molding compound layer 112 is on the sidewall 114 of the transparent substrate 110. The sidewall 114 of the transparent substrate 110 has a first height h 1 . The molding compound layer 112 has sidewalls 116 that have a first height h 1。The molded compound layer 112 is preferably an opaque material, such as a molded compound including a carbon black pigment, a plastic molded compound made of an opaque material, or some other opaque material or a combination of opaque materials that do not allow light to pass through. Using an opaque material enables the molded compound layer 112 to prevent light from escaping through the sidewalls 114 of the transparent substrate 110 after the light has entered through the uncovered surface of the transparent substrate 110, which will be discussed in more detail later in this disclosure.

[0034] The transparent substrate 110 includes a central portion 120 having a second height h 2 , which is greater than the first height h of the sidewalls 114 of the transparent substrate 110 and the sidewalls 116 of the molded compound layer 112 1 。The transparent substrate 110 further includes a peripheral portion 122 that surrounds the central portion 120 and forms a boundary or perimeter around the central portion 120. The peripheral portion 122 has the first height h of the sidewalls 114 of the transparent substrate 110 1 。

[0035] The transparent substrate 110 includes a connecting portion 124 having an inclined surface 126 that couples the peripheral portion 122 to the central portion 120. The central portion 120, the peripheral portion 122, and the connecting portion 124 are made of a continuous material of the transparent substrate 110. The inclination of the inclined surface 126 is defined by the height difference between the first height h of the peripheral portion 122 1 and the second height h of the central portion 2 。In some other embodiments, the first height h 1 may be greater than the second height h 2 , or the first height h 1 may be substantially the same as the second height h 2 。

[0036] The semiconductor die 128 is coupled to the central portion 120 of the transparent substrate 110. The die is coupled to the central portion 120 of the transparent substrate 110 by an adhesive (not shown). The adhesive can be glue, a die attach film (DAF), or some other adhesive material or a combination of adhesive materials. The semiconductor die 128 faces the second surface 108 of the package 100. The semiconductor die 128 includes active components and passive components to perform a desired function. For example, the semiconductor die 128 can include components configured to detect light, pressure, sound, temperature, humidity, or any other quality or quantity of the external environment.

[0037] The semiconductor die 128 includes an active surface 130 and a passive surface 132 opposite the active surface 130. The active surface 130 is on the central portion 120 of the transparent substrate 110 and faces the transparent substrate 110. The passive surface 132 is opposite the active surface 130 and faces away from the transparent substrate 110 and the active surface 130 of the semiconductor die 128. The passive surface 132 does not include any active or passive components, while the active surface 130 includes active components and conductive components. The inclined surface 133 of the semiconductor die 128 extends between the active surface 130 and the passive surface 132 of the semiconductor die 128.

[0038] The semiconductor die 128 includes a sensor 134 at the active surface 130 of the semiconductor die 128. The sensor 134 can be a light sensor as needed, such as an image sensor, a single photon avalanche diode (SPAD), or some other type of light sensor or a combination of light sensors. The sensor 134 can be configured to detect infrared light, ultraviolet light, visible light, or light of any wavelength as needed. The light sensor 134 can be a sensor array or a plurality of sensors positioned on the active surface 130 of the semiconductor die 128. In some other alternative embodiments, the sensor 134 can be another type of sensor, such as a sensor configured to detect pressure, sound, temperature, humidity, or any other quality or quantity of the external environment. The light sensor 134 can be positioned at the center of the active surface 130 of the semiconductor die 128.

[0039] The electrical connector 136 has a first end coupled to the light sensor 134 and a second end coupled to a contact 138 on the surface of the semiconductor die 128. The electrical connector 136 can be configured to communicate a signal from the light sensor 134 to the contact 138 or from the contact 138 to the light sensor 134 as needed. The electrical connector 136 can include a conductive material extending through or on the surface of the semiconductor die 128, such as copper or doped semiconductor. The electrical connector 136 can also include various circuit devices, such as transistors, diodes, or other conductive elements.

[0040] The contact 138 is a conductive material as needed, such as a copper material, a gold material, an aluminum material, an alloy material, or any other conductive material or a combination of conductive materials. The contact 138 extends outward from the edge of the semiconductor die 128 and extends away from the light sensor 134 of the semiconductor die 128. The contact 138 extends across the central portion 120 of the transparent substrate 110 to the edge of the transparent substrate 110, where the central portion 120 meets the connecting portion 124.

[0041] Another insulating layer 140 is on the passive surface 132 and the inclined surface 133 of the die. The insulating layer 140 is also on the contact 138. The insulating layer 140 can be any electrically insulating material as needed, such as an epoxy material, a plastic material, a passivation material, a re-passivation material, a dielectric material, or some other insulating material or combination of insulating materials. The insulating layer 140 is configured to separate the semiconductor die 128 from the conductive layer 142 to prevent the conductive layer 142 from contacting the semiconductor die 128.

[0042] The conductive layer 142 is on the insulating layer 140, the contact 138 of the semiconductor die 128, and the peripheral portion 122 and the connection portion 124 of the transparent substrate 110. The conductive layer 142 contacts the sidewall of the contact 138 of the semiconductor die 128. The conductive layer 142 allows signals to communicate from an external device to the contact 138 of the die and from the contact 138 of the die to the external device. For example, the external device can be a controller, an electronic device, a memory, or some other component of an electronic device configured to control or utilize the package 100 to perform a desired function. The conductive layer 142 includes a first end 144 on the peripheral portion 122 of the transparent substrate 110. In this embodiment, the first end 144 is positioned between the sidewall 114 of the transparent substrate 110 and the connection portion 124 of the transparent substrate 110. However, in other alternative embodiments, the first end 144 can be positioned on the connection portion 124 or can extend to the sidewall 114 of the transparent substrate 110. The conductive layer 142 can be referred to as an electrical connection, a redistribution layer (RDL), or some other conductive connection or combination of conductive connections as needed. In an alternative embodiment, the conductive layer can be a conductive via.

[0043] The insulating layer 101 is disposed on the conductive layer 142, the molding compound layer 112, the insulating layer 140, and the peripheral portion 122 and the connecting portion 124 of the transparent substrate 110. The insulating layer 101 is configured to protect the conductive layer 142 from external conductive materials, thereby avoiding short circuits or undesired electrical connections between the conductive layer 142 and external electrical components on the PCB or within the electronic device. The insulating layer 101 covers the first end 144 of the conductive layer 142. The insulating layer 101 includes sidewalls 148. The sidewalls 148 of the insulating layer 101 are substantially flush or coplanar with the sidewalls 116 of the molding compound layer 112. The insulating layer 101 includes an opening 106 that exposes the contact 104. The contact 104 is the portion of the conductive layer 142 exposed by the opening 106 in the insulating layer 101. The opening 106 is shown as having a square shape; however, in alternative embodiments, the opening may have a circular shape, a rectangular shape, or any other shape as needed. The insulating layer 101 may be any insulating material, such as an epoxy resin material, a plastic material, a passivation material, a re-passivation material, a dielectric material, or some other insulating material or a combination of insulating materials. The insulating layer 101 may be referred to as a protective layer.

[0044] In this embodiment, the dimensions of the package 100 are as follows. The transparent substrate 110 has a thickness of about 100 - 500 microns, the die has a thickness of 50 - 200 microns, the conductive layer 142 has a thickness of 3 - 5 microns, and the insulating layer 140 has a thickness of 10 - 30 microns. Although these are the thicknesses of the various components of the package 100 in this embodiment, for clarity purposes, these components are not Figure 1B drawn to scale in. Although in this embodiment, the above dimensions may be as listed, in some other alternative embodiments of the WLCSP, the WLCSP may have dimensions that are completely different from those set forth above.

[0045] Figure 1C is as Figure 1A and 1B a top plan view of an embodiment of the package 100 as seen in. As previously described, the package 100 includes a transparent substrate 110. The transparent substrate 110 includes a central portion 120, a peripheral portion 122, and a connecting portion 124. The connecting portion 124 extends between the central portion 120 and the peripheral portion 122 and couples the central portion 120 to the peripheral portion 122. Additionally, as previously discussed with respect to Figure 1B the peripheral portion 122 surrounds both the central portion 120 and the connecting portion 124 and forms a perimeter or boundary around both the central portion 120 and the connecting portion 124. Similarly, the connecting portion 124 surrounds the central portion 120 and forms a perimeter or boundary around the central portion 120. In Figure 1CThe relationship of these respective parts of the transparent substrate 110 can be clearly seen. Additionally, as previously discussed with respect to Figure 1B the semiconductor die 128 is located on the central portion 120 of the transparent substrate 110, and the sensor 134 is aligned with the central portion 120 of the transparent substrate 110, which can be clearly seen in Figure 1C .

[0046] Figure 2 FIG. Figure 1A is a cross-sectional view of an alternative embodiment of the package 200a. The package 200a can be a WLCSP or a semiconductor package. This cross-sectional view of the package 200a is taken along a line similar to 1B-1B in Figure 1A The package 200a has features similar to the embodiments in the package 100 illustrated in Figure 1B , and these features are denoted by the same reference numerals as in Figure 1B .

[0047] However, in this alternative embodiment, the package 200a includes a cavity 202. The cavity 202 is aligned with the central portion 120 of the transparent substrate 110. The cavity 202 is adjacent to and aligned with the optical sensor 134 of the semiconductor die 128. The cavity 202 spaces the central portion 120 of the transparent substrate 110 from the optical sensor 134. The cavity is formed in a material layer 208a between the semiconductor die 128 and the transparent substrate 110. In this alternative embodiment, the material layer 208a couples the semiconductor die 128 to the transparent substrate 110. The material layer 208a can be an insulating material, a non-conductive material, an adhesive material, or any combination of insulating or insulating materials as needed. Alternatively, in some other embodiments of the package, the cavity 202 can be formed by a multi-layer material instead of the material layer 208a. In other alternative embodiments, the cavity 202 can be within the central portion 120 of the transparent substrate 110, or extend into the central portion 120 of the transparent substrate 110. If the cavity 202 is within the central portion 120 of the transparent substrate 110, then the second height h 2 can be less than the first height h 1 , or the second height h 2 can be substantially the same as the first height h 1 . For example, if the cavity 202 extends far enough within the transparent substrate 110 toward the surface 108, the central portion 120 of the transparent substrate 110 will have a second height h 2 , which is less than the first height h 1 of the peripheral portion 122.

[0048] The thickness of the cavity 202 in the package 200a is substantially equal to the thickness of the material layer 208a. In some other embodiments, the cavity may have a thickness greater than or less than the thickness of the material layer 208a. In other words, the cavity 202 can have any size as needed.

[0049] In some embodiments of the package, the photosensor 134 may extend into the cavity 202. The cavity may be wide enough and deep enough to fully accommodate the sensor within the cavity or to partially accommodate the sensor within the cavity.

[0050] Figure 3 is a cross-sectional view of an alternative embodiment of the package 200b, which is similar to the Figure 2 package 200a in Figure 1B and Figure 2 The package 200b has features similar to those in the packages 100 and 200a in Figure 1B Figs. 1 and 2, and these features are denoted by the same reference numerals as in

[0051] However, in this alternative embodiment, the package 200b includes a multi-layer material 208b between the semiconductor die 128 and the transparent substrate 110. The multi-layer material 208b can be a multi-layer insulating material, a non-conductive material, a multi-layer adhesive material, or a multi-layer of any insulating material as needed. In this alternative embodiment, the multi-layer material 208b couples the semiconductor die to the transparent substrate 110. Different from Figure 2 the package 200a in

[0052] the package 200b includes a portion of the multi-layer material 208b between the transparent substrate 110 and the conductive layer 142, and the end 209 of the multi-layer material 208b has a surface covered by the molding compound layer 112. A portion of the multi-layer material 208b separates the conductive layer 142 from the transparent substrate 110. Different from the package 200a, the package 200b has a transparent substrate 110. However, the transparent substrate 110 has a height that is substantially the same as the length of the transparent substrate 100 extending between the sidewalls 114 of the transparent substrate 110.

[0053] The thickness of the cavity 202 in the package 200b is substantially equal to the thickness of the multi-layer material 208b. In some other embodiments, the cavity may have a thickness greater than or less than the thickness of the multi-layer material 208b. In other words, the cavity 202 can have any size as needed.

[0054] The package 200b includes an insulating layer 204 formed on the insulating layer 101 and below the under bump metallurgy (UBM) 206 in the insulating layers 101, 204. The insulating layer 204 can be an epoxy material, a plastic material, a passivation material, a re-passivation material, or some other insulating material or combination of insulating materials. As Figure 2 shown, each of the UBMs 206 includes a recess extending towards the semiconductor die 128 to enable better contact with solder bumps (discussed below) used to electrically connect the package 200a to a PCB or other device.

[0055] In some other alternative embodiments of the WLCSP, the UBM 206 can have different shapes or configurations. For example, the UBM 206 can extend outward from the insulating layer 204, or the UBM 206 can be on the insulating layer 204. Thus, the UBM 206 can have any shape or configuration as needed.

[0056] Figure 4A is a flowchart of an embodiment of a method 300 for manufacturing the package 100 disclosed in the present disclosure and alternative embodiments of the WLCSP. These steps will be discussed in detail with respect to Figures 4B - 4Q the structure illustrated in. This embodiment of the manufacturing method 300 relates to manufacturing Figures 1A - 1C the package 100 shown in. However, other alternative embodiments can be manufactured by adding additional steps to the method 300, such as Figure 2 and Figure 3 the packages 200a, 200b in.

[0057] The method 300 includes a wafer preparation process 301 that uses steps 302, 304, 306 to process and divide a 12-inch wafer into individual dies, and a reconstruction and molding process 303 that uses steps 308, 310, 312 to process the divided individual dies to form an 8-inch wafer. The remaining steps 314, 316, 318, 320, 322, 324, 326, 328 of the method 300 are other process steps for forming the package 100.

[0058] Step 302 of the wafer preparation process 301 of the method 300 is a wafer bonding step 302, in which the semiconductor wafer 330 is coupled to the transparent wafer 332, as Figure 4Bas shown. Prior to the wafer bonding step 302, the semiconductor wafer 330 will have been processed to form an electronic circuit device including the sensor 134. The active surface 333 of the semiconductor wafer 330 is coupled to the transparent wafer 332, which can be seen in Figure 4C as seen. Figure 4C is a cross-sectional view taken along the line 3C-3C in Figure 4A . The semiconductor wafer 330 can be a 12-inch wafer or have other diameters. The transparent wafer 332 can be any of the transparent materials discussed above for the transparent substrate 110 and will be formed by the transparent wafer 332 as discussed below. The semiconductor wafer 330 can be bonded to the transparent wafer 332 using any of the bonding materials discussed above with respect to coupling the semiconductor die 128 to the transparent substrate 110.

[0059] Step 304 of the wafer preparation process 301 is an optional back grinding step 304, in which the passive surface 338 of the semiconductor wafer 330 facing away from the transparent wafer 332 and the active surface 333 of the semiconductor wafer 330 are ground to reduce the thickness of the semiconductor wafer 330. In step 306, as shown in Figure 4C and Figure 4D , the semiconductor wafer 330 and the transparent wafer 332 are diced into substrate assemblies 339. Figure 4C illustrates a cutting tool 334 cutting along a dashed line 336, which indicates the position where the semiconductor wafer 330 and the transparent wafer 332 are diced by the cutting tool 334. Figure 4D illustrates a substrate assembly 339 that includes the transparent substrate 110 and the semiconductor die 128 shown in Figure 1B . The cutting tool 334 can be a laser, a saw, or some other mechanical cutting device or cutting technique as needed.

[0060] After step 306 in which the semiconductor wafer and the transparent wafer 332 are diced into substrate assemblies 339, in step 308, a plurality of transparent substrates 110 are coupled to a carrier support 340, which can be seen in Figure 4E as seen. Figures 4F to 4H is a cross-sectional view taken along the line 3F-3F in Figure 4E .

[0061] In one embodiment, the carrier support 340 is an 8-inch carrier support, but other sizes may be employed. The carrier support 340 may be a silicon (e.g., glass) carrier substrate, a support wafer, a dummy wafer, or some other support material or carrier support configured to support a plurality of substrate components 339 during further processing. The transparent substrate 110 is coupled to the carrier support 340 by a temporary bonding material (not shown). The temporary bonding material may be a thermally decomposable bonding material, a water decomposable bonding material, a photosensitive decomposable material, or some other bonding material that can be decomposed or removed without leaving a residue on the transparent substrate 110. For simplicity of discussion, the temporary adhesive will be a temporarily thermally decomposable bonding material.

[0062] A plurality of substrate components 339 may be positioned on the carrier support 340 by a pick and place machine. The substrate components 339 are spaced apart from each other by channels 342 having a width of d 1 as shown in Figure 4F shown.

[0063] After the step 308 in which the plurality of substrate components 339 are coupled to the carrier support 340, in step 310 a molding compound 343 is formed on the plurality of substrate components 339 and the carrier support 340, as can be seen in Figure 4G shown. The channels 342 between the plurality of dies 128 and the plurality of transparent substrates 110 are filled with the molding compound 343. The molding compound 343 is an opaque material. For example, the opaque material of the molding compound 343 may be a molding compound doped with carbon black pigment, a plastic molding compound doped with carbon black pigment, or may be some other opaque material or combination of opaque materials. The opaque material of the molding compound 343 does not allow light to pass through. Once the molding compound 343 is placed in the channels 342, on the plurality of dies 128, on the plurality of transparent substrates 110, and on the carrier support 340, the molding compound 343 is allowed to cure and harden.

[0064] After the molding compound 343 is formed, in step 312 the carrier support 340 is removed or separated from the molding compound 343 and the transparent substrate 110, as can be seen in Figure 4H shown. The carrier support 340 is removed by exposing the carrier support 340 and the temporarily thermally decomposable bonding material that couples the carrier support to the transparent substrate 110 so as to heat to decompose the temporarily thermally decomposable bonding material. Removing the carrier support 340 leaves a wafer 346 that includes the substrate components 339 and the molding compound 343, as can be seen in Figure 4Iseen in the upward plan view. In some other embodiments, the carrier support 340 itself may be a thermally decomposable material, a photo-decomposable material, a laser-decomposable material, a water-decomposable material, or some other type of decomposable material that is decomposed as needed to be removed.

[0065] After the step 312 of removing the carrier support 340 to form the wafer 346, in step 314, the wafer 346 is polished to remove the molding compound 343 covering the semiconductor die 128. The polishing of the wafer 346 may also remove a portion from the passive surface 132 of the die 128, thereby reducing the thickness of the die 128. However, in some alternative embodiments, the die 128 may not be polished. Polishing the molding compound 343 exposes the top of the die 128 while leaving the molding compound 343 in the channels 342 between the substrate assemblies 339.

[0066] This polishing step 314 may be referred to as a planarization step because the molding compound 343 and the passive surface 132 of the die 128 are made to be substantially flush and coplanar with each other, which can be seen in Figure 4J This polishing step 314 can be accomplished by a chemical mechanical polishing tool, a mechanical polishing tool, or some other polishing tool or planarization tool or technique to form a substantially flat surface of the wafer.

[0067] After the step 314 of polishing or planarizing the wafer 346, in step 316, a plurality of trenches 350 extending into the wafer 346 are formed, which can be seen in Figure 4K The plurality of trenches 350 are formed by removing portions of the molding compound 343 between the die 128 and portions of the die 128.

[0068] The plurality of trenches 350 can be formed by dry etching, wet etching, sawing, cutting, laser, or some other removal technique. For example, a lithography process can be used to define portions of the die 128 and the molding compound 343, and then a dry etching technique (such as plasma etching) is accomplished to remove portions of the die 128 and the molding compound 343.

[0069] The dry etching process forms the inclined surfaces 133 of each semiconductor die 128 and exposes the surfaces 352 of the contacts 138. These surfaces 352 of the contacts 138 face away from the transparent substrate 110. The first ends 144 of the contacts 138 are held covered by the portions 354 of the die 128 remaining after the trenches 350 are formed. Each of these portions 354 of each semiconductor die 128 extends from each first end 144 of each contact 138 to the sidewall 114 of the transparent substrate 110. The molding compound 343 is held positioned between the first ends 144 of the contacts 138 and the portions 354 of the adjacent semiconductor dies 128 in the 8-inch wafer 346. The molding compound 343 extends between the sidewalls 114 of the transparent substrate 110.

[0070] Each trench 350 extends a first distance d from the passive surface of the semiconductor die 128 to the molding compound 343 or the surface 352 of each contact 138 exposed by the trench 350 2 。

[0071] After the trenches 350 are formed, in step 318, the insulating layer 140 is formed, as can be seen in Figure 4L The insulating layer 140 is formed on the passive surface 132 and the inclined surface 133 of the die 128, on the surface 352 of the contacts 138, and on the molding compound 343 between the transparent substrate 110. The insulating layer 140 partially fills the plurality of trenches 350. The insulating layer 140 can be formed using chemical vapor deposition, physical vapor deposition, sputtering, or some other deposition technique or combination of deposition techniques.

[0072] After the insulating layer 140 is formed, in step 320, the plurality of trenches 350 are further extended into the wafer 346, as can be seen in Figure 4M Step 320 can use a sawing tool or other device to remove portions of the transparent substrate 110, portions of the molding compound 343, portions of the contacts 138, die portions 354, and portions of the insulating layer 140. Step 320 increases the distance d that the plurality of trenches 350 extend into the semiconductor die 128 2 。In some alternative embodiments, the distance d 2 can remain the same by not removing portions of the transparent substrate 110 and die portions 354.

[0073] Extending the trenches in step 320 forms the inclined surfaces 358 of each contact 138 of each semiconductor die 128 and the inclined surface 126 of the connecting portion 124 of the transparent substrate 110. The inclined surfaces 126, 358 can be substantially flush or coplanar with each other.

[0074] After step 320, step 322 directly forms a conductive layer 142 on the insulating layer 140, the inclined surface 358 of the contact 138, the transparent substrate 110, and the molding compound 343. The conductive layer 142 can be deposited by using a vapor deposition technique, an electrochemical deposition technique, a sputtering technique, or some other deposition technique or a combination of deposition techniques.

[0075] After the conductive layer 142 has been deposited, the conductive layer 142 is patterned to form an opening 362 through the conductive layer 142 on the insulating layer 140 and an opening 364 through the conductive layer 142 within the plurality of trenches 350, as Figure 4N shown. The conductive layer 142 can be patterned by using a sawing technique, a cutting technique, a dry etching technique, a wet etching technique, or some other patterning technique or a combination of patterning techniques to remove portions of the conductive layer 142. The openings 362, 364 separate portions of the conductive layer 142. The opening 362 in the conductive layer 142 exposes a portion of the insulating layer 140, and the opening 364 within the plurality of trenches 350 exposes the molding compound 343. After step 322 in which the conductive layer 142 is formed, in step 324, an insulating layer 101 is formed within the plurality of trenches 350, which can be seen Figure 4O in. The insulating layer 101 is formed on the patterned conductive layer 142, in the openings 362, 364 in the conductive layer 142, on the transparent substrate 110, on the insulating layer 140, and on the molding compound 343. The insulating layer 101 can be deposited by using a vapor deposition technique, a chemical deposition technique, a sputtering deposition technique, or some other deposition technique or a combination of deposition techniques. As discussed above, the insulating layer 101 can be patterned to form an opening 106 and expose the plurality of conductive contacts 104.

[0076] After forming the insulating layer 101, in step 326, solder balls 366 are formed in the opening 106 and on the plurality of conductive contacts 104, which can be seen Figure 4P in. The solder balls 366 can be formed by a reflow technique, by an injection technique, or by some other solder ball forming technique or a combination of solder ball forming techniques. The solder balls 366 are configured to allow the complete package 100 to be mounted onto a PCB or an electronic device. In some other embodiments, the solder balls 366 can be formed on the package 100 after dicing.

[0077] After forming the solder balls 366, in step 328, the wafer 346 after the above processing steps 314 - 326 is diced into individual and complete packages 100, which can be seen Figure 4P and 4QThis can be seen in. The dividing step 328 uses a cutting tool 370 to cut through the stacked layers of the material at the position indicated by the dashed line 368. The cutting tool 370 can be a saw, a laser, or some other cutting or dividing tool as needed. The molding compound 343 between the transparent substrates 110 acts as a buffer by protecting the transparent substrates 110 from the cutting tool 370 during the division.

[0078] The above method can be modified to form Figure 2 the package 200a in by depositing a material layer 208a on a 12-inch transparent wafer 332 and coupling a 12-inch wafer 330 to the 12-inch transparent substrate 332. The material layer 208a allows the cavity 202 to be formed between the die 128 and the transparent substrate 110 of the package 200a. The material layer 208a can be patterned to form the cavity 202.

[0079] The above method can be modified to form Figure 3 the package 200b in by depositing a multi-layer material 208b on a 12-inch transparent wafer 332 and coupling a 12-inch wafer 330 to the multiple layers 20b on the 12-inch transparent wafer 332. The multi-layer material 208b allows the cavity 202 to be formed between the die 128 and the transparent substrate 110 of the package 200b. When forming the package 200b, the multi-layer material 208b can be patterned to form the cavity 202, or can be deposited in selected areas to form the cavity 202.

[0080] Additionally, the above method can be modified to form the package 200b by depositing an insulating layer 204 on the insulating layer 101, in the opening 106, and on the contact 104 after step 324 and before step 326. After the insulating layer 204 is deposited, the insulating layer 204 is patterned to re-expose the contact 104. The insulating layer 204 can be patterned using etching techniques, saw techniques, laser techniques, or some other patterning techniques or a combination of patterning techniques. After the insulating layer 204 is patterned, a second conductive layer is deposited on the insulating layer 204 and covers the contact 104. After the second conductive layer is deposited, the second conductive layer is patterned to form the UBM 206.

[0081] Compared with existing technology methods, the methods described herein can provide many advantages. For example, directly coupling the semiconductor die 128 to the transparent substrate 110 makes the packages 100, 200 thinner than existing technology packages that utilize lid and lens arrangements. Many existing technology devices use such lids to cover and protect the die and sensors. This increases the overall thickness and lateral size of the package. Thus, by directly coupling the semiconductor die 128 to the transparent substrate 110, the overall size of the packages 100, 200 can be made smaller than conventional packages.

[0082] By using the remaining substrate components 339, method 300 can produce less waste than conventional methods, where the remaining substrate components are formed by dividing the 12-inch wafer 330 and the 12-inch transparent wafer 332 that were not used to form the first 8-inch wafer 346 when forming an additional second 8-inch wafer.

[0083] When the wafer 346 is divided into packages 100 in step 328, method 300 can increase the yield of usable packages 100 because the molding compound 343 protects the transparent substrate 110. The molding compound acting as a buffer reduces the likelihood of breakage or cracking in the transparent substrate 110 because the transparent substrate 110 is not directly cut by the cutting tool 370 during the dividing step 328. This reduction in the likelihood of breakage or cracking on the transparent substrate increases the yield of the number of usable packages 100.

[0084] In addition, method 300 can also reduce the overall cost of manufacturing the packages 100 by not requiring new highly specialized machines. Method 300 can use existing highly specialized machines that are only capable of using 8-inch wafers because the substrate components 339 can be formed from 12-inch wafers and placed on an 8-inch carrier 340. In some other embodiments of the method, a 12-inch wafer can be converted into another 12-inch wafer, an 8-inch wafer can be converted into a 12-inch wafer, an 8-inch wafer can be converted into another 8-inch wafer, or wafers of any size can be converted into another size as needed.

[0085] The various embodiments described above can be combined to provide other embodiments. Aspects of these embodiments can be modified if necessary by incorporating various patented, applications, and published concepts to provide yet further embodiments. These and other changes can be made to the embodiments in light of the detailed description above. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in this specification and the claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims. Thus, the claims are not limited by the present disclosure.

Claims

1. A semiconductor device, comprising: a transparent substrate including a first surface, a second surface, and sidewalls transverse to the first surface and the second surface, the second surface being opposite the first surface in a direction from the first surface toward the second surface; a molding compound on the sidewalls of the transparent substrate; a die on the second surface of the transparent substrate, the die including: a sensor aligned with the transparent substrate; contacts extending outward from an edge of the die in a transverse direction transverse to the direction and extending away from the sensor; and an electrical connector having a first end coupled to the sensor and a second end coupled to the contacts; a first insulating layer on the die and on the contacts of the die; and a conductive layer on the first insulating layer, the conductive layer including: a first end portion on the first insulating layer; and a transverse portion on the first insulating layer, the transverse portion being transverse to the first end portion, transverse to the contacts, and coupled to the contacts.

2. The semiconductor device according to claim 1, further comprising: a second insulating layer on the first insulating layer, the conductive layer, and the molding compound; an opening in the second insulating layer, the opening exposing a portion of the conductive layer; and wherein the conductive layer further includes a second end portion transverse to the transverse portion, the second end portion being closer to the second surface of the transparent substrate portion than the contacts of the die.

3. The semiconductor device according to claim 2, wherein the molding compound has a surface substantially flush with the surface of the second insulating layer.

4. The semiconductor device according to claim 1, further comprising: a cavity between the die and the transparent substrate, the cavity adjacent to the sensor of the die; and a non-conductive layer on the transparent substrate and between the contacts of the die and the transparent substrate.

5. The semiconductor device according to claim 4, wherein the surface of the end portion of the non-conductive layer is substantially flush with the surface of the molding compound.

6. The semiconductor device according to claim 1, wherein the molding compound is an opaque material.

7. The semiconductor device according to claim 1, wherein: a central portion of the transparent substrate has a first height extending in the direction; the sidewalls have a second height, the second height being less than the first height of the central portion of the transparent substrate, the second height extending in the direction; and the die is on the central portion of the transparent substrate.

8. A semiconductor device, comprising: a transparent substrate including: a center; a first surface; a second surface opposite the first surface; a central portion at the center, the central portion having a first height extending in a direction from the first surface toward the second surface; and An outer portion surrounding the central portion, the outer portion including sidewalls transverse to the first surface and the second surface, the sidewalls having a second height that extends in the direction from the first surface of the transparent substrate toward the second surface, the second height being less than the first height; A molding compound on the sidewalls of the transparent substrate, the molding compound having the second height; and A semiconductor die on the transparent substrate, the semiconductor die including conductive contacts on the transparent substrate, the conductive contacts extending outward from the edge of the semiconductor die.

9. The semiconductor device according to claim 8, wherein the transparent substrate further comprises: A connecting portion surrounding the central portion, the connecting portion connecting the central portion to the outer portion and having a third height in the direction, the third height varying between the first height and the second height.

10. The semiconductor device according to claim 9, wherein the first surface of the transparent substrate further comprises: The surface of the central portion; the surface of the outer portion surrounding the surface of the central portion; And the surface of the connecting portion connecting the surface of the outer portion to the surface of the central portion.

11. The semiconductor device according to claim 10, wherein the surface of the connecting portion of the first surface of the transparent substrate portion is an inclined surface.

12. A method of manufacturing a semiconductor device, comprising: Coupling a semiconductor wafer to a first surface of a transparent wafer; Dividing the semiconductor wafer and the transparent wafer to form a plurality of substrate assemblies, each substrate assembly including a transparent substrate and a semiconductor die coupled to each other; Coupling the plurality of substrate assemblies to a carrier support; Forming a molding compound on the plurality of substrate assemblies and the carrier support; Decoupling the carrier support from the plurality of substrate assemblies and the molding compound; Forming a plurality of trenches in the plurality of substrate assemblies and the molding compound; Forming a first insulating layer on the plurality of substrate assemblies, on the molding compound, and in the plurality of trenches; Further extending the plurality of trenches into the plurality of substrate assemblies and the molding compound and into the first insulating layer; Forming a conductive layer on the first insulating layer, on the contacts of each of the substrate assemblies in the plurality of substrate assemblies, and in the plurality of trenches, the conductive layer having ends that are closer to the second surface of the transparent wafer than the contacts of the substrate assemblies, the second surface being opposite the first surface of the transparent wafer; Forming a plurality of packages by dividing the plurality of substrate assemblies and the molding compound.

13. The method according to claim 12, further comprising: Forming a second insulating layer in the trenches and on the conductive layer.

14. The method according to claim 13, wherein extending the plurality of trenches further comprises: Remove a portion of the electrical contacts of each semiconductor die in the semiconductor dies of the plurality of base components.

15. The method according to claim 12, wherein the semiconductor wafer and the transparent wafer are 12-inch wafers, and the carrier support is an 8-inch glass carrier substrate.

16. The method according to claim 15, further comprising forming an 8-inch wafer by forming the molding compound and decoupling the carrier support from the molding compound and the plurality of base components.

17. The method according to claim 12, wherein forming the plurality of packages by dicing the plurality of base components and the molding compound further comprises: Forming a layer of the molding compound on the sidewalls of each of the transparent substrates in the plurality of base components.

18. The method according to claim 12, further extending the plurality of trenches into the plurality of base components and the molding compound further comprises: Forming a raised portion of each of the transparent substrates in the plurality of base components.

19. The method according to claim 12, further comprising planarizing the molding compound and the plurality of base components to form a surface of the molding compound flush with the surface of each semiconductor die in the semiconductor dies of the plurality of base components.

20. The method according to claim 12, wherein: Coupling the plurality of base components to the carrier support further comprises spacing each of the base components from each other; and Forming the molding compound comprises forming the molding compound between the base components.

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