Integrated circuit semiconductor device including through-silicon vias

Abstract

Disclosed is an integrated circuit semiconductor device, comprising: a substrate including a first surface and a second surface opposite to the first surface; a trench in the substrate, the trench extending from the first surface of the substrate towards the second surface of the substrate; a through-silicon via (TSV) landing portion in the trench, the TSV landing portion having a first portion spaced apart from the first surface of the substrate and a second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion; a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with the bottom surface of the TSV landing portion; and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing portion.

Description

[0001] Cross - reference to related applications

[0002] Korean Patent Application No. 10 - 2020 - 0037059, filed on March 26, 2020 with the Korean Intellectual Property Office and entitled "Integrated Circuit Semiconductor Device Including Through Silicon Via", is hereby incorporated by reference in its entirety. Technical field

[0003] Embodiments relate to an integrated circuit semiconductor device, and more particularly to an integrated circuit semiconductor device including a through - silicon via (TSV). Background art

[0004] In an integrated circuit semiconductor device, TSVs are formed to penetrate a substrate and electrically connect wirings (or terminals). Since the integrated circuit semiconductor device is highly integrated, the size of each TSV can be reduced. Summary of the invention

[0005] According to an aspect of an embodiment, there is provided an integrated circuit semiconductor device including: a substrate including a first surface and a second surface opposite to the first surface; a trench in the substrate, the trench extending from the first surface of the substrate toward the second surface of the substrate; a through - silicon via (TSV) landing part in the trench, the TSV landing part having a first part spaced apart from the first surface of the substrate and a second part between the first part and the first surface of the substrate, the first part being wider than the second part; a TSV hole in the substrate, the TSV hole extending from the second surface of the substrate and aligned with a bottom surface of the TSV landing part; and a TSV in the TSV hole and in contact with the bottom surface of the TSV landing part.

[0006] According to another aspect of an embodiment, there is provided an integrated circuit semiconductor device including: a substrate including a first surface and a second surface opposite to the first surface; a plurality of active elements formed at the first surface of the substrate; a plurality of through - silicon via (TSV) landing parts connected to the plurality of active elements and buried in trenches formed in the substrate, each of the plurality of TSV landing parts being configured such that its lower part is wider in width than its upper part; and a plurality of TSVs connected to the plurality of TSV landing parts and buried in a plurality of TSV holes aligned with lower surfaces of the plurality of TSV landing parts, wherein some of the plurality of TSV landing parts are connected to a power rail part or a ground rail part.

[0007] According to another aspect of the embodiment, an integrated circuit semiconductor device is provided, including: a substrate including a first surface and a second surface opposite to the first surface; a plurality of active elements formed at the first surface of the substrate, the plurality of active elements including a plurality of finFET transistors, the plurality of finFET transistors including: a plurality of pins disposed on the first surface of the substrate to extend in a first direction; a plurality of gate electrodes extending in a second direction perpendicular to the first direction, and a plurality of source regions and drain regions disposed on both sides of the plurality of gate electrodes along the second direction; a plurality of through-silicon via (TSV) landing pads connected to the source regions and drain regions of the plurality of finFET transistors and buried in the substrate, each of the plurality of TSV landing pads being configured such that a portion thereof away from the first surface is wider in width than a portion thereof adjacent to the first surface; and a plurality of TSVs connected to the plurality of TSV landing pads and buried in a plurality of TSV holes aligned with the lower surfaces of the plurality of TSV landing pads starting from the second surface, wherein some of the plurality of TSV landing pads are connected to a power rail portion or a ground rail portion disposed in the same direction as the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art from a detailed description of exemplary embodiments with reference to the attached drawings, in which:

[0009] Figure 1 is a cross-sectional view of an integrated circuit semiconductor device according to an embodiment;

[0010] Figure 2A and Figure 2B is Figure 1 a detailed cross-sectional view of the integrated circuit semiconductor device;

[0011] Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B and Figures 5A - 5C is a cross-sectional view of a trench for determining a through-silicon via (TSV) landing pad of an integrated circuit semiconductor device according to an embodiment;

[0012] Figures 6A to 6F is for manufacturing Figure 1 a cross-sectional view of a stage in a method of an integrated circuit semiconductor device;

[0013] Figure 7 is a layout diagram of an integrated circuit semiconductor device according to an embodiment;

[0014] Figure 8 is along Figure 7 a cross-sectional view taken along line A-A;

[0015] Figure 9A and Figure 9B is Figure 8 a detailed cross-sectional view of an integrated circuit semiconductor device;

[0016] Figures 10A to 10C is a cross-sectional view of a stage in a method for manufacturing a TSV landing portion of the integrated circuit semiconductor device in Figures 7 to 9B ;

[0017] Figures 11A to 11H is a cross-sectional view of a stage in a method for manufacturing the integrated circuit semiconductor device in Figures 7 to 9B ;

[0018] Figure 12 is a cross-sectional view of an integrated circuit semiconductor device according to an embodiment;

[0019] Figure 13 is a cross-sectional view of an integrated circuit semiconductor device according to an embodiment;

[0020] Figure 14 is a cross-sectional view of an integrated circuit semiconductor device according to an embodiment;

[0021] Figure 15 is a block diagram of a semiconductor chip including an integrated circuit semiconductor device according to an embodiment;

[0022] Figure 16 is a block diagram of a semiconductor chip including an integrated circuit semiconductor device according to an embodiment;

[0023] Figure 17 is a block diagram of an electronic device including an integrated circuit semiconductor device according to an embodiment; and

[0024] Figure 18 is an equivalent circuit block diagram of a static random access memory (SRAM) cell according to an embodiment. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0026] Figure 1 is a cross-sectional view of an integrated circuit semiconductor device 10 according to an embodiment.

[0027] Refer to Figure 1, the integrated circuit semiconductor device 10 may include: a substrate 50 including a first surface 50fs and a second surface 50bs opposite to the first surface 50fs. In some embodiments, the substrate 50 may include, for example, a silicon substrate. The substrate 50 may be referred to as a silicon layer. The first surface 50fs may be the front surface of the substrate 50. The second surface 50bs may be the back surface of the substrate 50. In some embodiments, the first surface 50fs may be the back surface of the substrate 50, and the second surface 50bs may be the front surface of the substrate 50.

[0028] The integrated circuit semiconductor device 10 may include: a plurality of through-silicon via (TSV) landing pads 56a and 56b and a plurality of TSVs 74a and 74b. The TSV landing pads 56a and 56b and the TSVs 74a and 74b may be referred to as via landing pads and vias, respectively. The TSV landing pads 56a and 56b may be buried in the substrate 50. The TSV landing pads 56a and 56b may be respectively buried in a plurality of trenches 52a and 52b formed at a specific depth from the first surface 50fs of the substrate 50.

[0029] The TSV landing pads 56a and 56b may include a first TSV landing pad 56a and a second TSV landing pad 56b, which are separately disposed from each other. In some embodiments, the shape of the first TSV landing pad 56a may be the same as or different from the shape of the second TSV landing pad 56b.

[0030] The TSV landing pads 56a and 56b may each include a conductive layer. Each of the first and second TSV landing pads 56a and 56b may include a metal layer, for example, a tungsten layer, a titanium nitride layer, a cobalt layer, or a combined layer thereof. Each of the first and second TSV landing pads 56a and 56b may include a silicon layer doped with impurities.

[0031] Each of the first and second TSV landing pads 56a and 56b may be configured such that a portion thereof away from the first surface 50fs in the direction toward the second surface 50bs is wider in width than a portion thereof adjacent to the first surface 50fs. For example, as Figure 1 shown, the width of a portion of each of the first and second TSV landing pads 56a and 56b vertically spaced apart from the first surface 50fs toward the second surface 50bs may be greater than the width of a portion adjacent to the first surface 50fs. A plurality of trench liner layers 54a and 54b may be respectively formed on the inner walls of the trenches 52a and 52b. Each of the trench liner layers 54a and 54b may include an insulating layer, for example, an oxide layer or a nitride layer.

[0032] TSV 74a and 74b can be buried in a plurality of TSV holes 70a and 70b extending from the second surface 50bs of the substrate 50, and the TSV holes 70a and 70b can be aligned with the bottom surfaces of the first and second TSV landing pads 56a and 56b. The TSV holes 70a and 70b can include a first TSV hole 70a and a second TSV hole 70b, which are separately arranged from each other. The first and second TSV holes 70a and 70b can be aligned with and formed on the bottom surfaces of the first and second TSV landing pads 56a and 56b. Therefore, the TSVs 74a and 74b can be easily buried into the TSV holes 70a and 70b.

[0033] In addition, each of the first and second TSV landing pads 56a and 56b can be configured such that its lower part (i.e., the part away from the first surface 50fs) is wider in width than its upper part (i.e., the part close to the first surface 50fs). Therefore, the TSVs 74a and 74b can be easily formed. In other words, the TSVs 74a and 74b can more easily land on the first and second TSV landing pads 56a and 56b, where the lower parts of the first and second TSV landing pads 56a and 56b (i.e., the parts in contact with the corresponding one of the TSVs 74a and 74b) are wider in width than their upper parts (i.e., the parts in contact with the first surface 50fs). The TSVs 74a and 74b can be in direct contact with the bottom parts of the first and second TSV landing pads 56a and 56b, for example, and thus can be mechanically or electrically connected to the first and second TSV landing pads 56a and 56b.

[0034] In some embodiments, each of the TSVs 74a and 74b can be formed such that its width decreases in the direction from the second surface 50bs to the first surface 50fs. Therefore, its side profile is inclined. For example, as Figure 1 shown, each of the TSVs 74a and 74b can have a gradually increasing width in the direction from the first surface 50sf towards the second surface 50bs, for example, having a trapezoidal cross-section. The TSVs 74a and TSV 74b can include a first TSV 74a and a second TSV 74b that are separately arranged from each other. The first TSV 74a and the second TSV 74b can be respectively buried in the first TSV hole 70a and the second TSV hole 70b. The first TSV 74a and the second TSV 74b can be in contact with the first TSV landing pad 56a and the second TSV landing pad 56b respectively, and thus can be mechanically and electrically connected to the first TSV landing pad 56a and the second TSV landing pad 56b.

[0035] Each of the first TSV 74a and the second TSV 74b may include a metal layer, for example, a copper layer, a tungsten layer, a titanium nitride layer, a cobalt layer, or a combined layer thereof. A plurality of via liner layers 72a and 72b may be formed at the inner sidewalls of the first and second TSV holes 70a and 70b. Each of the via liner layers 72a and 72b may include an insulating layer, for example, an oxide layer or a nitride layer.

[0036] In some embodiments, a plurality of upper contact pads 78a and 78b may be respectively formed on the first and second TSV landing pads 56a and 56b on the first surface 50fs. In some embodiments, a plurality of lower contact pads 76a and 76b may be respectively formed on the first and second TSVs 74a and 74b on the second surface 50bs of the substrate 50.

[0037] The integrated circuit semiconductor device 10 may include the first and second TSV landing pads 56a and 56b, and thus, the first and second TSVs 74a and 74b may be reliably formed. Further, in the integrated circuit semiconductor device 10, the width of each portion of the portion where the TSVs 74a and 74b land may be set to be greater than the width of each portion of the portion where the TSVs 74a and 74b do not land, and thus, the TSVs 74a and 74b may be easily formed.

[0038] In some embodiments, elements such as the TSV landing pads 56a and 56b and the TSVs 74a and 74b may be formed in the front-end-of-line (FEOL) or middle-end-of-line (MEOL) manufacturing process 20. Elements on the upper contact pads 78a and 78b on the first surface 50fs of the substrate 50 may be formed in the back-end-of-line (BEOL) manufacturing process 24. Elements on the lower contact pads 76a and 76b on the second surface 50bs of the substrate 50 may be formed in the BEOL manufacturing process 22.

[0039] The integrated circuit semiconductor device 10 may be referred to as a semiconductor device, a semiconductor chip, or a semiconductor die. In Figure 1 Although the integrated circuit semiconductor device 10 is shown as a single device, a stacked package semiconductor may also be formed by stacking other integrated circuit semiconductor devices on the integrated circuit semiconductor device 10 by using the upper contact pads 78a and 78b or the lower contact pads 76a and 76b. Thus, according to an embodiment, the integrated circuit semiconductor device 10 may be used for a semiconductor stacked package.

[0040] Figure 2A and Figure 2B is a detailed cross-sectional view provided for describing Figure 1 the integrated circuit semiconductor device 10.

[0041] Specifically, multiple TSV landing pads 56a and 56b of the integrated circuit semiconductor device 10 can be buried in multiple trenches 52a and 52b, and the multiple trenches 52a and 52b are formed at a first depth D1 from the first surface 50fs. The trenches 52a and 52b can include: multiple upper trenches 52a1 and 52b1, which are respectively formed at a first sub-depth D1a from the first surface 50fs; and multiple lower trenches 52a2 and 52b2, which are respectively formed at a second sub-depth D1b from the upper trenches 52a1 and 52b1.

[0042] As Figure 2A shown, the upper trenches 52a1 and 52b1 can respectively have upper widths W1a and W2a. The lower trenches 52a2 and 52b2 can respectively have lower widths W1b and W2b. The lower widths W1b and W2b can be greater than the corresponding upper widths W1a and W2a. The shape of each of the upper trenches 52a1 and 52b1 or the shape of each of the lower trenches 52a2 and 52b2 will be described in more detail below.

[0043] Multiple trench liner layers 54a and 54b can be formed on the inner sidewalls of the corresponding upper trenches 52a1 and 52b1 and the corresponding lower trenches 52a2 and 52b2. Multiple TSV landing pads 56a1, 56a2, 56b1 and 56b2 can be respectively buried in the multiple trench liner layers 54a and 54b in the upper trenches 52a1 and 52b1 and the lower trenches 52a2 and 52b2.

[0044] The TSV landing pads 56a1, 56a2, 56b1 and 56b2 can include: multiple upper TSV landing pads 56a1 and 56b1, which are respectively buried in the upper trenches 52a1 and 52b1; and multiple lower TSV landing pads 56a2 and 56b2, which are respectively buried in the lower trenches 52a2 and 52b2 that communicate with the upper trenches 52a1 and 52b1. For example, as Figure 2A shown, the upper trenches 52a1 and 52b1 can be in fluid communication with the corresponding lower trenches 52a2 and 52b2. For example, so that each pair of the lower trenches and the upper trenches forms a single unified cavity, so that the lower TSV landing pads 56a2 and 56b2 can be in direct contact with the corresponding one of the upper TSV landing pads 56a1 and 56b1 to be integrated with each other.

[0045] The cross-sectional shape of each of the lower TSV landing pads 56a2 and 56b2 can be determined based on the cross-sectional shape of each of the corresponding trenches 52a2 and 52b2. For example, the cross-sectional shape of the lower TSV landing pad 56a2 can be semi-circular, and the cross-sectional shape of the lower TSV landing pad 56b2 can be polygonal, for example, hexagonal.

[0046] As Figure 2BAs shown, due to the thickness of each of the trench bushing layers 54a and 54b, the upper TSV landing portions 56a1 and 56b1 can respectively have upper widths W1a' and W2a' that are less than the upper widths W1a and W2a of the upper trenches 52a1 and 52b1. The lower TSV landing portions 56a2 and 56b2 can respectively have lower widths W1b' and W2b', and the lower widths W1b' and W2b' are less than the lower widths W1b and W2b of the lower trenches 52a2 and 52b2. The lower widths W1b' and W2b' of the lower TSV landing portions 56a2 and 56b2 can be greater than the upper widths W1a' and W2a' of the upper TSV landing portions 56a1 and 56b1. The upper widths W1a' and W2a' can be related concepts to the lower widths W1b' and W2b'. The width of at least a portion of the lower TSV landing portion 56a2 (e.g., the lower width W1b') can be greater than the width of at least a portion of the upper TSV landing portion 56a1 (e.g., the upper width W1a'), and the width of at least a portion of the lower TSV landing portion 56b2 (e.g., the lower width W2b') can be greater than the width of at least a portion of the upper TSV landing portion 56b1 (e.g., the upper width W2a').

[0047] The TSVs 74a and 74b of the integrated circuit semiconductor device 10 can be buried in the TSV holes 70a and 70b having a second depth D2 from the second surface 50bs. The second depth D2 can be greater than the first depth D1. In some embodiments, as Figure 2A shown, the widths W3a and W4a of the portions of the TSV holes 70a and 70b adjacent to the second surface 50bs can be greater than the widths W3b and W4b of the portions of the TSV holes 70a and 70b away from the second surface 50bs and adjacent to the lower TSV landing portions 56a2 and 56b2.

[0048] Multiple via bushing layers 72a and 72b can be formed on the inner sidewalls of the TSV holes 70a and 70b. The TSVs 74a and 74b can be buried in the via bushing layers 72a and 72b in the TSV holes 70a and 70b. As Figure 2B shown, due to the thickness of each of the via bushing layers 72a and 72b, the TSVs 74a and 74b can respectively have widths W3a' and W4a' that are less than the widths W3a and W4a of the TSV holes 70a and 70b.

[0049] The portions of the TSVs 74a and 74b that are remote from the second surface 50bs and adjacent to the lower TSV landing portions 56a2 and 56b2 may have widths W3b' and W4b', respectively. The portions of the TSVs 74a and 74b adjacent to the second surface 50bs may have widths smaller than the widths W3a' and W4a'. Each of the TSVs 74a and 74b may be formed to have a width that gradually decreases in a direction from the second surface 50bs toward the first surface 50fs.

[0050] Figures 3A to 5C is a cross-sectional view of a trench for determining a TSV landing portion of an integrated circuit semiconductor device according to an embodiment.

[0051] Specifically, as described above, a plurality of TSV landing portions ( Figure 1 56a and 56b) may be buried in a plurality of trenches ( Figure 1 52a and 52b). The cross-sectional shape of each of the plurality of trenches ( Figure 1 52a and 52b) may be determined based on the cross-sectional shape of each TSV landing portion of the plurality of TSV landing portions ( Figure 1 56a and 56b). In Figures 3A to 5C , embodiments applied to the plurality of trenches ( Figure 1 52a and 52b) will be described.

[0052] Figures 3A to 7 The plurality of trenches EH1 to EH7 shown may be formed by etching (e.g., dry etching and / or wet etching) the substrate 50 using a mask layer 80. The trenches EH1 to EH7 may be formed by isotropic etching and / or anisotropic etching of the substrate 50 using a mask layer 80. In some embodiments, the trenches EH1 to EH7 may be formed by etching the substrate 50 a plurality of times (e.g., primary and secondary) using a mask layer 80.

[0053] In some embodiments, the trenches EH1 to EH7 may include: a plurality of upper trenches EP1a to EP7a, formed by primary etching of the substrate 50; and a plurality of lower trenches EP1b to EP7b, formed by secondary etching of the substrate 50, e.g., also communicating with the upper trenches EP1a to EP7a. The cross-sectional shape (or form) of each trench of the trenches EH1 to EH7 may be determined based on the crystal orientation of the substrate 50 and the shape and etching slope of the mask layer 80.

[0054] In some embodiments, the cross-sectional shape of each of the trenches EH1 to EH7 may be, for example, semi-circular, circular, or polygonal. Figure 3A The trench EH1 shown may be in communication with Figure 1corresponds to the groove 52a. Figure 4B The groove EH4 shown can be Figure 1 corresponds to the groove 52b.

[0055] The upper grooves EP1a to EP7a can respectively have upper widths W1a, W2a, W5a to W9a. The lower grooves EP1b to EP7b can respectively have lower widths W1b, W2b, W5b to W9b. The lower widths W1b, W2b, W5b to W9b of the lower grooves EP1b to EP7b can be greater than the upper widths W1a, W2a, W5a to W9a of the upper grooves EP1a to EP7a.

[0056] The width of at least a part of each of the lower grooves EP1b to EP7b (e.g., the lower widths W1b, W2b, W5b to W9b) can be greater than the width of at least a part of each of the upper grooves EP1a to EP7a (e.g., the upper widths W1a, W2a, W5a to W9a).

[0057] Figures 6A to 6F is a cross-sectional view of a stage in a method of manufacturing Figure 1 an integrated circuit semiconductor device.

[0058] Referring to Figure 6A , the formation of a plurality of grooves 52a and 52b is shown. A substrate 50 including a first surface 50fs and a second surface 50bs opposite to the first surface 50fs can be prepared. The grooves 52a and 52b can be formed by etching the substrate 50 to a specific depth from the first surface 50fs. The grooves 52a and 52b can be formed by using a photolithography process. The grooves 52a and 52b can be formed by etching the substrate 50 using a mask layer as an etching mask.

[0059] The grooves 52a and 52b can be formed in plurality, and the plurality of grooves 52a and 52b can be horizontally spaced apart from each other. The cross-sectional shape of the groove 52a can be different from the cross-sectional shape of the groove 52b. The lower widths W1b and W2b of the grooves 52a and 52b can be greater than the upper widths W1a and W2a of the grooves 52a and 52b. The cross-sectional shape of each TSV landing portion ( Figure 1 56a and 56b of

[0060] Referring to Figure 6B, shows the formation of a plurality of TSV landing portions 56a and 56b. The TSV landing portions 56a and 56b can be formed by filling conductive materials into the trenches 52a and 52b, in which trench liner layers 54a and 54b are formed. The lower widths W1b' and W2b' of the TSV landing portions 56a and 56b can be greater than the upper widths W1a' and W2a' of the TSV landing portions 56a and 56b.

[0061] Reference Figure 6C , shows the formation of a plurality of TSV holes 70a and 70b. The substrate 50 can be flipped, and in this state, the mask layer 80 can be formed using a photolithography process. According to this situation, a preliminary substrate (or carrier substrate) can be attached to the first surface 50fs of the substrate 50. The TSV holes 70a and 70b can be formed by etching the substrate 50 using the mask layer 80 as an etching mask.

[0062] The TSV holes 70a and 70b can be aligned with the TSV landing portions 56a and 56b and formed on the TSV landing portions 56a and 56b, wherein the width of the bottom surface of the TSV landing portions 56a and 56b is wider than the width of the top surface thereof. For example, as Figure 6C shown, the openings of the mask layer 80 can be aligned (e.g., overlapped) with the TSV landing portions 56a and 56b so that the TSV holes 70a and 70b can be formed through the substrate 50 until the TSV landing portions 56a and 56b are exposed. For example, since the portions of the TSV landing portions 56a and 56b facing the TSV holes 70a and 70b are formed wider, it substantially helps to align the openings of the mask layer 80 with the TSV landing portions 56a and 56b, and thus align the TSV holes 70a and 70b with the TSV landing portions 56a and 56b. Therefore, the TSV holes 70a and 70b can be reliably formed. The widths W3a and W4a of the portions of the TSV holes 70a and 70b adjacent to the second surface 50bs can be greater than the widths W3b and W4b of the portions of the TSV holes 70a and 70b away from the second surface 50bs and adjacent to the plurality of lower TSV landing portions 56a2 and 56b2.

[0063] Reference Figure 6D , shows the formation of a plurality of via liner layers 72a and 72b. The mask layer 80 can be removed, and then, the via liner layers 72a and 72b can be conformally formed, for example, on the inner sidewalls and bottoms of the TSV holes 70a and 70b and the substrate 50. Each of the via liner layers 72a and 72b can be formed as an insulating layer, for example, formed as an oxide layer or a nitride layer.

[0064] Reference Figure 6E, shows the removal of the via bushing layers 72a and 72b and the trench bushing layers 54a and 54b on the TSV landing portions 56a and 56b. The via bushing layers 72a and 72b and the trench bushing layers 54a and 54b on the TSV landing portions 56a and 56b can be removed from the inside of the TSV holes 70a and 70b.

[0065] Therefore, the bottom surfaces of the TSV landing portions 56a and 56b can be exposed inside the TSV holes 70a and 70b. That is, the bottom surfaces of the TSV landing portions 56a and 56b can be exposed in the direction toward the second surface 50bs.

[0066] Reference Figure 6F , shows the formation of a plurality of TSVs 74a and 74b. The TSVs 74a and 74b can be formed by filling the TSV holes 70a and 70b in which the via bushing layers 72a and 72b are formed with a conductive material layer. After the TSVs 74a and 74b are formed, the via bushing layers 72a and 72b on the substrate 50 can be removed.

[0067] The TSVs 74a and 74b can be reliably formed on the TSV landing portions 56a and 56b having a wider width thereunder. The widths W3b' and W4b' of the portions of the TSVs 74a and 74b that are away from the second surface 50bs and adjacent to the lower TSV landing portions 56a2 and 56b2 can be smaller than the widths W3a' and W4a' of the portions of the TSVs 74a and 74b that are close to the second surface 50bs.

[0068] Figure 7 is a layout diagram of an integrated circuit semiconductor device 100 according to an embodiment.

[0069] Reference Figure 7 , the integrated circuit semiconductor device 100 is an example of an active element, and shows a layout diagram including a plurality of finFET transistors (or fin transistors). In the integrated circuit semiconductor device 100, a layout diagram of complementary metal insulator semiconductor transistors (CMOS) including P-type metal insulator semiconductor (PMOS) transistors (PMOS transistors) and N-type metal insulator semiconductor (NMOS) transistors (NMOS transistors) is shown as an example of active elements. The embodiment is not limited to Figure 7 the layout diagram of.

[0070] In the integrated circuit semiconductor device 100, PMOS transistors and NMOS transistors may be repeatedly arranged along a second direction (Y direction). Each MOS transistor may include a plurality of pins 136a and 136b extending along a first direction (X direction). The pins 136a and 136b may include a plurality of P-type pins 136a and a plurality of N-type pins 136b. A plurality of gate lines 114 (e.g., four gate lines) may be arranged across the pins 136a and 136b along a second direction (Y direction) perpendicular to the first direction.

[0071] A plurality of source regions and drain regions 138a and 138b may be arranged on both sides of the gate lines 114 along the first direction. The source regions and drain regions 138a and 138b may include a plurality of P-type source regions and drain regions 138a and a plurality of N-type source regions and drain regions 138b.

[0072] Some portions of the source regions and drain regions 138a and 138b may be connected to a power supply rail portion 190b or a ground rail portion 190a extending along the first direction through a plurality of local wirings 140a and 140b. For example, some portions of the P-type source regions and drain regions 138a may be connected to the power supply rail portion 190b extending along the first direction through the local wiring 140b and the TSV landing portion 156b. Some portions of the N-type source regions and drain regions 138b may be connected to the ground rail portion 190a extending along the first direction through the local wiring 140a and the TSV landing portion 156a. Some portions of the source regions and drain regions 138a and 138b may be connected to a wiring layer through the local wiring 141 and the contact wiring 117.

[0073] Figure 8 is a cross-sectional view taken along line A-A of Figure 7

[0074] Specifically, in addition to a plurality of active elements (e.g., finFET transistors), the integrated circuit semiconductor device 100 may be substantially the same as the integrated circuit semiconductor device 10 of Figure 1 Figure 7 In the integrated circuit semiconductor device 100 of Figure 1 Figure 7 the active elements will be mainly described, and descriptions that are the same as or similar to those of

[0075] will be given only briefly or omitted. In addition, in the integrated circuit semiconductor device 100 of Figure 8 with reference to Figure 1 ​​​corresponds to the substrate 50. The first surface 150fs may be the front surface of the substrate 150. The second surface 150bs may be the back surface of the substrate 150.

[0076] The integrated circuit semiconductor device 100 may include a plurality of TSV landing pads 156a and 156b and a plurality of TSVs 174a and 174b. The TSV landing pads 156a and 156b may be buried in the substrate 150. The TSV landing pads 156a and 156b may be connected to Figure 7 the power rail portion 190b or the ground rail portion 190a.

[0077] The TSV landing pads 156a and 156b may correspond to Figure 1 the TSV landing pads 56a and 56b. Each of the TSV landing pads 156a and 156b may be configured such that a portion thereof that extends away from the first surface 150fs in a direction toward the second surface 150bs is wider in width than a portion thereof adjacent to the first surface 150fs. A plurality of trench liner layers 154a and 154b may be formed to surround the TSV landing pads 156a and 156b. The trench liner layers 154a and 154b may correspond to Figure 1 the trench liner layers 54a and 54b.

[0078] The TSVs 174a and 174b may be buried in a plurality of TSV holes 170a and 170b that are aligned with the bottom surfaces of the TSV landing pads 156a and 156b starting from the second surface 150bs. A plurality of via liner layers 172a and 172b may be formed on the inner sidewalls of the TSV holes 170a and 170b. The first and second TSV holes 170a and 170b may correspond to Figure 1 the first and second TSV holes 70a and 70b. The via liner layers 172a and 172b may correspond to Figure 1 the via liner layers 72a and 72b. The TSVs 174a and 174b may correspond to Figure 1 the TSVs 74a and 74b.

[0079] Each of the TSV landing pads 156a and 156b may be configured such that its lower portion is wider in width than its upper portion, so that the TSVs 174a and 174b can be easily formed, and thus the TSV landing pads 156a and 156b can also be easily formed.

[0080] In an integrated circuit semiconductor device 100, a plurality of well regions 132a, 132b, 134a, and 134b may be provided for forming active elements on a substrate 150. The well regions 132a, 132b, 134a, and 134b may be provided integrally with the substrate 150. In some embodiments, each of the well regions 132a and 134a may be a P-well region, and each of the well regions 132b and 134b may be an N-well region.

[0081] The well regions 132a, 132b, 134a, and 134b may be classified into a plurality of first well regions 132a and 132b and a plurality of second well regions 134a and 134b. The plurality of first well regions 132a and 132b and the plurality of second well regions 134a and 134b may be divided by an insulating layer 142.

[0082] A plurality of pins 136 spaced apart from each other may be formed on the well regions 132a, 132b, 134a, and 134b. The pins 136a and 136b may be formed spaced apart from each other in a second direction (Y direction). The pins 136a and 136b may include a plurality of P-type pins 136a and a plurality of N-type pins 136b. A plurality of source and drain regions 138a and 138b may be formed on the pins 136a and 136b. A plurality of P-type source and drain regions 138a may be formed on the P-type pins 136a. A plurality of N-type source and drain regions 138b may be formed on the N-type pins 136b.

[0083] A TSV landing pad 156a may be formed between the first well regions 132a and 132b and between the P-type pins 136a and the N-type pins 136b. A TSV landing pad 156b may be formed between the second well regions 134a and 134b and between the P-type pins 136a and the N-type pins 136b.

[0084] The TSV landing pad 156a may be connected to the first contact plug 137a through a first local wiring 140a connected to the first contact plug 137a. The TSV landing pad 156b may be connected to the second contact plug 137b through a second local wiring 140b connected to the second contact plug 137b. The first and second contact plugs 137a and 137b may be insulated from the first and second local wirings 140a and 140b by the insulating layer 142.

[0085] In some embodiments, elements such as the TSV landing pads 156a and 156b, the TSVs 174a and 174b, and the active elements may be formed in the front-end-of-line (FEOL) manufacturing process 122 and the middle-of-line (MEOL) manufacturing process 120. In some embodiments, elements such as the contact plugs and the local wirings may be formed in the middle-of-line (MEOL) manufacturing process 124.

[0086] Elements on the first and second contact plugs 137a and 137b and the first and second local wirings 140a and 140b on the first surface 150fs can be formed in the BEOL manufacturing process 126. Elements on the TSVs 174a and 174b on the second surface 150bs can be formed in the BEOL manufacturing process 128.

[0087] Figure 9A and Figure 9B is provided as a detailed cross-sectional view of the integrated circuit semiconductor device 100 for description Figure 8 of.

[0088] Specifically, in the integrated circuit semiconductor device 100, a plurality of active elements can be formed on the substrate 150. The active elements can be finFET transistors. The active elements can include: a plurality of well regions 132a, 132b, 134a, and 134b; a plurality of pins 136 ( Figure 8 from 136a to 136b); and a plurality of source and drain regions 138 ( Figure 8 from 138a and 138b). A part of the insulating layer 142 (i.e., part 133) can be formed to divide the plurality of first well regions 132a and 132b from the plurality of second well regions 134a and 134b.

[0089] The integrated circuit semiconductor device 100 can include a plurality of TSV landing pads 156a and 156b. The TSV landing pads 156a and 156b can be buried in a plurality of trenches 152a and 152b, and the plurality of trenches 152a and 152b can be formed at a specific depth from the first surface ( Figure 8 of 150fs) of the substrate 150. As Figure 9A shown, the trenches 152a and 152b can have upper widths W11a and W12a respectively. The trenches 152a and 152b can have lower widths W11b and W12b respectively. The lower widths W11b and W12b can be greater than the upper widths W11a and W12a.

[0090] As Figure 9B shown, due to the plurality of trench liner layers ( Figure 8For the thickness of each of 154a and 154b), the upper TSV landing portions 156a and 156b may respectively have upper widths W11a' and W12a' that are less than the upper widths W11a and W12a of the trenches 152a and 152b. The TSV landing portions 156a and 156b may respectively have lower widths W11b' and W12b' that are less than the lower widths W11b and W12b of the trenches 152a and 152b. The lower widths W11b' and W12b' of the TSV landing portions 156a and 156b may be greater than the upper widths W11a' and W12a' of the TSV landing portions 156a and 156b. The upper widths W11a' and W12a' may be related concepts of the lower widths W11b' and W12b'.

[0091] A plurality of TSVs 174a and 174b of the integrated circuit semiconductor device 100 may be buried in a plurality of TSV holes 170a and 170b, and the plurality of TSV holes 170a and 170b have a depth D11 from the second surface 150bs of the substrate 150. In some embodiments, as Figure 9A shown, the widths W13a and W14a of the portions of the TSV holes 170a and 170b adjacent to the second surface 150bs may be greater than the widths W13b and W14b of the portions of the TSV holes 170a and 170b away from the second surface 150bs and adjacent to the TSV landing portions 156a and 156b.

[0092] A plurality of via bushing layers 172a and 172b may be formed on the inner sidewalls of the TSV holes 170a and 170b. The TSVs 174a and 174b may be buried in the via bushing layers 172a and 172b in the TSV holes 170a and 170b. As Figure 9B shown, due to the thickness of each of the via bushing layers 172a and 172b, the TSVs 174a and 174b may respectively have widths W13a' and W14a' that are less than the widths W13a and W14a of the TSV holes 170a and 170b.

[0093] The portions of the TSVs 174a and 174b away from the second surface 150bs and adjacent to the TSV landing portions 156a and 156b may respectively have widths W13b' and W14b'. The widths W13b' and W14b' of the TSVs 174a and 174b may be respectively less than the W13a' and W14a' of the TSVs 174a and 174b. Each of the TSVs 174a and 174b may be formed to have a width that gradually decreases along the direction from the second surface 150bs toward the first surface 150fs.

[0094] Figures 10A to 10C is for detailed description of manufacturing Figures 7 to 9BCross-sectional view of the process of the TSV landing part of the integrated circuit semiconductor device 100 shown in

[0095] Reference Figure 10A , showing that a plurality of upper trenches 152a-1 and 152b-1 are formed on the substrate 150. A plurality of pins 136 of elements that are a plurality of active elements can be formed on the substrate 150. A mask layer can be formed on the substrate 150 by a photolithography process, and then, the pins 136 can be formed by etching the substrate 150 using the mask layer as an etching mask. After that, an insulating layer 142 can be formed between the plurality of pins 136. After that, the insulating layer 142 and the substrate 150 can be selectively etched by a photolithography process to form the upper trenches 152a-1 and 152b-1 on the substrate 150. The upper trenches 152a-1 and 152b-1 can be formed by an etching process (e.g., an anisotropic etching process).

[0096] Reference Figure 10B , the substrate 150 can be further etched in communication with the upper trenches 152a-1 and 152b-1 to form a plurality of lower trenches 152a-2 and 152b-2. The lower trenches 152a-2 and 152b-2 can be formed by isotropic etching and / or anisotropic etching of the substrate 150. The cross-sectional shape (or form) of each of the lower trenches 152a-2 and 152b-2 can be determined based on the crystal orientation or etching slope of the substrate 150. The general name of the upper trenches 152a-1 and 152b-1 and the lower trenches 152a-2 and 152b-2 can be trenches 152a and 152b.

[0097] Reference Figure 10C , a plurality of trench liner layers 154a and 154b can be formed in the trenches 152a and 152b, and then, a plurality of TSV landing parts 156a and 156b can be formed on the trench liner layers 154a and 154b in the trenches 152a and 152b. A conductive layer or a metal layer can be buried in the trenches 152a and 152b, and then, the TSV landing parts 156a and 156b are formed by grooving the trenches 152a and 152b to have a specific thickness. The trench liner layers 154a and 154b formed on the pins 136 and the insulating layer 142 can be removed by a subsequent process.

[0098] Figures 11A to 11H is the manufacturing Figures 7 to 9B Cross-sectional view of a stage in the method of the integrated circuit semiconductor device shown in

[0099] Reference Figure 11A, shows multiple active elements and multiple TSV landing pads 156a and 156b formed on a substrate 150. The active elements can be finFET transistors. The active elements can include: multiple well regions 132a, 132b, 134a, and 134b; multiple pins 136; and source and drain regions 138. For example, the multiple well regions 132a, 132b, 134a, and 134b can include multiple first well regions 132a and 132b and multiple second regions 134a and 134b. An insulating layer 142 can be formed to divide the first well regions 132a and 132b from the second regions 134a and 134b.

[0100] Multiple trench liner layers 154a and 154b and multiple TSV landing pads 156a and 156b can be formed in trenches 152a and 152b between the first well regions 132a and 132b and between the second regions 134a and 134b, respectively. The formation of the multiple trench liner layers 154a and 154b and the multiple TSV landing pads 156a and 156b has been described above, so the specific description thereof is omitted.

[0101] After that, a plug layer 137 can be formed on the TSV landing pads 156a and 156b in the trenches 152a and 152b. The plug layer 137 can be formed as a conductive layer. For example, it can be formed as a metal layer. The plug layer 137 can be formed as, for example, a copper layer or a tungsten layer.

[0102] Reference Figure 11B , shows the formation of multiple contact plugs 137a and 137b and multiple local wirings 140a and 140b. The contact plugs 137a and 137b can be formed on the TSV landing pads 156a and 156b by grooving the plug layer 137.

[0103] After that, local wirings 140a and 140b electrically connected to the contact plugs 137a and 137b can be formed in the insulating layer 142. The local wirings 140a and 140b can be formed by using a metal layer. In this embodiment, the formation of the multiple contact plugs 137a and 137b and the multiple local wirings 140a and 140b has been described by different processes, but the embodiment is not limited thereto, and the multiple contact plugs 137a and 137b and the multiple local wirings 140a and 140b can be formed by the same process.

[0104] Reference Figure 11C , shows an upper multi-wiring layer UWL formed on the local wirings 140a and 140b and the insulating layer 142. The upper multi-wiring layer UWL can include: an intermediate wiring insulating layer 143; multiple contact plugs 144a, 144b, and 147; and multiple wiring layers 146 and 148.

[0105] ReferenceFigure 11D and Figure 11E , showing the formation of a plurality of TSV holes 170a and 170b. As Figure 11D shown, the substrate 150 can be flipped, and the preliminary substrate 180 can be attached to the upper multi-layer wiring layer UWL by using the adhesive insulating layer 149. The adhesive insulating layer 149 can be, for example, an oxide layer. Thereafter, a plurality of mask layers 151a and 151b can be formed at the rear surface of the substrate 150 by using a lithography process.

[0106] As Figure 11E shown, a plurality of TSV holes 170a and 170b can be formed by etching the substrate 150 by using each of the mask layers 151a and 151b as an etching mask. The mask layer 151b can be removed when the TSV holes 170a and 170b are formed.

[0107] The TSV holes 170a and 170b can be aligned with the TSV landing portions 156a and 156b and formed on the TSV landing portions 156a and 156b, wherein the width of the bottom surface of the TSV landing portions 156a and 156b is wider than the width of their top surface. Therefore, the TSV holes 170a and 170b can be reliably formed.

[0108] Referring to Figure 11F , showing the formation of a plurality of via bushing layers 172a and 172b. After removing the mask layer 151a, a via bushing material layer 172 can be formed on the inner sidewalls and bottoms of the TSV holes 170a and 170b and on the substrate 150. The via bushing material layer 172 can be formed as an insulating layer, for example, an oxide layer or a nitride layer.

[0109] Referring to Figure 11G , showing the formation of a plurality of TSVs 174a and 174b. First, the via bushing material layer 172 in each of the via bushing material layer 172 formed on the rear surface of the substrate 150, the TSV holes 170a and 170b, and the trench bushing layers 154a and 154b on the TSV landing portions 156a and 156b can be removed.

[0110] Therefore, via bushing layers 172a and 172b are formed at the inner sidewalls of the TSV holes 170a and 170b, and the bottom surfaces of the TSV landing portions 156a and 156b can be exposed inside the TSV holes 170a and 170b. Thereafter, the TSVs 174a and 174b can be formed by filling the TSV holes 170a and 170b formed with the via bushing layers 172a and 172b with a conductive material layer.

[0111] Referring to Figure 11H, showing the formation of the lower multi-layer wiring layer LWL on the TSVs 174a and 174b. The lower multi-layer wiring layer LWL may include: an intermediate wiring insulating layer 181; a plurality of contact plugs 182a, 182b, and 184; and a plurality of wiring layers 183 and 185.

[0112] Figure 12 is a cross-sectional view of an integrated circuit semiconductor device 100a according to an embodiment.

[0113] Specifically, in addition to the plurality of power supply and ground terminals 187a and 187b, Figure 12 the integrated circuit semiconductor device 100a may be the same as Figure 11H the integrated circuit semiconductor device. In the integrated circuit semiconductor device 100a, a plurality of power supply and ground terminals 187a and 187b may be formed through the plurality of contact plugs 186a and 186b and on the wiring layer 185 configuring the lower multi-layer wiring layer LWL.

[0114] Therefore, the power supply and ground terminals 187a and 187b of the integrated circuit semiconductor device 100a may be connected to the plurality of TSV landing pads 156a and 156b via the lower multi-layer wiring layer LWL and the TSVs 174a and 174b. The integrated circuit semiconductor device 100a may apply power supply or ground voltage to the plurality of active elements through the TSV landing pads 156a and 156b, and the TSV landing pads 156a and 156b are connected to the power supply rail portions ( Figure 7 190a and 190b) or the ground rail portions ( Figure 7 190a and 190b) on the back surface of the substrate 150 by using the power supply and ground terminals 187a and 187b.

[0115] Figure 13 is a cross-sectional view of an integrated circuit semiconductor device 100b according to an embodiment.

[0116] Specifically, in addition to the plurality of signal input / output (I / O) terminals 187c and 187d, Figure 13 the integrated circuit semiconductor device 100b may be the same as Figure 12 the integrated circuit semiconductor device 100a. In the integrated circuit semiconductor device 100b, a plurality of signal I / O terminals 187c and 187d may be formed through the plurality of contact plugs 186c and 186d and on the wiring layer 185 configuring the lower multi-layer wiring layer LWL.

[0117] The signal I / O terminals 187c and 187d can be electrically connected to the plurality of TSVs 174c and 174d through the plurality of wiring layers 183a, 183b, 185a and 185d of the configured lower multi-layer wiring layer LWL, the plurality of contact plugs 182c, 182d, 184a and 184b, and the contact plugs 186c and 186d. The TSVs 174c and 174d can be electrically connected to the plurality of active components through the plurality of TSV landing pads 156c and 156d, the plurality of contact plugs 137c, 137d, 144c and 144d, and the plurality of local wirings 140c and 140d. The plurality of contact plugs 144c and 144d can be connected to the wiring layer 146 of the upper multi-layer wiring layer UWL.

[0118] Figure 13 The integrated circuit semiconductor device 100b can apply power and ground voltages using the TSV landing pads 156a and 156b and the TSVs 174a and 174b, and can apply signal I / O voltages using the TSV landing pads 156c and 156d and the TSVs 174c and 174d.

[0119] Figure 14 is a cross-sectional view of an integrated circuit semiconductor device 100c according to an embodiment.

[0120] Specifically, except for the signal I / O terminal 187e connected to the additional TSV 174e, Figure 14 the integrated circuit semiconductor device 100c can be the same as Figure 12 the integrated circuit semiconductor device 100a. In the integrated circuit semiconductor device 100c, the signal I / O terminal 187e can be formed through the contact plug 186e and on the wiring layer 185c of the configured lower multi-layer wiring layer LWL.

[0121] The signal I / O terminal 187e can be electrically connected to the additional TSV 174e through the plurality of wiring layers 183e and 185c of the configured lower multi-layer wiring layer LWL, the plurality of contact plugs 182e, 184c, and the contact plug 186e. The additional TSV 174e may not be electrically connected to the plurality of TSVs 174a and 174b.

[0122] Figure 14 The integrated circuit semiconductor device 100c can apply power and ground voltages using the TSV landing pads 156a and 156b and the TSVs 174a and 174b, and can apply signal I / O voltages using the additional TSV 174e, the local wiring 140e, the plurality of contact plugs 156e, 144e and 147, and the plurality of wiring layers 146 and 148.

[0123] Figure 15It is a block diagram showing a semiconductor chip 200 including an integrated circuit semiconductor device according to an embodiment.

[0124] Specifically, the semiconductor chip 200 may include a logic region 202, a SRAM region 204, and an I / O region 206. The logic region 202 may include a logic cell region 203. The SRAM region 204 may include a SRAM cell region 205 and a SRAM peripheral circuit region 208. A first transistor 210 may be disposed in the logic cell region 203, and a second transistor 212 may be disposed in the SRAM cell region 205. A third transistor 214 may be formed in the SRAM peripheral circuit region 208, and a fourth transistor 216 may be disposed in the I / O region 206.

[0125] The semiconductor chip 200 may include one or more of the integrated circuit semiconductor devices 100a, 100b, and 100c according to an embodiment. In some embodiments, each of the first transistor 210, the second transistor 212, the third transistor 214, and the fourth transistor 216 may include the above-mentioned fin-type transistor.

[0126] Figure 16 It is a block diagram showing a semiconductor chip 250 including an integrated circuit semiconductor device according to an embodiment.

[0127] Specifically, the semiconductor chip 250 may include a logic region 252. The logic region 252 may include a logic cell region 254 and an I / O region 256. A first transistor 258 and a second transistor 260 may be arranged in the logic cell region 254. The first transistor 258 and the second transistor 260 may be transistors of different conduction types. A third transistor 262 may be disposed in the I / O region 256.

[0128] The semiconductor chip 250 may include one or more of the integrated circuit semiconductor devices 100a, 100b, and 100c according to an embodiment. In some embodiments, each of the first transistor 258, the second transistor 260, and the third transistor 262 may include the above-mentioned fin-type transistor.

[0129] Figure 17 It is a block diagram showing an electronic device 300 including an integrated circuit semiconductor device according to an embodiment.

[0130] Specifically, the electronic device 300 may include a system-on-chip (SoC) 310. The SoC 310 may include a processor 311, an embedded memory 313, and a cache memory 315. The processor 311 may include one or more processor cores C1 to Cn. The processor cores C1 to Cn may process data and signals. The processor cores C1 and Cn may each include one or more of the integrated circuit semiconductor devices 100a, 100b, and 100c according to the embodiments.

[0131] The electronic device 300 may perform unique functions by using the processed data and the processed signals. For example, the processor 311 may be an application processor. The embedded memory 313 may exchange first data DATA1 with the processor 311. The first data DATA1 may be data obtained by being processed by each of the processor cores C1 and Cn or data to be processed by the processor cores C1 and Cn. The embedded memory 313 may manage the first data DATA1. For example, the embedded memory 313 may cache the first data DATA1. The embedded memory 313 may operate as a cache memory or a working memory of the processor 311.

[0132] The embedded memory 313 may be SRAM. The SRAM may operate at a higher speed than dynamic random access memory (DRAM). When the SRAM is embedded in the SoC 310, an electronic device 300 with a small size and operating at a faster speed can be implemented. In addition, when the SRAM is embedded in the SoC 310, the amount of active power consumed by the electronic device 300 can be reduced.

[0133] For example, the SRAM may include an integrated circuit semiconductor device according to the embodiments. The cache memory 315 and the processor cores C1 and Cn may be mounted on the SoC 310. The cache memory 315 may store cache data DATc. The cache data DATc may be data used by the processor cores C1 and Cn. The cache memory 315 may have a small storage capacity but may operate at a very fast speed.

[0134] For example, the cache memory 315 may include: SRAM, including an integrated circuit semiconductor device according to the embodiments. In the case of using the cache memory 315, the number of times the processor 311 accesses the embedded memory 313 and the time for the processor 311 to access the embedded memory 313 may be reduced. Therefore, in the case of using the cache memory 315, the operation speed of the electronic device 300 can be increased. For the sake of understanding, each of the cache memory 315 and the processor 311 in Figure 17 is shown as a separate element. However, the cache memory 315 may be configured to be included in the processor 311.

[0135] Figure 18 is an equivalent circuit diagram of an SRAM cell according to an embodiment.

[0136] Specifically, the SRAM cell can be implemented based on the integrated circuit semiconductor devices 100a, 100b, and 100c according to the embodiment. For example, the SRAM cell can be applied to the embedded memory 313 and / or the cache memory 315 described above, respectively. Figure 17 in the embedded memory 313 and / or the cache memory 315 described above.

[0137] The SRAM cell can include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first access transistor PA1, and a second access transistor PA2. The first and second pull-up transistors PU1 and PU2 can be PMOS transistors, and the first and second pull-down transistors PD1 and PD2 and the first and second access transistors PA1 and PA2 can be NMOS transistors.

[0138] The first pull-up transistor PU1 and the first pull-down transistor PD1 can configure a first inverter. The gate electrodes (gates) of the first pull-up transistor PU1 and the first pull-down transistor PD1 connected to each other can each correspond to the input terminal of the first inverter, and the first node N1 can correspond to the output terminal of the first inverter.

[0139] The second pull-up transistor PU2 and the second pull-down transistor PD2 can configure a second inverter. The gate electrodes (gates) of the second pull-up transistor PU2 and the second pull-down transistor PD2 connected to each other can each correspond to the input terminal of the second inverter, and the second node N2 can correspond to the output terminal of the second inverter.

[0140] The latch structure can be configured by a combination of the first and second inverters. The gate electrodes of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be electrically connected to the second node N2, and the gate electrodes of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be electrically connected to the first node N1.

[0141] The first source / drain of the first access transistor PA1 can be connected to the first node N1, and the second source / drain of the first access transistor PA1 can be connected to the first bit line BL1. The first source / drain of the second access transistor PA2 can be connected to the second node N2, and the second source / drain of the second access transistor PA2 can be connected to the second bit line BL2.

[0142] The gate electrodes of the first access transistor PA1 and the second access transistor PA2 may be electrically connected to the word line WL. Accordingly, the SRAM cell may be implemented by using the integrated circuit semiconductor devices 100a, 100b, and 100c according to the embodiments.

[0143] By way of summary and review, when the size (e.g., diameter or width) of the TSV is decreased, it may be difficult to reliably form the TSV. Accordingly, the embodiments provide an integrated circuit semiconductor device in which the TSV can be reliably formed.

[0144] Example embodiments have been disclosed herein, and although specific terms are employed, they are used only in a general descriptive sense and not for purposes of limitation. In some instances, those of ordinary skill in the art to which this application pertains will recognize that, unless otherwise explicitly stated, features, characteristics, and / or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An integrated circuit semiconductor device, comprising: A substrate, including a first surface and a second surface opposite to the first surface; A trench, in the substrate, the trench extending from the first surface of the substrate towards the second surface of the substrate; A through-silicon via (TSV) landing pad, in the trench, the TSV landing pad having: A first portion spaced apart from the first surface of the substrate, and A second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion; A TSV hole, in the substrate, the TSV hole extending from the second surface of the substrate and aligned with the bottom surface of the TSV landing pad, wherein the TSV hole is formed after forming the through-silicon via (TSV) landing pad; and A TSV, in the TSV hole and in contact with the bottom surface of the TSV landing pad, wherein the through-silicon via (TSV) landing pad and the TSV are different components.

2. The integrated circuit semiconductor device according to claim 1, wherein, The first surface is the front surface of the substrate, and the second surface is the back surface of the substrate.

3. The integrated circuit semiconductor device according to claim 1, wherein, The trench includes an upper trench and a lower trench communicating with each other, The second portion of the TSV landing pad is an upper TSV landing pad buried in the upper trench adjacent to the first surface of the substrate, and The first portion of the TSV landing pad is a lower TSV landing pad buried in the lower trench, the lower trench being between the upper trench and the second surface of the substrate.

4. The integrated circuit semiconductor device according to claim 3, wherein, At least a part of the width of the lower TSV landing pad is greater than a part of the width of the upper TSV landing pad.

5. The integrated circuit semiconductor device according to claim 3, wherein, The cross-sectional shape of the lower TSV landing pad is one of a circle, a semi-circle, and a polygon.

6. The integrated circuit semiconductor device according to claim 1, wherein, The trench has a first depth from the first surface, the TSV hole has a second depth from the second surface, and the second depth is greater than the first depth.

7. The integrated circuit semiconductor device according to claim 1, wherein, The TSV landing pad includes a first TSV landing pad and a second TSV landing pad spaced apart from each other, and the cross-sectional shape of the first TSV landing pad is different from the cross-sectional shape of the second TSV landing pad.

8. The integrated circuit semiconductor device according to claim 1, wherein, The width of the first portion of the TSV adjacent to the second surface is greater than the width of the second portion of the TSV adjacent to the TSV landing pad.

9. The integrated circuit semiconductor device according to claim 1, further comprising: A trench liner layer and a via liner layer, on the inner sidewalls of the trench and the TSV hole respectively.

10. An integrated circuit semiconductor device, comprising: A substrate, including a first surface and a second surface opposite to the first surface; An active element, on the first surface of the substrate; A through-silicon via (TSV) landing pad, connected to the active element, the TSV landing pad being buried in a corresponding trench in the substrate, and each TSV landing pad in the TSV landing pad having: A first portion spaced apart from the first surface of the substrate, and A second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion; A TSV hole, in the substrate, the TSV hole extending from the second surface of the substrate and aligned with the bottom surface of the TSV landing pad, wherein the TSV hole is formed after forming the through-silicon via (TSV) landing pad; and TSVs are respectively connected to the TSV landing portions, and the TSVs are respectively buried in the TSV holes. Some of the TSV landing portions among the TSV landing portions are connected to a power rail portion or a ground rail portion, and wherein, the through-silicon via TSV landing portion and the TSV are different elements.

11. The integrated circuit semiconductor device according to claim 10, wherein, Each of the trenches includes: an upper trench extending to a specific depth from the first surface; and a lower trench extending from the upper trench toward the second surface, the width of the lower trench being greater than the width of the upper trench, and the TSV landing portion is buried in the upper trench and the lower trench.

12. The integrated circuit semiconductor device according to claim 10, further comprising: A local wiring layer on the first surface of the substrate, the local wiring layer includes local wirings connected to the TSV landing portions, and the TSV landing portions are connected to the source regions and drain regions of the active elements through the local wirings.

13. The integrated circuit semiconductor device according to claim 12, further comprising: An upper multi-layer wiring layer on the local wiring layer.

14. The integrated circuit semiconductor device according to claim 10, further comprising: A lower multi-layer wiring layer on the second surface of the substrate; and Power and ground terminals on the lower multi-layer wiring layer and connected to the TSV landing portions, the power and ground terminals are connected to the power rail portion or the ground rail portion via the lower multi-layer wiring layer and the TSVs.

15. The integrated circuit semiconductor device according to claim 10, further comprising: A lower multi-layer wiring layer on the second surface of the substrate; and Signal input / output I / O terminals on the lower multi-layer wiring layer and connected to the TSV landing portions, the signal input / output I / O terminals are connected to the power rail portion or the ground rail portion via the lower multi-layer wiring layer and the TSVs.

16. The integrated circuit semiconductor device according to claim 10, further comprising: An upper multi-layer wiring layer on the first surface of the substrate; A lower multi-layer wiring layer on the second surface of the substrate; Additional TSVs in the substrate; and Signal input / output I / O terminals on the lower multi-layer wiring layer, and connected to the active elements through the upper multi-layer wiring layer via the lower multi-layer wiring layer and the additional TSVs.

17. An integrated circuit semiconductor device, comprising: A substrate including a first surface and a second surface opposite to the first surface; Active elements on the first surface of the substrate, the active elements include: finFET transistors having pins on the first surface of the substrate, the pins extending in a first direction, Gate electrodes extending in a second direction perpendicular to the first direction, and Source regions and drain regions at opposite sides of each of the gate electrodes in the gate electrodes; Through-silicon via TSV landing portions connected to the source regions and drain regions of the finFET transistors and buried in the substrate, each of the TSV landing portions among the TSV landing portions has: A first portion spaced apart from the first surface of the substrate, and A second portion between the first portion and the first surface of the substrate, the first portion being wider than the second portion; and TSVs connected to the TSV landing portions and buried in TSV holes aligned with the bottom surfaces of the TSV landing portions starting from the second surface, wherein the TSV holes are formed after the through-silicon via TSV landing portions are formed. Among them, some of the TSV landing portions in the TSV landing portion are connected to a power supply rail portion or a ground rail portion provided in the same direction as the first direction, and Among them, the through-silicon via TSV landing portion and the TSV are different elements.

18. The integrated circuit semiconductor device according to claim 17, further comprising: The signal input / output I / O terminal is electrically connected to some of the TSV landing portions in the TSV landing portion.

19. The integrated circuit semiconductor device according to claim 17, wherein, The first surface is the front surface of the substrate, The second surface is the back surface of the substrate, The preliminary substrate is also attached to the first surface, and The power supply and ground terminals connected to the lower multi-layer wiring layer are also positioned on the second surface.

20. The integrated circuit semiconductor device according to claim 17, wherein, Each of the TSV landing portions in the TSV landing portion has a specific depth from the first surface, and the cross-sectional shape of each of the TSV landing portions in the TSV landing portion is one of a circle, a semicircle, and a polygon.

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