Isolation regions in integrated circuit structures

Abstract

Disclosed herein are isolation regions in integrated circuit (IC) structures and related methods and components. For example, in some embodiments, an IC component can include: a first region including silicon; a second region including alternating layers of a second material and a third material, where the second material includes silicon and germanium, the third material includes silicon, and each of the layers in the second region has a thickness less than 3 nanometers; and a third region including alternating layers of the second material and the third material, where each of the layers in the third region has a thickness greater than 3 nanometers, and the second region is between the first region and the third region.

Description

Background Technology

[0001] Electronic components can include active electrical elements, such as transistors. The design of these elements can affect the size, performance, and reliability of the electronic components. Attached Figure Description

[0002] The embodiments will be readily understood through the following detailed description in conjunction with the accompanying drawings. For ease of description, similar reference numerals denote similar structural elements. In the various figures of the drawings, embodiments are shown by way of example rather than limitation.

[0003] Figure 1A-1D This is a cross-sectional view of an integrated circuit (IC) structure according to various embodiments.

[0004] Figures 2A-2D , Figures 3A-3D , Figures 4A-4D , Figures 5A-5D , Figures 6A-6D , Figures 7A-7D , Figures 8A-8D , Figures 9A-9D , Figure 10A-10D , Figure 11A-11D , Figure 12A-12D , Figures 13A-13D , Figures 14A-14D , Figures 15A-15D , Figure 16A-16D , Figures 17A-17D , Figures 18A-18D , Figures 19A-19D , Figure 20A-20D , Figures 21A-21D , Figures 22A-22D , Figures 23A-23D , Figures 24A-24D , Figures 25A-25D , Figures 26A-26D , Figures 27A-27D , Figures 28A-28D , Figures 29A-29D , Figures 30A-30D , Figures 31A-31D , Figures 32A-32D , Figures 33A-33D , Figures 34A-34D , Figures 35A-35D , Figures 36A-36D , Figures 37A-37D , Figures 38A-38D , Figures 39A-39D , Figure 40A-40D ,and Figures 41A-41D Manufacturing according to various embodiments Figure 1A-1D Cross-sectional views of various stages in an exemplary process of an IC structure.

[0005] Figures 42A-42D This is a cross-sectional view of another IC structure according to various embodiments.

[0006] Figure 43This is a cross-sectional view of another IC structure according to various embodiments.

[0007] Figure 44-47 Exemplary IC structure layouts according to various embodiments are shown.

[0008] Figure 48 This is a top view of a wafer and die that may include an IC structure, according to any of the embodiments disclosed herein.

[0009] Figure 49 This is a side cross-sectional view of an IC component that may include an IC structure, according to any of the embodiments disclosed herein.

[0010] Figure 50 This is a side cross-sectional view of an IC package that may include an IC structure, according to any of the embodiments disclosed herein.

[0011] Figure 51 This is a side cross-sectional view of an IC component assembly that may include an IC structure, according to any of the embodiments disclosed herein.

[0012] Figure 52 This is a block diagram of an exemplary electrical device that may include an IC structure according to any of the embodiments disclosed herein. Detailed Implementation

[0013] This document discloses isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region comprising silicon; a second region comprising alternating layers of a second and a third material, wherein the second material comprises silicon and germanium, the third material comprises silicon, and each layer in the second region has a thickness of less than 3 nanometers; and a third region comprising alternating layers of a second and a third material, wherein each layer in the third region has a thickness of greater than 3 nanometers, and the second region lies between the first and third regions.

[0014] Gate-all-around (GAA) transistors can comprise a stack of vertically oriented lateral semiconductor channels (e.g., line channels) encased in a gate material. During operation, current may flow through these semiconductor channels and be modulated by electrical signals applied to the gate and adjacent source / drain (S / D) regions. However, during operation, undesirable parasitic channels may also form beneath the transistor (e.g., in a substrate or other underlying material), which can degrade transistor performance (e.g., potentially causing elevated source-to-drain leakage current in the transistor's off-state). Such parasitic channel problems can be exacerbated in GAA transistors compared to fin-based transistors because the parasitic "sub-fin" regions may be too wide to provide any short-channel control to suppress leakage.

[0015] This paper discloses a novel IC structure that provides improved isolation between device regions (e.g., S / D and channel regions) and underlying material to mitigate or eliminate source-to-drain leakage through parasitic channels. The fabrication techniques disclosed herein can provide this isolation without using expensive conventional silicon-on-insulator (SOI) substrates and without adding significant fabrication complexity (thus accelerating adoption and reducing costs).

[0016] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description, wherein similar reference numerals always denote similar parts, and wherein illustrative embodiments that may be implemented are shown. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as limiting.

[0017] Multiple operations are described as a series of discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the presented order. The described operations may be performed in an order different from that of the described embodiment. In other embodiments, multiple additional operations may be performed and / or the described operations may be omitted.

[0018] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The phrase "A or B" means (A), (B), or (A or B). The figures are not necessarily drawn to scale. Although many figures show straight structures with flat walls and right-angle corners, this is only for illustrative purposes, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

[0019] The specification uses the phrases "in one embodiment" or "in an embodiment," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "having," etc., used with respect to embodiments of this disclosure are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" indicates a range including both X and Y. As used herein, unless otherwise stated, the term "insulating" means "electrically insulating." For convenience, the phrase "Figure 1" can be used to refer to... Figure 1A-1D The collection of attached figures; the phrase "Figure 2" can be used to refer to... Figures 2A-2D A collection of attached images.

[0020] Figure 1 provides a cross-sectional view of an IC structure 100 according to various embodiments. Specifically, Figure 1A Through Figure 1C and 1D A cross-sectional view taken from section AA (perpendicular to the longitudinal axis of channel region 202 and across the source / drain regions 128 / 130 of different channel regions 202). Figure 1B Through Figure 1C and 1D A cross-sectional view taken from section BB (perpendicular to the longitudinal axis of channel region 202 and transverse to the gate 204 spanning multiple channel regions 202). Figure 1C Through Figure 1A and 1B A cross-sectional view taken from section CC (along the longitudinal axis of channel region 202), and Figure 1D Through Figure 1A and 1B The cross section DD (parallel to the longitudinal axis of the channel region 202 between adjacent channel regions 202). Sub-figures “A”, “B”, “C”, and “D” of FIG2-41 share the same viewpoint as sub-figures “A”, “B”, “C”, and “D” of FIG1, respectively. Although the various figures in the figures depict a specific number of device regions 206 (e.g., three), channel regions 202 in device regions 206 (e.g., three), and a specific arrangement of channel material 106 in channel regions 202 (e.g., two lines), this is merely for illustrative purposes, and IC structure 100 may include more or fewer device regions 206 and / or channel regions 202, and / or other arrangements of channel material 106.

[0021] Device regions 206 may be vertically oriented relative to the underlying substrate 102, wherein a plurality of device regions 206 are arranged along the substrate 102. The substrate 102 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). For example, the substrate 102 may include a crystalline substrate formed using bulk silicon. The substrate 102 may include a silicon dioxide layer on a bulk silicon or gallium arsenide substrate. The substrate 102 may include a converted layer (e.g., a silicon layer that has been converted to silicon dioxide during an oxygen-based annealing process). In some embodiments, the substrate 102 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, Group III-V, or Group IV may also be used to form the substrate 102. While some examples of materials that can form the substrate 102 are described herein, any material or structure that can serve as the basis of the IC structure 100 may be used. The substrate 102 can be a single-unit die (e.g., Figure 48The die 1502) or wafer (e.g., Figure 48 This is a portion of a wafer 1500. In some embodiments, the substrate 102 itself may include interconnect layers, insulating layers, passivation layers, etch stop layers, additional device layers, etc. As shown in FIG1, the substrate 102 may include a base 222, around which a dielectric material 110 may be disposed; the dielectric material 110 may include any suitable material, such as a shallow trench isolation (STI) material (e.g., an oxide material, such as silicon oxide).

[0022] IC structure 100 may include one or more device regions 206, the device regions 206 having a vertical axis (from... Figure 1A and 1B Entering the page from the user's perspective, and according to... Figure 1C and 1D The channel material 106 (viewed from left to right) is used in the device region 206. The channel material 106 of the device region 206 can be arranged in any of a variety of ways. For example, FIG1 shows the channel material 106 of the device region 206 as comprising multiple semiconductor lines (e.g., nanowires or nanoribbons in a GAA, forksheets, dual-gate, or pseudo-dual-gate transistors). While the various figures depict a specific number of lines in the channel material 106 of the device region 206, this is for illustrative purposes only, and the device region 206 may include more or fewer lines as the channel material 106. More generally, any of the IC structures 100 disclosed herein or their substructures (e.g., insulating material region 158 discussed below) can be used in transistors having any desired architecture, such as forksheet transistors, dual-gate transistors, or pseudo-dual-gate transistors. In some embodiments, the channel material 106 may comprise silicon and / or germanium. In some embodiments, the channel material 106 may include indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, or other materials classified as Group II-VI, Group III-V, or Group IV. In some embodiments, the channel material 106 may include a semiconductor oxide (e.g., indium gallium zinc oxide). In some embodiments, the material composition of the channel material 106 used in different wires in a particular device region 206 may be different or the same.

[0023] Source / drain (S / D) regions 128 / 130 can be electrically contacted with the longitudinal ends of the channel material 106, thereby allowing current to flow from one S / D region 128 / 130 through the channel material 106 to another S / D region 128 / 130 during operation (after an appropriate potential is applied to the S / D region 128 / 130 via the S / D contact 164). Although Figure 1A(And other figures in the accompanying drawings) depict a single S / D contact 164 spanning (“short-circuiting”) multiple S / D regions 128 / 130, but this is merely illustrative, and the S / D contact 164 may be arranged to isolate and connect the individual S / D regions 128 / 130, as desired. As discussed further below with reference to Figures 2-42, S / D regions 128 may have a specific dopant type (i.e., n-type or p-type), while S / D regions 130 may have the opposite dopant type (i.e., p-type or n-type, respectively); the specific arrangement of S / D regions 128 / 130 in the figures is merely illustrative, and any desired arrangement may be used (e.g., with appropriate selective masks). S / D regions 128 / 130 may be laterally defined by insulating material regions including dielectric material 112, dielectric material 118, and dielectric material 120; these insulating material regions may provide barriers between S / D regions 128 / 130 in adjacent device regions 206. Figure 1A As shown, in some embodiments, dielectric material 112 may have a U-shaped cross-section with "spacers" formed by dielectric material 118 thereon and dielectric material 120 therebetween.

[0024] In some embodiments, S / D regions 128 / 130 may include silicon alloys such as silicon-germanium or silicon carbide. In some embodiments, S / D regions 128 / 130 may include dopants such as boron, arsenic, or phosphorus. In some embodiments, S / D regions 128 / 130 may include one or more alternating semiconductor materials such as germanium or group III-V materials or alloys. For example, for a p-type metal-oxide-semiconductor (PMOS) transistor, S / D regions 128 / 130 may include group IV semiconductor materials such as silicon, germanium, silicon-germanium, germanium-tin, or silicon-germanium alloyed with carbon. Exemplary p-type dopants in silicon, silicon-germanium, and germanium include boron, gallium, indium, and aluminum. For example, for an n-type metal-oxide-semiconductor (NMOS) transistor, the S / D region 128 / 130 may include group III-V semiconductor materials, such as indium, aluminum, arsenic, phosphorus, gallium, and antimony, as well as some exemplary compounds, including indium aluminum arsenide, indium arsenide, indium gallium arsenide, indium gallium arsenide, gallium antimony, gallium aluminum antimony, indium gallium antimony, or indium gallium phosphide.

[0025] The channel material 106 may contact the gate dielectric 136. In some embodiments, the gate dielectric 136 may surround the channel material 106 (e.g., as shown in FIG. 1, when the channel material 106 comprises a wire). The gate dielectric 136 may comprise a single layer or a stack of layers. One or more layers may comprise silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may comprise elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric 136 include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and zinc lead niobate. In some embodiments, when using a high-k material, an annealing process can be performed on the gate dielectric 136 to improve its quality.

[0026] A gate dielectric 136 may be disposed between the channel material 106 and the gate metal 138. In some embodiments, the gate metal 138 may surround the channel material 106 (e.g., as shown in FIG. 1, when the channel material 106 comprises a line). The gate metal 138 and the gate dielectric 136 together may provide a gate 204 for the associated channel material 106 in the associated channel region 202, wherein the impedance of the channel material 106 is modulated by a potential applied to the associated gate 204 (through the gate contact 140). Depending on whether the transistor in which the gate metal 138 is a part is a PMOS transistor or an NMOS transistor, the gate metal 138 may include at least one p-type work function metal or an n-type work function metal (or both). In some embodiments, the gate metal 138 may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. For other purposes, other metal layers may be included, such as barrier layers (e.g., tantalum, tantalum nitride, aluminum-containing alloys, etc.). In some embodiments, gate metal 138 may include a capping layer (e.g., copper, gold, cobalt, or tungsten) to reduce resistance. For PMOS transistors, metals that can be used for gate metal 138 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed herein with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for gate metal 138 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment). In some embodiments, gate metal 138 may include a (increasing or decreasing) concentration gradient of one or more of these materials. Dielectric material 118 can separate gate metal 138, gate dielectric 136, and gate contact 140 from adjacent S / D contact 164, and dielectric material 124 can separate gate dielectric 136 from adjacent S / D regions 128 / 130. For example, dielectric materials 118 and 124 may include silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, silicon oxynitride, or carbon-doped silicon oxynitride. Channel material 106, gate dielectric 136, gate metal 138, and associated S / D regions 128 / 130 can together form a transistor.

[0027] In the IC structure 100 of FIG1, an insulating material region 158 may be present between the S / D regions 128 / 130 and the substrate 102; as described above, the presence of such an insulating material region 158 helps to isolate the S / D regions 128 / 130 from the underlying material, and thus mitigates or eliminates the formation of undesirable parasitic channels in the underlying material. The insulating material region 158 may comprise an oxide of the channel material 106; for example, if the channel material 106 is silicon, the insulating material region 158 may comprise silicon oxide. As discussed below with reference to FIG2-41, the insulating material region 158 may be formed during the “release” of the channel material 106 from the adjacent layer of the sacrificial material 104, and thus the insulating material region 158 may be formed in the IC structure 100 without increasing the manufacturing complexity of the IC structure 100.

[0028] The dimensions of the components in the IC structure of Figure 1 (and other embodiments disclosed herein) can take any suitable form. For example, in some embodiments, the gate length 208 of the gate 204 can be between 3 nanometers and 100 nanometers; different gates 204 in device region 206 can have the same gate length 208 or different gate lengths 208, as desired. In some embodiments, the width 210 of the channel material 106 can be between 3 nanometers and 30 nanometers. In some embodiments, the thickness 212 of the channel material 106 can be between 1 nanometer and 500 nanometers (e.g., between 5 nanometers and 40 nanometers when the channel material 106 is a line). In some embodiments where the channel region 202 includes semiconductor lines, the spacing 214 between adjacent lines in the channel region 202 can be between 5 nanometers and 40 nanometers.

[0029] In some embodiments, IC structure 100 may be part of a storage device, and the transistors of IC structure 100 may store information in IC structure 100 or facilitate access to storage elements of the storage device (e.g., read and / or write). In some embodiments, IC structure 100 may be part of a processing device. In some embodiments, IC structure 100 may be part of a device that includes memory and logic devices (e.g., a processor and a cache) (e.g., in a single die 1502, as discussed below). More generally, IC structure 100 disclosed herein may be part of a storage device, a logic device, or both.

[0030] Figures 2-41 illustrate stages in an exemplary process for manufacturing the IC structure 100 of Figure 1. While the operation of this process can be illustrated with reference to specific embodiments of the IC structure 100 disclosed herein, the process of Figures 2-41 and its variations can be used to form any suitable IC structure. Operations are shown in Figures 2-41 in a specific number and order, but can be reordered and / or repeated as desired (e.g., different operations performed in parallel when multiple IC structures 100 are manufactured simultaneously).

[0031] Figure 2 illustrates an assembly including a substrate 102, a stack 148 of material layers on the substrate 102, and a stack 230 of material layers on the substrate 102. The stack 148 of material layers may include one or more second material layers 152 spaced apart from each other by intermediate first material layers 150, while the stack 230 of material layers may include one or more channel material layers 106 spaced apart from each other (and spaced apart from the stack 148) by intermediate sacrificial material layers 104. As discussed further below, the size and arrangement of the material layers in the stack 230 of the assembly of Figure 2 correspond to the desired size and arrangement of the channel material 106 in the IC structure 100, and therefore the material layers in the assembly of Figure 2 may differ from the specific embodiment shown in Figure 2. For example, the thickness of the channel material layer 106 may correspond to the channel thickness 212 discussed above (although the thickness of the channel material layer 106 may differ from the final channel thickness 212 due to material loss during processing, etc.), and the thickness of the sacrificial material layer 104 may correspond to the line spacing 214 discussed above (although the thickness of the sacrificial material layer 104 may differ from the final line spacing 214 due to material loss during processing, etc.). The sacrificial material 104 may be any material that can be appropriately and selectively removed in subsequent processing operations (as discussed below with reference to FIG. 30). For example, the sacrificial material 104 may be silicon germanium, and the channel material 106 may be silicon. In another example, the sacrificial material 104 may be silicon dioxide, and the channel material 106 may be silicon or germanium. In yet another example, the sacrificial material 104 may be gallium arsenide, and the channel material 106 may be indium gallium arsenide, germanium, or silicon germanium. The components in Figure 2 can be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), metal-organic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), physical vapor deposition (PVD), atomic layer deposition (ALD), or layer transfer processes.

[0032] The dimensions and material composition of the first material 150 and the second material 152 can be selected such that techniques used to facilitate the “release” of the channel material 106 from the sacrificial material 104 (e.g., as discussed below with reference to FIG. 36) transform the material of the stack 148 into a dielectric material (forming the insulating material region 158, as discussed above with reference to FIG. 1). For example, in some conventional techniques, the channel material 106 can be “released” during fabrication by performing a cleaning operation that oxidizes and etches the channel material 106 at a relatively slow rate, but oxidizes and etches the sacrificial material 104 at a much faster rate. In such an embodiment, the first material 150 may be selected to have the same material composition as the sacrificial material 104, the second material 152 may be selected to have the same material composition as the channel material 106, and the thicknesses of the first material layer 150 and the second material layer 152 may be less than the thicknesses of the sacrificial material layer 104 and the channel material layer 106, respectively (i.e., less than the line spacing 214 and the channel thickness 212, respectively), so that during a cleaning operation, the first material 150 can be substantially etched away, while the second material 152 is oxidized, resulting in the insulating material region 158 (discussed below with reference to FIG. 36).

[0033] In some such embodiments, the sacrificial material 104 and the first material 150 may comprise silicon germanium (e.g., silicon germanium having a germanium content greater than 30 atomic percent), and the channel material 106 and the second material 152 may comprise silicon. Furthermore, in some such embodiments, the thickness of the first material layer 150 and the second material layer 152 may be less than 3 nanometers, and the thickness of the sacrificial material layer 104 and the channel material layer 106 (i.e., the line spacing 214 and the channel thickness 212) may be greater than 3 nanometers. Other combinations of materials and thicknesses may be appropriately used in accordance with the teachings disclosed herein.

[0034] Figure 3 illustrates the assembly after a patterned hard mask 108 has been formed on the assembly of Figure 2. Forming the patterned hard mask 108 may include depositing a hard mask (using any suitable method) and then selectively removing portions of the hard mask 108 (e.g., using photolithography) to form the patterned hard mask 108. In some embodiments, the pattern of the patterned hard mask 108 may first be formed on the initially deposited hard mask in another material, and the pattern may then be transferred from the other material into the hard mask 108. The location of the hard mask 108 may correspond to device region 206 in the IC structure 100, as discussed further below. In the embodiment of Figure 3, the hard mask 108 may be patterned as a plurality of parallel rectangular portions (corresponding to fins 220 discussed below).

[0035] Figure 4 illustrates the assembly after fins 220 have been formed in a material stack of the assembly of Figure 2 according to a patterned hard mask 108. Etching techniques can be used to form the fins 220, including wet and / or dry etching schemes as well as isotropic and / or anisotropic etching schemes. The fins 220 may include sacrificial material 104 and channel material 106, as well as a portion of substrate 102; the portion of substrate 102 included in the fins 220 provides a base 222. The width of the fins 220 may be equal to the width 210 of the channel material 106, as discussed above. Any suitable number of fins 220 (e.g., greater than or less than 3) may be included in the assembly of Figure 4. Although the fins 220 depicted in Figure 4 (and other figures) are perfectly rectangular, this is merely for illustrative purposes, and in actual manufacturing settings, the shape of the fins 220 may not be perfectly rectangular. For example, the fins 220 may be tapered, widening towards the substrate 102. The top surface of the fin 220 may not be flat, but may be curved, rounded into the side surface of the fin 220, and these non-ideal features may be incorporated into subsequent processing operations. In some embodiments, the spacing 101 of the fin 220 may be between 20 nanometers and 50 nanometers (e.g., between 20 nanometers and 40 nanometers).

[0036] Figure 5 illustrates the assembly after the dielectric material 110 is formed between the fins 220 on the substrate 102 of the assembly of Figure 4. The dielectric material 110 may include any suitable material, such as an STI material (e.g., an oxide material, such as silicon oxide). The dielectric material 110 can be formed by depositing the dielectric material 110 at a uniform thickness and then recessing the dielectric material 110 back to a desired thickness. In some embodiments, the thickness of the dielectric material 110 may be selected such that the top surface of the dielectric material 110 is above the top surface of the base 222 (e.g., substantially coplanar with the top surface of the stack 148). In some embodiments, the height 103 of the fins 220 above the top surface of the dielectric material 110 may be between 40 nm and 100 nm (e.g., between 50 nm and 70 nm).

[0037] Figure 6 shows the assembly after a conformal layer of dielectric material 112 has been formed on top of the assembly of Figure 5. Any suitable technique (e.g., ALD) can be used to form the dielectric material 112. The dielectric material 112 may comprise any suitable material (e.g., silicon oxide).

[0038] Figure 7 shows the assembly after the dielectric material 114 has been formed on top of the assembly of Figure 6. The dielectric material 114 may extend over the top surface of the fin 220, as shown, and may be used as a "dummy gate". The dielectric material 114 may include any suitable material (e.g., polysilicon).

[0039] Figure 8 illustrates the assembly after a patterned hard mask 116 has been formed on the assembly of Figure 7. The hard mask 116 may comprise any suitable material (e.g., silicon nitride, carbon-doped silicon oxide, or carbon-doped silicon oxynitride). The hard mask 116 may be patterned to be oriented perpendicular to the longitudinal axis of the fin 220 (according to...). Figure 8C and 8D The bar (entering and exiting the page from the user's perspective) corresponds to the position of the gate 204 in the IC structure 100, as discussed further below.

[0040] Figure 9 shows the assembly after the dielectric material 114 (“dummy gate”) of the assembly of Figure 8 has been etched using a patterned hard mask 116 as a mask. The location of the remaining dielectric material 114 can correspond to the location of the gate 204 in the IC structure 100, as discussed further below.

[0041] Figure 10 illustrates the assembly after a conformal layer of dielectric material 118 is deposited on the assembly of Figure 9, and then a directional “down” etching is performed to remove the dielectric material 118 from the horizontal surface, leaving the dielectric material 118 as a “spacer” on the side of the exposed surface, as shown. The dielectric material 118 can be deposited to any desired thickness using any suitable technique (e.g., ALD). The dielectric material 118 can comprise any suitable dielectric material (e.g., silicon oxycarbonitride). The dielectric material 118 may be adjacent to fins 220 in the volume replaced by S / D regions 128 / 130, as discussed below.

[0042] Figure 11 shows the assembly after the dielectric material 120 has been deposited on the assembly of Figure 10. The dielectric material 120 can be deposited on the assembly of Figure 10 with a uniform thickness, and can then be polished (e.g., by chemical mechanical polishing (CMP)) or otherwise recessed such that the top surface of the dielectric material 120 is coplanar with the top surface of the patterned hard mask 116, as shown. Figure 11D and 11C As shown. The dielectric material 120 may include any suitable material (e.g., oxides, such as silicon oxide).

[0043] Figure 12 shows the assembly after the hard mask 126 has been deposited on the assembly of Figure 11. The hard mask 126 can have any suitable material composition; for example, in some embodiments, the hard mask 126 may include titanium nitride.

[0044] Figure 13 illustrates the assembly after the hard mask 126 of the component of Figure 12 has been patterned to selectively remove the hard mask 126 in areas corresponding to the S / D regions 130, while otherwise leaving the hard mask 126 in place. Any suitable patterning technique (e.g., photolithography) can be used to pattern the hard mask 126. The specific arrangement of the S / D regions 130 in the IC structure 100 depicted in the various figures (and therefore the specific layout of the patterned hard mask 126) is merely exemplary, and any desired arrangement can be used; for example, Figure 42 depicts an IC structure 100 with a different arrangement of the S / D regions 130.

[0045] Figure 14 shows the assembly after the exposed dielectric material 120 (i.e., the dielectric material 120 not protected by the hard mask 126) of the assembly of Figure 13 has been recessed. The exposed dielectric material 120 can be recessed using any suitable selective etching technique (e.g., isotropic etching). The dielectric material 120 can be retained in the area not protected by the hard mask 126.

[0046] Figure 15 shows the assembly after some of the dielectric material 118 exposed in the assembly of Figure 14 has been removed. This operation can widen the "canyon" between adjacent portions of the hard mask 116 / dielectric material 114, thereby facilitating subsequent operations. In some embodiments, the removal of some of the dielectric material 118 can be achieved by partially isotropic etching (e.g., partially isotropic etching of the nitride portion when the dielectric material 118 comprises a nitride).

[0047] Figure 16 shows the assembly after further recessing of the exposed dielectric material 120 (i.e., the dielectric material 120 not protected by the hard mask 126) of the assembly of Figure 15. The exposed dielectric material 120 can be recessed using any suitable selective etching technique (e.g., isotropic etching). The dielectric material 120 can be retained in the area not protected by the hard mask 126.

[0048] Figure 17 illustrates the assembly after conformally depositing additional dielectric material 118 on the assembly of Figure 16, and then performing a "downward" etching in another direction to remove the dielectric material 118 from the horizontal surface, thereby "repairing" the dielectric material 118 into a "spacer" on the side of the exposed surface, as shown. As shown, the etching of Figure 17 (e.g., reactive ion etching (RIE)) can also remove the dielectric material 112 from the top surface of the sacrificial material 104.

[0049] Figure 18 shows the assembly after (e.g., using any suitable etching technique) removing portions of the sacrificial material 104 and channel material 106 not covered by the hard mask 126 from the assembly of Figure 17 to form the opening volumes 224. As discussed further below, these opening volumes 224 may correspond to the locations of the S / D regions 130 in the IC structure 100, and as shown, the opening volumes 224 are self-aligned with the dielectric material 112.

[0050] Figure 19 illustrates the situation where the exposed sacrificial material 104 of the component in Figure 18 is recessed without simultaneously recessing the exposed channel material 106 (e.g., Figure 19C (As shown) the subsequent components. Any suitable selective etching technique can be used. Because the lateral recess of this portion of the exposed sacrificial material 104 is self-aligned with the exposed channel material 106, the width of the recess of the exposed sacrificial material 104 across the channel material 106 can be uniform (i.e., from...). Figure 19A (The left and right directions of the viewpoint).

[0051] Figure 20 illustrates the assembly after conformally depositing dielectric material 124 over the assembly of Figure 19. Dielectric material 124 may include any suitable material (e.g., a low-k dielectric material) and may be deposited to fill depressions formed by recessing the exposed sacrificial material 104 (as discussed above with reference to Figure 19). In some embodiments, conformally depositing dielectric material 124 may include multiple rounds (e.g., three rounds) of deposition of one or more dielectric materials.

[0052] Figure 21 shows the assembly after the dielectric material 124 of the assembly of Figure 20 has been recessed. The exposed dielectric material 124 can be recessed using any suitable selective etching technique (e.g., isotropic etching). Figure 21C As shown, the dielectric material 124 can be retained on the side surface of the sacrificial material 104 near the opening volume 224. For example... Figure 21C As shown, the amount of recess can be such that the recessed surface of the dielectric material 124 is flush with (not shown) or slightly extends beyond the side surface of the channel material 106. Excessive recess of the exposed dielectric material 124 beyond the side surface of the channel material 106 may lead to degraded device performance (e.g., due to increased parasitic contact-to-gate coupling capacitance) and / or device defects (e.g., due to contact-to-gate short circuits).

[0053] Figure 22 shows the assembly after the S / D region 130 has been formed in the opening volume 224 of the assembly of Figure 21. The S / D region 130 can be formed by epitaxial growth, which forms a seed layer from the exposed surfaces of the substrate 102 and the channel material 106, and the lateral extent of the S / D region 130 (e.g., in...) Figure 22AThe S / D region 130 (in the left-right direction) may be limited by a dielectric material 112 adjacent to the opening volume 224. In some embodiments, the S / D region 130 may include an n-type epitaxial material (e.g., a heavily in-situ phosphorus-doped material for NMOS transistors). In some embodiments, the epitaxial growth of the S / D region 130 may include an initial nucleation operation to provide a seed layer, followed by a main epitaxial operation in which the remainder of the S / D region 130 is formed on the seed layer.

[0054] Figure 23 shows the assembly after a conformal layer of dielectric material 142 has been deposited on the assembly of Figure 22. The dielectric material 142 may be a contact etch stop layer (CESL) and may be formed of any suitable material (e.g., silicon nitride).

[0055] Figure 24 illustrates the deposition of dielectric material 122 on the assembly of Figure 23, and then the dielectric material 122 and dielectric material 142 are polished to expose the assembly behind the hard mask 126. In some embodiments, dielectric material 122 may be a pre-metal dielectric (PMD), such as an oxide material (e.g., silicon oxide).

[0056] Figure 25 illustrates the assembly after removing the hard mask 126 from the assembly of Figure 24, then depositing and patterning the hard mask 127. The hard mask 127 can have any suitable material composition; for example, in some embodiments, the hard mask 127 may comprise titanium nitride. The hard mask 127 can be patterned to selectively remove the hard mask 127 in regions corresponding to the S / D regions 128, while otherwise leaving the hard mask 127 in place. Any suitable patterning technique (e.g., photolithography) can be used to pattern the hard mask 127. As noted above, the specific arrangement of the S / D regions 128 in the IC structure 100 depicted in the various figures (and therefore the specific layout of the patterned hard mask 127) is merely exemplary, and any desired arrangement can be used; for example, Figure 42 depicts an IC structure 100 with different arrangements of the S / D regions 128.

[0057] Figure 26 shows the assembly after the exposed dielectric material 120 (i.e., the dielectric material 120 not protected by the hard mask 127) of the assembly of Figure 25 has been recessed. The exposed dielectric material 120 can be recessed using any suitable selective etching technique, such as isotropic etching.

[0058] Figure 27 shows the assembly after some of the exposed dielectric material 118 in the assembly of Figure 26 has been removed. This operation can widen the "canyon" between adjacent portions of the hard mask 116 / dielectric material 114, thereby facilitating subsequent operations. In some embodiments, the removal of some of the dielectric material 118 can be achieved by partially isotropic etching (e.g., partially isotropic etching of the nitride when the dielectric material 118 comprises nitride).

[0059] Figure 28 shows the assembly after further recessing of the exposed dielectric material 120 (i.e., the dielectric material 120 not protected by the hard mask 127) of the assembly of Figure 27. Any suitable selective etching technique (e.g., isotropic etching) can be used to recess the exposed dielectric material 120.

[0060] Figure 29 illustrates the assembly after conformally depositing additional dielectric material 118 on the assembly shown in Figure 28, and then performing a "downward" etching in another direction to remove the dielectric material 118 from the horizontal surface, thereby "repairing" the dielectric material 118 into a "spacer" on the side of the exposed surface, as shown. As shown, the etching (e.g., RIE) of Figure 29 can also remove the dielectric material 112 from the top surface of the sacrificial material 104.

[0061] Figure 30 shows the assembly after (e.g., using any suitable etching technique) removing portions of the sacrificial material 104 and channel material 106 from the assembly of Figure 29 that were not covered by the hard mask 127 to form the opening volumes 225. As discussed further below, these opening volumes 225 may correspond to the locations of the S / D regions 128 in the IC structure 100, and as shown, the opening volumes 225 are self-aligned with the dielectric material 112.

[0062] Figure 31 shows the assembly after conformally depositing and recessing the dielectric material 124 by recessing the exposed sacrificial material 104 of the assembly of Figure 30 without simultaneously recessing the exposed channel material 106. These operations can take any of the forms discussed above with reference to Figures 19-21. Figure 31C As shown, dielectric material 124 can be retained on the side surface of sacrificial material 104 near the opening volume 225.

[0063] Figure 32 illustrates the assembly after forming an S / D region 128 in the opening volume 225 of the assembly of Figure 31 to deposit a conformal layer of dielectric material 154, and after depositing dielectric material 156. The S / D region 128 can be formed by epitaxial growth, which forms a seed layer from the exposed surfaces of the substrate 102 and the channel material 106, and the lateral extent of the S / D region 128 (e.g., in…) Figure 32AThe S / D region 130 (in the left-right direction) may be limited by a dielectric material 112 adjacent to the opening volume 225. In some embodiments, the S / D region 130 may include a p-type epitaxial material (e.g., a heavily in-situ boron-doped material for PMOS transistors). In some embodiments, the epitaxial growth of the S / D region 128 may include an initial nucleation operation to provide a seed layer, followed by a main epitaxial operation in which the remainder of the S / D region 128 is formed on the seed layer. In some embodiments, the S / D region 128 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternating semiconductor materials such as germanium or group III-V materials or alloys may be used to form the S / D region 128. The dielectric material 154 may be CESL and may be formed of any suitable material (e.g., silicon nitride). In some embodiments, the dielectric material 156 may be PMD, such as an oxide material (e.g., silicon oxide).

[0064] Figure 33 shows the assembly after the hard mask 127, dielectric material 122, dielectric material 142, dielectric material 154, and dielectric material 156 of the assembly of Figure 32 have been polished (e.g., using CMP technology) to expose the hard mask 116 over the channel region 202.

[0065] Figure 34 shows the assembly after the hard mask 116, dielectric material 114 (“dummy gate”), and dielectric material 112 have been removed from the assembly of Figure 33 to form the opening volume 226. Any suitable etching technique can be used.

[0066] Figure 35 shows the assembly after the dielectric material 110 of the assembly of Figure 34 has been recessed, exposing the sides of the stack 148 (including the first material layer 150 and the second material layer 152). Any suitable etching technique can be used.

[0067] Figure 36 illustrates the assembly after the channel material 106 in the stack 230 of the assembly of Figure 35 has been "released" by removing the sacrificial material 105. As described above, in some embodiments, as shown, the etching technique used to remove the sacrificial material 104 can cause simultaneous removal of a first material layer 150 and oxidation of a second material layer 152 in the stack 148, resulting in an insulating material region 158. The insulating material region 158 may contact the base 222 of the substrate 102 and may be disposed between the channel material 106 and the substrate 102 (and between the S / D regions 128 / 130 and the substrate 102). Furthermore, the release operation may cause a thin oxide layer 157 (e.g., silicon oxide when the channel material 106 comprises silicon) on the exposed surface of the channel material 106.

[0068] Figure 37 illustrates the assembly after performing a cleaning operation to remove oxide 157 from the assembly of Figure 36, and then forming a conformal gate dielectric 136 on the resulting assembly. Any suitable technique (e.g., ALD) can be used to form the gate dielectric 136, and the gate dielectric 136 may include any material discussed herein with reference to the gate dielectric 136.

[0069] Figure 38 illustrates the assembly after the gate metal 138 has been formed on top of the assembly of Figure 37. The gate metal 138 may include any one or more layers of material, such as any material discussed herein with reference to the gate metal 138.

[0070] Figure 39 shows the assembly after the gate metal 138 and gate dielectric 136 of the assembly of Figure 38 have been polished to remove the gate metal 138 and gate dielectric 136 over dielectric material 122 and dielectric material 156. Any suitable polishing technique, such as CMP, can be used.

[0071] Figure 40 illustrates the assembly after recessing the gate metal 138 and gate dielectric 136 (e.g., using one or more etching techniques) to form a recess in the assembly of Figure 39 and then forming the gate contact 140 in the recess. The gate contact 140 may comprise any one or more materials (e.g., an adhesion liner, a barrier liner, one or more filler metals, etc.).

[0072] Figure 41 illustrates the assembly after the dielectric materials 134 and 132 of the assembly of Figure 40 are patterned to form recesses, and then the S / D contact 164 is formed in these recesses. The S / D contact 164 may comprise any one or more materials (e.g., an adhesive liner, a barrier liner, one or more filler metals, etc.). The assembly of Figure 41 may take the form of the IC structure 100 of Figure 1.

[0073] As described above, the specific arrangements of the S / D regions 128 / 130 in the IC structure 100 depicted in the various figures are merely illustrative, and any desired arrangement may be used. For example, Figure 42 depicts an IC structure 100 with different arrangements of the S / D regions 128 / 130. In particular, the IC structure 100 of Figure 42 can be fabricated by patterning the hard masks 126 / 127 such that the boundary between the S / D regions 128 and 130 is between and parallel to the adjacent channel regions 202. Any other desired arrangement of the S / D regions 128 / 130 may be implemented according to this disclosure.

[0074] In some embodiments, repeated deposition and etching operations may be performed around the dielectric material 118, such that the “cap” of the dielectric material 118 extends over the insulating material 120. Figure 43 This is a side cross-sectional view of this IC structure 100, sharing the viewpoint of the "A" sub-view herein. The resulting dielectric material 118 may have the same inverted "U" and may be nested within a U-shaped dielectric material 112. Any embodiment disclosed herein may include having Figure 43 118 is a dielectric material with a structure.

[0075] As described above, during the fabrication of the transistor device in IC structure 100, the stack 148 of the components in FIG. 2 (and other figures) can be transformed into an insulating material region 158. Therefore, in the device region 206 of IC structure 100, it may not be easy to identify the different material layers of the stack 148. However, in the regions of IC structure 100 where such transistor devices are not formed, different material layers of the stack 148 (including alternating first material layer 150 and second material layer 152, the thickness of which is less than the channel thickness 212) may exist. For example, Figure 44 It is IC structure 100 (which can be, for example, part of a die, as shown in the reference below). Figure 48 (Discussed) Top view, IC structure 100 includes a protective ring 180 (e.g., a metal ring for providing electrical shielding) surrounding an inner region 182. Figure 45 yes Figure 44 Side view of IC structure 100 Figure 44 In some embodiments, an insulating material region 158 may be disposed below an inner region 182 (e.g., because a transistor disclosed herein is present below the inner region 182), while a stack 148 (comprising alternating first material layers 150 and second material layers 152, the thickness of which is less than the channel thickness 212) may be retained below a guard ring 180 (e.g., because no transistor device is present below the guard ring 180). In another example, Figure 46 It is IC structure 100 (which may be, for example, part of a die, as shown in the reference below). Figure 48 (Discussed) Top view, IC structure 100 includes memory array region 186 surrounded by peripheral region 184 surrounding memory array region 186. Figure 47 yes Figure 46 Side view of IC structure 100 Figure 46In some embodiments, an insulating material region 158 may be disposed beneath a memory array region 186 (e.g., as part of a static random access memory (SRAM) cell or a memory cell with other architecture, since transistors disclosed herein are present beneath the memory array region 186), while a stack 148 (comprising alternating first material layers 150 and second material layers 152, the thickness of which is less than the channel thickness 212) may be retained beneath a peripheral region 184 (e.g., since no transistor devices are present beneath the peripheral region 184).

[0076] The IC structure 100 disclosed herein can be included in any suitable electronic component. Figures 48-52 Various examples of devices that may include any IC structure 100 disclosed herein are shown.

[0077] Figure 48 This is a top view of a wafer 1500 and a die 1502 that may include one or more IC structures 100 according to any embodiment disclosed herein. The wafer 1500 may be made of semiconductor material and may include one or more dies 1502 having an IC structure (e.g., IC structure 100 disclosed herein) formed on the surface of the wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is fabricated, the wafer 1500 may undergo a unitization process in which the dies 1502 are separated from each other to provide discrete “chips” of the semiconductor product. The die 1502 may include one or more IC structures 100 (e.g., as referenced below). Figure 49 (discussed), one or more transistors (e.g., see reference below) Figure 49 Some transistors discussed), and / or supporting circuitry for routing electrical signals to transistors, and any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridged RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be combined with a processing device (e.g., Figure 52 The processing device 1802 or other logic unit configured to store information in a storage device or execute instructions stored in a storage array is formed on the same die 1502.

[0078] Figure 49This is a side cross-sectional view of an IC component 1600 that may include one or more IC structures 100 according to any embodiment disclosed herein. One or more IC components 1600 may be included in one or more dies 1502. Figure 48 IC component 1600 can be formed on substrate 1602 (e.g., Figure 48 On a 1500 wafer, and can be included in a die (e.g., Figure 48 In the die 1502. The substrate 1602 may take the form of any embodiment of the substrate 102 disclosed herein.

[0079] IC component 1600 may include one or more device layers 1604 disposed on substrate 1602. Device layer 1604 may include features of one or more IC structures 100, other transistors, diodes, or other devices formed on substrate 1602. For example, device layer 1604 may include source and / or drain (S / D) regions, a gate for controlling current flow between S / D regions, S / D contacts for routing electrical signals to / from S / D regions, and gate contacts for routing electrical signals to / from S / D regions (e.g., according to any embodiment discussed above with reference to IC structure 100). For example, transistors that may be included in device layer 1604 are not limited to any particular type or construction and may include any one or more of planar transistors, non-planar transistors, or combinations thereof. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors such as dual-gate transistors or tri-gate transistors, and gate-surrounding or all-around transistors such as nanoribbon and nanowire transistors (e.g., as discussed above with reference to IC structure 100).

[0080] One or more interconnect layers can be disposed on device layer 1604 (in Figure 49 The interconnect layers 1606-1610 (shown as interconnect layers 1606-1610) route electrical signals, such as power and / or input / output (I / O) signals, to and / or from devices in the device layer 1604 (e.g., IC structure 100). For example, conductive features of the device layer 1604 (e.g., gate contacts and S / D contacts) may be electrically coupled to the interconnect structure 1628 of the interconnect layers 1606-1610. One or more interconnect layers 1606-1610 may form a metallized stack (also referred to as an "ILD stack") 1619 of the IC component 1600. Although Figure 49 Only one face of the device layer 1604 is depicted in the ILD stack 1619, but in other embodiments, the IC component 1600 may include two ILD stacks 1619 such that the device layer 1604 is between the two ILD stacks 1619.

[0081] Interconnect structure 1628 can be arranged within interconnect layers 1606-1610 to route electrical signals according to various designs (in particular, the arrangement is not limited to...). Figure 49 The specific configuration of the interconnect structure 1628 shown. Although in Figure 49 A specific number of interconnect layers 1606-1610 are shown, but embodiments of this disclosure include IC components having more or fewer interconnect layers than shown.

[0082] In some embodiments, the interconnect structure 1628 may include lines 1628a and / or vias 1628b filled with a conductive material such as a metal. Lines 1628a may be arranged to route electrical signals in a direction substantially parallel to a plane on which the device layer 1604 is formed on the substrate 1602. For example, from Figure 49 From this angle, line 1628a can route electrical signals in the direction of entering and exiting the paper. Via 1628b can be arranged to route electrical signals in a direction perpendicular to a plane substantially perpendicular to the surface of substrate 1602 on which device layer 1604 is formed. In some embodiments, via 1628b can electrically couple lines 1628a of different interconnect layers 1606-1610 together.

[0083] Interconnect layers 1606-1610 may include a dielectric material 1626 disposed between interconnect structures 1628, such as Figure 49 As shown. In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different layers of interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

[0084] A first interconnect layer 1606 may be formed above the device layer 1604. In some embodiments, the first interconnect layer 1606 may include a line 1628a and / or a via 1628b, as shown. The line 1628a of the first interconnect layer 1606 may be coupled to a contact portion (e.g., an S / D contact portion or a gate contact portion) of the device layer 1604.

[0085] A second interconnect layer 1608 may be formed over a first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via 1628b to couple a line 1628a of the second interconnect layer 1608 to a line 1628a of the first interconnect layer 1606. Although for clarity, the lines 1628a and vias 1628b are structurally depicted with lines within each interconnect layer (e.g., within the second interconnect layer 1608), in some embodiments the lines 1628a and vias 1628b may be continuous in structure and / or material (e.g., simultaneously filled during a dual damascene process).

[0086] The third interconnect layer 1610 (and desired additional interconnect layers) can be sequentially formed on the second interconnect layer 1608 according to similar techniques and configurations described in conjunction with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher” (i.e., further away from the device layer 1604) in the metallization stack 1619 of the IC component 1600 can be thicker.

[0087] IC component 1600 may include solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606-1610. Figure 49 In this embodiment, conductive contact 1636 is shown in the form of a bonding pad. Conductive contact 1636 may be electrically coupled to interconnect structure 1628 and configured to route electrical signals from device layer 1604 to other external devices. For example, solder bonds may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including IC component 1600 to another component (e.g., a circuit board). IC component 1600 may include additional or alternative structures to route electrical signals from interconnect layers 1606-1610; for example, conductive contact 1636 may include other similar features (e.g., pillars) to transmit electrical signals to external components. In embodiments where IC component 1600 includes ILD stacks 1619 at each opposite face of device layer 1604, IC component 1600 may include conductive contact 1636 on each ILD stack 1619 (allowing interconnects to IC component 1600 to be formed on both opposite faces of IC component 1600).

[0088] Figure 50 This is a side cross-sectional view of an exemplary IC package 1650 that may include one or more IC structures 100 according to any embodiment disclosed herein. In some embodiments, the IC package 1650 may be a system-in-package (SiP).

[0089] The encapsulation substrate 1652 may be formed of a dielectric material (e.g., ceramic, cumulative film, epoxy film having filler particles therein, glass, organic material, inorganic material, combination of organic and inorganic materials, embedded portion formed of different materials, etc.) and may have conductive paths extending through the dielectric material between surfaces 1672 and 1674, or between different locations on surface 1672, and / or between different locations on surface 1674. These conductive paths may take the form described above. Figure 49 The form of any of the interconnects 1628 discussed.

[0090] The package substrate 1652 may include conductive contacts 1663 coupled to a conductive path (not shown) through the package substrate 1652, thereby allowing circuitry within the die 1656 and / or the interposer 1657 to be electrically coupled to the respective conductive contacts in the conductive contacts 1664.

[0091] IC package 1650 may include an interposer 1657 coupled to package substrate 1652 via conductive contact 1661 of interposer 1657, first-level interconnect 1665 and conductive contact 1663 of package substrate 1652. Figure 50 The first-level interconnect 1665 shown is a solder bump, but any suitable first-level interconnect 1665 can be used. In some embodiments, the interposer 1657 may not be included in the IC package 1650; instead, the die 1656 can be directly coupled to the conductive contact 1663 at face 1672 via the first-level interconnect 1665. More generally, one or more dies 1656 can be coupled to the package substrate 1652 via any suitable structure (e.g., silicon bridge, organic bridge, one or more waveguides, one or more interposers, wire bonding, etc.).

[0092] IC package 1650 may include one or more dies 1656 coupled to interposer 1657 via conductive contacts 1654 of die 1656, first-level interconnect 1658, and conductive contacts 1660 of interposer 1657. Conductive contacts 1660 can be coupled to conductive paths (not shown) via interposer 1657, allowing circuitry within die 1656 to be electrically coupled to individual conductive contacts in conductive contacts 1661 (or electrically coupled to other devices included in interposer 1657, not shown). Figure 50 The first-level interconnect 1658 shown is a solder bump, but any suitable first-level interconnect 1658 can be used. As used herein, "conductive contact" can refer to a portion of conductive material (e.g., metal) that serves as an interface between different components; conductive contacts can be recessed into the surface of a component, flush with or extending away from the surface of a component, and can take any suitable form (e.g., conductive pad or socket).

[0093] In some examples, an underfill material 1666 may be disposed around a first-level interconnect 1665 between the package substrate 1652 and the interposer 1657, and a molding compound 1668 may be disposed around the die 1656 and the interposer 1657 and contact the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the molding compound 1668. Exemplary materials that may be used for the underfill material 1666 and the molding compound 1668, where appropriate, are epoxy molding materials. A second-level interconnect 1670 may be coupled to a conductive contact 1664. Figure 50The second-level interconnect 1670 shown is a solder ball (e.g., for a ball grid array arrangement), but any suitable second-level interconnect 1670 can be used (e.g., a pin in a pin grid array arrangement or a pad in a pad grid array arrangement). The second-level interconnect 1670 can be used to couple the IC package 1650 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and referenced below. Figure 51 The subject of discussion.

[0094] Die 1656 may take the form of any embodiment of die 1502 discussed herein (e.g., any embodiment that may include IC component 1600). In embodiments where IC package 1650 includes multiple dies 1656, IC package 1650 may be referred to as a multi-chip package (MCP). Die 1656 may include circuitry for performing any desired function. For example, one or more of dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of dies 1656 may be memory dies (e.g., high-bandwidth memory). In some embodiments, die 1656 may include one or more IC structures 100 (e.g., as referenced above). Figure 48 and Figure 49 (As discussed).

[0095] Despite Figure 50 The IC package 1650 shown is a flip-chip package, but other package architectures can be used. For example, IC package 1650 can be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, IC package 1650 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although in Figure 50 Two dies 1656 are shown in the IC package 1650, but the IC package 1650 may include any desired number of dies 1656. The IC package 1650 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on a first side 1672 or a second side 1674 of the package substrate 1605, or disposed on either side of the interposer 1657. More generally, the IC package 1650 may include any other active or passive components known in the art.

[0096] Figure 51This is a side cross-sectional view of an IC component assembly 1700 according to any embodiment disclosed herein. The IC component assembly may include one or more IC packages or other electronic components (e.g., dies) including one or more IC structures 100. The IC component assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC component assembly 1700 includes components disposed on a first surface 1740 and an opposing second surface 1742 of the circuit board 1702; typically, components may be disposed on one or both surfaces 1740 and 1742. Any IC package discussed below with reference to the IC component assembly 1700 may take the form of the above reference. Figure 50 The form of any embodiment of the IC package 1650 discussed (e.g., one or more IC structures 100 may be included in a die).

[0097] In some examples, circuit board 1702 may be a printed circuit board (PCB) comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more metal layers may be formed in a desired circuit pattern to route electrical signals (optionally combined with other metal layers) between components coupled to circuit board 1702. In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0098] Figure 51 The illustrated IC component assembly 1700 includes an interposer-on-package structure 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling member 1716. The coupling member 1716 electrically and mechanically couples the interposer-on-package structure 1736 to the circuit board 1702 and may include solder balls (e.g., ...). Figure 51 (as shown), the protrusions and recesses of the socket, adhesive, bottom filler material and / or any other suitable electrical and / or mechanical coupling structure.

[0099] The on-package structure 1736 may include an IC package 1720 coupled to the on-package interposer 1704 via a coupling member 1718. The coupling member 1718 may take any suitable form for the application, such as the form discussed above with reference to coupling member 1716. Although in Figure 51 A single IC package 1720 is shown, but multiple IC packages can be coupled to the package interposer 1704; in fact, additional interposers can be coupled to the package interposer 1704. The package interposer 1704 can provide an interposer substrate for bridging the circuit board 1702 and the IC package 1720. The IC package 1720 can be or includes, for example, a die ( Figure 48 1502 die), IC components (e.g.) Figure 49The IC component 1600 or any other suitable component. Typically, the package interposer 1704 can extend the connection to a wider spacing or rewire the connection to a different connection. For example, the package interposer 1704 can couple an IC package 1720 (e.g., a die) to a set of BGA conductive contacts on a coupling member 1716 for coupling to a circuit board 1702. Figure 51 In the illustrated embodiment, IC package 1720 and circuit board 1702 are attached to opposite sides of package interposer 1704; in other examples, IC package 1720 and circuit board 1702 may be attached to the same side of package interposer 1704. In some embodiments, three or more components may be interconnected via package interposer 1704.

[0100] In some embodiments, the package interposer 1704 may be formed as a PCB, comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternating rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to through-silicon vias (TSVs) 1706. The package interposer 1704 may also include embedded devices 1714, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, converters, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices (e.g., radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices) can also be formed on the package interposer 1704. The package-on-interposer structure 1736 can take the form of any package-on-interposer structure known in the art.

[0101] IC component assembly 1700 may include IC package 1724 coupled to a first side 1740 of circuit board 1702 via coupling member 1722. Coupling member 1722 may take the form of any embodiment discussed above with reference to coupling member 1716, and IC package 1724 may take the form of any embodiment discussed above with reference to IC package 1720.

[0102] Figure 51The illustrated IC component assembly 1700 includes a stacked package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling member 1728. The stacked package structure 1734 may include IC packages 1726 and 1732 coupled together via a coupling member 1730, such that IC package 1726 is disposed between the circuit board 1702 and IC package 1732. Coupling members 1728 and 1730 may take the form of any embodiment of the coupling member 1716 described above, and IC packages 1726 and 1732 may take the form of any embodiment of IC package 1720 described above. The stacked package structure 1734 can be configured according to any stacked package structure known in the art.

[0103] Figure 52 This is a block diagram of an exemplary electrical device 1800 that may include one or more IC structures 100 according to any embodiment disclosed herein. For example, any suitable component of the electrical device 1800 may include one or more of the IC component assembly 1700, IC package 1650, IC component 1600, or die 1502 disclosed herein. Figure 52 Multiple components are shown as included in electrical device 1800, but any one or more of these components may be omitted or repeated as appropriate for the application. In some embodiments, some or all of the components included in electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0104] Additionally, in various embodiments, electrical equipment 1800 may not include... Figure 52 The electrical device 1800 may include one or more components, but may also include interface circuitry for coupling to one or more components. For example, the electrical device 1800 may not include display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include audio input device 1824 or audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 1824 or audio output device 1808 may be coupled.

[0105] Electrical device 1800 may include processing device 1802 (e.g., one or more processing devices). As used herein, the terms "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform said electronic data into other electronic data that can be stored in registers and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device. Electrical device 1800 may include memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory can be used as a cache memory and can include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0106] In some embodiments, electrical device 1800 may include communication chip 1812 (e.g., one or more communication chips). For example, communication chip 1812 may be configured to manage wireless communication for data transmission to and from electrical device 1800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data via non-solid media using modulated electromagnetic radiation. This term does not imply that the relevant devices do not contain any wires, although they may be absent in some embodiments.

[0107] The 1812 communication chip can implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) projects, and any revisions, updates, and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an abbreviation for Global Microwave Access Interoperability, a certification mark for products that have passed IEEE 802.16 standard conformance and interoperability testing. The 1812 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication chip 1812 may operate according to Enhanced Data Rate GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and beyond. In other embodiments, communication chip 1812 may operate according to other wireless protocols. Electrical device 1800 may include antenna 1822 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0108] In some embodiments, the communication chip 1812 can manage wired communication such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1812 may include multiple communication chips. For example, a first communication chip 1812 may be dedicated to short-range wireless communication (e.g., Wi-Fi and Bluetooth), and a second communication chip 1812 may be dedicated to long-range wireless communication (e.g., Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.). In some embodiments, the first communication chip 1812 may be dedicated to wireless communication, and the second communication chip 1812 may be dedicated to wired communication.

[0109] Electrical device 1800 may include battery / power circuit 1814. Battery / power circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 1800 to an energy source (e.g., AC line power) separate from electrical device 1800.

[0110] Electrical device 1800 may include display device 1806 (or corresponding interface circuitry, as discussed above). Display device 1806 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0111] Electrical device 1800 may include audio output device 1808 (or corresponding interface circuitry, as discussed above). Audio output device 1808 may include any device that generates a sound indicator, such as a speaker, headphones, or earphones.

[0112] Electrical device 1800 may include audio input device 1824 (or a corresponding interface circuit, as discussed above). Audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0113] Electrical device 1800 may include GPS device 1818 (or a corresponding interface circuit, as discussed above). GPS device 1818 may communicate with satellite-based systems and may receive the location of electrical device 1800, as known in the art.

[0114] Electrical device 1800 may include other output devices 1810 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0115] Electrical device 1800 may include other input devices 1820 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1820 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0116] Electrical device 1800 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet, laptop, netbook, ultrabook, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop electrical device, server equipment or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some embodiments, electrical device 1800 can be any other electronic device that processes data.

[0117] The following paragraphs provide various examples of the embodiments disclosed herein.

[0118] Example 1 is an integrated circuit (IC) component comprising: a first region including silicon; a second region including alternating second and third material layers, wherein the second material includes silicon and germanium, and the third material includes silicon; and a third region including alternating second and third material layers, wherein the second region is between the first and third regions, and the thickness of each layer in the second region is less than the thickness of each layer in the third region.

[0119] Example 2 includes the subject of Example 1 and further specifies that the second region includes at least two layers of second material.

[0120] Example 3 includes the subject of Example 1 and also specifies that the second region includes at least three layers of second material.

[0121] Example 4 includes the subject of any one of Examples 1-3, and further specifies that the first region includes crystalline silicon.

[0122] Example 5 includes the subject of any one of Examples 1-4, and further specifies that the first region, the second region, and the third region are distributed along an axis perpendicular to the plane of the second material layer and the third material layer.

[0123] Example 6 includes the subject matter of any one of Examples 1-5, and further specifies that the third region includes at least three third material layers.

[0124] Example 7 includes the subject of any one of Examples 1-6, and further specifies that: the second region is laterally aligned with the fourth region, and the fourth region includes silicon and oxygen.

[0125] Example 8 includes the subject of Example 7 and further specifies that: the first region, the second region, and the third region are under the protection ring of the IC component, and the fourth region is not under the protection ring.

[0126] Example 9 includes the subject of Example 7 and further specifies that: the first region, the second region, and the third region are at the periphery of the storage array, and the fourth region is not at the periphery of the storage array.

[0127] Example 10 includes the subject matter of any one of Examples 1-7, and further specifies that: the IC component also includes a gate all-around (GAA) transistor in the fourth region, and the third material layer in the third region is laterally aligned with the line channels in at least some of the GAA transistors in the fourth region.

[0128] Example 11 includes the subject of Example 10 and further specifies that: the first region, the second region, and the third region are under the protection ring of the IC component, and the fourth region is not under the protection ring.

[0129] Example 12 includes the subject of Example 10 and further specifies that: the first region, the second region, and the third region are at the periphery of the storage array, and the fourth region is not at the periphery of the storage array.

[0130] Example 13 includes the subject of any one of Examples 1-7, and further specifies that the first region, the second region, and the third region are under the protection ring of the IC component.

[0131] Example 14 includes the subject of any one of Examples 1-7, and further specifies that the first region, the second region, and the third region are located at the periphery of the storage array.

[0132] Example 15 includes the subject matter of any one of Examples 1-14 and further specifies that the IC component also includes: an array of channel regions including a first channel region and an adjacent second channel region, wherein the first channel region is parallel to and offset from the axis of the second channel region; a first source / drain region adjacent to the first channel region; a second source / drain region adjacent to the second channel region; and an insulating material region, which is at least partially located between the first source / drain region and the second source / drain region.

[0133] Example 16 includes the subject matter of Example 15 and further specifies that: the insulating material region includes a first insulating material and a second insulating material, wherein the first insulating material has a U-shaped cross section and the first insulating material is between the second insulating material and the first source / drain region.

[0134] Example 17 is an integrated circuit (IC) component comprising: a substrate; a first region comprising alternating first and second material layers, wherein each layer has a thickness of less than 3 nanometers; and a second region comprising alternating first and second material layers, wherein each layer has a thickness of greater than 3 nanometers, and the first region being located between the substrate and the second region.

[0135] Example 18 includes the subject of Example 17 and further specifies that the second region includes at least two layers of second material.

[0136] Example 19 includes the subject of Example 17 and further specifies that the second region comprises at least three layers of second material.

[0137] Example 20 includes the subject matter of any one of Examples 17-19, and further specifies that the substrate comprises silicon.

[0138] Example 21 includes the subject of any one of Examples 17-20, and further specifies that the second region includes at least three layers of second material.

[0139] Example 22 includes the subject matter of any one of Examples 17-21, and further specifies that the first material and the second material are semiconductor materials.

[0140] Example 23 includes the subject of any one of Examples 17-22, and further specifies that the first material and the second material include silicon.

[0141] Example 24 includes the subject of any of Examples 17-23, and further specifies that: the first region is laterally aligned with the third region, and the third region includes dielectric material.

[0142] Example 25 includes the subject of Example 24 and further specifies that the dielectric material includes oxygen.

[0143] Example 26 includes the subject of any one of Examples 24-25, and further specifies that: the first and second regions are under the protection ring of the IC component, and the third region is not under the protection ring.

[0144] Example 27 includes the subject of any one of Examples 24-25, and further specifies that: the first region and the second region are at the periphery of the storage array, and the third region is not at the periphery of the storage array.

[0145] Example 28 includes the subject matter of any one of Examples 17-23, and further specifies that: the IC component also includes a gate all-around (GAA) transistor in the third region, and the second material layer in the second region is laterally aligned with the line channels in at least some of the GAA transistors in the third region.

[0146] Example 29 includes the subject of Example 28 and further specifies that: the first and second regions are under the protection ring of the IC component, and the third region is not under the protection ring.

[0147] Example 30 includes the subject of Example 28 and further specifies that: the first region and the second region are at the periphery of the storage array, and the third region is not at the periphery of the storage array.

[0148] Example 31 includes the subject of any one of Examples 17-23, and further specifies that the first and second regions are under the protection ring of the IC component.

[0149] Example 32 includes the subject of any of Examples 17-23, and further specifies that the first and second regions are located at the periphery of the storage array.

[0150] Example 33 includes the subject matter of any one of Examples 17-32 and further specifies that the IC component also includes: an array of channel regions including a first channel region and an adjacent second channel region, wherein the first channel region is parallel to and offset from the axis of the second channel region; a first source / drain region adjacent to the first channel region; a second source / drain region adjacent to the second channel region; and an insulating material region, which is at least partially located between the first source / drain region and the second source / drain region.

[0151] Example 34 includes the subject of Example 33 and further specifies that: the insulating material region includes a first insulating material and a second insulating material, wherein the first insulating material has a U-shaped cross section and the first insulating material is between the second insulating material and the first source / drain region.

[0152] Example 35 includes the subject of any of Examples 17-34, and further specifies that the IC component is a die.

[0153] Example 36 is an electronic component, including: an IC component of any one of Examples 1-35; and a support component electrically coupled to the IC component.

[0154] Example 37 includes the subject of Example 36 and further specifies that the support includes a packaging substrate.

[0155] Example 38 includes the subject of any of Examples 36-37, and further specifies that the support includes an interpolator.

[0156] Example 39 includes the subject of any of Examples 36-37, and further specifies that the support includes a printed circuit board.

[0157] Example 40 includes the subject matter of any one of Examples 36-39, and also includes: the housing surrounding the IC component and the support.

[0158] Example 41 includes the subject of Example 40 and further specifies that the housing is a handheld computing device housing.

[0159] Example 42 includes the subject of Example 40 and also specifies that the shell is a server shell.

[0160] Example 43 includes the subject of any one of Examples 40-42, and also includes: a display coupled to the housing.

[0161] Example 44 includes the subject of Example 43 and also specifies that the display is a touchscreen display.

Claims

1. An integrated circuit (IC) component, comprising: A first region, the first region comprising silicon; A second region comprising alternating layers of a second material and a third material, wherein the second material comprises silicon and germanium, and the third material comprises silicon; and A third region comprising alternating layers of the second and third materials, wherein the first, second, and third regions are distributed along an axis perpendicular to a plane of the second and third materials, the second region being between the first and third regions, and each layer of the second and third materials in the second region having a thickness less than the thickness of each layer of the second and third materials in the third region.

2. The IC component according to claim 1, wherein, The second region includes at least two layers of the second material.

3. The IC component according to claim 1, wherein, The second region includes at least three layers of the second material.

4. The IC component according to any one of claims 1-3, wherein, The first region comprises crystalline silicon.

5. The IC component according to any one of claims 1-3, wherein, The third region includes at least three layers of the third material.

6. The IC component according to any one of claims 1-3, wherein, The second region is laterally aligned with the fourth region, and the fourth region comprises silicon and oxygen.

7. The IC component according to claim 6, wherein, The first region, the second region, and the third region are under the protection ring of the IC component, while the fourth region is not under the protection ring.

8. The IC component according to claim 6, wherein, The first region, the second region, and the third region are located at the periphery of the storage array, while the fourth region is not located at the periphery of the storage array.

9. An integrated circuit (IC) component, comprising: Substrate; A first region comprising alternating first and second material layers, wherein each of the first and second material layers in the first region has a thickness of less than 3 nanometers; and The second region comprises alternating layers of the first and second materials, wherein each layer of the first and second materials in the second region has a thickness greater than 3 nanometers, the substrate, the first region, and the second region are distributed along an axis perpendicular to a plane of the first and second materials, and the first region is located between the substrate and the second region.

10. The IC component according to claim 9, wherein, The IC component also includes a gate-all-around (GAA) transistor in the third region, and the second material layer in the second region is laterally aligned with the line channels in at least some of the GAA transistors in the third region.

11. The IC component according to claim 10, wherein, The first region and the second region are under the protection ring of the IC component, while the third region is not under the protection ring.

12. The IC component according to claim 10, wherein, The first region and the second region are located at the periphery of the storage array, while the third region is not located at the periphery of the storage array.

13. The IC component according to any one of claims 9-12, wherein, The first region and the second region are under the protective ring of the IC component.

14. The IC component according to any one of claims 9-12, wherein, The first region and the second region are located on the periphery of the storage array.

15. The IC component according to any one of claims 9-12, wherein, The IC component also includes: An array of channel regions, the array of channel regions including a first channel region and an adjacent second channel region, wherein the axes of the first channel region and the second channel region are parallel and offset; The first source / drain region is close to the first channel region; The second source / drain region is adjacent to the second channel region; and An insulating material region, which is at least partially located between the first source / drain region and the second source / drain region.

16. The IC component according to claim 15, wherein, The insulating material region includes a first insulating material and a second insulating material, wherein the first insulating material has a U-shaped cross-section and is located between the second insulating material and the first source / drain region.

17. The IC component according to any one of claims 9-12, wherein, The IC component is a die.

18. An electronic component, comprising: Integrated circuit (IC) components, including: The first region includes silicon. The second region comprises alternating layers of a second material and a third material, wherein the second material comprises silicon and germanium, and the third material comprises silicon, and A third region comprising alternating layers of the second and third material materials, wherein the first, second, and third regions are distributed along an axis perpendicular to a plane of the second and third material materials, the second region lies between the first and third regions, and each layer in the second and third material materials in the second region has a thickness less than the thickness of each layer in the third region; and A support member electrically coupled to the IC component.

19. The electronic component according to claim 18, wherein, The support includes a packaging substrate, an interposer, or a circuit board.

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