Integrated circuit structure and method for forming the same

Abstract

The IC structure includes a first cell row and a second cell row extending in a first direction. The first cell row includes: first cells, each including one or more first fins having a first source / drain region of a first conductivity type and one or more second fins having a second source / drain region of a second conductivity type opposite to the first conductivity type. The second cell row includes: second cells, each including one or more third fins having a third source / drain region of the first conductivity type and one or more fourth fins having a fourth source / drain region of the second conductivity type. The first cell has the same first number of one or more first fins, and the second cell has the same second number of one or more third fins that is less than the first number of one or more first fins. Embodiments of the present application also relate to a method for forming an IC structure.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit structures and methods for forming the same. Background Art

[0002] The scaling of semiconductor devices has followed Moore's Law for the past few decades. Due to lithography and integration limitations, improvements in manufacturing processes independently cannot catch up with the trend of constant device scaling, so layout design technology also contributes to further scaling of semiconductor devices. Summary of the invention

[0003] Some embodiments of the present application provide an integrated circuit (IC) structure, comprising: one or more first cell rows extending in a first direction, each first cell row comprising a plurality of first cells arranged along the first direction, wherein each of the plurality of first cells comprises one or more first fins having a first source / drain region of a first conductivity type and one or more second fins having a second source / drain region of a second conductivity type opposite to the first conductivity type; and one or more second cell rows extending in the first direction, each second cell row comprising a plurality of second cells arranged along the first direction, wherein each of the plurality of second cells comprises one or more third fins having a third source / drain region of the first conductivity type and one or more fourth fins having a fourth source / drain region of the second conductivity type, wherein the plurality of first cells have the same first number of the one or more first fins, and the plurality of second cells have the same second number of the one or more third fins which is less than the first number of the one or more first fins.

[0004] Other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a plurality of first cells, each having a first number of one or more P-type field effect transistor (PFET) fins, wherein a first subset of the plurality of first cells is arranged along a first direction in a first cell row; and a plurality of second cells, each having a second number of one or more PFET fins different from the first number of one or more PFET fins, wherein the first subset of the plurality of second cells is arranged along the first direction in a second cell row adjacent to the first cell row, wherein each of the one or more PFET fins in the first cell row spans the entire first subset of the plurality of first cells, and each of the one or more PFET fins in the second cell row spans the entire first subset of the plurality of second cells.

[0005] Still other embodiments of the present application provide a method for forming an integrated circuit structure, comprising: placing a plurality of first cells, each having a first number of NFET fins, in a layout; swapping the plurality of first cells with a plurality of second cells, each having a second number of NFET fins less than the first number of NFET fins; determining a timing critical path in the layout after swapping the plurality of first cells with the plurality of second cells; swapping some of the plurality of second cells in the determined timing critical path with a plurality of third cells, each having a third number of NFET fins greater than the second number of NFET fins; and manufacturing an integrated circuit based on the layout after swapping some of the plurality of second cells in the determined timing critical path with the plurality of third cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 is a perspective view of an exemplary FinFET device.

[0008] Figure 2 A cross-sectional view of a FinFET transistor in a CMOS configuration is shown.

[0009] Figure 3 A top view of the fin layout of some cells of an exemplary integrated circuit designed by the systems and methods of the present invention is shown in accordance with some embodiments.

[0010] Figure 4A According to some embodiments, Figure 3 Top view of an exemplary integrated circuit of a fin layout.

[0011] Figure 4B is along Figure 4A A cross-sectional view of the integrated circuit taken along line BB' in FIG.

[0012] Figure 4C is along Figure 4A A cross-sectional view of the integrated circuit taken along the CC' line.

[0013] Figure 4D is along Figure 4A A cross-sectional view of the integrated circuit taken along the line D-D' in FIG.

[0014] Figure 4E is along Figure 4A A cross-sectional view of the integrated circuit taken along line EE'.

[0015] Figure 5 is a flow chart of an exemplary method of fabricating an integrated circuit according to some embodiments of the present invention.

[0016] Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A and Fig. 10A The present invention shows some embodiments of the Figure 5 Top view of an integrated circuit at various stages of fabrication process.

[0017] Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B The present invention shows some embodiments of the Figure 5 A cross-sectional view of an integrated circuit at various stages of fabrication of the method.

[0018] Figure 6C , Figure 7C , Figure 8C , Fig. 9C and Fig. 10C The present invention shows some embodiments of the Figure 5 A cross-sectional view of an integrated circuit at various stages of fabrication of the method.

[0019] Fig.11 A top view of the fin layout of some cells of another exemplary integrated circuit designed by the systems and methods of the present invention is shown in accordance with some embodiments.

[0020] Fig.12 A top view of the fin layout of some cells of yet another exemplary integrated circuit designed by the systems and methods of the present invention is shown in accordance with some embodiments.

[0021] Fig.13 is a block diagram including an information handling system (IHS), a mask room, and a fabrication plant according to some embodiments of the present invention.

[0022] Fig.14 A flow chart including an IC design flow and an IC manufacturing flow according to some embodiments of the present invention is shown.

[0023] Fig.15 A flow chart including a reference IC design flow, a first improved IC design flow, and a second improved IC design flow according to some embodiments of the present invention is shown.

[0024] Fig.16 is a graph providing exemplary simulation results for a layout generated from a reference IC design flow, a layout generated from a first improved IC design flow, and a layout generated from a second improved IC design flow. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0026] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0027] Embodiments of the present invention are directed to, but not limited to, fin field effect transistor (FinFET) devices. FinFET devices may be, for example, complementary metal oxide semiconductor (CMOS) devices including P-type metal oxide semiconductor (PMOS) FinFET devices and N-type metal oxide semiconductor (NMOS) FinFET devices. The following disclosure will continue with one or more FinFET examples to illustrate various embodiments of the present invention. However, it should be understood that unless specifically claimed, the present application should not be limited to a specific type of device.

[0028] The use of FinFET devices has become widespread in the semiconductor industry. Figure 1 , a perspective view of an exemplary FinFET device 50 is shown. The FinFET device 50 is a non-planar multi-gate transistor built on a substrate (such as a bulk substrate). A thin silicon-containing "fin" structure (hereinafter referred to as a "fin") forms the body of the FinFET device 50. The fin is connected to the substrate 100 and the fin 100 is connected to the substrate 100. Figure 1 The fin has a fin width W measured along the Y direction orthogonal to the X direction. fin The gate 60 of the FinFET device 50 wraps around the fin, for example, around the top surface and the opposing sidewall surfaces of the fin. Thus, a portion of the gate 60 is located above the fin in the Z direction, which is orthogonal to the X and Y directions.

[0029] L G t represents the length (or width, depending on the perspective view) of the gate 60 measured in the X direction. The gate 60 may include a gate electrode 60A and a gate dielectric layer 60B. The gate dielectric layer 60B has a thickness t measured in the Y direction. ox A portion of the gate 60 is located above a dielectric isolation structure such as shallow trench isolation (STI). A source region 70 and a drain region 80 of the FinFET device 50 are formed in an extension of the fin on opposite sides of the gate 60. The portion of the fin wrapped by the gate 60 serves as a channel region of the FinFET device 50. The effective channel length of the FinFET device 50 is determined by the size of the fin.

[0030] Figure 2 A schematic cross-sectional side view of a FinFET transistor in a CMOS configuration is shown. The CMOS FinFET includes a substrate SS, for example, a silicon substrate. An N-type well 93 and a P-type well 94 are formed in the substrate SS. A dielectric isolation structure 92, such as a shallow trench isolation (STI), is formed over the N-type well 93 and the P-type well 94. A P-type FinFET 90 is formed over the N-type well 93, and an N-type FinFET 91 is formed over the P-type well 94. The P-type FinFET 90 includes a PFET fin 95 protruding upward from the STI 92, and the N-type FinFET 91 includes an NFET fin 96 protruding upward from the STI 92. The PFET fin 95 includes a channel region of the P-type FinFET 90, and the NFET fin 96 includes a channel region of the N-type FinFET 91. In some embodiments, the PFET fin 95 is composed of silicon germanium (SiGe) for strain and / or stress enhancement, and the NFET fin 96 is composed of silicon. A gate dielectric 97 is formed over the fins 95-96 and over the STI 92, and a gate electrode 98 is formed over the gate dielectric 97. In some embodiments, the gate dielectric 97 comprises a high-k dielectric material, and the gate electrode 98 comprises a metal gate electrode, such as tungsten and / or other refractory metals. In some other embodiments, the gate dielectric 97 may comprise SiON, and the gate electrode 98 may comprise polysilicon. A gate contact 99 is formed on the gate electrode 98 to provide an electrical connection to the gate.

[0031] FinFET devices offer several advantages over planar metal oxide semiconductor field effect transistor (MOSFET) devices. These advantages may include better chip area efficiency, improved carrier mobility, and a manufacturing process that is compatible with the manufacturing process of planar devices. Therefore, it may be desirable to design an integrated circuit (IC) chip that uses FinFET devices for part or all of the IC chip.

[0032] IC design is based on a collection of cells selected from a cell library. The layout includes at least one logic block customized for a specific purpose. The logic block is an arrangement of cells placed in a routing grid of vertical and horizontal routing tracks. Conductive structures such as metal wires are routed on the routing tracks to provide connections between cells. The design of IC layout can be performed by automatic placement and routing (APR) tools (including placers and routers) by selecting standard cells from a standard cell library and placing and routing cells according to a number of design rules. The placer determines the optimal location for each standard cell in the integrated circuit, and the router optimizes the routing of input / output lines and the connections between standard cells so that the IC layout does not become overcrowded due to input / output terminals and other wiring.

[0033] Cells with fewer fins are used to achieve high integration and low power consumption, while cells with more fins are used for high-speed operation (i.e., high-performance operation). With the increasing demand for higher speed and lower power integrated circuits suitable for certain applications (e.g., server chips, mobile chips, etc.), logic blocks are modified to include cells with fewer fins and cells with more fins. This hybrid cell design typically results in a layout and wiring layout with discontinuous PFET fins. In order to manufacture an IC structure with such a layout, a fin disconnection process (interchangeably referred to as a fin cutting process) is implemented to disconnect the continuous PFET fins into multiple discontinuous PFET fins. However, the fin disconnection process will result in stress relaxation in the PFET fins formed by SiGe, which in turn will result in a reduction in hole mobility in the PFET fins, thereby reducing the on-current of the P-type FinFET.

[0034] In some embodiments, a layout design method for placing cells with fewer fins and cells with more fins is provided. The layout design method designs an odd-row cell library storing odd-row cells sharing the same number of PFET fins and an even-row cell library storing even-row cells sharing the same number of PFET fins. The number of PFET fins of the odd-row cells is different from the number of PFET fins of the even-row cells. In addition, the odd-row cells differ from each other at least in the number of NFET fins. Similarly, the even-row cells differ from each other at least in the number of NFET fins. By using this layout design method, high-speed cells (interchangeably referred to as speed-oriented cells) and lower power cells (interchangeably referred to as power-oriented cells) can be generated in the layout without generating discontinuous PFET fins in the layout.

[0035] For example, in some embodiments where the number of PFET fins of odd-row cells is greater than the number of PFET fins of even-row cells, speed-oriented cells (i.e., having more fins) may be formed by placing odd-row cells side by side along odd-rows, and power-oriented cells (i.e., having fewer fins) may be formed by placing even-row cells side by side along even-rows, without generating discontinuous PFET fins in either odd-row or even-rows. On the other hand, in some embodiments where the number of PFET fins of even-row cells is greater than the number of PFET fins of odd-row cells, speed-oriented cells may be formed by placing even-row cells side by side along even-rows, and power-oriented cells may be formed by placing odd-row cells along odd-rows, without generating discontinuous PFET fins in either odd-row or even-rows.

[0036] Figure 3 A top view of the fin layout of some cells of an exemplary integrated circuit 100 designed by the system and method of the present invention is shown according to some embodiments. However, not all of the components shown are required, and some embodiments of the present invention may include Figure 3 Additional components not shown in the drawings may be included. The arrangement and types of components may be changed without departing from the scope of the invention as described herein. Additional, different or fewer components may be included.

[0037] like Figure 3 As shown, integrated circuit 100 includes cell groups 110, 120, 130, and 140 arranged (i.e., laid out) in corresponding "cell rows" or "lines" relative to grid 101. In addition, in some embodiments, each cell group includes one or more cells arranged side by side along a corresponding row. For example, cell group 110 includes cells 111, 112, 113, and 114 arranged in the first row (Row1) of grid 101; cell group 120 includes cells 121, 122, 123, and 124 arranged in the second row (Row2) of grid 101; cell group 130 includes cells 131, 132, 133, and 134 arranged in the third row (Row3) of grid 101; cell group 140 includes cells 141, 142, 143, and 144 arranged in the fourth row (Row4) of grid 101. In some embodiments, integrated circuit 100 includes a number of rows other than four. Each row in the plurality of rows Row1-Row4 extends along an X direction. In some embodiments, the X direction is a horizontal direction of a top view of the integrated circuit 100. In some embodiments, the X direction is a direction other than a horizontal direction. The rows in the plurality of rows Row1-Row4 are adjacent to each other in a Y direction perpendicular to the X direction. In some embodiments, the Y direction is a vertical direction of a top view of the integrated circuit 100. In some embodiments, the Y direction is a direction other than a vertical direction.

[0038] Cells of cell groups 110, 120, 130, and 140 are retrieved from corresponding standard cell libraries having different numbers of PFET fins. As a non-limiting example, cells of cell groups 110 and 130 are retrieved from an odd-row cell library including a plurality of odd-row cells, each odd-row cell sharing a first number of PFET fins; cells of cell groups 120 and 140 are retrieved from an even-row cell library including a plurality of even-row cells, each even-row cell sharing a second number of PFET fins. In other words, cells 111-114 are a subset of the odd-row cell library, cells 131-134 are another subset of the odd-row cell library, cells 121-124 are a subset of the even-row cell library, and cells 141-144 are another subset of the even-row cell library. Because the cells 111-114 and 131-134 retrieved from the odd-row cell library share the same first PFET fin number (e.g., two PFET fins FP_odd in the exemplary integrated circuit 100), and the cells 121-124 and 141-144 retrieved from the even-row cell library share the same second PFET fin number (e.g., one PFET fin FP_even in the exemplary integrated circuit 100), the integrated circuit 100 does not include discontinuous PFET fins. Each of the cells 111-114, 131-134 in the odd-row cell library and each of the cells 121-124, 141-144 in the even-row cell library are associated with specific logical functions and / or characteristics (e.g., timing characteristics). Therefore, it should be noted that although the cells 111-114 and 131-134 are retrieved from the odd-row cell library, not all cells share the same cell width (e.g., the width measured in the X direction). Similarly, although cells 121 - 124 and cells 141 - 144 are retrieved from the even-row cell library, not all cells share the same cell width.

[0039] In some embodiments, along Row1 of the grid 101, the cells 111-114 respectively include two PFET fins FP_odd extending continuously across the cells 111-114 along the X direction; along Row2 of the grid 101, the cells 121-124 respectively include one PFET fin FP_even extending continuously across the cells 121-124 along the X direction; along Row3 of the grid 101, the cells 131-134 respectively include two PFET fins FP_odd extending continuously across the cells 131-134 along the X direction; along Row4 of the grid 101, the cells 141-144 respectively include one PFET fin FP_even extending continuously across the cells 141-144 along the X direction. In this configuration, cells in the same odd row (e.g., Row1 or Row3) share the same number of PFET fins (e.g., two PFET fins FP_odd), and cells in the same even row (e.g., Row2 or Row4) share the same number of PFET fins (e.g., one PFET fin FP_even). Therefore, all PFET fins FP_odd and FP_even do not come from the fin cutting process, thereby preventing stress relaxation in the PFET fins FP_odd and FP_even caused by the fin cutting process.

[0040] In addition, along Row1 of the grid 101, cell 111 includes two NFET fins FN_odd, cell 112 includes one NFET fin FN_odd, cell 113 includes two NFET FN_odd, and cell 114 includes one NFET fin FN_odd. Similarly, along Row3 of the grid 101, cell 131 includes two NFET fins FN_odd, cell 132 includes one NFET fin FN_odd, cell 133 includes two NFET FN_odd, and cell 134 includes one NFET fin FN_odd. In other words, adjacent two of the cells 111-114 in Row1 and the cells 131-134 in Row3 differ in at least the number of NFET fins. Therefore, the NFET fins of the cells in Row1 and Row3 can be manufactured using a fin cutting process to break a single continuous NFET fin into a plurality of discontinuous NFET fins FN_odd. Because NFET fins (e.g., silicon fins without germanium) suffer less stress relaxation caused by the fin cutting process than PFET fins (e.g., silicon germanium fins), the fin cutting process for manufacturing discontinuous NFET fins FN_odd will have no effect or negligible effect on the on-current of the NFETs of the cells in Row1 and Row3.

[0041] Along Row2 of the grid 101, cell 121 includes one NFET fin FN_even, cell 122 includes two NFET fins FN_even, cell 123 includes one NFET FN_even, and cell 124 includes two NFET fins FN_even. Similarly, along Row4 of the grid 101, cell 141 includes one NFET fin FN_even, cell 142 includes two NFET fins FN_even, cell 143 includes one NFET FN_even, and cell 144 includes two NFET fins FN_even. In other words, adjacent two of the cells 121-124 in Row2 and the cells 141-144 in Row4 differ in at least the number of NFET fins. Therefore, the NFET fins of the cells in Row2 and Row4 can be manufactured using a fin cutting process to break a single continuous NFET fin into a plurality of discontinuous NFET fins NFET fins FN_even. Because NFET fins (e.g., silicon fins without germanium) suffer less stress relaxation caused by the fin cutting process than PFET fins (e.g., silicon germanium fins), the fin cutting process used to manufacture the discontinuous NFET fins FN_even will have no effect or a negligible effect on the on-current of the NFETs of the cells in Row2 and Row4.

[0042] The cells 111, 113 in Row1 and the cells 131, 133 in Row3 have two PFET fins and two NFET fins, and thus these cells can be determined as 2P2N cells in the odd-row cell library. The cells 112, 114 in Row1 and the cells 132, 134 in Row3 have two PFET fins and one NFET fin, and thus these cells can be determined as 2P1N cells in the odd-row cell library. The cells 121, 123 in Row2 and the cells 141, 143 in Row4 have one PFET fin and one NFET fin, and thus these cells can be determined as 1P1N cells in the even-row cell library. The cells 122, 124 in Row2 and the cells 142, 144 in Row4 have one PFET fin and two NFET fins, and thus these cells can be determined as 1P2N cells in the even-row cell library. Therefore, the odd-row cell library includes at least 2P2N cells and 2P1N cells, and the even-row cell library includes at least 1P2N cells and 1P1N cells. Therefore, the maximum number of fins (e.g., four fins) of the cells in the odd-row cell library is greater than the maximum number of fins (e.g., three fins) of the cells in the even-row cell library. Therefore, the odd-row cells can be operated at a higher speed and are therefore suitable for high-speed applications. The even-row cells can be operated with less power and are therefore useful for low-power applications. However, in some other embodiments, the maximum number of fins of the cells in the odd-row cell library may be less than the maximum number of fins of the cells in the even-row cell library, and therefore the odd-row cells can be used for low-power applications and the even-row cells are suitable for high-speed applications.

[0043] In some embodiments, the integrated circuit 100 including 2P2N cells, 2P1N cells, 1P2N cells, and 1P1N cells is suitable for mobile chips. However, the number of PFET fins and the number of NFET fins of the cells in the odd-row cell library and the even-row cell library as discussed above are not intended to limit the embodiments of the present invention, and the odd-row cell library and the even-row cell library may include cells other than the above-mentioned cells. For example, in some other embodiments, the odd-row cell library includes 3P3N cells (i.e., cells with three PFET fins and three NFET fins) and 3P2N cells (i.e., cells with three PFET fins and two NFET fins), and the even-row cell library includes 2P3N cells (i.e., cells with two PFET fins and three NFET fins) and 2P2N cells (i.e., cells with two PFET fins and two NFET fins). The integrated circuit including 3P3N cells, 3P2N cells, 2P3N cells, and 2N2N cells is suitable for, for example, server chips, which have more stringent speed requirements than mobile chips.

[0044] In some embodiments, the cells in the odd-row cell library and the cells in the even-row cell library are standard cells. Standard cells include but are not limited to INV, AND, OR, NAND, NOR, XOR, AOI, OAI, MUX, BUFF, adder, filler, flip-flop, latch, delayer, clock unit, etc. Optionally, these cells are custom cells.

[0045] Each of the odd row cells 111-114 and 131-134 has a substantially rectangular shape, which includes a top boundary TB1, a bottom boundary BB1 and an opposite side boundary SB1. The top boundary TB1 and the bottom boundary BB1 are parallel to the X direction. The side boundary SB1 is parallel to the Y direction. The odd row cells 111-114 and 131-134 share the same cell height CH_odd, which is defined between the top boundary TB1 and the bottom boundary BB1. Therefore, the odd rows Row1 and Row3 have a row height RH_odd equal to the cell height CH_odd. Similarly, each of the even row cells 121-124 and 141-144 has a substantially rectangular shape, which includes a top boundary TB2, a bottom boundary BB2 and an opposite side boundary SB2. The top boundary TB2 and the bottom boundary BB2 are parallel to the X direction. The side boundary SB2 is parallel to the Y direction. Even row cells 121-124 and 141-144 share the same cell height CH_even, which is defined between top boundary TB2 and bottom boundary BB2. Therefore, even rows Row2 and Row4 have a row height RH_even equal to the cell height CH_even. In some embodiments, the even row height RH_even is equal to the odd row height RH_odd. In some embodiments, the even row height RH_even is less than the odd row height RH_odd.

[0046] When cells 111-114 in Row1 abut cells 121-124 in Row2, the top border TB2 of cells 121-124 merges with the bottom border BB1 of cells 111-114. Similarly, the top border TB1 of cells 131-134 in Row3 merges with the bottom border BB2 of cells 121-124 in Row2, and the top border TB2 of cells 141-144 merges with the bottom border BB1 of cells 131-134 in Row3.

[0047] Figure 4A According to some embodiments, Figure 3 1 is a top view of an exemplary integrated circuit 100 of a fin layout. Figure 4B is along Figure 4A A cross-sectional view of the integrated circuit 100 taken along the line BB' in FIG. Figure 4C is along Figure 4A A cross-sectional view of the integrated circuit 100 taken along the line CC' in FIG. Figure 4D is along Figure 4A A cross-sectional view of the integrated circuit 100 taken along the line DD' in FIG. Figure 4E is along Figure 4A FIG. 1 is a cross-sectional view of the integrated circuit 100 taken along line EE′.

[0048] The integrated circuit 100 includes a substrate 400. The substrate 400 may be made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a Group IV compound semiconductor (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide), etc. In addition, the substrate 400 may include an epitaxial layer (epitaxial layer), which may be stretched to enhance performance, and / or may include a silicon-on-insulator (SOI) structure. In some embodiments, the substrate 400 is a non-SiGe substrate or a germanium-free substrate, such as a silicon substrate.

[0049] The substrate 400 includes N-well regions and P-well regions alternately arranged along the Y direction. Figure 4A As shown. The PFET fins FP_odd and FP_even extend in the N-well region, and the NFET fins FN_odd and FN_even extend in the P-well region. In some embodiments, the N-well region includes N-type dopants, such as phosphorus and arsenic. In some other embodiments, the P-well region includes P-type dopants, such as boron. In some embodiments, the PFET fins FP_odd and FP_even are composed of SiGe (for enhancing the strain effect), but the NFET fins FN_odd and FN_even are composed of non-SiGe semiconductor materials or germanium-free semiconductor materials (e.g., silicon (Si)). Therefore, the PFET fins FP_odd and FP_even can form a distinguishable interface with the Si substrate 400, and there may be no interface between the NFET fins FN_odd, FN_even and the Si substrate 400.

[0050] The integrated circuit 100 also includes gate structures 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, and 161 that are spaced a corresponding distance apart from each other, and each runs across Row1-Row4 in the Y direction. The gate structures 151-161 wrap around three sides of the PFET fins FP_odd and FP_even and the NFET fins FN_odd and FN_even. The gate structures 151-161 are arranged equidistantly with a gate pitch GP (i.e., the center-to-center spacing between adjacent gate structures). In some embodiments, the odd row height RH_odd of the odd rows (e.g., Row1 and Row3) is equal to or greater than three times the gate pitch GP. In addition, the fin length (measured in the X direction) of the PFET fins FP_odd and FP_even is greater than or equal to twice the gate pitch GP, and the fin length of the NFET fins FN_odd and FN_even is also greater than or equal to twice the gate pitch GP. In some embodiments, the NFET fin disconnect length B_odd between adjacent NFET fins FN_odd (measured in the X direction) in odd rows is greater than or equal to two times the gate pitch GP, and the NFET fin disconnect length B_even between adjacent NFET fins FN_even in even rows is also greater than or equal to two times the gate pitch GP. These relationships related to the gate pitch GP are selected to improve the performance of the integrated circuit 100, for example, to improve the RC delay.

[0051] exist Figure 4A In the illustrated embodiment, adjacent cells 111 and 112 share a single boundary gate structure 153 at their side boundaries, and adjacent cells 131 and 132 also share a single boundary gate structure 153 at their side boundaries. However, this arrangement is for illustrative purposes only and is not restrictive. In some other embodiments, adjacent cells 111 and 112 have separated boundary gate structures near the side boundaries between cells 111 and 112, but are separated by, for example, source / drain regions, and adjacent cells 131 and 132 have separated boundary gate structures near the side boundaries between cells 131 and 132, but are also separated by, for example, source / drain regions. Similarly, adjacent cells 122 and 123 share a single boundary gate structure 157 at their side boundaries, and adjacent cells 142 and 143 also share a single boundary gate structure 157 at their side boundaries. However, this arrangement is for illustrative purposes only and is not restrictive. In some other embodiments, adjacent cells 122 and 123 have separated boundary gate structures near the side boundary between cells 122 and 123, but are separated by, for example, source / drain regions. Adjacent cells 142 and 143 have separated boundary gate structures near the side boundary between cells 142 and 143, but are separated by, for example, source / drain regions.

[0052] The fins FN_odd, FP_odd, FN_even, and FP_even are electrically isolated from each other by the isolation structure 172. FIG. 4C to FIG. 4E In some embodiments, the isolation structure 172 is a shallow trench isolation (STI) structure, which includes a trench filled with one or more dielectric materials. In some embodiments, the STI structure includes silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

[0053] The STI structure 172 may be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trenches around the fins FN_odd, FP_odd, FN_even, and FP_even, and then recessing the top surface of the dielectric material to fall below the topmost portions of the fins FN_odd, FP_odd, FN_even, and FP_even. The dielectric material of the STI structure 172 may be deposited using high density plasma chemical vapor deposition (HDP-CVD), low pressure CVD (LPCVD), sub-atmospheric pressure CVD (SACVD), flowable CVD (FCVD), spin coating, etc., or a combination thereof. After deposition, an annealing process or a curing process may be performed. In some cases, the STI structure 172 may include a liner, such as a thermal oxide liner grown by oxidizing the silicon surface. The recessing process may use, for example, a planarization process (e.g., chemical mechanical polishing (CMP)) followed by a selective etching process (e.g., wet etching or dry etching or a combination thereof) that may recess the top surface of the dielectric material in the STI structure 172, thereby causing the upper portions of the fins FN_odd, FP_odd, FN_even, and FP_even to protrude from the surrounding insulating STI structure 172.

[0054] The PFET fins FP_odd and FP_even each include a channel region overlapping the corresponding gate structure 151-161, and a P-type source / drain region SDP located on an opposite side corresponding to one of the gate structures 151-161. The P-type source / drain region SDP includes a P-type dopant, such as boron. On the other hand, the NFET fins FN_odd and FN_even each include a channel region overlapping the corresponding gate structure 151-161, and an N-type source / drain region SDN located on an opposite side corresponding to one of the gate structures 151-161. The N-type source / drain region SDN includes an N-type dopant, such as phosphorus and arsenic.

[0055] In some embodiments, the source / drain regions SDP and SDN may be epitaxially grown regions. For example, the gate spacer 174 may be formed next to the dummy gate structure (which will be replaced by the final gate structure 151-161) by depositing a spacer material (e.g., silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof) and anisotropically etching the spacer material, and subsequently, the source / drain regions SDP and SDN may be formed to be self-aligned with the gate spacer 174. For example, the P-type source / drain region SDP is formed by first etching the PFET fins FP_odd and FP_even to form a groove and then depositing a crystalline semiconductor material (e.g., silicon germanium) in the groove by a selective epitaxial growth (SEG) process (which may fill the groove in the PFET fins FP_odd, FP_even and may further extend beyond the original surface of the PFET fins FP_odd, FP_even to form a raised source / drain region epitaxial structure in some embodiments). In some embodiments, a P-type dopant (e.g., boron) is doped in the epitaxial structure to form a P-type source / drain region SDP. Similarly, an N-type source / drain region SDN is formed by first etching the NFET fins FN_odd and FN_even to form a groove and then depositing a crystalline semiconductor material (e.g., silicon or silicon carbide) in the groove by a selective epitaxial growth (SEG) process (which can fill the groove in the NFET fins FN_odd, FN_even and can further extend beyond the original surface of the NFET fins FN_odd, FN_even to form a raised source / drain region epitaxial structure in some embodiments), and in some embodiments, an N-type dopant (e.g., phosphorus or arsenic) is doped in the epitaxial structure to form an N-type source / drain region SDN.

[0056] The SEG process for forming the source / drain regions SDN, SDP may use any suitable epitaxial growth method, such as vapor / solid / liquid phase epitaxy (VPE, SPE, LPE) or metal organic CVD (MOCVD) or molecular beam epitaxy (MBE), etc. High dose (e.g., from about 10 14 cm -2 to about 10 16 cm -2 ) P-type dopants can be introduced into the P-type source / drain regions SDP in situ during SEG or by an ion implantation process performed after SEG, or by a combination thereof. Similarly, a high dose (e.g., from about 10 14 cm -2 to about 10 16 cm -2) N-type dopants may be introduced into the N-type source / drain regions SDN in-situ during SEG or by an ion implantation process performed after SEG, or by a combination thereof.

[0057] The integrated circuit 100 also includes an interlayer dielectric (ILD) layer 176 formed over the source / drain regions SDN and SDP. Exemplary materials of the ILD layer 176 include, but are not limited to, silicon oxide, spin-on glass (SOG), fluorinated silicon oxide glass (FSG), carbon-doped silicon oxide, other suitable dielectric materials, and / or combinations thereof. In some embodiments, the ILD layer 176 is formed by a high-density plasma (HDP) deposition process. In one or more embodiments, the ILD layer 176 is planarized by a chemical mechanical polishing (CMP) process to be flush with the gate spacer 174.

[0058] In some embodiments, the gate structures 151-161 are high-k metal gate (HKMG) structures that can be formed using a gate-last process flow (interchangeably referred to as a gate replacement process). In the gate-last process flow, a sacrificial dummy gate structure (e.g., a polysilicon gate, not shown) is formed after forming the STI structure 172. The dummy gate structure may include a dummy gate dielectric, a dummy gate electrode (e.g., a polysilicon gate), and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, etc.) may be deposited. Next, a dummy gate material (e.g., polysilicon) may be deposited and then planarized (e.g., by CMP) over the dummy gate dielectric. A hard mask layer (e.g., silicon nitride, silicon carbide, etc.) may be formed over the dummy gate material. Then, the dummy gate structure is formed by patterning the hard mask layer and transferring the pattern to the dummy gate dielectric and dummy gate material using appropriate photolithography and etching techniques. The dummy gate structure may extend along three sides of the protruding fins FP_odd, FN_odd, FP_even, FN_even, and extend between two adjacent ones of the fins FP_odd, FN_odd, FP_even, FN_even above the surface of the STI structure 172. After forming the source / drain regions SDN, SDP and the ILD layer 176, the dummy gate structure is replaced by the HKMG gate structure 151-161. The materials for forming the dummy gate structure and the hard mask may be deposited using any suitable method (such as CVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), etc.) or by thermal oxidation of the semiconductor surface or a combination thereof.

[0059] In some embodiments, each of the HKMG gate structures 151-161 includes a high-k gate dielectric material and one or more gate metals. Exemplary high-k gate dielectric materials include, but are not limited to, silicon nitride, silicon oxynitride, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), silicon nitride oxide (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric includes a stack of an interface dielectric material and a high-k dielectric material. In some embodiments, the interface dielectric material includes silicon oxide. A gate metal is formed over the gate dielectric. Exemplary gate metals include, for example, copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN), or molybdenum nitride (MoN). The gate replacement process includes, for example, removing the dummy gate structure by an etching process to form a gate trench between corresponding gate spacers 174, depositing a high-k gate dielectric layer and one or more gate metal layers in the gate trench, and then performing a CMP process to remove excess material of the high-k gate dielectric layer and one or more gate metal layers outside the gate trench until the ILD layer 176 is exposed.

[0060] Figure 5 A flow chart of an exemplary method 500 of fabricating integrated circuit 100 according to some embodiments of the present invention is shown in FIG. 6A to 10C Some embodiments of the present invention are shown Figure 5 The various processes of the various stages of the method 500 are shown in FIG. Throughout the various views and illustrative embodiments, like reference numerals are used to indicate like elements. 6A to 10C In the “A” graph (e.g., Fig. 6A , Fig. 7A etc.) shows a top view, and the "B" diagram (e.g., Figure 6B , Figure 7B ) shows a cross-sectional view along the Y direction corresponding to the line BB' shown in the "A" figure, and the "C" figure (for example, Figure 6C , Figure 7C ) shows a cross-sectional view along the Y direction corresponding to the line CC' shown in the "A" figure. It should be understood that for additional embodiments of the method, 6A to 10CAdditional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchanged.

[0061] exist Figure 5 In operation S501 of the method 500, a SiGe epitaxial layer 610 is formed on a portion of the non-SiGe substrate 600. FIG. 6A to FIG. 6C As shown. In some embodiments, the non-SiGe substrate 600 may be made of a suitable non-germanium element semiconductor, such as silicon; a germanium-free alloy or compound semiconductor, such as a Group IV compound semiconductor (silicon carbide (SiC) or SiSn), a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide), etc. In addition, the non-SiGe substrate 600 may include an epitaxial layer (epitaxial layer), which may be stretched to enhance performance, and / or may include a silicon-on-insulator (SOI) structure.

[0062] The non-SiGe substrate 600 includes a P-well region and an N-well region alternately arranged along the Y direction. In some embodiments, the N-type well region and the P-type well region are formed by ion implantation by doping the non-SiGe substrate 600 with corresponding N-type and P-type dopants. Exemplary P-type dopants include, but are not limited to, boron or BF2. Exemplary N-type dopants include, but are not limited to, phosphorus and arsenic. During the formation of the P-well region, other regions of the non-SiGe substrate 600 are covered by a patterned mask. Similarly, during the formation of the N-well region, other regions of the non-SiGe substrate 600 are covered by another patterned mask.

[0063] Silicon germanium epitaxial layer 610 is formed by, for example, recessing a portion of substrate 600 within the N-well region using suitable photolithography and etching techniques, epitaxially growing a SiGe epitaxial layer from the recessed portion of substrate 600 , and then performing an optional CMP process to planarize the SiGe epitaxial layer with substrate 600 .

[0064] exist Figure 5 In operation S502 of the method 500, the SiGe layer 610 and the non-SiGe substrate 600 are patterned into SiGe fins 710 and non-SiGe fins 720, such as 7A to 7C The SiGe fin 710 and the non-SiGe fin 720 can be patterned by using photolithography and etching techniques. FIG. 6A to FIG. 6C) and non-SiGe substrate 600 are formed. For example, a spacer image transfer (SIT) patterning technique can be used for semiconductor fins. In this method, a sacrificial layer is formed and patterned over the SiGe layer 610 and non-SiGe substrate 600 using suitable lithography and etching processes to form a mandrel. Sidewall spacers are formed next to the mandrel using a self-aligned process. The sacrificial layer is then removed by an appropriate selective etching process. Each remaining spacer can then be used as a hard mask to etch a trench into the SiGe layer 610 and non-SiGe substrate 600 using, for example, reactive ion etching (RIE) to pattern the corresponding SiGe fins 710 and non-SiGe fins 720.

[0065] exist Figure 5 In operation S503 of method 500, a patterned mask 800 is formed over the SiGe fin 710 and the non-SiGe fin 720, so that a portion of the non-SiGe fin 720 is exposed. FIG. 8A to FIG. 8C As shown. In some embodiments, the patterned mask layer 800 may include an organic material, such as a photoresist material, and may be formed using a spin coating process, followed by patterning the photoresist material using a suitable photolithography technique to form a plurality of holes 810 and 820 extending through the patterned mask layer 800. For example, irradiate (exposure) and develop the photoresist material to remove the portion of the photoresist material. In more detail, a photomask (not shown) may be placed above the photoresist material, which may then be exposed to radiation light that may be ultraviolet (UV) or an excimer laser (such as a krypton fluoride (KrF) excimer laser or an argon fluoride (ArF) excimer laser). As a non-limiting example, the exposure of the photoresist material may be implemented using an immersion lithography tool or an extreme ultraviolet (EUV) tool to increase resolution and reduce the minimum achievable spacing. A baking or curing operation may be implemented to harden the exposed photoresist material, and depending on whether a positive or negative resist is used, a developer may be used to remove the exposed or unexposed portion of the photoresist material. Therefore, a layer such as Fig. 8A and Figure 8C Holes 810 and 820 are shown to expose isolated portions of the non-SiGe fins 720 .

[0066] exist Figure 5 In operation S504 of method 500, with patterned mask 800 in place, non-SiGe fins 720 exposed by holes 810 and 820 of patterned mask 800 are broken into a plurality of discontinuous non-SiGe fins 722 and 724 that are shorter than adjacent non-SiGe fins 720, such as 9A to 9C As shown. The fin disconnection process (or fin cutting process) may be implemented using, for example, a dry etching process, a wet etching process, and / or a combination thereof. Fig. 9AAs shown, the fin cutting process breaks the non-SiGe fin 720 into discontinuous non-SiGe fins 722 and 724, while leaving the other non-SiGe fin 720 intact. Therefore, the fin cutting process generates a 2P2N cell (a cell having two SiGe fins and two non-SiGe fins) 111, a 2P1N cell (a cell having two SiGe fins and one non-SiGe fin) 112, a 2P2N cell 113, and a 2P1N cell 114 arranged side by side along the X direction.

[0067] exist Figure 5 In operation S505 of method 500, the patterned mask 800 is removed, for example, using a plasma ashing process. In some embodiments, the plasma ashing process is performed so that the temperature of the photoresist mask 800 is increased until the photoresist mask 800 undergoes thermal decomposition and can be removed. However, any other suitable process, such as wet stripping, may be utilized. FIG. 10A to FIG. 10C The resulting structure is shown in .

[0068] exist Figure 5 In operation S506 of method 500, NFETs are formed on non-SiGe fins 720, 722, and 724, and PFETs are formed on SiGe fins 710. The fabrication of NFETs and PFETs includes, for example, forming an STI structure (e.g., such as a STI structure) laterally surrounding non-SiGe fins 720, 722, and 724 and a lower portion of SiGe fin 710. FIG. 4C to FIG. 4E forming a dummy gate structure (e.g., a polysilicon gate) extending along the Y direction across the non-SiGe fins 720, 722, and 724 and the SiGe fin 710; forming a gate spacer (e.g., as shown in FIG. 1 ) on opposite sidewalls of the dummy gate structure; and forming a gate spacer (e.g., as shown in FIG. 1 ). FIG. 4A to FIG. 4C forming a P-type source / drain region (eg, as shown in the gate spacer 174) in the portion of the SiGe fin 710 exposed by the dummy gate structure and the gate spacer; and forming a P-type source / drain region (eg, as shown in the gate spacer 174) in the portion of the SiGe fin 710 exposed by the dummy gate structure and the gate spacer. Figure 4B The P-type source / drain regions SDP shown in FIG. 1 ) are formed, and N-type source / drain regions (eg, as shown in FIG. 1 ) are formed in the portions of the non-SiGe fins 720, 722, and 724 exposed by the dummy gate structure and the gate spacers. Figure 4C An N-type source / drain region SDN as shown); an ILD layer is formed over the source / drain region (eg, Figure 4B and Figure 4C and replacing the gate structure (e.g., as shown in the ILD layer 176); Figure 4A The HKMG gate structures 151-161 shown in the figure replace the dummy gate structures. FIG. 4A to FIG. 4E The resulting structure is shown in .

[0069] Fig.11A top view of the fin layout of some cells of an exemplary integrated circuit 1100 designed by the system and method of the present invention is shown according to some embodiments. However, not all of the components shown are required, and some embodiments of the present invention may include Fig.11 Additional components not shown in the drawings may be included. The arrangement and types of components may be changed without departing from the scope of the invention as described herein. Additional, different or fewer components may be included.

[0070] like Fig.11 As shown, integrated circuit 1100 includes cell groups 1110, 1120, and 1130 arranged (i.e., laid out) in corresponding "cell rows" or "lines" relative to grid 1101. Furthermore, in some embodiments, each cell group includes one or more cells arranged side by side along a corresponding row. For example, cell group 1110 includes cells C101, C102, C103, C104, C105, C106, C107, C108, C109, C110 and C111 arranged in the first row (Row1) of grid 1101; cell group 1120 includes cells C201, C202, C203, C204, C205, C206 and C207 arranged in the second row (Row2) of grid 1101; cell group 1130 includes cells C301, C302, C303, C304, C305, C306, C307 and C308 arranged in the third row (Row3) of grid 1101.

[0071] Cells of cell groups 1110, 1120, and 1130 are retrieved from corresponding standard cell libraries having different numbers of PFET fins. As a non-limiting example, cells of cell groups 1110 and 1130 are retrieved from an odd-row cell library including a plurality of odd-row cells, each odd-row cell sharing a first number of PFET fins (e.g., three PFET fins); and cells of cell group 1120 are retrieved from an even-row cell library including a plurality of even-row cells, each even-row cell sharing a second number of PFET fins (e.g., two PFET fins). In other words, cells C101-C111 and C301-C308 are a subset of the odd-row cell library, and cells C201-C207 are a subset of the even-row cell library. Each of the cells C101-C111 and C301-C308 in the odd-row cell library and the cells C201-C207 in the even-row cell library are associated with specific logic functions and / or characteristics (e.g., timing characteristics). Therefore, it should be noted that although the cells C101-C111 and C301-C308 are retrieved from the odd-row cell library, not all cells share the same cell width. Similarly, although the cells C201-C207 are retrieved from the even-row cell library, not all cells share the same cell width.

[0072] In some embodiments, along Row1 of the grid 1101, cells C101-C111 respectively include three PFET fins FP_odd extending continuously across cells C101-C111 along the X direction; along Row2 of the grid 1101, cells C201-C207 respectively include two PFET fins FP_even extending continuously across cells C201-C207 along the X direction; along Row3 of the grid 1101, cells C301-C308 respectively include three PFET fins FP_odd extending continuously across cells C301-C308 along the X direction. In this configuration, cells in the same odd row (e.g., Row1 or Row3) share the same number of PFET fins (e.g., three PFET fins FP_odd), and cells in the same even row (e.g., Row2) share the same number of PFET fins (e.g., two PFET fins FP_even). Therefore, all the PFET fins FP_odd and FP_even do not come from the fin cutting process, so that stress relaxation in the PFET fins FP_odd and FP_even caused by the fin cutting process can be prevented.

[0073] In addition, along Row1 of the grid 1101, cells C101, C102, C103, C105, C107, C108, C109, and C111 include three NFET fins FN_odd, and cells C104, C106, and C110 include two NFET fins FN_odd, respectively. Along Row3 of the grid 1101, cells C301, C303, C305, C306 include three NFET fins FN_odd, respectively, and cells C302, C304, C307, and C308 include two NFET fins FN_odd, respectively. Along Row2 of the grid 1101, cells C201, C202, C204, C206, and C207 include three NFET fins FN_even, respectively, and cells C203 and C205 include two NFET fins FN_even, respectively.

[0074] The NFET fins of the cells in Row1-Row3 may be fabricated using a fin cutting process to break a single continuous NFET fin into multiple discontinuous NFET fins, as previously described. 6A to 10C Because NFET fins (e.g., silicon fins without germanium) suffer less stress relaxation caused by the fin cutting process than PFET fins (e.g., SiGe fins), the fin cutting process used to manufacture discontinuous NFET fins will have no effect or a negligible effect on the on-current of the NFETs of the cells in Row1-Row3.

[0075] Cells C101, C102, C103, C105, C107, C108, C109, and C111 in Row1 and C301, C303, C305, and C306 in Row3 have three PFET fins FP_odd and three NFET fins FN_odd, and thus these cells can be determined as 3P3N cells in the odd-row cell library. Cells C104, C106, and C110 in Row1 and cells C302, C304, C307, and C308 in Row3 have three PFET fins FP_odd and two NFET fins FN_odd, and thus these cells can be determined as 3P2N cells in the odd-row cell library. The cells C201, C202, C204, C206, and C207 in Row2 have two PFET fins FP_even and three NFET fins FN_even, and therefore these cells can be determined as 2P3N cells in the even-row cell library. The cells C203 and C205 in Row2 have two PFET fins FP_even and two NFET fins FN_even, and therefore these cells can be determined as 2P2N cells in the even-row cell library. Therefore, the odd-row cell library includes at least 3P3N cells and 3P2N cells, and the even-row cell library includes at least 2P3N cells and 2P2N cells. Therefore, the maximum number of fins (e.g., six fins) of the cells in the odd-row cell library is greater than the maximum number of fins (e.g., five fins) of the cells in the even-row cell library. Therefore, the odd-row cells can operate at a higher speed and are therefore suitable for high-speed applications. The even-row cells can operate with less power and are therefore useful for low-power applications. However, in some other embodiments, the maximum number of fins of cells in the odd-row cell library may be less than the maximum number of fins of cells in the even-row cell library, and thus the odd-row cells may be used for low-power applications and the even-row cells are suitable for high-speed applications. In some embodiments, the integrated circuit 1100 including the 3P3N cells and 3P2N cells in the speed-oriented rows, and the 2P3N cells and 2P2N cells in the power-oriented rows is suitable for a server chip.

[0076] In the integrated circuit 1100 suitable for a server chip, the row height of the speed-oriented rows (e.g., Row1 and Row3) is equal to or greater than three times the gate pitch of the integrated circuit 1100; the number of PFET fins in the speed-oriented rows is equal to or greater than three; the number of NFET fins in the speed-oriented rows is greater than or equal to one; the fin length of the fins in the speed-oriented rows is greater than or equal to twice the gate pitch of the integrated circuit 1100; and the NFET fin disconnection length between adjacent NFET fins in the speed-oriented rows is greater than or equal to twice the gate pitch of the integrated circuit 1100.

[0077] In addition, in the integrated circuit 1100 suitable for the server chip, the row height of the power-oriented row (e.g., Row2) is equal to or less than the row height of the speed-oriented row (e.g., Row1 and Row3); the number of PFET fins in the power-oriented row is equal to or less than the number of PFET fins in the speed-oriented row; the number of NFET fins in the power-oriented row is greater than or equal to one; the fin length of the fins in the power-oriented row is greater than or equal to twice the gate pitch of the integrated circuit 1100; and the NFET fin disconnection length between adjacent NFET fins in the power-oriented row is greater than or equal to twice the gate pitch of the integrated circuit 1100.

[0078] Fig.12 A top view of the fin layout of some cells of an exemplary integrated circuit 1200 designed by the system and method of the present invention is shown according to some embodiments. However, not all of the components shown are required, and some embodiments of the present invention may include Fig.12 Additional components not shown in the drawings may be included. The arrangement and types of components may be changed without departing from the scope of the invention as described herein. Additional, different or fewer components may be included.

[0079] like Fig.12 As shown, integrated circuit 1200 includes cell groups 1210, 1220, and 1230 that are respectively arranged relative to grid 1201. Furthermore, in some embodiments, each cell group includes one or more cells arranged side by side along a corresponding row. For example, cell group 1210 includes cells C401, C402, C403, C404, C405, C406, C407, C408, C409, C410 and C411 arranged in the first row (Row1) of grid 1201; cell group 1220 includes cells C501, C502, C503, C504, C505, C506 and C507 arranged in the second row (Row2) of grid 1201; cell group 1230 includes cells C601, C602, C603, C604, C605, C606, C607 and C608 arranged in the third row (Row3) of grid 1201.

[0080] Cells of cell groups 1210, 1220, and 1230 are retrieved from corresponding standard cell libraries having different numbers of PFET fins. As a non-limiting example, cells of cell groups 1210 and 1230 are retrieved from an odd-row cell library including a plurality of odd-row cells, each odd-row cell sharing a first number of PFET fins (e.g., two PFET fins); and cells of cell group 1220 are retrieved from an even-row cell library including a plurality of even-row cells, each even-row cell sharing a second number of PFET fins (e.g., one PFET fin). In other words, cells C401-C411 and C601-C608 are a subset of the odd-row cell library, and cells C501-C507 are a subset of the even-row cell library. Each of the cells C401-C411 and C601-C608 in the odd-row cell library and the cells C501-C507 in the even-row cell library are associated with specific logic functions and / or characteristics (e.g., timing characteristics). Therefore, it should be noted that although the cells C401-C411 and C601-C608 are retrieved from the odd-row cell library, not all cells share the same cell width. Similarly, although the cells C501-C507 are retrieved from the even-row cell library, not all cells share the same cell width.

[0081] In some embodiments, along Row1 of the grid 1201, cells C401-C411 respectively include two PFET fins FP_odd extending continuously across cells C401-C411 along the X direction; along Row2 of the grid 1201, cells C501-C507 respectively include one PFET fin FP_even extending continuously across cells C501-C507 along the X direction; along Row3 of the grid 1201, cells C601-C608 respectively include two PFET fins FP_odd extending continuously across cells C601-C608 along the X direction. In this configuration, cells in the same odd row (e.g., Row1 or Row3) share the same number of PFET fins (e.g., two PFET fins FP_odd), and cells in the same even row (e.g., Row2) share the same number of PFET fins (e.g., one PFET fin FP_even). Therefore, all the PFET fins FP_odd and FP_even do not come from the fin cutting process, so that stress relaxation in the PFET fins FP_odd and FP_even caused by the fin cutting process can be prevented.

[0082] In addition, along Row1 of the grid 1201, cells C401, C402, C403, C405, C407, C408, C409 and C411 include two NFET fins FN_odd respectively, and cells C404, C406 and C410 include one NFET fin FN_odd respectively; along Row3 of the grid 1201, cells C601, C603, C605, C606 include two NFET fins FN_odd respectively, and cells C602, C604, C607 and C608 include one NFET fin FN_odd respectively; along Row2 of the grid 1201, cells C501, C502, C504, C506 and C507 include two NFET fins FN_even respectively, and cells C503 and C505 include one NFET fin FN_even respectively. The NFET fins of the cells in Row1-Row3 may be fabricated using a fin cutting process to break a single continuous NFET fin into a plurality of discontinuous NFET fins, as previously described with respect to 6A to 10C discussed.

[0083] Cells C401, C402, C403, C405, C407, C408, C409, and C411 in Row1 and C601, C603, C605, and C606 in Row3 have two PFET fins FP_odd and two NFET fins FN_odd, and thus these cells can be determined as 2P2N cells in the odd-row cell library. Cells C404, C406, and C410 in Row1 and cells C602, C604, C607, and C608 in Row3 have two PFET fins FP_odd and one NFET fin FN_odd, and thus these cells can be determined as 2P1N cells in the odd-row cell library. The cells C501, C502, C504, C506, and C507 in Row2 have one PFET fin FP_even and two NFET fins FN_even, and therefore these cells can be determined as 1P2N cells in the even-row cell library. The cells C503 and C505 in Row2 have one PFET fin FP_even and one NFET fin FN_even, and therefore these cells can be determined as 1P1N cells in the even-row cell library. Therefore, the odd-row cell library includes at least 2P2N cells and 2P1N cells, and the even-row cell library includes at least 1P2N cells and 1P1N cells. Therefore, the maximum number of fins (e.g., four fins) of the cells in the odd-row cell library is greater than the maximum number of fins (e.g., three fins) of the cells in the even-row cell library. Therefore, the odd-row cells can operate at a higher speed and are therefore suitable for high-speed applications. The even-row cells can operate with less power and are therefore useful for low-power applications. However, in some other embodiments, the maximum number of fins of cells in the odd-row cell library may be less than the maximum number of fins of cells in the even-row cell library, and thus the odd-row cells may be used for low-power applications and the even-row cells are suitable for high-speed applications. In some embodiments, the integrated circuit 1200 including the 2P2N cells and the 2P1N cells in the speed-oriented rows, and the 1P2N cells and the 1P1N cells in the power-oriented rows is suitable for mobile chips.

[0084] In an integrated circuit 1200 suitable for a mobile chip, the row height of a speed-oriented row (e.g., Row1 and Row3) is greater than or equal to twice the gate pitch of the integrated circuit 1200; the number of PFET fins in the speed-oriented row is equal to or greater than two; the number of NFET fins in the speed-oriented row is greater than or equal to one; the fin length of the fins in the speed-oriented row is greater than or equal to twice the gate pitch of the integrated circuit 1200; and the NFET fin disconnection length between adjacent NFET fins in the speed-oriented row is greater than or equal to twice the gate pitch of the integrated circuit 1200.

[0085] Moreover, in the integrated circuit 1200 suitable for mobile chips, the row height of the power-oriented row (e.g., Row2) is equal to or less than the row height of the speed-oriented row (e.g., Row1 and Row3); the number of PFET fins in the power-oriented row is equal to or less than the number of PFET fins in the speed-oriented row; the number of NFET fins in the power-oriented row is greater than or equal to one; the fin length of the fins in the power-oriented row is greater than or equal to twice the gate pitch of the integrated circuit 1200; and the NFET fin disconnection length between adjacent NFET fins in the power-oriented row is greater than or equal to twice the gate pitch of the integrated circuit 1200.

[0086] Reference now Fig.13 , according to some embodiments of the present invention, a block diagram of an information handling system (IHS) 1300 is provided. IHS 300 can be a computer platform for implementing any or all of the processes discussed herein to design integrated circuits with mixed row fin numbers (e.g., integrated circuits 100, 1100, and 1200). IHS 1300 may include a processing unit 1310, such as a desktop computer, an operating station, a laptop computer, or a dedicated unit customized for a specific application. IHS 1300 may be equipped with a display 1314 and one or more input / output (I / O) components 1312, such as a mouse, keyboard, or printer. Processing unit 1310 may include a central processing unit (CPU) 1320 connected to a bus 1330, a memory 1322, a mass storage device 1324, a video adapter 1326, and an I / O interface 1328.

[0087] Bus 1330 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or a video bus. CPU 1320 may include any type of electronic data processor, and memory 1322 may include any type of system memory such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).

[0088] Mass storage device 1324 may include any type of storage device configured to store data, programs, and other information and make the data, programs, and other information accessible via bus 1330. Mass storage device 1324 may include, for example, one or more of a hard drive, a magnetic disk drive, an optical disk drive, etc.

[0089] Video adapter 1326 and I / O interface 1328 provide interfaces for coupling external input and output devices to processing unit 1310. Fig.13As shown, examples of input and output devices include a display 1314 coupled to a video adapter 1326 and an I / O component 1312 coupled to an I / O interface 1328, such as a mouse, keyboard, printer, etc. Other devices can be coupled to the processing unit 1310, and additional or fewer interface cards can be used. For example, a serial interface card (not shown) can be used to provide a serial interface for a printer. The processing unit 1310 can also include a network interface 1340, which can be a wired link and / or a wireless link to a local area network (LAN) or a wide area network (WAN) 1316. The IHS 1300 may include other components / devices. For example, the IHS 1300 may include a power supply, a cable, a motherboard, a removable storage medium, a housing, etc. These other components / devices (but not shown) are considered part of the IHS 1300.

[0090] In some embodiments of the present invention, electronic design automation (EDA) is a program code executed by CPU 1320 to analyze user files to obtain the layout of an integrated circuit (e.g., integrated circuits 100, 1100, and 1200 as discussed above). In addition, during the execution of the EDA, the EDA can analyze the functional components of the layout. CPU 1320 can access the program code remotely from memory 1322, mass storage device 1324, etc., via bus 1330, or through network interface 1340.

[0091] Fig.13 Also shown is a mask room 1350 that receives a verified layout generated from IHS 1300, for example, via a communication network such as LAN / WAN 1316. Mask room 1350 has a plurality of devices for manufacturing one or more photomasks (e.g., such as a plurality of photomasks) based on the verified layout generated from IHS 1300. FIG. 8A to FIG. 8C The IC manufacturing facility ("Fab") 1360 may be connected to the mask room 1350 and the IHS 1300 via a communication network such as the LAN / WAN 1316. The fabrication facility 1360 includes an IC manufacturing tool 1362 for manufacturing IC chips using the photomasks manufactured by the mask room 1350. As an example but not limiting, the IC manufacturing tool 1362 may be a cluster tool for manufacturing IC chips. The cluster tool may be a multi-reaction chamber type composite device including a multi-sided transfer chamber with a wafer handling robot inserted at its center, a plurality of process chambers (e.g., CVD chambers, PVD chambers, etching chambers, annealing chambers, etc.) located on each wall of the multi-sided transfer chamber, and load lock chambers installed on different walls of the transfer chamber.

[0092] In some embodiments, two or more of the IHS 1300, the mask room 1350, and the fabrication plant 1360 are owned by a single company. For example, two or more of the IHS, the mask room 1350, and the fabrication plant 1360 are simultaneously present in a common facility and use common resources. In some other embodiments, the IHS 1300 is owned by a design house, which is a different entity from the mask room 1350 and the fabrication plant 1360. In such embodiments, each of the mask room 1350, the fabrication plant 1360, and the design house that owns the IHS 1300 interacts with one or more other entities and provides services to and / or receives services from the one or more other entities.

[0093] Fig.14 1400 and an IC manufacturing process 1420 according to some embodiments of the present invention are shown. The IC design process 1400 implements IC design from high-level specifications to physical layout, which has been verified for, for example, functionality, speed performance, power, and is developed for generating masks. The IC manufacturing process 1420 manufactures IC chips using photomasks manufactured based on the layout generated from the IC design process 1400. According to some embodiments of the present invention, the IC design process 1400 can be performed by, for example, an IHS 1300 having EDA functions (such as Fig.13 1400) to generate a physical layout of an integrated circuit including a mixed number of row fins. In various embodiments, the operation of the IC design flow 1400 is performed by Fig.13 For the purpose of discussion, the components shown are implemented in Fig.13 The following embodiment of the IC design flow 1400 is described. The illustrated embodiment of the IC design flow 1400 is merely an example. Therefore, it should be understood that any of the various operations may be omitted, reordered, and / or added while remaining within the scope of the present invention.

[0094] IC design flow 1400 begins with providing operations of "performance / functional design S1401" and "design constraints S1402". In some embodiments, performance / functional design S1401 specifies the desired performance or functionality of an integrated circuit (e.g., integrated circuits 100, 1100, and / or 1200 as discussed above) based on various signals or stimuli applied to the input of the integrated circuit overall design, and can be written in a suitable language such as a hardware description language (HDL). Performance / functional design S1401 can be implemented through I / O interface 1328 (e.g., Fig.131320) to the processing unit 1310, such as a file generated by a user when executing EDA. Optionally, the performance / function design S1401 can be uploaded and / or saved in the memory 1322 or the mass storage device 1324, or the performance / function design S1401 can be uploaded from a remote user via the network interface 1340 (such as Fig.13 In these cases, the CPU 1320 will access the performance / function design S1401 during the execution of the EDA.

[0095] In addition, the user also provides design constraints S1402 to constrain the overall design of the physical layout of the performance / functional design S1402. In some embodiments, the design constraints S1402 may be input, for example, via the I / O interface 1328, downloaded via the network interface 1340, etc. The design constraints S1402 may specify timing, process parameters, and other suitable constraints that are expected to conform to the performance / functional design S1401 once it is physically formed into an integrated circuit.

[0096] After providing the performance / function design S1401 and the design constraints S1402, the IC design flow 1400 continues to the operation "synthesis S1403" to generate a functionally equivalent logic circuit description, such as a netlist. Synthesis S1403 forms a functionally equivalent logic circuit description by matching the performance and / or function required by the performance / function design S1401 with (standard) cells in a set of cell libraries S1410, while satisfying the constraints specified by the design constraints S1402.

[0097] In some embodiments, the group of cell libraries S1410 may include multiple cell libraries having cells with different numbers of fins, such as, for example, cell library A, cell library B, etc. In some embodiments, cell libraries A and B may correspond to the above-mentioned odd-row cell library and even-row cell library, respectively. Each of the multiple cell libraries contains a pre-designed list of cells, each cell has a common number of PFET fins, and a specific logic function can be implemented on a small scale. For example, the cells of cell library A may share a first number of PFET fins, and the cells of cell library B may share a second number of PFET fins that is different from the first number of PFET fins. The cells are stored in the cell library (e.g., cell library A, cell library B, etc.) as information, which includes internal circuit elements, various connections to these circuit elements, and pre-designed physical layout patterns including the number of PFET fins, the number of NFET fins, cell height, dopant type, doping concentration, wells, etc. In addition, the stored cell page may include the shape of the cell, the terminal position for external connection, delay characteristics, power consumption, etc.

[0098] Once synthesis S1403 generates a functionally equivalent logic circuit description from the performance / functional design S1401 and the design constraints S1402 using cells of a group of cell libraries S1410 (eg, cell library A, cell library B, etc.), the IC design flow 1400 continues to operation "place and route S1404".

[0099] Implementation of placement and routing S1404 to generate an actual physical design for the entire structure. By placing the cells selected from the cell library S1410 into the corresponding rows, the layout S1404 forms a physical design. This placement and routing S1404 can be automatically completed by an automatic placement and routing (APR) tool, or this placement and routing S1404 can be optionally implemented by a manual process part, so that the user can manually insert one or more cells into the row. The detailed structure and related geometry of the device (e.g., transistor) of the integrated circuit are determined in the placement operation. After the placement operation, the interconnection between different devices is routed. The implementation of the placement and routing operations all conforms to the design rule check (DRC) platform so that the manufacturing requirements of the integrated circuit are met. In some embodiments, the clock tree synthesis operation is implemented in the placement and routing stage S1404 of the digital circuit, wherein the clock generator and the circuit are combined into the design. Once the placement and routing stage S1404 is completed, an initial placement and routing layout with an actual physical design for the entire structure is generated, and then the IC design process 1400 continues to the operation "power reduction S1405".

[0100] In the power reduction stage S1405, some or all of the cells in the initial layout and wiring layout are swapped or replaced with cells having fewer fins, which in turn can reduce the power of the actual physical design of the entire structure. The power reduction stage S1405 can be completed automatically by, for example, an APR tool, or can optionally be partially implemented by a manual process, so that the user can manually swap the cells in the initial layout and wiring layout with cells having fewer fins. Once the power reduction stage is completed, a first modified layout with an actual physical design for the entire structure is generated, and then the IC design process 1400 continues to the operation "static timing analysis S1406".

[0101] As a non-limiting example, based on the resistance and capacitance (RC) extraction results of the first modified layout generated from the power reduction stage S1405, a static timing analysis (STA) stage S1406 is implemented. The RC extraction is implemented by an RC extraction tool to determine parasitic parameters, such as parasitic resistance and parasitic capacitance of the cells in the first modified layout. Such parasitic parameters are not what the circuit designer wants, but occur due to the configuration and / or materials of the various cells in the integrated circuit. STA is implemented using the extracted parasitic resistance and capacitance to evaluate the time delay along each signal path in the first modified layout. Therefore, the timing critical path and the non-timing critical path in the first modified layout can be determined in the STA stage S1406. In some embodiments, the timing critical path is a signal path between an input and an output, having a maximum time delay or an unacceptable time delay determined based on the RC extraction results, and the non-timing critical path is a signal path determined according to the RC extraction results, and the delay between the input delay and the output delay can be ignored.

[0102] Once the critical timing path is determined in the STA stage S1406, the IC design process 1400 continues to operation "Timing Recovery S1407". In the timing recovery stage S1407, some or all of the cells in the determined timing critical path are swapped with cells having more fins, which in turn can increase the operating speed of the cells, thereby reducing the time delay in the determined timing critical path. The timing recovery stage S1407 can be completed automatically by, for example, an APR tool, or can also be partially implemented by a manual process, so that the user can manually swap the cells in the determined timing critical path with cells having more fins. Once the timing recovery stage S1407 is completed, a second modified layout with an actual physical design for the entire structure is generated, and then the IC design process 1400 continues to another static timing analysis S1408.

[0103] As a non-limiting example, the STA stage S1408 is implemented based on the RC extraction results for the second modified layout generated from the timing recovery stage S1407. The RC extraction tool is implemented by the RC extraction tool to determine parasitic parameters, such as parasitic resistance and parasitic capacitance of the cells in the second modified layout. The STA stage S1408 is implemented using the extracted parasitic resistance and capacitance to evaluate the time delay along various signal paths in the second modified layout.

[0104] Then the method continues to determine operation S1409 to check whether the design requirements match. In some embodiments, in determining operation S1409, various requirements can be checked, such as, for example, the time delay in the layout of the second modification, the power of the layout of the second modification, and the spacing utilization of the layout of the second modification (that is, the area of ​​the substrate occupied by the unit), etc., by using a circuit simulator (for example, a simulation program with integrated circuit emphasis (SPICE)) to implement one or more simulations. If all design requirements in determining operation S1409 are met, the second modification layer is accepted as a verification layout, and then signed accordingly. However, if one of the design requirements is not met, the IC design flow 1400 loops back to the previous stage to adjust the layout of the second modification. For example, if the time delay in the layout of the second modification is unfavorable, the IC design flow 1400 can loop back to the timing recovery stage S1407, wherein the units in the timing critical path are re-swapped to solve the time delay problem.

[0105] Once the IC design flow 1400 is completed, the verified layout is retrieved, and then the IC manufacturing flow 1420 begins at the mask manufacturing stage S1421 to manufacture one or more photomasks based on the verified layout accepted in the IC design flow 1400. For example, the mask house 1350 (e.g., Fig.13 ) using the validated layout accepted at the determination stage S1409 of the IC design flow 1400 to manufacture one or more photomasks (e.g., FIG. 8A to FIG. 8C The photomask used in the manufacturing steps shown in FIG. 1 is used to manufacture the fin and gate structures of the IC chip according to the verified layout.

[0106] In the mask manufacturing stage S1421, the mask room 1350 performs mask data preparation, in which the verified layout is converted into a representative data file ("RDF"). The mask data preparation provides the RDF to the mask manufacturing tool 1352 in the mask room. The mask manufacturing tool 1352 includes, for example, a mask writer. The mask writer 1342 converts the RDF into an image on a substrate such as a photomask (reticle). The verified layout can be manipulated by the mask data preparation to conform to the specific characteristics of the mask writer and / or the requirements of the manufacturing plant 1360.

[0107] In some embodiments, mask data preparation includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the verified layout accepted in the IC design flow 1400. In some embodiments, mask data preparation includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary components, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0108] In some embodiments, the mask data preparation operation includes a mask rule checker (MRC) for checking a verified layout generated by the IC design flow 1400, which has been processed in the OPC and uses a set of mask generation rules to include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the verified layout to compensate for the constraints during mask manufacturing, which can undo some of the modifications implemented by the OPC to meet the mask generation rules.

[0109] In some embodiments, mask data preparation includes a lithography process check (LPC) that simulates a process to be performed by the fabrication plant 1360 to manufacture an IC chip. The LPC simulates the process based on a verified layout generated from the IC design flow 1400 to produce a simulated manufactured IC chip. The processing parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or a combination thereof. In some embodiments, after a simulated manufactured device is generated by LPC, if the shape of the simulated IC chip is not close enough to meet the design rules, the OPC and / or MRC are repeated to further improve the verified layout generated from the IC design flow 1400.

[0110] Those of ordinary skill will appreciate that the above description of mask data preparation has been simplified for the purpose of clarity. In some embodiments, data preparation includes additional features such as logic operations (LOPs) to modify the verified layout generated from the IC design flow 1400 according to manufacturing rules. In addition, the processes applied to the verified layout generated from the IC design flow 1400 during data preparation can be performed in a variety of different orders.

[0111] Based on the verified layout generated from the IC design process 1400, a photomask or a set of photomasks is manufactured using a mask manufacturing tool 1352. In some embodiments, the mask manufacturing tool 1352 implements one or more photolithographic exposures based on the verified layout generated from the IC design process 1400. In some embodiments, based on the verified layout generated from the IC design process 1400, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on the photomask. The photomask can be formed with a variety of techniques. In some embodiments, a photomask is formed using a binary technique. In some embodiments, the mask pattern includes an opaque region and a transparent region. A radiation beam, such as an ultraviolet (UV) beam, used to expose a radiation-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque region and transmitted through the transparent region. In one example, a binary mask version of the photomask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque region of the binary mask. In another example, a photomask is formed using a phase shift technique. In a phase shift mask (PSM) version of one or more photomasks, various features in the pattern formed on the phase shift photomask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various instances, the phase shift photomask can be an attenuated PSM or an alternating PSM. The photomasks manufactured by the mask manufacturing tool 1352 are used in a variety of processes. For example, such photomasks are used in subsequent IC manufacturing stages S1422, including, for example, ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0112] Once the mask fabrication stage S1421 is completed, the IC fabrication process 1420 continues to the IC fabrication stage S1422, where the IC fabrication process 1420 is performed using, for example, the fabrication plant 1360 (eg, Fig.13 The manufacturing plant 1360 uses the IC manufacturing tool 1362 to manufacture IC chips (such as the photomask manufactured by the mask chamber 1350). Fig.13 1400). Thus, the fabrication plant 1360 at least indirectly uses the verified layout generated from the IC design flow 1400 to fabricate IC chips. In some embodiments, semiconductor wafers (e.g., Si wafers) undergo various processes (e.g., Figure 5 In some embodiments, IC manufacturing S1422 at least includes performing one or more photolithography exposures based on the verified layout generated from IC design flow 1400 indirectly.

[0113] Fig.15A flowchart including a reference IC design flow 1500, a first improved IC design flow 1510, and a second improved IC design flow 1520 according to some embodiments of the present invention is shown. In the reference IC design flow 1500, the synthesis stage S1501 forms a functionally equivalent logic circuit description by matching the performance and / or function required by the performance / function design with the 3P3N cells from cell library A and / or cell library B, while satisfying the restrictions specified by the design restrictions.

[0114] Once the synthesis phase S1501 is completed, the reference IC design flow 1500 continues to the APR phase S1502 to generate the actual physical design of the entire structure. The APR phase S1502 forms the physical design by taking the selected 3P3N cells and placing them into corresponding rows.

[0115] Once the APR stage S1502 is completed, the reference IC design flow 1500 then continues to the STA stage S1503, where the time delays along various signal paths are calculated from the placement and routing placement paths generated from the APR stage S1502. From the reference IC design flow 1500, it can be seen that the cells in the synthesis stage S1501, the APR stage S1502, and the STA stage S1503 are all 3P3N cells.

[0116] In the first improved IC design flow 1510, the synthesis stage S1511 forms a functionally equivalent logic circuit description by matching the rows and / or functions required by the row / function design with 3P3N cells from cell library A and / or cell library B while satisfying the constraints specified by the design constraints.

[0117] Once the synthesis phase S1511 is completed, the first improved IC design flow 1510 continues to the APR phase S1512 to generate the actual physical design of the entire structure. The APR phase S1512 forms the physical design by selecting selected 3P3N cells and placing these 3P3N cells into corresponding rows.

[0118] Once the APR stage S1512 is completed, the first improved IC design flow 1510 then continues to the power minimization stage S1513 to reduce power. As a non-limiting example, in the power minimization stage S1513, all 3P3N cells in the odd rows of the placement and routing layout generated from the APR stage S1512 are swapped with 3N2N cells selected from the cell library A (i.e., the odd row cell library), and all 3P3N cells in the even rows of the placement and routing layout are swapped with 2P2N cells selected from the cell library A (i.e., the odd row cell library). The power minimization stage S1512 can be completed by, for example, an APR tool.

[0119] Once the power minimization phase S1513 is completed, a first modified layout having 3P2N cells in odd rows and 2P2N cells in even rows is generated, and then the first improved IC design flow 1510 continues to the first STA phase S1514, where timing critical paths and non-timing critical paths in the first modified layout are determined based on the RC extraction results for the first modified layout, as previously described for Fig.14 The STA stage S1406 shown is discussed.

[0120] Once the first STA phase S1514 is completed, the first improved IC design flow 1510 continues to the timing recovery phase S1515. The timing recovery phase S1515 is similar to Fig.14 The timing recovery stage S1407 of the IC design flow 1400 is shown. As a non-limiting example, in the timing recovery stage S1515, the 3P2N odd rows in the timing critical path determined in the first STA stage S1514 are swapped with 3P3N cells selected from cell library A (i.e., odd row cell library), and the 2P2N even row cells in the timing critical path determined in the first STA stage S1514 are swapped with 2P3N cells selected from cell library B (i.e., even row cell library).

[0121] Once the timing recovery phase S1515 is completed, a second modified layout is generated and includes 3P3N odd row cells and 2P3N even row cells in the timing critical path and 3P2N odd row cells and 2P2N even row cells in the non-timing critical path. Then, the first improved IC design process 1510 continues to the second STA phase S1516, in which the time delays along various signal paths in the second modified layout generated from the timing recovery phase S1515 are evaluated. It can be seen from the first improved IC design process 1510 that the cells in the synthesis phase S1511 and the APR phase S1512 are all 3P3N cells, the cells in the first STA phase S1514 are 3P2N cells in odd rows and 2P2N cells in even rows, and the cells in the second STA phase S1516 are 3P3N cells, 3P2N cells in odd rows, and 2P3N cells, 2P2N cells in even rows.

[0122] In the second improved IC design process 1520, the synthesis stage S1521 forms a functionally equivalent logic circuit description by matching the rows and / or functions required by the row / function design with the 3P3N cells, 3P2N cells, 2P3N cells and 2P2N cells in cell library A and / or cell library B while satisfying the restrictions specified by the design constraints.

[0123] Once the synthesis phase S1521 is completed, the second improved IC design flow 1520 continues to the APR phase S1522 to generate the actual physical design for the entire structure. The APR phase S1522 forms the physical design by placing the selected 3P3N cells and 3P2N cells into odd rows and the selected 2P3N cells and 2P2N cells into even rows.

[0124] Once the APR stage S1522 is completed, the second improved IC design flow 1520 then continues to the reasonable placement stage S1523 to reduce power. The reasonable placement stage S1523 swaps all cells with three NFET fins in the layout and routing layout generated from the APR stage S1522 with cells with two NFET fins. As a non-limiting example, in the reasonable placement stage S1523, the 3P3N cells and 2P3N cells in the layout and routing layout generated from the APR stage S1522 are swapped with 3P2N cells or 2P2N cells selected from cell library A and / or cell library B. The reasonable placement stage S1523 can be completed by, for example, an APR tool.

[0125] Once the reasonable placement phase S1523 is completed, a first modified layout with 3P2N cells and 2P2N cells is generated, and then the second improved IC design flow 1520 continues to the first STA phase S1524, where the timing critical paths and non-timing critical paths in the first modified layout are determined based on the RC extraction results of the first modified layout, as previously described. Fig.14 The STA stage S1406 shown is discussed.

[0126] Once the first STA stage S1524 is completed, the second improved IC design flow 1520 continues to the timing recovery stage S1525. As a non-limiting example, in the timing recovery stage S1525, the 3P2N cells in the timing critical path determined in the first STA stage S1524 are swapped with 3P3N cells selected from cell library A and / or cell library B, and the 2P2N cells in the timing critical path determined in the first STA stage S1524 are swapped with 2P3N cells selected from cell library A and / or cell library B.

[0127] Once the timing recovery phase S1525 is completed, a second modified layout is generated and includes 3P3N cells and 2P3N cells in the timing critical path and 3P2N cells and 2P2N cells in the non-timing critical path. The second improved IC design flow 1520 then continues to the second STA phase S1526, where the time delays along the various signal paths in the second modified layout generated from the timing recovery phase S1525 are evaluated. It can be seen from the second improved IC design process 1520 that the cells in the synthesis stage S1521 are 3P3N cells, 3P2N cells, 2P3N cells and 2P2N cells, the cells in the APR stage S1522 are 3P3N cells and 3P2N cells in odd rows and 2P3N cells and 2P2N cells in even rows, the cells in the first STA stage S1524 are 3P2N cells and 2P2N cells, and the cells in the second STA stage S1526 are 3P3N cells, 3P2N cells, 2P3N cells and 2P2N cells.

[0128] Fig.16 16 is a graph 1600 providing exemplary simulation results for a layout generated from a reference IC design flow 1500, a layout generated from a first improved IC design flow 1510, and a layout generated from a second improved IC design flow 1520. The first improved IC design flow 1510 results in a layout power reduction of about 13% to about 15%, a speed reduction of about 1% to about 3%, and an area (i.e., space utilization) increase of about 0% to about 1% compared to the reference IC design flow 1500. In addition, the second improved IC design flow 1520 results in a layout power reduction of about 11% to about 13%, a speed reduction of about 1% to about 3%, and an area increase of about 5% to about 7% compared to the reference IC design flow 1500. The simulation results indicate that the improved IC design flow can have an acceptable or negligible impact on the space utilization and speed performance of the IC in exchange for significant power improvements of the IC.

[0129] Based on the above discussion, it can be seen that the present invention provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages must be discussed here, and no particular advantage is required for all embodiments. One advantage is that the carrier mobility of the PFET fin can be maintained because the improved layout design does not require the fin cutting process to be performed on the PFET fin. Another advantage is that power consumption can be significantly reduced.

[0130] In some embodiments of the present invention, the IC structure includes one or more first cell rows and one or more second cell rows extending in a first direction. Each of the one or more first cell rows includes a plurality of first cells arranged along the first direction. Each of the plurality of first cells includes one or more first fins having a first source / drain region of a first conductivity type and one or more second fins having a second source / drain region of a second conductivity type opposite to the first conductivity type. Each of the one or more second cell rows includes a plurality of second cells arranged along the first direction. Each of the plurality of second cells includes one or more third fins having a third source / drain region of the first conductivity type and one or more fourth fins having a fourth source / drain region of the second conductivity type. The plurality of first cells have the same first number of one or more first fins, and the plurality of second cells have the same second number of one or more third fins that is less than the first number of one or more first fins.

[0131] In some embodiments, the plurality of first cells differ at least in the number of the one or more second fins. In some embodiments, the plurality of second cells differ at least in the number of the one or more fourth fins. In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type. In some embodiments, the one or more first fins and the one or more third fins are formed of the same first semiconductor material, and the one or more second fins and the one or more fourth fins are formed of the same second semiconductor material different from the first semiconductor material. In some embodiments, the first semiconductor material is germanium-containing, and the second semiconductor material is germanium-free. In some embodiments, the one or more first cell rows are arranged alternately with the one or more second cell rows along a second direction perpendicular to the first direction. In some embodiments, the one or more first fins extend continuously across the plurality of first cells along the first direction, and two of the one or more second fins are spaced apart along the first direction. In some embodiments, one of the one or more second fins extends across the plurality of first cells along the first direction. In some embodiments, the one or more third fins extend continuously across the plurality of second cells along the first direction, and two of the one or more fourth fins are spaced apart along the first direction. In some embodiments, one of the one or more fourth fins extends across the plurality of second cells along the first direction.

[0132] In some embodiments of the present invention, the IC structure includes a plurality of first cells and a plurality of second cells. Each of the plurality of first cells has a first number of one or more P-type field effect transistor (PFET) fins. A first subset of the plurality of first cells is arranged along a first direction in a first cell row. Each of the plurality of second cells has a second number of one or more PFET fins that is different from the first number of one or more PFET fins. A first subset of the plurality of second cells is arranged along a first direction in a second cell row adjacent to the first cell row. Each of the one or more PFET fins in the first cell row spans the entire first subset of the plurality of first cells, and each of the one or more PFET fins in the second cell row spans the entire first subset of the plurality of second cells.

[0133] In some embodiments, a first one of the first subset of the plurality of first cells has a first number of one or more N-type field effect transistor (NFET) fins, and a second one of the first subset of the plurality of first cells has a second number of one or more NFET fins that is different from the first number of one or more NFET fins. In some embodiments, one of the one or more NFET fins in the first cell row does not span the entire first subset of the plurality of first cells. In some embodiments, a first one of the first subset of the plurality of second cells has a third number of one or more NFET fins, and a second one of the first subset of the plurality of second cells has a fourth number of one or more NFET fins that is different from the third number of one or more NFET fins. In some embodiments, the third number of the one or more NFET fins of the first one of the first subset of the plurality of second cells is equal to the first number of the one or more NFET fins of the first one of the first subset of the plurality of first cells, and the fourth number of the one or more NFET fins of the second one of the first subset of the plurality of second cells is equal to the second number of the one or more NFET fins of the second one of the first subset of the plurality of first cells. In some embodiments, a second subset of the plurality of first cells is disposed along the first direction in a third cell row, a second subset of the plurality of second cells is disposed along the first direction in a fourth cell row, and the first cell row, the second cell row, the third cell row, and the fourth cell row are arranged in an alternating configuration along a second direction perpendicular to the first direction.

[0134] In some embodiments of the present invention, the method includes: placing multiple first cells, each having a first number of NFET fins, in a layout; swapping the multiple first cells with multiple second cells, each having a second number of NFET fins less than the first number of NFET fins; determining a timing critical path in the layout after swapping the multiple first cells with the multiple second cells; swapping some of the multiple second cells in the determined timing critical path with multiple third cells, each having a third number of NFET fins greater than the second number of NFET fins; and manufacturing an integrated circuit based on the layout after swapping some of the multiple second cells in the determined timing critical path with the multiple third cells.

[0135] In some embodiments, swapping the plurality of first cells with the plurality of second cells comprises: swapping a first group of the plurality of first cells in odd rows of the layout with a first group of the plurality of second cells each having a first number of PFET fins; and swapping a second group of the plurality of first cells in even rows of the layout with a second group of the plurality of second cells each having a second number of PFET fins less than the first number of PFET fins. In some embodiments, swapping some of the plurality of second cells in the determined timing critical path with the plurality of third cells comprises: swapping some of the first group of the plurality of second cells in the timing critical path with a first group of the plurality of third cells each having a third number of PFET fins equal to the first number of PFET fins; and swapping some of the second group of the plurality of second cells in the timing critical path with the second group of the plurality of third cells each having a fourth number of PFET fins equal to the second number of PFET fins.

[0136] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit structure, comprising: one or more first cell rows extending in a first direction, each first cell row comprising a plurality of first cells arranged along the first direction, wherein each of the plurality of first cells comprises one or more first fins having a first source / drain region of a first conductivity type and one or more second fins having a second source / drain region of a second conductivity type opposite to the first conductivity type; and One or more second cell rows extending in a first direction, each second cell row comprising a plurality of second cells arranged along the first direction, wherein each of the plurality of second cells comprises one or more third fins having a third source / drain region of the first conductivity type and one or more fourth fins having a fourth source / drain region of the second conductivity type, wherein the plurality of first units have the same first number of the first fins, and the plurality of second units have the same second number of the third fins, the second number being smaller than the first number, wherein the one or more first fins extend continuously across the plurality of first units along the first direction, and two of the second fins are spaced apart along the first direction.

2. The integrated circuit structure according to claim 1, wherein: The plurality of first units differ in at least the number of the second fins.

3. The integrated circuit structure according to claim 1, wherein: The plurality of second units are different in at least the number of the fourth fins.

4. The integrated circuit structure according to claim 1, wherein: The first conductivity type is a P type, and the second conductivity type is an N type.

5. The integrated circuit structure according to claim 1, wherein: The one or more first fins and the one or more third fins are formed of a same first semiconductor material, and the one or more second fins and the one or more fourth fins are formed of a same second semiconductor material that is different from the first semiconductor material.

6. The integrated circuit structure according to claim 5, wherein: The first semiconductor material is germanium-containing and the second semiconductor material is germanium-free.

7. The integrated circuit structure according to claim 1, wherein: The one or more first unit rows are alternately arranged with the one or more second unit rows along a second direction perpendicular to the first direction.

8. The integrated circuit structure of claim 1 , further comprising: A plurality of gate structures span the one or more first cell rows and the one or more second cell rows along a second direction perpendicular to the first direction.

9. The integrated circuit structure according to claim 8, wherein: A second fin among the one or more second fins extends across the plurality of first cells along the first direction.

10. The integrated circuit structure according to claim 1, wherein: The one or more third fins extend continuously across the plurality of second cells along the first direction, and two of the fourth fins are spaced apart along the first direction.

11. The integrated circuit structure according to claim 10, wherein: A fourth fin among the one or more fourth fins extends across the plurality of second cells along the first direction.

12. An integrated circuit structure comprising: a plurality of first cells, each having a first number of one or more PFET fins, wherein a first subset of the plurality of first cells are arranged along a first direction in a first row of cells; and a plurality of second cells, each having a second number of one or more PFET fins, the second number being different from the first number, each of the second cells further having one or more NFET fins, wherein a first subset of the plurality of second cells is arranged along a first direction in a second cell row adjacent to the first cell row, Wherein, each of the PFET fins in the first cell row spans the entire first subset of the multiple first cells, and each of the PFET fins in the second cell row spans the entire first subset of the multiple second cells, and one of the NFET fins in the second cell row does not span the entire first subset of the multiple second cells.

13. The integrated circuit structure according to claim 12, wherein: A first one of the first subsets of the plurality of first cells has a first number of NFET fins, and a second one of the first subsets of the plurality of first cells has a second number of NFET fins, the second number being different than the first number.

14. The integrated circuit structure according to claim 13, wherein: One of the NFET fins in the first row of cells does not span the entire first subset of the plurality of first cells.

15. The integrated circuit structure according to claim 13, wherein: A first one of the first subsets of the second plurality of cells has a third number of NFET fins and a second one of the first subsets of the second plurality of cells has a fourth number of NFET fins that is different than the third number.

16. The integrated circuit structure according to claim 15, wherein: The third number of NFET fins of the first first subset of the multiple second cells is equal to the first number of NFET fins of the first first subset of the multiple first cells, and the fourth number of NFET fins of the second first subset of the first subset of the multiple second cells is equal to the second number of NFET fins of the second first subset of the first subset of the multiple first cells.

17. The integrated circuit structure according to claim 12, wherein: A second subset of the plurality of first cells is arranged along the first direction in a third cell row, a second subset of the plurality of second cells is arranged along the first direction in a fourth cell row, and the first cell row, the second cell row, the third cell row and the fourth cell row are arranged in an alternating configuration along a second direction perpendicular to the first direction.

18. A method of forming an integrated circuit structure, comprising: placing a plurality of first cells each having a first number of NFET fins in the layout; swapping the plurality of first cells with a plurality of second cells each having a second number of NFET fins less than the first number of NFET fins; After swapping the plurality of first cells with the plurality of second cells, determining a timing critical path in the layout; swapping some of the plurality of second cells in the determined timing critical path with a plurality of third cells each having a third number of NFET fins greater than the second number of NFET fins; as well as After swapping some of the plurality of second cells in the determined timing critical path with the plurality of third cells, each PFET fin in the first cell, the second cell, and the third cell in the odd rows of the layout continuously extends across the odd rows along the row direction, and one NFET fin in the first cell, the second cell, and the third cell in the odd rows does not cross the odd rows along the row direction, and an integrated circuit is manufactured based on the layout.

19. The method according to claim 18, wherein: Exchanging the plurality of first units with the plurality of second units comprises: swapping a first group of the plurality of first cells in odd-numbered rows of the layout with a first group of the plurality of second cells each having a first number of PFET fins; and A second group of the plurality of first cells in even-numbered rows of the layout are swapped with a second group of the plurality of second cells each having a second number of PFET fins less than the first number of PFET fins.

20. The method according to claim 19, wherein: Swapping some of the plurality of second cells in the determined timing critical path with the plurality of third cells comprises: swapping some of the first plurality of second cells in the timing critical path with a first plurality of third cells each having a third number of PFET fins equal to the first number of PFET fins; and Some of the second plurality of second cells in the timing critical path are swapped with a second plurality of third cells each having a fourth number of PFET fins equal to the second number of PFET fins.

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