Image sensing device

Abstract

An image sensing device includes a pixel array, which includes a plurality of unit pixels arranged in rows and columns. Each of the plurality of unit pixels includes: a photoelectric conversion element that generates charge carriers by converting light incident on the photoelectric conversion element; a plurality of floating diffusion regions that are separated from the photoelectric conversion element to hold the charge carriers; a plurality of recycling gates that are located on both sides of the photoelectric conversion element along each of a first direction and a second direction perpendicular to the first direction, configured to generate an electric field in different regions of the photoelectric conversion element based on a recycling control signal, and configured to cause movement of the charge carriers; and a plurality of transfer gates that are located between the recycling gates and configured to transfer the charge carriers generated by the photoelectric conversion element to the corresponding floating diffusion regions.

Description

Technical Field

[0001] The technologies and implementations disclosed in this patent document generally relate to an image sensing device. Background Art

[0002] Image sensors are devices for converting optical images into electrical signals. With the recent development of the automotive, medical, computer and communication industries, the demand for high-performance image sensors is increasing in various devices such as digital cameras, camcorders, personal communication systems (PCS), game consoles, surveillance cameras, medical micro cameras, robots, etc. Summary of the invention

[0003] Various embodiments of the disclosed technology are directed to an image sensing device having a new structure to improve its operating characteristics.

[0004] In one embodiment of the disclosed technology, an image sensing device may include a pixel array including a plurality of unit pixels arranged in rows and columns. Each of the plurality of unit pixels includes: a photoelectric conversion element that generates charge carriers by converting light incident on the photoelectric conversion element; a plurality of floating diffusion regions that are separated from the photoelectric conversion element to hold the charge carriers; a plurality of recycling gates that are located on both sides of the photoelectric conversion element along each of a first direction and a second direction perpendicular to the first direction, configured to generate an electric field in different regions of the photoelectric conversion element based on a recycling control signal, and configured to cause the movement of charge carriers; and a plurality of transfer gates that are located between the recycling gates and configured to transfer the charge carriers generated by the photoelectric conversion element to the corresponding floating diffusion regions.

[0005] In another embodiment of the disclosed technology, an image sensing device may include a pixel array including a plurality of unit pixels for performing photoelectric conversion of incident light and outputting an electrical signal corresponding to the incident light. Each of the plurality of unit pixels may include: a photoelectric conversion element that generates charge carriers by converting incident light; a plurality of recycling gates that are located on both sides of the photoelectric conversion element in each of a first direction and a second direction perpendicular to the first direction; a plurality of transfer gates that are located between the recycling gates and are alternately arranged with the recycling gates; and a plurality of floating diffusion regions that are located on one side of each of the plurality of transfer gates in a direction opposite to the photoelectric conversion element based on each of the plurality of transfer gates.

[0006] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0008] Figure 2 The invention is a method for illustrating some implementations based on the disclosed technology. Figure 1 FIG. 1 is a plan view of an example of a unit pixel formed in a pixel array shown.

[0009] Figure 3A is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line AA′ is shown.

[0010] Figure 3B is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line BB′ is shown.

[0011] Figure 3C is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line CC' is shown.

[0012] Figure 3D is a diagram showing some implementations based on the disclosed technology. Figure 2 A cross-sectional view of an example of a unit pixel taken along line DD′ is shown.

[0013] Figure 4A Some implementations based on the disclosed technology are shown. Figure 2 Shown is how electrons move through a recycling gate in a unit pixel.

[0014] Figure 4B Some implementations based on the disclosed technology are shown. Figure 2 The unit pixel shown here transfers electrons to the floating diffusion region through the transfer gate.

[0015] Figure 5 Some implementations based on the disclosed technology are shown Figure 2 A timing diagram of the operation of a unit pixel is shown.

[0016] 6A to 6H is a diagram showing some embodiments of the disclosed technology configured to Figure 5 A schematic diagram of the operations on a unit pixel in the steps shown. DETAILED DESCRIPTION

[0017] In order to acquire a three-dimensional (3D) image using an image sensor, color information of the 3D image and the distance (or depth) between a target object and the image sensor are required.

[0018] The image sensor can use either a passive method or an active method when acquiring information associated with the distance between the target object and the image sensor.

[0019] The passive method can calculate the distance between the target object and the image sensor using only the image information of the target object without providing an optical signal to the target object. The passive method can be applied to a stereo camera.

[0020] Unlike passive methods, active methods can use artificial light signals provided by lasers or LEDs to measure the distance between a target object and an image sensor. Examples of such active methods may include triangulation and time-of-flight (TOF) methods. After a light signal has been sent to a target from a light source (e.g., a laser source or LED) spaced a predetermined distance from the image sensor, the triangulation method can detect the light reflected from the target object and use the detected light to calculate the distance between the target object and the image sensor. After a light signal has been sent from a light source to a target object, the TOF method can measure the round-trip time of the light signal reflected from the target object and returned to the image sensor to calculate the distance between the target object and the image sensor.

[0021] This patent document provides an implementation and example of an image sensing device including a new structure for improving operating characteristics.

[0022] Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to represent the same or similar parts. In the following description, detailed descriptions of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter.

[0023] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0024] In some implementations, the image sensing device can use the time of flight (TOF) principle to measure the distance. In one example, the TOF sensor can work by illuminating the target object with a modulated light source and observing the reflected light. The phase shift between the illumination and the reflection is measured and converted into the distance between the target object and the TOF sensor. The image sensing device may include a light source 100, a lens module 200, a pixel array 300, and a control circuit 400.

[0025] When receiving the clock signal MLS from the control circuit 400, the light source 100 can emit light to the target object 1. In one example, the light source 100 can be a laser diode (LD) or a light emitting diode (LED) for emitting infrared light or visible light. In another example, the light source 100 can be a monochromatic light source combined with a near-infrared laser (NIR), a point light source, a white light lamp and a monochromator, or a combination of other laser sources. For example, the light source 100 can emit infrared light with a wavelength of 800nm ​​to 1000nm. Although for the convenience of description, Figure 1 Only one light source 100 is shown, but the scope or spirit of the disclosed technology is not limited thereto, and a plurality of light sources may also be arranged near the lens module 200 .

[0026] The lens module 200 may collect light reflected from the target object 1, and may focus the collected light onto the pixel (PX) of the pixel array 300. The lens module 200 may include a focusing lens having a surface formed of glass or plastic or another cylindrical optical element having a surface formed of glass or plastic. The lens module 200 may include a focusing lens having a convex structure.

[0027] The pixel array 300 may include unit pixels (PX) arranged in a two-dimensional (2D) array in succession, wherein the unit pixels are arranged in rows and columns. The unit pixel (PX) may convert light received through the lens module 200 into an electrical signal corresponding to the received light, so that each unit pixel can output a pixel signal. In some implementations, the pixel signal may be an electrical signal converted from the reflected light by the TOF sensor unit pixel to indicate a time delay based on the distance to the target object 1 rather than indicating the color of the target object 1. Some implementations of the disclosed technology may implement two mechanisms to allow each unit pixel (PX) to (1) move charge carriers (e.g., electrons) generated by the photoelectric conversion element based on the reflected light in a predetermined direction (i.e., clockwise or counterclockwise), and (2) transfer the electrons collected by such movement to a plurality of floating diffusion regions. Here, the two mechanisms may be performed separately from each other. In some implementations, each unit pixel (PX) may include a plurality of circulation gates and a plurality of transfer gates formed to surround the photoelectric conversion element. Such a recycling gate and transfer gate are operated so that a certain voltage is applied to the recycling gate in sequence, and a certain voltage is applied to the transfer gate in sequence in a clockwise or counterclockwise continuous order. As a result, the electrons generated in the photoelectric conversion element can move or transfer in a predetermined direction as the voltage levels at the recycling gate and the transfer gate change. As described above, when the TOF sensor illuminates the target object with a light source and observes the reflected light, the movement and transmission of such electrons performed separately from each other can allow for a more effective analysis of the time delay or phase shift between illumination and reflection (which is converted into the distance between the TOF sensor and the target object 1). In some embodiments, the structure and operation of the unit pixel (PX) are implemented as described below.

[0028] The control circuit 400 can control the light source 100 so that light can be sent to the target object 1 at the correct timing. The control circuit 400 can also process each pixel signal corresponding to the light reflected from the target object 1 by operating the unit pixel (PX) of the pixel array 300, and can measure the time delay based on the distance to the surface of the target object 1.

[0029] In some implementations, the control circuit 400 may include a row decoder 410 , a light source driver 420 , a timing controller 430 , a modulation driver 440 , and a logic circuit 450 .

[0030] The row decoder 410 may activate the unit pixel (PX) of the pixel array 300 in response to the timing signal generated from the timing controller 430. For example, the row decoder 410 may generate a control signal capable of selecting at least one of the plurality of row lines. The control signal may include not only a reset signal required to initialize the unit pixel (PX), but also other signals required to transmit a tap signal generated from a floating diffusion region of the unit pixel (PX) to the logic circuit 450.

[0031] The light source driver 420 may generate a clock signal MLS capable of operating the light source 100 in response to a control signal from the timing controller 430 .

[0032] The timing controller 430 may generate timing signals to control the row decoder 410 , the light source driver 420 , the modulation driver 440 , and the logic circuit 450 .

[0033] The modulation driver 440 may generate a control signal for controlling a modulation operation of the unit pixel (PX) based on a control signal of the timing controller 430, and may transmit the generated control signal to the pixel array 300. For example, the modulation driver 440 may generate a circulation control signal for controlling the movement of electrons in the photoelectric conversion element of the unit pixel (PX) and a transfer control signal for sequentially transferring the moved electrons to the floating diffusion region, so that the modulation driver 440 can provide the circulation control signal and the transfer control signal to the pixel array 300.

[0034] The logic circuit 450 may process the pixel signal received from the pixel array 300 based on the timing signal of the timing controller 430, and thereby may calculate the time delay based on the distance to the target object 1. The logic circuit 450 may include a correlated double sampler (CDS) circuit for performing correlated double sampling (CDS) on the pixel signal generated from the pixel array 300. In addition, the logic circuit 450 may include an analog-to-digital converter (ADC) for converting an output signal of the CDS circuit into a digital signal.

[0035] Figure 2 The following are some examples of implementations based on the disclosed technology. Figure 1 A plan view of an example of a unit pixel in a pixel array shown.

[0036] In some implementations, each unit pixel (PX) may include a photoelectric conversion element (PD), a plurality of floating diffusion regions FD1-FD4, a plurality of drain nodes D1-D4, a plurality of transfer gates TG1-TG4, and a plurality of recycling gates CG1-CG4.

[0037] The photoelectric conversion element (PD) may be formed in a semiconductor substrate. The photoelectric conversion element (PD) may generate charge carriers by converting a light beam reflected from a target object 1 and incident on a semiconductor substrate. For example, the photoelectric conversion element (PD) may generate electron and hole pairs in response to such a reflected light beam. The photoelectric conversion element (PD) may include a stacked structure in which different types of impurity regions are vertically stacked on top of each other. For example, the photoelectric conversion element may include a photodiode (PD) or a pinned photodiode (PPD) in which an N-type impurity region and a P-type impurity region are vertically stacked on top of each other.

[0038] Each of the floating diffusion regions FD1-FD4 may be located on one side of a corresponding one of the transfer gates TG1-TG4, and may hold electrons transferred through the transfer gates TG1-TG4. Signals corresponding to the amount of charge carriers (e.g., electrons) stored in the floating diffusion regions FD1-FD4 may be output as tap signals TAP1-TAP4, respectively. The tap signals TAP1-TAP4 may be applied to the gates of the corresponding source follower transistors (not shown) through wires. For example, the floating diffusion regions FD1-FD4 may be connected to the gates of the corresponding source follower transistors (not shown) through wires. In addition, the tap signals TAP1-TAP4 may be applied to the terminals of the corresponding reset transistors (not shown) through wires. For example, the floating diffusion regions FD1-FD4 may be connected to the terminals of the corresponding reset transistors (not shown) through wires. Each of the floating diffusion regions FD1-FD4 may include an impurity region formed by injecting N-type impurities into a semiconductor substrate to a predetermined depth.

[0039] The drain nodes D1-D4 may be located at one side of the corresponding cyclic gates CG1-CG4, respectively, and each of the drain nodes D1-D4 may be connected to an input terminal of a drain voltage (Vd) through a wire. The drain voltage (Vd) may be at a low voltage (e.g., ground voltage) level during a modulation period (during which charge carriers (photogenerated electrons) generated by the photoelectric conversion element (PD) are collected and then transferred to the floating diffusion regions FD1-FD4 through the transfer gates TG1-TG4), and may be at a high voltage (e.g., power supply voltage) level during a readout period after the modulation period. Each of the drain nodes D1-D4 may include an impurity region formed by injecting N-type impurities into a semiconductor substrate to a predetermined depth.

[0040] The transfer gates TG1 - TG4 may transfer electrons generated in the photoelectric conversion element (PD) to the floating diffusion regions FD1 - FD4 upon receiving transfer control signals TFv1 - TFv4 . The transfer control signals TFv1 - TFv4 may be received from the modulation driver 440 .

[0041] The cyclic gates CG1-CG4 may be operated in response to the cyclic control signals Vcir1-Vcir4 during the modulation period so that the charge carriers (electrons) generated in the photoelectric conversion element (PD) can move in a predetermined direction (e.g., in a counterclockwise direction) in the photoelectric conversion element (PD). During the readout period, the cyclic gates CG1-CG4 may fix the voltage level of the photoelectric conversion element (PD) at the drain voltage (Vd) based on the draining control signal (draining control signal) (Vdrain). The cyclic control signals Vcir1-Vcir4 and the draining control signal (Vdrain) may be received from the modulation driver 440.

[0042] In some implementations, when viewed from above, the cyclic gates CG1-CG4 may be respectively located in regions corresponding to four sides of a rectangular shape formed to surround the photoelectric conversion element (PD). During the modulation period, the cyclic gates CG1-CG4 may sequentially receive the cyclic control signals Vcir1-Vcir4 in a clockwise or counterclockwise continuous order, so that the cyclic gates CG1-CG4 can locally generate an electric field in an edge region of the photoelectric conversion element (PD), and can change the electric field in a corresponding direction at a predetermined time interval. In this way, the electrons of the photoelectric conversion element (PD) can move in a direction that is changed based on the electric field generated and changed as described above.

[0043] In this case, the cyclic control signals Vcir1-Vcir4 may have a voltage level insufficient to electrically couple the photoelectric conversion element (PD) to the drain nodes D1-D4. In other words, during the modulation period, the cyclic gates CG1-CG4 may be used to move electrons of the photoelectric conversion element (PD) from one place to another within the photoelectric conversion element (PD).

[0044] During the readout period, the cyclic gates CG1-CG4 may fix the voltage level of the photoelectric conversion element (PD) at the drain voltage (Vd) in response to the drain control signal (Vdrain), so that the cyclic gates CG1-CG4 can prevent noise from being introduced into the photoelectric conversion element (PD), thereby preventing signal distortion. For example, when the drain control signal (Vdrain) is activated to a high level, the drain control signal (Vdrain) may have a high voltage, and the cyclic gates CG1-CG4 may electrically couple the photoelectric conversion element (PD) to the drain node D1-D4 through the high voltage. That is, the activated drain control signal (Vdrain) may be at a higher voltage than the activated cyclic control signals Vcir1-Vcir4.

[0045] Therefore, during the readout period, the drain control signal (Vdrain) can be activated to a high level. In this case, the drain nodes D1-D4 are electrically coupled to the photoelectric conversion element (PD), so that the voltage level of the photoelectric conversion element (PD) can be fixed to a high drain voltage (Vd). During the modulation period, the drain control signal (Vdrain) can be disabled to a low level.

[0046] During the modulation period, each of the cyclic gates CG1-CG4 can receive a cyclic control signal Vcir1-Vcir4 in response to a switching operation of a corresponding switching element in the switching elements S1-S4. During the readout period, each of the cyclic gates CG1-CG4 can receive a drain control signal (Vdrain) in response to a switching operation of the switching elements S1-S4.

[0047] In order to generate and change the electric field at a higher speed in a region as large as possible, the cyclic gates CG1-CG4 may be such that the region formed to overlap the photoelectric conversion element (PD) in each of the cyclic gates CG1-CG4 has a maximum length (or maximum width) W1. For example, the width (W1) of each of the cyclic gates CG1-CG4 may be greater than the length (i.e., width) (W2) of the region formed to overlap the photoelectric conversion element (PD) in each of the transfer gates TG1-TG4. When viewed from above, each of the cyclic gates CG1-CG4 may be formed into a rectangular shape. For example, each of the cyclic gates CG1 and CG3 may be formed into a rectangular shape, wherein the length of each of the cyclic gates CG1 and CG3 in the second direction (i.e., the Y-axis direction) is longer than the length of each of the cyclic gates CG1 and CG3 in the first direction (i.e., the X-axis direction), and each of the cyclic gates CG2 and CG4 may be formed into a rectangular shape, wherein the length of the first direction (i.e., the X-axis direction) is longer than the length of the second direction (i.e., the Y-axis direction).

[0048] The transfer gates TG1-TG4 and the cyclic gates CG1-CG4 may be spaced a predetermined distance apart from each other while being alternately arranged on the semiconductor substrate. When viewed from above, the transfer gates TG1-TG4 and the cyclic gates CG1-CG4 may be arranged in a ring shape surrounding the photoelectric conversion element (PD).

[0049] The cyclic gates CG1 and CG3 may be located on both sides of the photoelectric conversion element (PD) along the first direction on the semiconductor substrate, and the cyclic gates CG2 and CG4 may be located on both sides of the photoelectric conversion element (PD) along the second direction. For example, the cyclic gates CG1-CG4 may be located in a region corresponding to four sides of a rectangular shape formed to surround the photoelectric conversion element (PD), and a portion of the cyclic gates CG1-CG4 may overlap the photoelectric conversion element (PD).

[0050] Each of the transfer gates TG1-TG4 can be separated from two adjacent recycle gates by a predetermined distance and can be arranged between the corresponding recycle gates at the same time. For example, the transfer gates TG1-TG4 can be located in the region corresponding to the vertices of the rectangular shape, and a portion of the transfer gates TG1-TG4 can overlap with the photoelectric conversion element (PD).

[0051] Figure 3A is along Figure 2 The cross-sectional view of the unit pixel is taken along the line AA′. Figure 3B is along Figure 2 The cross-sectional view of the unit pixel is taken along the line BB′. Figure 3C is along Figure 2 The cross-sectional view of the unit pixel is taken along the line CC'. Figure 3D is along Figure 2 The cross-sectional view of the unit pixel is taken along the line DD′.

[0052] Reference Figure 3A , the semiconductor substrate 10 may include a first surface on which the reflected light is incident and a second surface facing the first surface.

[0053] The photoelectric conversion element (PD) may be located at a central portion of the unit pixel (PX) in the semiconductor substrate 10, and may include a stacked structure in which an N-type impurity region (n) and a P-type impurity region (p+) are vertically stacked. The photoelectric conversion element (PD) may generate charge carriers by photoelectrically converting incident light (reflected light) received through the first surface of the semiconductor substrate 10.

[0054] The drain nodes D1 and D3 may be located at both sides of the photoelectric conversion element (PD) so that the drain nodes D1 and D3 can be spaced apart from the photoelectric conversion element (PD) by a predetermined distance along a first direction within the semiconductor substrate 10. Each of the drain nodes D1 and D3 may include an impurity region formed by implanting N-type high-density impurities (n+) into the semiconductor substrate 10. Each of the drain nodes D1 and D3 may be coupled to an input terminal of a drain voltage (Vd) through a wire.

[0055] The cyclic gate CG1 may be formed between the photoelectric conversion element (PD) and the drain node D1 at the second surface of the semiconductor substrate 10, and the cyclic gate CG3 may be formed between the photoelectric conversion element (PD) and the drain node D3 at the second surface of the semiconductor substrate 10. For example, the drain node D1 and the photoelectric conversion element (PD) may be located on both sides of the cyclic gate CG1, so that the drain node D1 and the photoelectric conversion element (PD) are connected to the cyclic gate CG1. As a result, the drain node D1 and the photoelectric conversion element (PD) may be used as the source region / drain region of the cyclic gate CG1. In addition, the drain node D3 and the photoelectric conversion element (PD) may be located on both sides of the cyclic gate CG3, so that the drain node D3 and the photoelectric conversion element (PD) are connected to the cyclic gate CG3. As a result, the drain node D3 and the photoelectric conversion element (PD) may be used as the source region / drain region of the cyclic gate CG3.

[0056] The insulating layer 20 may be formed on the photoelectric conversion element (PD) at the second surface of the semiconductor substrate 10 .

[0057] Reference Figure 3B The photoelectric conversion element (PD) may be located in a central portion of the unit pixel (PX), and may include a stacked structure in which an N-type impurity region (n) and a P-type impurity region (p+) are vertically stacked in the semiconductor substrate 10.

[0058] The drain nodes D2 and D4 may be located at both sides of the photoelectric conversion element (PD) while being spaced apart from the photoelectric conversion element (PD) by a predetermined distance in the second direction in the semiconductor substrate 10. Each of the drain nodes D2 and D4 may include an impurity region formed by injecting N-type high-density impurities (n+) into the semiconductor substrate 10. Each of the drain nodes D2 and D4 may be coupled to an input terminal of a drain voltage (Vd) through a wire.

[0059] The cyclic gate CG2 may be formed between the photoelectric conversion element (PD) and the drain node D2 at the second surface of the semiconductor substrate 10, and the cyclic gate CG4 may be formed between the photoelectric conversion element (PD) and the drain node D4 at the second surface of the semiconductor substrate 10. For example, the drain node D2 and the photoelectric conversion element (PD) may be located on both sides of the cyclic gate CG2, so that the drain node D2 and the photoelectric conversion element (PD) are connected to the cyclic gate CG2. As a result, the drain node D2 and the photoelectric conversion element (PD) may be used as the source region / drain region of the cyclic gate CG2. In addition, the drain node D4 and the photoelectric conversion element (PD) are located on both sides of the cyclic gate CG4, so that the drain node D4 and the photoelectric conversion element (PD) are connected to the cyclic gate CG4. As a result, the drain node D4 and the photoelectric conversion element (PD) may be used as the source region / drain region of the cyclic gate CG4.

[0060] The insulating layer 20 may be formed on the photoelectric conversion element (PD) at the second surface of the semiconductor substrate 10 .

[0061] That is, a cross-sectional structure of the unit pixel (PX) along the first direction may be identical in shape to a cross-sectional structure of the unit pixel (PX) along the second direction.

[0062] Reference Figure 3C The photoelectric conversion element (PD) may be located in a central portion of the unit pixel (PX), and may include a stacked structure in which an N-type impurity region (n) and a P-type impurity region (p+) are vertically stacked in the semiconductor substrate 10.

[0063] The floating diffusion (FD) regions FD1 and FD3 may be located at both sides of the photoelectric conversion element (PD) while being spaced apart from the photoelectric conversion element (PD) by a predetermined distance along a third direction in the semiconductor substrate 10. In this case, the third direction may refer to a specific direction formed to pass between the first direction and the second direction.

[0064] Each of the floating diffusion regions FD1 and FD3 may include an impurity region formed by injecting N-type high-density impurities (n+) into the semiconductor substrate 10. The floating diffusion region FD1 may output a tap signal TAP1 through a conductive line, and the floating diffusion region FD3 may output a tap signal TAP3 through a conductive line. The tap signal TAP1 may refer to a signal corresponding to the amount of charge carriers (e.g., electrons) transferred to the floating diffusion region FD1 through the transfer gate TG1, and the tap signal TAP3 may refer to a signal corresponding to the amount of charge carriers (e.g., electrons) transferred to the floating diffusion region FD3 through the transfer gate TG3.

[0065] The tap signals TAP1 and TAP3 may be applied to the gates of corresponding source follower transistors (not shown) through conductive lines. In addition, the tap signals TAP1 and TAP3 may be applied to the terminals of corresponding reset transistors (not shown) through conductive lines.

[0066] The transfer gate TG1 may be formed between the photoelectric conversion element (PD) and the floating diffusion area FD1 at the second surface of the semiconductor substrate 10, and the transfer gate TG3 may be formed between the photoelectric conversion element (PD) and the floating diffusion area FD3 at the second surface of the semiconductor substrate 10. That is, each of the transfer gates TG1 and TG3 may be used as a gate of a transistor, wherein the photoelectric conversion element (PD) and the floating diffusion areas FD1 and FD3 are used as source / drain areas.

[0067] The insulating layer 20 may be formed on the photoelectric conversion element (PD) at the second surface of the semiconductor substrate 10 .

[0068] Reference Figure 3D The photoelectric conversion element (PD) may be located in a central portion of the unit pixel (PX), and may include a stacked structure in which an N-type impurity region (n) and a P-type impurity region (p+) are vertically stacked in the semiconductor substrate 10.

[0069] The floating diffusion regions FD2 and FD4 may be located at both sides of the photoelectric conversion element (PD) while being spaced apart from the photoelectric conversion element (PD) by a predetermined distance in a fourth direction perpendicular to the third direction within the semiconductor substrate 10 .

[0070] Each of the floating diffusion regions FD2 and FD4 may include an impurity region formed by injecting N-type high-density impurities (n+) into the semiconductor substrate 10. The floating diffusion region FD2 may output a tap signal TAP2 through a conductive line, and the floating diffusion region FD4 may output a tap signal TAP4 through a conductive line. The tap signal TAP2 may refer to a signal corresponding to the amount of charge carriers (e.g., electrons) transferred to the floating diffusion region FD2 through the transfer gate TG2, and the tap signal TAP4 may refer to a signal corresponding to the amount of charge carriers (e.g., electrons) transferred to the floating diffusion region FD4 through the transfer gate TG4.

[0071] The tap signals TAP2 and TAP4 may be applied to the gates of corresponding source follower transistors (not shown) through conductive lines. In addition, the tap signals TAP2 and TAP4 may be applied to the terminals of corresponding reset transistors (not shown) through conductive lines.

[0072] The transfer gate TG2 may be formed between the photoelectric conversion element (PD) and the floating diffusion area FD2 at the second surface of the semiconductor substrate 10, and the transfer gate TG4 may be formed between the photoelectric conversion element (PD) and the floating diffusion area FD4 at the second surface of the semiconductor substrate 10. That is, each of the transfer gates TG2 and TG4 may be used as a gate of a transistor, wherein the photoelectric conversion element (PD) and the floating diffusion areas FD2 and FD4 are used as source / drain areas.

[0073] The insulating layer 20 may be formed on the photoelectric conversion element (PD) at the second surface of the semiconductor substrate 10 .

[0074] Figure 4A Shown in Figure 2 Figure 2 shows how electrons in a unit pixel move through a recycling gate.

[0075] Reference Figure 4A, when the cyclic control signals Vcir1-Vcir4 are respectively applied to the cyclic gates CG1-CG4, an electric field can be formed in the peripheral region of the cyclic gates CG1-CG4, so that the electrons generated by the photoelectric conversion element (PD) can be gathered near the cyclic gates CG1-CG4 at the edge region of the photoelectric conversion element (PD). In this case, when the voltage level of each of the cyclic control signals Vcir1-Vcir4 is less than a threshold level (the threshold level can generate a channel capable of electrically coupling the photoelectric conversion element (PD) to each of the drain nodes D1-D4), the electrons can accumulate near the cyclic gates CG1-CG4 without moving to the drain nodes D1-D4.

[0076] However, from Figure 2 It can be seen that the cyclic gates CG1-CG4 are arranged to surround the upper part of the photoelectric conversion element (PD). The cyclic control signals Vcir1-Vcir4 are not applied simultaneously, but are applied to the cyclic gates CG1-CG4 in a clockwise or counterclockwise continuous order, so that the electrons can move along the edge region of the photoelectric conversion element (PD) according to the desired operation sequence of the cyclic gates CG1-CG4. In this way, the electrons can move in a predetermined direction in the edge region of the photoelectric conversion element (PD).

[0077] In some implementations, at a first time point, a recycling control signal (Vcir1) is applied to the recycling gate CG1, and electrons generated by the photoelectric conversion element (PD) can be accumulated near the recycling gate CG1 by an electric field formed in a peripheral region of the recycling gate CG1.

[0078] After a predetermined period of time, at a second time point, the circulation control signal (Vcir2) is applied to the circulation gate CG2 adjacent to the circulation gate CG1, and the application of the circulation control signal (Vcir1) to the circulation gate CG1 is stopped. Therefore, the electrons accumulated near the circulation gate CG1 can move toward the circulation gate CG2.

[0079] After a predetermined period of time, at a third time point, a circulation control signal (Vcir3) is applied to the circulation gate CG3 adjacent to the circulation gate CG2, and the circulation control signal (Vcir2) is stopped from being applied to the circulation gate CG2. Therefore, the electrons accumulated near the circulation gate CG2 can move toward the circulation gate CG3.

[0080] After a predetermined period of time, at a fourth time point, a circulation control signal (Vcir4) is applied to the circulation gate CG4 adjacent to the circulation gate CG3, and the circulation control signal (Vcir3) is stopped from being applied to the circulation gate CG3. Therefore, the electrons accumulated near the circulation gate CG3 can move toward the circulation gate CG4.

[0081] After a predetermined period of time, at a fifth time point, the circulation control signal (Vcir1) is applied to the circulation gate CG1 adjacent to the circulation gate CG4, and the circulation control signal (Vcir4) is stopped from being applied to the circulation gate CG4. Therefore, the electrons accumulated near the circulation gate CG4 can move toward the circulation gate CG1.

[0082] If the above-described operation is continuously and repeatedly performed, electrons can circulate along the edge region of the photoelectric conversion element (PD).

[0083] Figure 4B Show Figure 2 The unit pixel shown here transfers electrons to the floating diffusion region through the transfer gate.

[0084] In some implementations, when transfer control signals TFv1-TFv4 are applied to transfer gates TG1-TG4, electrical channels are generated in the semiconductor substrate 10 below the transfer gates TG1-TG4, thereby coupling the photoelectric conversion element (PD) to the floating diffusion regions FD1-FD4. Electrons generated by the photoelectric conversion element (PD) can be transferred to the floating diffusion regions FD1-FD4 through the channels.

[0085] The transfer control signals TFv1-TFv4 are not applied simultaneously, but are applied to the transfer gates TG1-TG4 in a clockwise or counterclockwise sequential order. Figure 4A The desired operating sequence of the cyclic gates CG1-CG4 is shown, with transfer control signals TFv1-TFv4 applied sequentially to transfer gates TG1-TG4.

[0086] For example, in the case where electrons accumulated near the recycling gate CG1 move toward the recycling gate CG2, the transfer control signal (TFv1) can be applied only to the transfer gate TG1 located between the recycling gates CG1 and CG2. In this case, the transfer control signal (TFv1) can have a higher voltage level than each of the recycling control signals Vcir1 and Vcir2.

[0087] As described above, in the arrangement structure in which the transfer gate TG1 and the recycling gates CG1 and CG2 are arranged in an L-shaped structure, when the transfer gate TG1 is located at the vertex position and the signal (TFv1) applied to the transfer gate TG1 is at a higher voltage level than each of the signals Vcir1 and Vcir2 applied to the recycling gates CG1 and CG2, most of the electrons collected by the recycling gates CG1 and CG2 and the transfer gate TG1 can be intensively collected in an area located close to the transfer gate TG1. That is, most of the collected electrons can be concentrated in a narrow area. Therefore, even when a transfer gate TG1 having a relatively small size is used, electrons can be quickly transferred to the floating diffusion area FD1.

[0088] In the same manner as described above, in the case where electrons accumulated near the recycling gate CG2 move toward the recycling gate CG3, the transfer control signal (TFv2) can be applied only to the transfer gate TG2 located between the recycling gates CG2 and CG3. In addition, if electrons accumulated near the recycling gate CG3 move toward the recycling gate CG4, the transfer control signal (TFv3) can be applied only to the transfer gate TG3 located between the recycling gates CG3 and CG4. Similarly, if electrons accumulated near the recycling gate CG4 move toward the recycling gate CG1, the transfer control signal (TFv4) can be applied only to the transfer gate TG4 located between the recycling gates CG4 and CG1.

[0089] Figure 5 It is shown Figure 2 A timing diagram of the operation of a unit pixel is shown. 6A to 6H is shown configured to Figure 5 The schematic diagram of the operation of the unit pixel of the step operation shown in FIG. Figure 5 As can be seen from the time points t1-t7 shown, the time intervals between adjacent time points can be the same. 6A to 6H , the outermost lines are lines schematically showing how electrons are concentrated and moved by operation of a recycling gate or a transfer gate.

[0090] Reference Figure 5 and Fig. 6A , if the enable signal (V EN ) is activated to a high level, a modulation period for moving and transferring electrons can be started. The period at the end of the modulation period can be used as a readout period for reading out the tap signals TAP1-TAP4 corresponding to the amount of charge carriers (e.g., electrons) that have been transferred to the floating diffusion areas FD1-FD4 during the modulation period.

[0091] In the modulation period, the drain voltage (Vd) applied to the drain nodes D1-D4 may be at a low voltage (e.g., ground voltage) level. During the readout period, the drain voltage (Vd) applied to the drain nodes D1-D4 may be at a high voltage (e.g., power supply voltage) level. For example, if the drain voltage (Vd) is at a high voltage level even in the modulation period, the drain voltage (Vd) may prevent electrons collected by the recycling gate from moving to the transfer gate, and thus the drain voltage (Vd) may be at a low voltage level in the modulation period.

[0092] In the modulation period, the discharge control signal (Vdrain) for fixing the photoelectric conversion element (PD) to the drain voltage (Vd) may also be at a low voltage (VL) level. In the readout period, the discharge control signal (Vdrain) may be at a high voltage (VH) level.

[0093] After a predetermined time has passed from the start of the modulation period, the circulation control signal (Vcir1) may be activated at a time point (t2). In other words, the circulation control signal (Vcir1) may be applied to the circulation gate CG1 at a time point (t2). In this case, the circulation control signal (Vcir1) may have a voltage (V M ). The cycle control signal (Vcir1) may be activated within a predetermined time t2-t4.

[0094] Since the circulation control signal (Vcir1) is applied to the circulation gate CG1, an electric field may be formed in a region adjacent to the circulation gate CG1 at an edge region of the photoelectric conversion element (PD). As a result, electrons generated by photoelectric conversion of reflected light in the photoelectric conversion element (PD) may move toward the circulation gate CG1 through the electric field, so that the electrons are collected in a region near the circulation gate CG1.

[0095] Reference Figure 5 and Figure 6B , after a predetermined time from the end of the time point (t2), the transfer control signal (TFv1) and the circulation control signal (Vcir2) may be activated at the time point (t3). For example, if the circulation control signal (Vcir2) is applied to the circulation gate CG2 and the transfer control signal (TFv1) is applied to the transfer gate TG1 while the circulation control signal (Vcir1) is still activated, the circulation gates CG1 and CG2 and the transfer gate TG1 can be operated simultaneously. In this case, the transfer control signal (TFv1) may have a higher voltage (V H ), expressed as “V M <V H”. The transfer control signal (TFv1) may be activated during a predetermined time period t3-t4, and the cycle control signal (Vcir2) may be activated during a predetermined time period t3-t5.

[0096] Therefore, electrons collected near the recycling gate CG1 during the period t2-t3 can move toward the transfer gate TG1. In addition, electrons additionally collected by the transfer gate TG1 and the recycling gates CG1 and CG2 during the period t3-t4 can also move toward the transfer gate TG1.

[0097] That is, although the recycling gates CG1 and CG2 and the transfer gate TG1 are arranged in an L-shaped structure, the transfer gate TG1 is arranged at the vertex position and a relatively high voltage is applied to the transfer gate TG1, so that electrons can be concentratedly collected in the area close to the transfer gate TG1 (i.e., the vertex area).

[0098] The collected electrons can be transferred to the floating diffusion area FD1 through the transfer gate TG1. That is, the electrons are concentratedly collected in a narrow vertex area so that the electrons can be quickly transferred to the floating diffusion area FD1 using the small-sized transfer gate TG1.

[0099] Reference Figure 5 , Figure 6C and Fig.6D , the circulation control signal (Vcir1) and the transfer control signal (TFv1) may be deactivated at the time point (t4), and the transfer control signal (TFv2) and the circulation control signal (Vcir3) may be activated at the time point (t4). That is, the transfer gate TG1 and the circulation gate CG1 located on one side of the circulation gate CG2 may stop operating, and the transfer gate TG2 and the circulation gate CG3 located on the other side of the circulation gate CG2 may start operating. In this case, the transfer control signal (TFv2) may have a higher voltage (VH) than the circulation control signal (Vcir3).

[0100] However, although the transfer control signal (TFv2) and the circulation control signal (Vcir3) are activated, a predetermined time (i.e., a rising time) may be consumed before the voltage levels of the control signals TFv2 and Vcir3 reach a predetermined level at which the gates TG2 and CG3 can actually operate. That is, a period of time in which the transfer gate TG1 stops operating and the transfer gate TG2 has not yet operated may occur.

[0101] Therefore, the circulation control signal (Vcir2) continues to be activated until the time point (t5) is reached. As a result, during the predetermined time when the transfer gate TG2 has not been operated, the electrons may not be dispersed and move toward the circulation gate CG2. For example, Figure 6CAs shown, not only are electrons not transferred by the transfer gate TG1, but also the newly generated electrons can move toward the recycling gate CG2.

[0102] like Fig.6D As shown, if the rising time of each of the control signals TFv2 and Vcir3 has been terminated, the transfer gate TG2 and the recycle gate CG3 can be operated by the transfer control signal (TFv2) and the recycle control signal (Vcir3). That is, the recycle gates CG2 and CG3 and the transfer gate TG2 can be operated at the same time. In this case, since the voltage (V H ) is higher than the voltage (V M ), so the electrons can move toward the transfer gate TG2 and can flow into the floating diffusion area FD2 through the transfer gate TG2.

[0103] Reference Figure 5 , Fig. 6E and Fig. 6F , the circulation control signal (Vcir2) and the transfer control signal (TFv2) may be deactivated at the time point (t5), and the transfer control signal (TFv3) and the circulation control signal (Vcir4) may be activated at the time point (t5). That is, the transfer gate TG2 and the circulation gate CG2 located on one side of the circulation gate CG3 may stop operating, and the transfer gate TG3 and the circulation gate CG4 located on the other side of the circulation gate CG3 may start operating. In this case, the transfer control signal (TFv3) may have a higher voltage (V H ).

[0104] In this case, the cyclic control signal (Vcir3) continues to be activated until the time point (t6) is reached. Fig. 6E As shown, during a predetermined time when the transfer gate TG3 has not been operated, the electrons may not be dispersed and move toward the recycling gate CG3.

[0105] If the rising time of each of the control signals TFv3 and Vcir4 has been terminated, the transfer gate TG3 and the recycling gate CG4 may be operated by the control signals TFv3 and Vcir4, as shown in FIG. Fig. 6F That is, the cyclic gates CG3 and CG4 and the transfer gate TG3 can be operated simultaneously. In this case, due to the voltage (V H ) is higher than the voltage (V M), so the electrons can move toward the transfer gate TG3 and can flow into the floating diffusion area FD3 through the transfer gate TG3.

[0106] Reference Figure 5 , Figure 6G and Figure 6H , the circulation control signal (Vcir3) and the transfer control signal (TFv3) may be deactivated at the time point (t6), and the transfer control signal (TFv4) and the circulation control signal (Vcir1) may be activated at the time point (t6). In this case, the transfer control signal (TFv4) may have a higher voltage (V H ), and the cycle control signal (Vcir4) can remain activated until the time point (t7) is reached.

[0107] Therefore, if Figure 6G As shown, the electrons can move to the recycling gate CG4. Thereafter, if the rising time of each of the control signals TFv4 and Vcir1 has expired, as shown in FIG. Figure 6H As shown, electrons may flow into the floating diffusion region FD4 through the transfer gate TG4.

[0108] Until the modulation period after the time point (t7) is completed, the electron movement in the time period t3-t7 and the sequential transfer of these electrons flowing into the floating diffusion areas FD1-FD4 can be repeated. That is, during the modulation period, the circulation control signal applied to the circulation gate CG1-CG4 of each unit pixel (PX) and the transfer control signal applied to the transfer gate TG1-TG4 of each unit pixel (PX) can be repeatedly circulated and changed in the counterclockwise direction. If the modulation period has been terminated, the deactivation enable signal (V EN ), so that the readout period can be started. In this case, the drain voltage (Vd) can be at a high voltage level, and the drain control signal (Vdrain) can be activated to a high voltage (VH) level. Based on the switching operation of the switching elements S1-S4, the drain control signal (Vdrain) can be applied to the recycling gates CG1-CG4.

[0109] Therefore, the photoelectric conversion element (PD) can be electrically coupled to the drain nodes D1-D4 through the cyclic gates CG1-CG4, so that the voltage level of the photoelectric conversion element (PD) can be fixed at the drain voltage (Vd) during the readout period.

[0110] As apparent from the above description, an image sensing device based on some implementations of the disclosed technology can improve its operating characteristics.

[0111] Although a number of exemplary embodiments have been described, it should be understood that numerous other modifications and embodiments could be devised based on what is described and / or illustrated in this patent document.

[0112] CROSS-REFERENCE TO RELATED APPLICATIONS

[0113] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0037366, filed on March 27, 2020, the entire contents of which are incorporated by reference as a part of the disclosure of this patent document.

Claims

1. An image sensing device, comprising: a pixel array comprising a plurality of unit pixels arranged in rows and columns, Wherein, each of the plurality of unit pixels comprises: a photoelectric conversion element that generates charge carriers by converting light incident on the photoelectric conversion element; a plurality of floating diffusion regions, the plurality of floating diffusion regions being spaced apart from the photoelectric conversion element to retain the charge carriers; a plurality of cyclic gates, the plurality of cyclic gates being located at both sides of the photoelectric conversion element along each of a first direction and a second direction perpendicular to the first direction, configured to generate an electric field in different regions of the photoelectric conversion element based on a cyclic control signal, and configured to cause the charge carriers to move along a predetermined direction; and A plurality of transfer gates are respectively located between the plurality of recycling gates and are configured to transfer the charge carriers generated by the photoelectric conversion element to corresponding floating diffusion regions.

2. The image sensing device according to claim 1, wherein: The plurality of cyclic gates include: a first cyclic gate, the first cyclic gate being located at both sides of the photoelectric conversion element along the first direction and being formed into a rectangular shape in which a length of the first cyclic gate along the second direction is longer than a length of the first cyclic gate along the first direction; and A second recurring gate is located at both sides of the photoelectric conversion element along the second direction and is formed in a rectangular shape in which a length of the second recurring gate along the first direction is longer than a length of the second recurring gate along the second direction.

3. The image sensing device according to claim 2, wherein: The plurality of transfer gates are respectively located between the first recycling gate and the second recycling gate.

4. The image sensing device according to claim 1, wherein: The plurality of transfer gates and the plurality of recycling gates are positioned to at least partially overlap the photoelectric conversion element.

5. The image sensing device according to claim 4, wherein: The longest axis of a region where each of the plurality of recycle gates overlaps the photoelectric conversion element is longer than the longest axis of a region where each of the plurality of transfer gates overlaps the photoelectric conversion element.

6. The image sensing device according to claim 1, wherein: The plurality of recycle gates are configured to fix a voltage level of the photoelectric conversion element at a predetermined drain voltage based on a drain control signal.

7. The image sensing device according to claim 6, further comprising: A plurality of switch elements are configured to selectively provide one of the circulation control signal and the drain control signal to the plurality of circulation gates.

8. The image sensing device according to claim 6, further comprising: A plurality of drain nodes are each located on one side of a corresponding one of the plurality of recycling gates in a direction opposite to the photoelectric conversion element and configured to receive the drain voltage.

9. The image sensing device according to claim 8, wherein: The plurality of drain nodes are spaced apart from the photoelectric conversion element by a predetermined distance and include an impurity region formed by implanting first type impurities.

10. The image sensing device according to claim 1, wherein: The plurality of recurring gates are respectively located in regions corresponding to four sides of a rectangular shape formed to surround the photoelectric conversion element, and The plurality of transfer gates are respectively located in regions corresponding to four vertices of the rectangular shape.

11. The image sensing device according to claim 1, wherein: The plurality of cyclic gates are configured to sequentially receive the cyclic control signal along a predetermined direction.

12. The image sensing device according to claim 11, wherein: The transfer gates are configured and coupled to sequentially receive transfer control signals along the predetermined direction.

13. The image sensing device according to claim 12, wherein: Each of the plurality of transfer gates is configured and coupled to receive the transfer control signal when the recycling gates located at both sides of the transfer gate among the plurality of recycling gates receive the recycling control signal.

14. An image sensing device, comprising: a pixel array including a plurality of unit pixels for performing photoelectric conversion on incident light and outputting an electrical signal corresponding to the incident light, Wherein, each of the plurality of unit pixels comprises: a photoelectric conversion element that generates charge carriers by converting the incident light; a plurality of recurring gates, the plurality of recurring gates being located on both sides of the photoelectric conversion element along each of a first direction and a second direction perpendicular to the first direction and configured to cause the charge carriers to move along a predetermined direction; a plurality of transfer gates, the plurality of transfer gates being respectively located between the plurality of recycle gates and arranged alternately with the plurality of recycle gates; and A plurality of floating diffusion regions are respectively located on one side of a corresponding one of the plurality of transfer gates in a direction opposite to the photoelectric conversion element based on the corresponding one of the plurality of transfer gates.

15. The image sensing device according to claim 14, further comprising: A plurality of drain nodes are respectively located on one side of a corresponding one of the plurality of recycling gates along a direction opposite to the photoelectric conversion element based on a corresponding one of the plurality of recycling gates, and the plurality of drain nodes are connected to an input terminal of a drain voltage.

16. The image sensing device according to claim 14, further comprising: A plurality of switch elements are configured to selectively provide one of a circulation control signal and a drain control signal to the plurality of circulation gates.

17. The image sensing device according to claim 14, wherein: The plurality of recycling gates and the plurality of transfer gates are disposed to at least partially overlap the photoelectric conversion element.

18. The image sensing device according to claim 17, wherein: The longest axis of a region where the recycle gate overlaps the photoelectric conversion element is longer than the longest axis of a region where the transfer gate overlaps the photoelectric conversion element.

19. The image sensing device according to claim 14, wherein: The plurality of cyclic gates include: a first cyclic gate, the first cyclic gate being located at both sides of the photoelectric conversion element along the first direction and being formed such that a length of the first cyclic gate along the second direction is longer than a length of the first cyclic gate along the first direction; and A second recurring gate is located at both sides of the photoelectric conversion element along the second direction and is formed such that a length of the second recurring gate along the first direction is longer than a length of the second recurring gate along the second direction.

20. The image sensing device according to claim 14, wherein: The plurality of recycle gates and the plurality of transfer gates are spaced apart from each other by a predetermined distance and are arranged in a ring shape surrounding the photoelectric conversion element.

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