SiC MOSFET device with shallow P + structure and preparation process thereof

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device with a shallow P + structure, which comprises a drain electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a side P + layer, an N well layer and a P well layer, a groove is etched in the surface of the semiconductor epitaxial layer, the source electrode is embedded in the semiconductor epitaxial layer through the groove, and the P well layer is embedded in the side P + layer. The section height of the source electrode is the same as that of the semiconductor epitaxial layer; a lower covering P + layer is arranged in the N drift layer and located below the P well layer, and the lower covering P + layer is in contact with the side P + layer. Charge carriers can be guided to flow along a more effective path through the low-doped N layer, the current crowding effect is reduced, the structure is beneficial to enhancing the conductivity modulation effect, low on-resistance can be maintained under the high-voltage condition, and the low-doped N layer can help to homogenize electric field distribution especially in high-voltage application.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a SiC MOSFET device with a shallow P+ structure and a preparation process thereof. Background Art

[0002] In SiC MOSFET, shallow P+ structure usually refers to forming a shallowly doped P+ layer under or near the gate through ion implantation or diffusion process. This P+ layer is not in contact with the P well layer, but is located inside the N drift layer, close to the gate. Its main purpose is to optimize the electric field distribution, increase the breakdown voltage, reduce the on-resistance and improve other key performance indicators.

[0003] The existing patent discloses a SiC MOSFET structure with a shallow P+ structure (publication number CN115799303A). Based on the conventional planar SiC MOSFET structure, this structure diffuses a high-concentration P-type doping layer directly below the N+ source region. In the technology disclosed in this patent, local overheating will occur under high-voltage environment, which increases the probability of uneven electric field distribution. At this time, when the device is under transient overvoltage, it is very easy to break down due to avalanche. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a SiC MOSFET device with a shallow P+ structure and a preparation process thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a SiC MOSFET device with a shallow P+ structure includes a drain, a gate, a gate oxide layer and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, a side P+ layer, an N well layer and a P well layer, a surface of the semiconductor epitaxial layer is etched with a groove, wherein a source electrode is embedded in the semiconductor epitaxial layer through the groove, and a cross-sectional height of the source electrode is the same as a cross-sectional height of the semiconductor epitaxial layer; A lower covering P+ layer is further provided inside the N drift layer and below the P well layer, and the lower covering P+ layer is in contact with the side P+ layer.

[0006] Furthermore, two symmetrical low-doped N layers are formed on the inner bottom side of the N drift layer by ion implantation, and an opening for charge flow is formed between the two low-doped N layers.

[0007] Furthermore, a plurality of doping media are doped inside the N-drift layer and between the drain and the gate, wherein the distances between any two of the doping media are equal, and the doping media inside the N-drift layer are distributed in an inverted triangle shape.

[0008] Furthermore, a central P+ layer that is not in contact with the P well layer is formed inside the N drift layer and below the gate by ion implantation.

[0009] Furthermore, the cross-sectional width of the central P+ layer is not less than the width of the opening formed between the two low-doped N layers.

[0010] A preparation process of a SiC MOSFET device with a shallow P+ structure, comprising: S1. Select a semiconductor epitaxial layer that has passed the quality inspection, and form a low-doped N layer and a central P+ layer by ion implantation; S2. The doping medium is doped layer by layer inside the N drift layer to make the doping medium distributed in an inverted triangle shape; S3. Perform a short-circuit performance test on the formed SiC MOSFET device, and determine whether the performance of the SiC MOSFET device meets the standard based on the short-circuit test data.

[0011] Furthermore, in step S3, whether the performance of the SiC MOSFET device meets the standard is determined according to the stable value of the drain-source current, the applied drain-source voltage and the threshold voltage after the SiC MOSFET device is short-circuited, then: In the formula, Indicates the condition coefficient for the tested SiC MOSFET device to meet the performance standard, Represents the stable value of the drain-source current of the SiC MOSFET device after short circuit, Indicates the magnitude of the applied drain-source short-circuit voltage, Indicates the threshold voltage of the device.

[0012] Furthermore, when When , it means that the performance of the SiC MOSFET device tested meets the standard; when , it means that the performance of the SiC MOSFET device under test does not meet the standard.

[0013] The present invention provides a SiC MOSFET device with a shallow P+ structure and a preparation process thereof. Compared with the prior art, the method has the following effects: 1. The present invention can guide charge carriers to flow along a more efficient path through a low-doped N layer, thereby reducing the current crowding effect. This structure helps to enhance the conductivity modulation effect, thereby maintaining a lower on-resistance even under high voltage conditions. The low-doped N layer can help to uniformize the electric field distribution, especially in high-voltage applications.

[0014] 2. The present invention can solve the problem of difficulty in forming a charge channel by providing a lower covering P+ layer, while retaining the advantage of the shallow P well layer with fast response time.

[0015] 3. The present invention can effectively disperse the electric field by distributing the doping medium in an inverted triangle shape, avoiding early breakdown caused by excessive local electric field, and by reasonably arranging the doping medium, a more uniform electric field distribution can be achieved in the entire N drift layer. This distribution method can guide the current to flow along a more effective path.

[0016] 4. The present invention can form a local high-doping area under the gate through the central P+ layer, which helps to shield the electric field under the gate to prevent electric field concentration, and can also effectively reduce the electric field strength at the edge of the gate to avoid early breakdown. The design of the P+ layer helps to distribute heat more evenly inside the device, avoiding local overheating, thereby improving the overall thermal stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of Example 1 of the present invention; Figure 2 It is a schematic diagram of Example 2 of the present invention; Figure 3 It is a schematic diagram of Example 3 of the present invention; Figure 4 It is a schematic diagram of Example 4 of the present invention; Figure 5 This is a schematic diagram of the structure in Embodiment 3 of the present invention after the gate voltage is connected; Figure 6 The graph shows the change of drain-source current over time in four different sets of structures of the embodiments of the present invention under short-circuit test conditions.

[0018] In the figure: 1. drain; 2. gate; 3. gate oxide layer; 4. source; 5. N substrate layer; 6. N drift layer; 7. side P+ layer; 8. N well layer; 9. P well layer; 10. lower covering P+ layer; 11. low-doped N layer; 12. doped medium; 13. center P+ layer. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] like Figure 1-6 As shown, a preparation process of a SiC MOSFET device with a shallow P+ structure includes: 1) Select a semiconductor epitaxial layer that has passed the quality inspection, and form a low-doped N layer 11 and a central P+ layer 13 by ion implantation; 2) The doping medium 12 is doped layer by layer inside the N drift layer 6 so that the doping medium 12 is distributed in an inverted triangle shape; 3) Perform short-circuit performance test on the formed SiC MOSFET device, and judge whether the performance of the SiC MOSFET device meets the standard based on the short-circuit test data. According to the stable value of the drain-source current after the SiC MOSFET device is short-circuited, the applied drain-source voltage and the threshold voltage, the performance of the SiC MOSFET device meets the standard. Then: In the formula, Indicates the condition coefficient for the tested SiC MOSFET device to meet the performance standard, Represents the stable value of the drain-source current of the SiC MOSFET device after short circuit, Indicates the magnitude of the applied drain-source short-circuit voltage, Indicates the threshold voltage of the device.

[0021] when When , it means that the performance of the SiC MOSFET device tested meets the standard; when , it means that the performance of the SiC MOSFET device under test does not meet the standard.

[0022] The performance of the SiC MOSFET structure in Example 1 is tested. The stable value of the drain-source current of the SiC MOSFET device after short circuit is taken as (A), the applied drain-source short-circuit voltage is (V), the threshold voltage of the device is (V), then we have: From the above calculation, it can be known that the device in Example 1 tested meets the performance. And compare multiple groups of example data (such as Figure 6 In the figure, the red line segment is the detection parameter of Example 1, the green line segment is the detection parameter of Example 2, the blue line segment is the detection parameter of Example 3, and the black line segment is the detection parameter of Example 4), there are: Table 1 Parameters and performance status of structure detection in four groups of embodiments It can be seen from the data in Table 1 that the four embodiment samples disclosed in the present invention all meet the actual use requirements.

[0023] Example 1 like Figure 1As shown, according to one aspect of the present invention, a SiC MOSFET device with a shallow P+ structure is provided, comprising a drain 1, a gate 2, a gate oxide layer 3 and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer 5, an N drift layer 6, a side P+ layer 7, an N well layer 8 and a P well layer 9, characterized in that: a groove is etched on the surface of the semiconductor epitaxial layer, wherein the source 4 is embedded in the semiconductor epitaxial layer through the groove, and the cross-sectional height of the source 4 is the same as the cross-sectional height of the semiconductor epitaxial layer; a lower covering P+ layer 10 is also provided inside the N drift layer 6 and below the P well layer 9, and the lower covering P+ layer 10 is in contact with the side P+ layer 7. If there is no lower covering P+ layer 10, and since the resistance of the P well layer 9 is often particularly large, and the P well layer 9 is particularly shallow, the resistivity of the P well layer 9 will be further increased, and when the charge of the source 4 is introduced into the P well layer 9 only through the side P+ layer 7, it is often necessary to apply a multiple of the gate voltage to form a charge channel on the P well layer 9, and the reaction of the formed charge channel will also be delayed. However, after adding the lower covering P+ layer 10, the problem of difficulty in forming a charge channel will be solved, while the advantage of the shallow P well layer 9 with fast response time will be retained.

[0024] Example 2 like Figure 2 As shown, two symmetrical low-doped N layers 11 are formed on the inner bottom side of the N drift layer 6 by ion implantation, and an opening for charge flow is formed between the two low-doped N layers 11. The design of the low-doped N layer 11 can guide the charge carriers to flow along a more effective path, reduce the current crowding effect, and thus reduce the on-resistance. This structure helps to enhance the conductivity modulation effect, so that a low on-resistance can be maintained even under high voltage conditions. The low-doped N layer 11 can help to uniformize the electric field distribution, especially in high-voltage applications; and can also effectively prevent the early breakdown caused by excessive local electric field. The presence of the low-doped area increases the width of the depletion region and increases the breakdown voltage of the device. By optimizing the current path, the electromigration phenomenon in the metal interconnect layer can be reduced and the service life of the device can be extended.

[0025] Example 3 like Figure 3 , 5As shown, a plurality of doping media 12 are doped inside the N drift layer 6 and between the drain 1 and the gate 2, wherein the spacing between the doping media 12 is equal, and the doping media 12 inside the N drift layer 6 is distributed in an inverted triangle shape. The inverted triangle distribution can effectively disperse the electric field and avoid early breakdown caused by excessive local electric field. By rationally arranging the doping media, a more uniform electric field distribution can be achieved in the entire N drift layer. This distribution method can guide the current to flow along a more effective path; the inverted triangle distribution helps to distribute the heat more evenly inside the device, avoiding local overheating, and can even out the electric field distribution and increase the breakdown voltage so that the device has better tolerance under transient overvoltage conditions, and enhances the ability to resist avalanche breakdown.

[0026] Example 4 like Figure 4 As shown, a central P+ layer 13 that is not in contact with the P well layer 9 is formed inside the N drift layer 6 and below the gate 2 by ion implantation. The cross-sectional width of the central P+ layer 13 is not less than the width of the opening formed between the two low-doped N layers 11. The central P+ layer 13 can form a local high-doping area below the gate, which helps to shield the electric field below the gate and prevent electric field concentration. This can effectively reduce the electric field strength at the edge of the gate and avoid early breakdown. The design of the P+ layer 13 helps to distribute heat more evenly inside the device, avoiding local overheating, thereby improving the overall thermal stability.

[0027] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SiC MOSFET device with a shallow P+ structure, comprising a drain (1), a gate (2), a gate oxide layer (3) and a semiconductor epitaxial layer, wherein the semiconductor epitaxial layer comprises an N substrate layer (5), an N drift layer (6), a side P+ layer (7), an N well layer (8) and a P well layer (9), characterized in that: A groove is etched on the surface of the semiconductor epitaxial layer, wherein the source electrode (4) is embedded in the semiconductor epitaxial layer through the groove, and the cross-sectional height of the source electrode (4) is the same as the cross-sectional height of the semiconductor epitaxial layer; A lower covering P+ layer (10) is also provided inside the N drift layer (6) and below the P well layer (9), and the lower covering P+ layer (10) is in contact with the side P+ layer (7).

2. The SiC MOSFET device with a shallow P+ structure according to claim 1, characterized in that: Two mutually symmetrical low-doped N layers (11) are formed on the inner bottom side of the N drift layer (6) by ion implantation, and an opening for charge flow is formed between the two low-doped N layers (11).

3. The SiC MOSFET device with a shallow P+ structure according to claim 2, characterized in that: A plurality of doping media (12) are doped inside the N drift layer (6) and between the drain (1) and the gate (2), wherein the spacing between two of the doping media (12) is equal, and the doping media (12) inside the N drift layer (6) are distributed in an inverted triangle shape.

4. The SiC MOSFET device with a shallow P+ structure according to claim 3, characterized in that: A central P+ layer (13) that is not in contact with the P well layer (9) is formed inside the N drift layer (6) and below the gate (2) by ion implantation.

5. The SiC MOSFET device with a shallow P+ structure according to claim 4, characterized in that: The cross-sectional width of the central P+ layer (13) is not less than the width of the opening formed between the two low-doped N layers (11).

6. A process for preparing a SiC MOSFET device having a shallow P+ structure, characterized in that: Applicable to the SiC MOSFET device according to any one of claims 1 to 5, the preparation process of the SiC MOSFET device with a shallow P+ structure comprises: S1, selecting a semiconductor epitaxial layer that has passed quality inspection, and forming a low-doped N layer (11) and a central P+ layer (13) by ion implantation; S2, doping the doping medium (12) layer by layer inside the N drift layer (6) so that the doping medium (12) is distributed in an inverted triangle shape; S3. Perform a short-circuit performance test on the formed SiC MOSFET device, and determine whether the performance of the SiC MOSFET device meets the standard based on the short-circuit test data.

7. The process for preparing a SiC MOSFET device with a shallow P+ structure according to claim 6, characterized in that: In step S3, whether the performance of the SiC MOSFET device meets the standard is determined according to the stable value of the drain-source current, the applied drain-source voltage and the threshold voltage after the SiC MOSFET device is short-circuited: In the formula, Indicates the condition coefficient for the tested SiC MOSFET device to meet the performance standard, Represents the stable value of the drain-source current of the SiC MOSFET device after short circuit, Indicates the magnitude of the applied drain-source short-circuit voltage, Indicates the threshold voltage of the device.

8. The process for preparing a SiC MOSFET device with a shallow P+ structure according to claim 7, characterized in that: when When , it means that the performance of the SiC MOSFET device tested meets the standard; when , it means that the performance of the SiC MOSFET device under test does not meet the standard.

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