High electron mobility transistor and method of making the same

Abstract

A high electron mobility transistor includes a III-V channel layer, a passivation layer, a III-V barrier layer, a gate structure, and at least one source / drain electrode, wherein the passivation layer is disposed on the III-V channel layer and includes a gate contact hole and a source / drain contact hole, the III-V barrier layer is disposed between the III-V channel layer and the passivation layer. The gate structure includes a III-V gate layer, a gate etch stop layer, and a gate electrode stacked in sequence, wherein the gate electrode is disposed in the gate contact hole and conformally covers a portion of a top surface of the passivation layer. The at least one source / drain electrode is disposed in the at least one source / drain contact hole and conformally covers another portion of the top surface of the passivation layer.

Description

Technical Field

[0001] This invention relates to the field of transistors, and more particularly to a high electron mobility transistor and a method for manufacturing the same. Background Technology

[0002] In semiconductor technology, III-V group semiconductor compounds can be used to form various integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). HEMTs are transistors with a two-dimensional electron gas (2DEG), which is located near the junction between two materials with different band gaps (i.e., a heterojunction). Because HEMTs do not use doped regions as carrier channels but rather use 2DEGs, they possess several attractive characteristics compared to existing metal-oxide-semiconductor field-effect transistors (MOSFETs), such as high electron mobility and the ability to transmit signals at high frequencies.

[0003] However, in the existing HEMT manufacturing process, multiple photolithography, etching, and metal deposition processes are required to define the gate contact hole, source / drain contact hole, gate electrode, and source / drain electrode of the HEMT, which undoubtedly increases the complexity of the process and the manufacturing cost. Summary of the Invention

[0004] In view of this, it is necessary to propose an improved high electron mobility transistor to overcome the shortcomings of existing high electron mobility transistors.

[0005] According to one embodiment of the present invention, a high electron mobility transistor is provided, comprising a III-V channel layer, a passivation layer, a III-V barrier layer, a gate structure, and source / drain electrodes. The passivation layer is disposed on the III-V channel layer and includes a gate contact hole and a source / drain contact hole. The III-V barrier layer is disposed between the III-V channel layer and the passivation layer. The gate structure includes a III-V gate layer, a gate etch stop layer, and a gate electrode stacked sequentially. The gate electrode is disposed in the gate contact hole and oriented to cover a portion of the top surface of the passivation layer. The source / drain electrodes are disposed in at least one source / drain contact hole and oriented to cover another portion of the top surface of the passivation layer.

[0006] According to another embodiment of the present invention, a method for fabricating a high electron mobility transistor is provided, comprising: providing a substrate on which a III-V channel layer, a III-V barrier layer, a III-V gate layer and a gate etch stop layer are sequentially disposed; forming a passivation layer covering the III-V barrier layer and the gate etch stop layer; forming a gate contact hole and a source / drain contact hole in the passivation layer, wherein the gate contact hole exposes the gate etch stop layer and the source / drain contact hole exposes the III-V channel layer; and forming a conductive layer disposed oriented on the top surface of the passivation layer, wherein the conductive layer is disposed in the gate contact hole and the source / drain contact hole.

[0007] According to embodiments of the present invention, gate contact holes and source / drain contact holes can be simultaneously formed in the passivation layer by performing the same photolithography and etching process. Furthermore, appropriate etching parameters can be adjusted so that the bottom of the gate contact hole does not penetrate the gate etch stop layer, and the bottom of the source / drain contact hole does not penetrate the III-V channel layer. Subsequently, the gate electrode and source / drain electrode can be simultaneously formed using the same deposition, photolithography, and etching process. Therefore, embodiments of the present invention can simplify process complexity and reduce manufacturing costs. Attached Figure Description

[0008] To facilitate understanding, the accompanying drawings and detailed textual descriptions are provided while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale; therefore, the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0009] Figure 1 This is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present invention.

[0010] Figure 2 This is a cross-sectional schematic diagram of a HEMT having a III-V channel layer, a III-V barrier layer, a III-V semiconductor layer, and an etch stop layer disposed on a substrate, according to an embodiment of the present invention.

[0011] Figure 3 This is a cross-sectional schematic diagram of a HEMT with an active region disposed on a substrate, according to an embodiment of the present invention.

[0012] Figure 4 This is a cross-sectional schematic diagram of a HEMT having a III-V gate layer and a gate etch stop layer on a substrate, as illustrated in an embodiment of the present invention.

[0013] Figure 5This is a cross-sectional schematic diagram of a HEMT in which the III-V gate layer and the gate etch stop layer are covered by a passivation layer, according to an embodiment of the present invention.

[0014] Figure 6 This is a schematic cross-sectional view of a HEMT after forming gate contact holes and source / drain contact holes in a passivation layer, according to an embodiment of the present invention.

[0015] Figure 7 This is a schematic cross-sectional view of a HEMT after full deposition of a conductive layer according to an embodiment of the present invention.

[0016] Figure 8 This is a schematic cross-sectional view of a HEMT after forming a gate electrode and a source / drain electrode in a contact hole, according to an embodiment of the present invention.

[0017] Figure 9 This is a flowchart of a method for manufacturing HEMT according to an embodiment of the present invention.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 10 High Electron Mobility Transistors

[0020] 20 High Electron Mobility Transistors

[0021] 100 base

[0022] 102 Buffer Layer

[0023] 104 III-V group channel layer

[0024] 106 III-V group barrier layer

[0025] 108 III-V semiconductor layer

[0026] 110 Etching Stop Layer

[0027] 112 III-V group gate layer

[0028] 114 Gate Etching Stop Layer

[0029] 120 Two-dimensional electron gas region

[0030] 122 Two-dimensional electron gas cutoff region

[0031] 124 passivation layer

[0032] 126 Gate contact hole

[0033] 128 Source / Drain Contact Cave

[0034] 132 First conductive layer

[0035] 134 Second conductive layer

[0036] 140 Gate electrode

[0037] 142 Source / Drain Electrode

[0038] 150 gate structure

[0039] 160 interlayer dielectric layers

[0040] 200 methods

[0041] 202 steps

[0042] 204 steps

[0043] 206 steps

[0044] 208 steps

[0045] 210 steps

[0046] 212 steps

[0047] 214 steps

[0048] 216 steps

[0049] R1 Platform Area Detailed Implementation

[0050] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature forming on or above a second feature" may mean "the first feature and the second feature are in direct contact," or it may mean "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0051] Furthermore, for the spatially related descriptive terms mentioned in this invention, such as "below," "low," "down," "above," "above," "below," "top," "bottom," and similar terms, for ease of description, their usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

[0052] Although this invention uses terms such as first, second, third, etc., to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves indicate or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing methods. Therefore, without departing from the scope of the specific embodiments of this invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

[0053] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0054] In this invention, "group III-V semiconductor" refers to a compound semiconductor containing at least one group III element and at least one group V element. The group III element can be boron (B), aluminum (Al), gallium (Ga), or indium (In), while the group V element can be nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). Furthermore, "III-V semiconductors" may include, but are not limited to, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), aluminum nitride (AlN), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), aluminum indium arsenide (InAlAs), gallium indium arsenide (InGaAs), and combinations thereof. Additionally, depending on requirements, III-V semiconductors may also include dopants to create III-V semiconductors with a specific conductivity type, such as N-type or P-type III-V semiconductors.

[0055] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted, and these omitted details are within the scope of knowledge of those skilled in the art.

[0056] This invention relates to a high electron mobility transistor (HEMT) that can be used as a power switching transistor in voltage converter applications. Compared to silicon power transistors, III-V HEMTs have a wider band gap, resulting in lower on-state resistance and lower switching losses.

[0057] Figure 1 This is a schematic cross-sectional view of a high electron mobility transistor (HEMT) according to an embodiment of the present invention. Figure 1As shown, a high electron mobility transistor 10, such as an enhancement-mode high electron mobility transistor, is disposed on a substrate 100. A III-V channel layer (or III-V channel layer) 104, a III-V barrier layer (or III-V barrier layer) 106, a III-V gate layer (or III-V gate layer) 112, a gate etch stop layer 114, and a passivation layer 124 are sequentially disposed on the substrate 100. The III-V barrier layer 106 is disposed above the III-V channel layer 104. The passivation layer 124 may contain a gate contact hole 126 and at least one source / drain contact hole (e.g., a separately disposed dual source / drain contact hole 128). The gate electrode 140 may be oriented in the gate contact hole 126 and directly contact the gate etch stop layer 114 exposed from the gate contact hole 126, and the gate electrode 140 may orientedly cover a portion of the top surface of the passivation layer 124. Furthermore, the gate etch stop layer 114, the passivation layer 124, and the gate electrode 140 may constitute a gate structure 150. The source / drain electrodes 142 may be oriented in the source / drain contact hole 128 and directly contact the III-V barrier layer 106 or the III-V channel layer 104 exposed from the source / drain contact hole 128, and the source / drain electrodes 142 may orientedly cover another portion of the top surface of the passivation layer 124.

[0058] According to one embodiment of the present invention, the substrate 100 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, but is not limited thereto. According to one embodiment of the present invention, the III-V channel layer 104 may comprise one or more III-V semiconductor layers, the composition of which may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. Furthermore, the III-V channel layer 104 may also be one or more doped III-V semiconductor layers, such as a p-type III-V semiconductor layer. For the p-type III-V semiconductor layer, the dopant may be C, Fe, Mg, or Zn, or is not limited thereto. The aforementioned III-V barrier layer 106 may comprise one or more III-V semiconductor layers, and its composition may differ from that of the III-V semiconductor in the III-V channel layer 104. For example, the III-V barrier layer 106 may comprise AlN, Al... y Ga (1-y)N (0 < y < 1) or a combination thereof. According to one embodiment, the III-V channel layer 104 may be an undoped GaN layer, while the III-V barrier layer 106 may be an essentially N-type AlGaN layer. Due to the discontinuous bandgap between the III-V channel layer 104 and the III-V barrier layer 106, by stacking the III-V channel layer 104 and the III-V barrier layer 106 together, electrons are concentrated at the heterojunction between the III-V channel layer 104 and the III-V barrier layer 106 due to the piezoelectric effect, thus creating a thin layer with high electron mobility, i.e., a two-dimensional electron gas (2DEG) region 120. In contrast, the region covered by the III-V gate layer 112, since no two-dimensional electron gas is formed, can be considered as a two-dimensional electron gas cutoff region 122.

[0059] Furthermore, the III-V gate layer 112 disposed above the III-V barrier layer 106 may comprise one or more III-V semiconductor layers, and the composition of the III-V semiconductor layer may be GaN, AlGaN, InGaN, or InAlGaN, but is not limited thereto. Additionally, the III-V gate layer 112 may also be one or more doped III-V semiconductor layers, such as a P-type III-V semiconductor layer. For the P-type III-V semiconductor layer, the dopant may be C, Fe, Mg, or Zn, but is not limited thereto. According to an embodiment of the present invention, the III-V gate layer 112 may be a P-type GaN layer.

[0060] According to one embodiment of the present invention, the gate etch stop layer 114 may be disposed above the III-V gate layer 112. The gate etch stop layer 114 and the passivation layer 124 may have different etch rates, and the gate etch stop layer 114 may form a Schottky contact with the III-V gate layer 112. For example, the gate etch stop layer 114 may comprise a metal nitride containing a refractory metal, and the refractory metal may be selected from the group consisting of titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, uranium, rhenium, ruthenium, osmium, rhodium, and iridium. According to one embodiment of the present invention, the gate etch stop layer 114 may be, for example, titanium nitride.

[0061] According to one embodiment of the present invention, the passivation layer 124 can be used to eliminate or reduce surface defects present on the sidewalls of the III-V channel layer 104 and the top surface of the III-V barrier layer 106, thereby improving the electron mobility of the two-dimensional electron gas region 120. According to one embodiment of the present invention, the passivation layer 124 may be silicon nitride (SiN), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (Al2O3), or silicon oxide (SiO2), but is not limited thereto.

[0062] According to one embodiment of the present invention, the gate electrode 140 and the III-V gate layer 112 form a Schottky contact, while the source / drain electrode 142 and the III-V channel layer 104 form an ohmic contact. Furthermore, the gate electrode 140 and the source / drain electrode 142 can be single-layer or composite conductive layers, for example, comprising a first conductive layer 132 and a second conductive layer 134 from bottom to top. The first conductive layer 132 can be used to increase the adhesion of the second conductive layer 134 to other layers, and the second conductive layer 134 can be a conductive layer with low resistance. In one embodiment of the present invention, the first conductive layer 132 and the second conductive layer 134 can be titanium and aluminum, respectively, but are not limited thereto. In other embodiments of the present invention, the gate electrode 140 and the source / drain electrode 142 can each be a composite conductive layer composed of titanium / aluminum / titanium / gold.

[0063] Furthermore, according to one embodiment of the present invention, a buffer layer 102 may be further included between the substrate 100 and the III-V channel layer 104, which can be used to reduce the degree of stress or lattice mismatch present between the substrate 100 and the III-V channel layer 104. Additionally, the high electron mobility transistor 10 may further include an interlayer dielectric layer 160 covering the passivation layer 124, the gate electrode 140, and the source / drain electrode 142, and the interlayer dielectric layer 160 may be SiN, AlN, Al2O3, SiON, or SiO2, but is not limited thereto.

[0064] To enable those skilled in the art to implement the invention, the method for fabricating the high electron mobility transistor of the present invention is further described below.

[0065] Figure 2 This is a cross-sectional schematic diagram of a HEMT (Heat-Etching Media) with a III-V channel layer, a III-V barrier layer, a III-V semiconductor layer, and an etch stop layer disposed on a substrate, according to an embodiment of the present invention. Figure 2As shown, in one process stage of the high electron mobility transistor 20, a buffer layer 102, a III-V channel layer 104, a III-V barrier layer 106, a III-V semiconductor layer 108, and an etch stop layer 110 can be sequentially stacked on the substrate 100. These stacked layers on the substrate 100 can be formed using any suitable method, such as molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), or other suitable methods. The buffer layer 102 may include multiple sub-semiconductors, and its overall resistance is higher than that of other layers on the substrate 100. Specifically, the proportion of certain elements in the buffer layer 102, such as metal elements, gradually changes from the substrate 100 towards the III-V channel layer 104. For example, in the case where the substrate 100 and the III-V channel layer 104 are a silicon substrate and a GaN layer, respectively, the buffer layer 102 can be aluminum gallium nitride (Al₂O₃) with a gradually varying composition. x Ga (1-x) N), and along the direction from the substrate 100 to the III-V channel layer 104, the X value will decrease from 0.9 to 0.15 in a continuous or stepwise manner.

[0066] Figure 3 This is a cross-sectional schematic diagram of a HEMT with an active region disposed on a substrate, according to an embodiment of the present invention. Figure 3 As shown, one or more photolithography and etching processes can be performed to sequentially etch away portions of the etch stop layer 110, the III-V semiconductor layer 108, the III-V barrier layer 106, and the III-V channel layer 104, thereby forming a mesa region R1 on the substrate 100. The mesa region R1 is a protruding structure. In subsequent processes, an insulating structure will be provided around the mesa region R1 to prevent unnecessary electrical connections between the mesa region R1 and other surrounding semiconductor components.

[0067] Figure 4 This is a cross-sectional schematic diagram of a HEMT (Heated Metal Transformer) with a III-V gate layer and a gate etch stop layer disposed on a substrate, according to an embodiment of the present invention. The etch stop layer 110 and the III-V semiconductor layer 108 on the substrate 100 can be patterned simultaneously or separately to form a HEMT as described above. Figure 4The diagram shows a gate etch stop layer 114 and a III-V gate layer 112, exposing a portion of the top surface of the III-V barrier layer 106. The gate etch stop layer 114 and the III-V gate layer 112 may have the same width, making them substantially coextensive. Furthermore, after forming the gate etch stop layer 114 and the III-V gate layer 112, in the area not covered by the III-V gate layer 112, a two-dimensional electron gas is formed in the two-dimensional electron gas region 120 due to the piezoelectric effect between the III-V channel layer 104 and the III-V barrier layer 106. In contrast, the area covered by the III-V gate layer 112 does not form a two-dimensional electron gas and can therefore be considered a two-dimensional electron gas cutoff region 122.

[0068] Figure 5 This is a schematic cross-sectional view of a HEMT (Heated Iron Media) according to an embodiment of the present invention, showing a III-V group gate layer and a gate etch stop layer covered by a passivation layer. Figure 5 As shown, a passivation layer 124 can be formed through a suitable deposition process. The material of the passivation layer 124 can be SiN, AlN, Al2O3 or SiO2, but is not limited to these, and it can completely cover the gate etch stop layer 114, the III-V gate layer 112, the III-V channel layer 104 and the III-V barrier layer 106.

[0069] Figure 6 This is a schematic cross-sectional view of a HEMT after forming gate contact holes and source / drain contact holes in the passivation layer, according to an embodiment of the present invention. Figure 6As shown, a gate contact hole 126 can be formed above the III-V gate layer 112 using photolithography and etching processes, and at least one source / drain contact hole can be formed on both sides of the III-V gate layer 112, such as a separately arranged dual source / drain contact hole 128. During the etching process to form the contact hole, by selecting appropriate etching components and parameters, the etching selectivity ratio between the passivation layer 124 and the gate etch stop layer 114, and the etching selectivity ratio between the passivation layer 124 and the III-V channel layer 104, can each be higher than a preset value, such as a preset value of 5 to 300. Therefore, when the etching process is completed, the bottom surface of the gate contact hole 126 will be located on the top surface of the gate etch stop layer 114, thus exposing the top surface of the gate etch stop layer 114; while the bottom surface of each source / drain contact hole 128 will be located on the top surface of the III-V channel layer 104 or extend into the III-V channel layer 104, thus exposing the III-V channel layer 104. In addition, since the bottom surface of the source / drain contact hole 128 will be located on the top surface of the III-V channel layer 104 or extend into the III-V channel layer 104, a two-dimensional electron gas cutoff region 122 will be formed below each source / drain contact hole 128.

[0070] Figure 7 This is a schematic cross-sectional view of a HEMT after full deposition of a conductive layer according to an embodiment of the present invention. A conductive layer, such as a composite conductive layer including a first conductive layer 132 and a second conductive layer 134, can be oriented onto the top surface of the passivation layer 124, within the gate contact hole 126, and within the source / drain contact hole 128 via a suitable deposition process. According to an embodiment of the present invention, for the gate contact hole 126 with a small opening area, the second conductive layer 134 may completely fill the gate contact hole 126.

[0071] Figure 8 This is a schematic cross-sectional view of a HEMT after forming a gate electrode and a source / drain electrode in a contact hole, according to an embodiment of the present invention. Photolithography and etching processes can be performed to pattern the first conductive layer 132 and the second conductive layer 134, thereby forming a HEMT as described above. Figure 8 The gate electrode 140 and source / drain electrode 142 are shown. The gate electrode 140 is located within the gate contact hole 126 and also covers a portion of the top surface of the passivation layer 124 in a oriented manner; while the source / drain electrode 142 is located within the source / drain contact hole 128 and also covers another portion of the top surface of the passivation layer 124 in a oriented manner.

[0072] Next, an interlayer dielectric layer can be deposited on the passivation layer 124, the gate electrode 140, and the source / drain electrode 142 to obtain, as shown in the figure. Figure 1 The high electron mobility transistor 10 is shown.

[0073] Figure 9 This is a flowchart illustrating a method for fabricating a HEMT according to an embodiment of the present invention. Figure 9 As shown, according to an embodiment of the present invention, a method 200 for fabricating a high electron mobility transistor may include: step 202: providing a substrate; step 204: sequentially depositing a III-V channel layer, a III-V barrier layer, a III-V semiconductor layer, and an etch stop layer on the substrate; step 206: patterning the III-V semiconductor layer and the etch stop layer; step 208: depositing a passivation layer; step 210: forming gate contact holes and source / drain contact holes in the passivation layer; step 212: simultaneously depositing a conductive layer on the top surface of the passivation layer within the gate contact holes and the source / drain contact holes; step 214: patterning the conductive layer; and step 216: depositing an interlayer dielectric layer.

[0074] According to the above embodiments of the present invention, gate contact holes and source / drain contact holes can be simultaneously formed in the passivation layer by performing the same photolithography and etching process. Furthermore, appropriate etching components and parameters can be adjusted so that the bottom of the gate contact hole does not penetrate the gate etch stop layer, and the bottom of the source / drain contact hole does not penetrate the III-V channel layer. Subsequently, the gate electrode and source / drain electrode can be simultaneously formed through the same deposition, photolithography, and etching process, thus simplifying the process complexity and reducing manufacturing costs.

[0075] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high electron mobility transistor, characterized in that, include: The first, third, and fifth generation channel layers are set on a base; A passivation layer is disposed on the III-V channel layer and includes a gate contact hole and at least one source / drain contact hole; A group 135 barrier layer is disposed between the group 35 channel layer and the passivation layer; A gate structure includes a group III-V gate layer, a gate etch stop layer, and a gate electrode stacked in sequence, wherein the gate electrode is disposed in the gate contact hole and conforms to the gate contact hole, and covers a portion of the top surface of the passivation layer; At least one source / drain electrode is disposed in and conforms to the at least one source / drain contact hole, wherein the at least one source / drain electrode covers another portion of the top surface of the passivation layer; as well as An interlayer dielectric layer covers the passivation layer, the gate electrode, and the at least one source / drain electrode.

2. The high electron mobility transistor as described in claim 1, characterized in that, The passivation layer comprises silicon oxide, aluminum nitride, aluminum oxide, silicon oxynitride, or silicon nitride.

3. The high electron mobility transistor as described in claim 1, characterized in that, The 3V gate layer is a P-type 3V gate layer.

4. The high electron mobility transistor as described in claim 1, characterized in that, The gate etch stop layer comprises a metal nitride, wherein the metal in the metal nitride is selected from the group consisting of refractory metals.

5. The high electron mobility transistor as described in claim 1, characterized in that, The gate etch stop layer and the III-V gate layer are connected by a Schottky contact.

6. The high electron mobility transistor as claimed in claim 1, characterized in that, The gate electrode is in direct contact with the gate etching stop layer.

7. The high electron mobility transistor as claimed in claim 1, characterized in that, The at least one source / drain electrode is in direct contact with the III-V channel layer.

8. The high electron mobility transistor as claimed in claim 1, characterized in that, The gate electrode and the at least one source / drain electrode have the same composition.

9. The high electron mobility transistor as described in claim 8, characterized in that, The interlayer dielectric layer comprises aluminum nitride, aluminum oxide, silicon nitride, silicon oxynitride, or silicon oxide.

10. A method for fabricating a high electron mobility transistor, characterized in that, include: A substrate is provided on which a group III-V channel layer, a group III-V barrier layer, a group III-V gate layer, and a gate etch stop layer are sequentially disposed. A passivation layer is formed to cover the III-V group barrier layer and the gate etch stop layer; A gate contact hole and at least one source / drain contact hole are formed in the passivation layer, wherein the gate contact hole exposes the gate etch stop layer and the at least one source / drain contact hole exposes the III-V channel layer; A conductive layer is formed on a top surface of the passivation layer and disposed in the gate contact hole and the at least one source / drain contact hole; The conductive layer is etched to form a gate electrode and at least one source / drain electrode, wherein the gate electrode conformally covers a portion of the top surface of the passivation layer and conforms to the gate contact hole, and the at least one source / drain electrode conformally covers another portion of the top surface of the passivation layer and conforms to the at least one source / drain contact hole. as well as An inter-dielectric layer is formed to cover the gate electrode and the at least one source / drain electrode.

11. The method for fabricating a high electron mobility transistor as described in claim 10, characterized in that, The 3V gate layer is a P-type 3V gate layer.

12. The method for fabricating a high electron mobility transistor as described in claim 10, characterized in that, The gate etch stop layer comprises a metal nitride, wherein the metal in the metal nitride is selected from the group consisting of refractory metals.

13. The method for fabricating a high electron mobility transistor as described in claim 10, characterized in that, The passivation layer comprises silicon oxide, aluminum nitride, aluminum oxide, silicon oxynitride, or silicon nitride.

14. The method for fabricating a high electron mobility transistor as described in claim 10, characterized in that, The gate etch stop layer and the III-V gate layer are connected by a Schottky contact.

15. The method for fabricating a high electron mobility transistor as described in claim 10, characterized in that, The conductive layer is in direct contact with the gate etch stop layer.

16. The method for fabricating a high electron mobility transistor as described in claim 10, characterized in that, The at least one source / drain electrode is in direct contact with the III-V channel layer.

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