Bidirectional scan cell for single-path reversible scan chain

Abstract

The circuit includes a plurality of scan chains. The plurality of scan chains include bidirectional scan units. Each bidirectional scan unit includes two serial input-output ports, which are used as serial data input ports or serial data output ports based on a control signal. Each of the plurality of scan chains is configured to perform a shift operation in a first direction or a second direction based on the control signal. The first direction is opposite to the second direction.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 804,320, filed on February 12, 2019, and U.S. Provisional Patent Application No. 62 / 837,218, filed on April 23, 2019, which are hereby incorporated by reference in their entirety. Technical Field

[0003] The presently disclosed technology relates to circuit testing. Various embodiments of the disclosed technology may be particularly useful for scan chain diagnostics. Background Art

[0004] Building circuits on silicon as test chips can provide insight into how new manufacturing processes work. Traditionally, semiconductor manufacturers have relied primarily on SRAM (static random-access memory) test chips to improve, verify, and monitor new semiconductor manufacturing processes. However, the transistors and circuit geometries used on SRAM test chips represent only a small fraction of the transistors and circuit geometries found in actual products. In recent years, test chips with logic circuit components (hereinafter referred to as logic test chips) are often used to supplement or replace SRAM test chips. Although more closely representing chips with real circuit designs, logic test chips are not as easy to test or diagnose as SRAM test chips.

[0005] In order to check whether the logic test chip is manufactured according to the design and to locate potential defects, scan testing is usually used. In this technology, a series of known values ​​(test stimulus or test pattern) are shifted into (or loaded into) a state element called a scan cell through their sequential input. These scan cells are interconnected into a scan chain for scan testing. The shift-in is achieved by placing the integrated circuit in a specific mode called a shift mode and then applying a series of clock pulses called "shift pulses" or "shift clock pulses". Each shift clock pulse pushes the test stimulus bit into the scan cell in each scan chain. This continues until all scan cells in the scan chain are filled with test mode bits. Then, one or more clock pulses called "capture pulses" or "capture clock pulses" are applied to the circuit, just as they are in normal operation. This is called capture mode. After the test mode bit is injected into the circuit, the test result (test response) is "captured" and stored in the scan cell. Then, the circuit returns to the shift mode, and with each additional clock pulse, as each bit of the new test mode is pushed in or shifted in, the test response bit is pushed out or shifted out. The shifted test response is then compared to the expected result to determine and locate any errors. The shift mode and capture mode are collectively referred to as the test mode.

[0006] The scan chain and its associated clock circuits are themselves a major source of circuit failures. It is reported that defects occurring on the scan chain account for approximately 30% to 50% of all faulty chips. Therefore, the scan chain needs to be tested and diagnosed first. As discussed in detail below, faulty scan chains can be detected by relatively simple methods. However, locating defective scan cells is challenging. Physical fault analysis instruments are sometimes used in conjunction with testers to search for defective responses along the scan chain. These hardware-based methods typically rely on specially designed scan chains and scan cells. Although effective in isolating scan chain defects, the requirement for additional hardware may be unacceptable in many actual products. Moreover, it is difficult to apply these methods to chips with embedded compression circuits without adopting a bypass mode.

[0007] Software-based techniques use algorithmic diagnostic procedures to identify faulty scan cells. They can use traditional scan chains with or without embedded compression to run chain diagnostics. Current software-based chain diagnostic techniques can be further divided into two categories: model-based algorithms and data-driven algorithms. In the model-based chain diagnostic process, fault models and pattern simulations are used. In the data-driven chain diagnostic process, signal analysis, filtering, and edge detection are applied. Each algorithm type has its own advantages and disadvantages. The two can also be combined to improve diagnostic resolution and diagnostic accuracy. Although traditional methods can achieve satisfactory results for defects whose behavior is exactly the same as the modeled faults (for example, fixed 0 faults at the output of the scan cell), defects in the scan chain usually exhibit unmodeled fault behavior (for example, intermittent fault behavior). For unmodeled faults, both diagnostic accuracy and diagnostic resolution may be significantly reduced.

[0008] The use of bidirectional scan chains (or reversible scan chains) to improve chain diagnostic accuracy and resolution was first proposed by P. Song in "A New Scan Architecture for Improving Scan Chain Diagnosis and Delay Fault Coverage," Proceedings of the 9th IEEE North Atlantic Test Workshop (NATW), 2000, pp. 14-18. Similar techniques are discussed in a paper entitled "Bidirectional Scan Chains for Digital Circuit Testing" published by Ip.com on November 21, 2007. U.S. Patents No. 9,222,978 and No. 10,156,607 also disclose scan testing in both forward and reverse directions using reversible scan chains. All of these techniques in the literature have a common feature: the two opposite scan paths for the scan chain are partially separated outside the scan cells on the scan chain.

[0009] Figure 1An example of two block diagrams 110 and 120 of a reversible scan chain according to these disclosed techniques is shown. The scan chain includes three scan units 130, 140, and 150, and four multiplexers 135, 145, 155, and 165. The control signal provided from the port 160 is used as a selection signal for the four multiplexers 135 to 165. In the block diagram 110, as shown by the solid line with an arrow, the control signal enables a scan path that follows the order of multiplexer 135-scan unit 130-multiplexer 145-scan unit 140-multiplexer 155-scan unit 150-multiplexer 165. In block diagram 120, as indicated by the solid arrowed line, the control signal inverts and enables different scan paths multiplexer 155-scan unit 150-multiplexer 145-scan unit 140-multiplexer 135-scan unit 130-multiplexer 165. The two paths do share common segments, such as one segment between multiplexer 135 and scan unit 130, but many other segments are unique to either the forward path or the reverse path. Conventional architectures, while facilitating chain diagnostics, incur too much silicon area overhead and routing congestion. Summary of the invention

[0010] Various aspects of the disclosed technology relate to chain testing and diagnosis in a reversible scan architecture. In one aspect, there is a circuit, comprising: a circuit including a plurality of scan chains including bidirectional scan cells, each of the bidirectional scan cells including two serial input-output ports, the serial input-output ports being used as serial data input ports or serial data output ports based on a control signal, each of the plurality of scan chains being configured to perform a shift operation in a first direction or a second direction based on the control signal, the first direction being opposite to the second direction.

[0011] Each of the bidirectional scanning units may further include two tri-state buffers, the outputs of the two tri-state buffers are respectively coupled to the two serial input-output ports of each of the bidirectional scanning units, and the two tri-state buffers are respectively controlled by the control signal and the inversion of the control signal. The two tri-state buffers are in a demultiplexer. Each of the scanning units may further include a multiplexer, the two inputs of the multiplexer are respectively coupled to the outputs of the two tri-state buffers. Each of the scanning units may further include a conventional scanning unit, the serial output of the conventional scanning unit is coupled to the inputs of the two tri-state buffers.

[0012] Alternatively, each of the scanning units may further include a multiplexer and a demultiplexer, two outputs of the demultiplexer are respectively coupled to the two serial input-output ports, and two inputs of the multiplexer are respectively coupled to the two serial input-output ports.

[0013] Alternatively, each of the scanning units further comprises a first pair of tri-state buffers and a second pair of tri-state buffers respectively controlled by the control signal and the inversion of the control signal, wherein an output of one tri-state buffer of the first pair of tri-state buffers is coupled to one of the two serial input-output ports, and an output of one tri-state buffer of the second pair of tri-state buffers is coupled to the other of the two serial input-output ports.

[0014] In another aspect, there are one or more computer-readable media storing computer-executable instructions for causing a computer to execute a method, the method comprising: creating multiple scan chains in a circuit design to test a chip manufactured according to the circuit design, the multiple scan chains comprising: a bidirectional scan unit, each of the bidirectional scan units comprising two serial input-output ports, the serial input-output ports being used as a serial data input port or a serial data output port based on a control signal, each of the multiple scan chains being configured to perform a shift operation in a first direction or a second direction based on the control signal, the first direction being opposite to the second direction.

[0015] In another aspect, there is a bidirectional scanning unit, comprising: two serial input-output ports, which are used as serial data input ports or serial data output ports based on control signals; two three-state buffers, whose outputs are respectively coupled to the two serial input-output ports, and the two three-state buffers are respectively controlled by the control signal and the inversion of the control signal; and a state element, whose outputs are coupled to the inputs of the two three-state buffers.

[0016] The two tri-state buffers may be in a demultiplexer. The state element may be a flip-flop.

[0017] The bidirectional scanning unit may further include a multiplexer, two inputs of the multiplexer being respectively coupled to the outputs of the two tri-state buffers.

[0018] The bidirectional scanning unit may further include two additional tri-state buffers, inputs of the two additional tri-state buffers are respectively coupled to the two serial input-output ports, and the two additional tri-state buffers are respectively controlled by the control signal and the inversion of the control signal.

[0019] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features in the independent claim and with features in other dependent claims as appropriate and not just as explicitly set out in a claim.

[0020] Certain objects and advantages of various inventive aspects have been described above. Of course, it should be understood that not all of these objects or advantages can be achieved according to any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology can be embodied or implemented in a manner that achieves or optimizes one advantage or a group of advantages as taught herein without achieving other objects or advantages taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 An example of two block diagrams showing a reversible scan chain including a conventional scan unit, respectively, for two different scan directions is shown.

[0022] Figure 2A An example of a reversible scan chain including a bidirectional scan unit according to various embodiments of the disclosed technology is shown.

[0023] Figure 2B An example of a block diagram of a bidirectional scanning unit according to various embodiments of the disclosed technology is shown.

[0024] Figure 3 Examples of two block diagrams of reversible scan chains respectively used for two different scan directions according to various embodiments of the disclosed technology are shown.

[0025] Figure 4 Another example of two block diagrams of reversible scan chains respectively used for two different scan directions according to various embodiments of the disclosed technology is shown.

[0026] Figure 5A Yet another example of two block diagrams of reversible scan chains respectively used for two different scan directions according to various embodiments of the disclosed technology is shown.

[0027] Figure 5B It is shown that various embodiments of the disclosed technology can be Figure 5A An example of a block diagram of a demultiplexer used in a bidirectional scan unit in FIG.

[0028] Fig. 6A An example of a pipeline unit inserted into a bidirectional scanning unit for one scanning direction is shown.

[0029] Figure 6B An example of a pipeline unit inserted into a bidirectional scanning unit for two scanning directions is shown.

[0030] Figure 7 A programmable computer system is shown upon which various embodiments of the disclosed technology may be employed. DETAILED DESCRIPTION

[0031] Various aspects of the disclosed technology relate to chain testing and diagnosis in a reversible scanning architecture. In the following description, many details are set forth for the purpose of explanation. However, one of ordinary skill in the art will recognize that the disclosed technology can be practiced without using these specific details. In other cases, well-known features are not described in detail to avoid confusing the disclosed technology.

[0032] Some of the techniques described herein may be implemented by software instructions stored on a computer-readable medium, software instructions executed on a computer, or a combination of the two. For example, some of the disclosed techniques may be implemented as part of an electronic design automation (EDA) tool. The method may be executed on a single computer or a networked computer.

[0033] Although the operations of the disclosed methods are described in a particular order for ease of expression, it should be understood that such descriptions encompass reordering unless a particular ordering is required by the specific language set forth below. For example, operations described in order may in some cases be reordered or performed simultaneously. In addition, for simplicity, the disclosed flow charts and block diagrams generally do not show the various ways in which a particular method may be used in conjunction with other methods.

[0034] The detailed description of the method or device sometimes uses terms such as "perform" to describe the disclosed method or device function / structure. This term is a high-level description. The actual operation or function / structure corresponding to these terms will vary according to the specific implementation, and it is easy for ordinary technicians in this field to discern.

[0035] Furthermore, as used herein, the term "design" is intended to encompass data describing an entire integrated circuit device. However, the data is also intended to encompass smaller data sets describing one or more components of the entire device (eg, a portion of an integrated circuit device).

[0036] As used in this application, the singular forms "a", "an" and "the" include the plural forms unless the context clearly dictates otherwise. In addition, the term "include" encompasses "comprises". In addition, the term "coupled" includes mechanical, electrical, magnetic, optical, and other practical ways of coupling or linking objects together, and does not exclude the presence of intermediate elements between the coupled objects. In addition, as used herein, the term "and / or" means any one or more combinations of the phrases.

[0037] The reduction in feature size increases the likelihood that a manufacturing defect in an integrated circuit will result in a faulty chip. A very small defect can result in a faulty transistor or interconnect. Even a single faulty transistor or interconnect can cause the entire chip to operate incorrectly. Nevertheless, manufacturing defects cannot be avoided, whether the manufacturing process is in the prototype stage or in high-volume manufacturing. Therefore, it is necessary to test the chips during the manufacturing process. It is also necessary to diagnose faulty chips to improve and maintain manufacturing yield.

[0038] Testing typically involves applying a set of test stimuli (test patterns) to the circuit under test and then analyzing the responses generated by the circuit under test. Functional testing attempts to verify that the circuit under test operates in accordance with its functional specifications, while structural testing attempts to determine whether the circuit under test is correctly assembled from some low-level building blocks specified in the structural netlist, and whether these low-level building blocks and their wiring connections are manufactured without defects. For structural testing, it is assumed that if functional verification has demonstrated the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should operate correctly. Structural testing has been widely adopted, at least in part because it enables test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements without having to deal with an exponential explosion of multiple functional states and state transitions.

[0039] In order to make it easier to develop and apply test patterns, certain testability features are added to the circuit design, which is called test design or testability design (DFT). Scan testing is the most common DFT method. In the basic scan test scheme, all or most of the internal timing state elements (latches, triggers, etc.) in the circuit design are controllable and observable through a serial interface. These functional state elements are usually replaced by dual-purpose state elements called scan cells. Scan cells are connected together to form a scan chain-a serial shift register for shifting in test patterns and out of test responses. Scan cells can be operated as originally intended for functional purposes (functional / task mode) and can be scanned as a unit in a scan chain (scan mode). Widely used scan cell types include edge-triggered flip-flops with bidirectional multiplexers for data input. Bidirectional multiplexers are usually controlled by a single control signal called scan_enable, which selects input signals for the scan cell from a scan signal input port or a system signal input port. The scan signal input port is usually connected to the output of another scan cell, and the system signal input port is connected to the functional logic. Scan cells can act as both control points and observation points. Control points can be used to set certain logic values ​​at some locations in the circuit under test, trigger (activate) faults and propagate erroneous values ​​to observation points. Scan testing enables the test equipment to access deeply embedded gates through primary inputs / outputs and / or some physical test points and eliminates the need for complex state transition sequences when trying to control or observe what is happening in some internal circuit elements.

[0040] Test patterns for scan testing are usually generated through the process of automatic test pattern generation (ATPG). ATPG usually focuses on a set of faults derived from gate-level fault models. A defect is an error caused in a device during the manufacturing process. A fault model is a description of how a defect changes the behavior of a design. In other words, a defect is a fault or physical flaw that may cause a failure. For a given target fault, ATPG includes two stages: fault activation and fault propagation. Fault activation establishes a signal value at the fault site that is opposite to the signal value generated by the fault. Fault propagation propagates the fault effect forward by sensitizing the path from the fault site to the scan cell or the main output. If the test response value captured by the scan cell or the main output is different from the expected value, the fault at the site is said to be detected by the test pattern. The goal of ATPG is to discover test patterns that, when applied to a circuit, enable the tester to distinguish between correct circuit behavior and faulty circuit behavior caused by one or more specific faults. The effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern count), which should be proportional to the test application time. Here, fault coverage is defined as the ratio of the number of detected faults to the total number of faults.

[0041] The most popular fault model used in practice is the single fixed fault model. In this model, it is assumed that one of the signal lines in the circuit is fixed at a fixed logic value, regardless of the input provided to the circuit. The fixed fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the circuit function based on its timing. Delay faults are caused by the limited rise and fall time periods of the signal in the gate and the propagation delay of the interconnection between the gates. Conversion faults are used to model point defects that affect the delay at the gate input or the gate output due to their simplicity. Under scan-based testing, conversion faults are associated with additional delays that are large enough to cause any path through the fault site to be delayed by more than the time period. The cell internal fault model can be derived using transistor-level circuit simulation (analog simulation). This method can accurately locate the defect location within the cell for various cell internal defects.

[0042] During the circuit design and manufacturing process, manufacturing tests screen out chips (die) containing defects. However, testing itself does not identify the cause of the unacceptably low or fluctuating yields that may be observed. Physical failure analysis (PFA) can examine the faulty chips to locate one or more defect locations and discover the root cause. The process typically involves etching away certain layers and then imaging the silicon surface with a scanning electron microscope or a focused ion beam system. The PFA process is laborious and time consuming. To facilitate the PFA process, diagnosis (also called scanning diagnosis) is typically used to narrow down one or more possible defect locations based on analyzing failure logs (failure files, failure files, or failure reports). Failure logs typically contain information about when (e.g., tester cycle), where (e.g., in which tester channel), how (e.g., at what logic value) the test failed, and which test model generated the expected test response. Layout information of the circuit design can also be used to further reduce the number of suspected defects.

[0043] Diagnosis includes logical diagnosis (sometimes called scan diagnosis or diagnosis) and chain diagnosis. Logical diagnosis can use a fault dictionary or directly check the syndrome (e.g., effect) of the faulty chip to determine the possible defect location (suspected defect). The latter method can include structural pruning (backtracking), fault injection and evaluation (fault simulation of both failed test patterns and passed test patterns). The quality of diagnosis can be measured by diagnostic resolution (the relationship between the number of actual defects and the number of suspected defects). Diagnostic resolution is not only related to the algorithm used for diagnosis, but also to the test pattern used for manufacturing testing (manufacturing test pattern). In order to improve the quality of diagnosis, a diagnostic test pattern generation process can be used. This process generates test patterns that can improve the set of suspected defects.

[0044] Chain diagnosis determines scan cells that may be defective. During the chain diagnosis process, two types of test modes can be used. The first type is called chain mode. Chain mode is a mode used in a process including shift-in and shift-out without the need for pulse clock capture. Other types are generally called scan modes. Scan mode is a mode used in a process including shift-in, one or more capture clock cycles, and shift-out, and the scan mode includes a mode generated by ATPG for testing system logic, a specific chain diagnostic mode generated only for the purpose of diagnosing the scan chain, and some specific functional modes. Chain mode can be used to test the integrity of the scan chain and / or determine the fault model associated with the faulty scan chain, while scan mode can be used to inject certain values ​​into some scan cells for locating defective scan cells.

[0045] Test applications in chip manufacturing testing are usually performed by automatic test equipment (ATE, automatic test equipment) (a type of tester). Scan-based testing consumes a lot of storage space and test time on ATE. The amount of data increases with the number of logic gates on the chip, and the same applies to the number of scan cells. However, practical considerations and ATE specifications usually limit both the number of available pins for scan input / scan output and the maximum scan frequency. It is very necessary to reduce the amount of test data that needs to be loaded into ATE and ultimately loaded into the circuit being tested. Fortunately, test patterns are compressible, mainly because only 1% to 5% of the test pattern bits are usually designated bits (focus bits), while the rest are undesignated bits (don't care bits). Undesignated bits can take any value without affecting fault coverage. Test compression can also take advantage of the fact that test cubes tend to be highly correlated. Test cubes are deterministic test patterns in which irrelevant bits are not filled by ATPG. The correlation exists because faults are structurally correlated in the circuit.

[0046] Various test compression techniques have been developed. Generally speaking, additional on-chip hardware is inserted before the scan chain and after the scan chain. The hardware added before the scan chain (decompressor) is configured to decompress the test stimulus from the ATE, while the hardware added after the scan chain (compressor) is configured to compress the test response captured by the scan chain. The decompressor expands the data from n test channels to fill more than n scan chains. The increase in the number of scan chains shortens each scan chain and therefore reduces the number of clock cycles required to shift into each test mode. Therefore, test compression can not only reduce the amount of data stored on the tester, but also reduce the test time for a given test data bandwidth.

[0047] All of the above processes, design insertion for test, test pattern generation and logic diagnostics, are typically performed by various electronic design automation tools, such as those available from Mentor Graphics Corporation, Wilsonville, Oregon, in the Tessent family of software tools.

[0048] Figure 2A An example of a reversible scan chain 200 according to various embodiments of the disclosed technology is shown. The reversible scan chain 200 includes bidirectional scan units 230, 240, ... and 250. Each of these bidirectional scan units 230, 240, ... and 250 includes two serial input-output ports, which can be configured to be used as serial data input or serial data output based on the control signal 210. Therefore, the reversible scan chain 200 can be scanned through the same scan path (rather than through the same scan path) based on the control signal Figure 1The bidirectional scanning units 230, 240, ... and 250 may include more components than conventional scanning units, but do not require Figure 1 The additional wiring between the multiplexers 135, 145, 155 and the scan cells is shown. Moreover, the bidirectional scan cells can be designed and optimized to be not significantly larger than conventional scan cells. In general, the increase in silicon area overhead (compared to conventional unidirectional scan chains) caused by the single-path reversible scan chain implemented according to various embodiments of the disclosed technology can be less than the increase in silicon area overhead caused by conventional dual-path reversible scan chains.

[0049] Each of the bidirectional scanning units 230, 240, ... and 250 may also include two tri-state buffers. A tri-state buffer is a device whose output port has three states: a high impedance state, a logic 1 state, and a logic 0 state. The output port presenting a high impedance state effectively removes the output of the tri-state buffer from the circuit. Whether the output port presents a logic 1 state or a logic 0 state depends on the signal at the input port. The control signal at the control port of the tri-state buffer determines whether the output port presents a high impedance state. Figure 2B An example of a block diagram of such a bidirectional scanning unit 220 according to various embodiments of the disclosed technology is shown. The scanning unit 220 includes two tri-state buffers 260 and 270. The tri-state buffer 260 is controlled by a control signal 221, and the tri-state buffer 270 is controlled by the inversion of the control signal 221. The outputs of the two tri-state buffers 260 and 270 are respectively coupled to the serial input-output ports 223 and 222 of the bidirectional scanning unit 220. When the control signal 210 is valid (asserted), the tri-state buffer 270 presents a high impedance state, allowing the serial input-output port 222 to be used as the serial input port of the bidirectional scanning unit 220; when the control signal 210 is invalid, the tri-state buffer 260 presents a high impedance state, allowing the serial input-output port 223 to be used as the serial input port of the bidirectional scanning unit 220. Each of the bidirectional scanning units 230, 240, ... and 250 may further include a regular scanning unit. The serial output of the regular scanning unit is coupled to the input of the two tri-state buffers.

[0050] Figure 3Examples of two block diagrams 300 and 305 of reversible scan chains for two different scan directions, respectively, according to various embodiments of the disclosed technology are shown. The reversible scan chain includes three bidirectional scan units 310, 320, 330. Each bidirectional scan unit 310, 320, 330 includes a scan element (311, 321, 331), a pair of tri-state buffers (312 / 313, 322 / 323, 332 / 333) controlled by a control signal 340, and a pair of tri-state buffers (314 / 315, 324 / 325, 334 / 335) controlled by the inversion of the control signal 340. Here, the scan element includes a state element such as a flip-flop.

[0051] In block diagram 300, control signal 340 is active. Tristate buffer pairs 312 / 313, 322 / 323, 332 / 333 are in a state that allows their outputs to follow their inputs, while tristate buffer pairs 314 / 315, 324 / 325, 334 / 335 are in a high impedance state that blocks their outputs. Therefore, the signal path in the shift operation follows the order of tristate buffer 312 - scan element 311 - tristate buffer 313 - tristate buffer 322 - scan element 321 - tristate buffer 323 - tristate buffer 332 - scan element 331 - tristate buffer 333. Therefore, when control signal 340 is active, the direction of the shift operation is from left to right.

[0052] In block diagram 305, control signal 340 is inactive. Tristate buffer pairs 314 / 315, 324 / 325, 334 / 335 are in a state that allows their outputs to follow their inputs, while tristate buffer pairs 312 / 313, 322 / 323, 332 / 333 are in a high impedance state that blocks their outputs. Therefore, the signal path in the shift operation follows the sequence of tristate buffer 333 - scan element 331 - tristate buffer 332 - tristate buffer 323 - scan element 321 - tristate buffer 322 - tristate buffer 313 - scan element 331 - tristate buffer 312. Therefore, when control signal 340 is inactive, the direction of the shift operation is from right to left.

[0053] Figure 4Another example of two block diagrams 400 and 405 of a reversible scan chain for two different scan directions, respectively, according to various embodiments of the disclosed technology is shown. The reversible scan chain includes three bidirectional scan units 410, 420, 430. Each bidirectional scan unit 410, 420, 430 includes a scan element (411, 421, 431), a tri-state buffer (413, 423, 433) controlled by a control signal 440, a tri-state buffer (414, 424, 434) controlled by the inversion of the control signal 440, and a multiplexer (412, 422, 432) controlled by the control signal 440. Here, the scan element includes a state element such as a flip-flop.

[0054] In block diagram 400, control signal 440 is active. Tri-state buffers 413, 423, 433 are in a state that allows their outputs to follow their inputs, while tri-state buffers 414, 424, 434 are in a high impedance state that blocks their outputs. Multiplexers 412, 422, 432 select their first input (the input at the top of the diagram) for output. Therefore, the signal path in the shift operation follows the order of multiplexer 412 - scan element 411 - tri-state buffer 413 - multiplexer 422 - scan element 421 - tri-state buffer 423 - multiplexer 432 - scan element 431 - tri-state buffer 433. Therefore, when control signal 440 is active, the direction of the shift operation is from left to right.

[0055] In block diagram 405, control signal 440 is inactive. Tri-state buffers 414, 424, 434 are in a state that allows their outputs to follow their inputs, while tri-state buffers 413, 423, 433 are in a high impedance state that blocks their outputs. Multiplexers 412, 422, 432 select the second input (the input at the bottom of the diagram) for output. Therefore, the signal path in the shift operation follows the order of multiplexer 432 - scan element 431 - tri-state buffer 434 - multiplexer 422 - scan element 421 - tri-state buffer 424 - multiplexer 412 - scan element 411 - tri-state buffer 414. Therefore, when control signal 440 is inactive, the direction of the shift operation is from right to left.

[0056] Figure 5AAnother example of two block diagrams 500 and 505 of a reversible scan chain for two different scan directions according to various embodiments of the disclosed technology is shown. The reversible scan chain includes three bidirectional scan units 510, 520, 530. Each bidirectional scan unit 510, 520, 530 includes a scan element (511, 521, 531), a multiplexer (512, 522, 532) and a demultiplexer (513, 523, 533). The multiplexer (512, 522, 532) and the demultiplexer (513, 523, 533) are all controlled by a control signal 540. Here, the scan element includes a state element such as a flip-flop.

[0057] In block diagram 500, control signal 540 is active. Multiplexers 512, 522, 532 select their first inputs (the topmost inputs in the figure) for output, and demultiplexers 513, 523, 533 output their input signals on their first outputs (the topmost outputs in the figure). Therefore, the signal path in the shift operation follows the order of multiplexer 512-scan element 511-demultiplexer 513-multiplexer 522-scan element 521-demultiplexer 523-multiplexer 532-scan element 531-demultiplexer 533. Therefore, when control signal 540 is active, the direction of the shift operation is from left to right.

[0058] In block diagram 505, control signal 540 is inactive. Multiplexers 512, 522, 532 select their second inputs (the inputs at the bottom of the figure) for output, and demultiplexers 513, 523, 533 output their input signals on their second outputs (the outputs at the bottom of the figure). Therefore, the signal path in the shift operation follows the order of multiplexer 532-scan element 531-demultiplexer 533-multiplexer 522-scan element 521-demultiplexer 523-multiplexer 512-scan element 511-demultiplexer 513. Therefore, when control signal 540 is inactive, the direction of the shift operation is from left to right.

[0059] Figure 5B It is shown that various embodiments of the disclosed technology can be Figure 5A5. An example of a block diagram of a demultiplexer 550 used in a bidirectional scan unit 510, 520, 530 in FIG. The demultiplexer 550 includes two tri-state buffers 551, 552 and an inverter 553. A signal input 555 of the demultiplexer 550 is coupled to the inputs of the tri-state buffers 551, 552; a first signal output 557 of the demultiplexer 550 is coupled to the output of the tri-state buffer 551; and a second signal output 556 of the demultiplexer 550 is coupled to the output of the tri-state buffer 552. A control signal provided through a select port 554 of the demultiplexer directly controls the tri-state buffer 551 and indirectly controls the tri-state buffer 552 through the inverter 553. When the control signal is valid, the tri-state buffer 551 is in a state that allows the first input 557 to follow the input 555, while the tri-state buffer 552 is in a high impedance state that blocks the second output 556. When the control signal is inactive, tri-state buffer 552 is in a state that allows second input 556 to follow input 555 , while tri-state buffer 551 is in a high impedance state that blocks first output 557 .

[0060] Figure 3 , Figure 4 , Figure 5A The parallel data input and parallel data output of each bidirectional scanning unit are not shown for ease of illustration. A multiplexer can be placed immediately before the data input of the flip-flop in the bidirectional scanning unit to select the serial data input or the parallel data input, and the output of the flip-flop can be directly coupled to the functional circuit. It will be understood by those skilled in the art that Figure 3 , Figure 4 , Figure 5A The scanning elements in the bidirectional scanning unit shown can be conventional unidirectional scanning units. Figure 3 , Figure 4 , Figure 5A Only three bidirectional scanning units are shown in each of the embodiments, but the disclosed technology can be applied to scan chains containing various numbers of bidirectional scanning units.

[0061] The pipeline unit can be inserted into the bidirectional scanning unit for use in one scanning direction or in both scanning directions. Fig. 6A An example of a pipeline unit 614 inserted into the bidirectional scanning unit 600 for one scanning direction is shown. The bidirectional scanning unit 600 includes a multiplexer 612, a flip-flop 611, and a demultiplexer 613. The pipeline unit 614 is inserted between the second output of the demultiplexer 613 and the second input of the multiplexer 612. Therefore, the pipeline unit 614 works on the scanning direction from right to left. Figure 6BAn example of a pipeline unit 615 inserted into the bidirectional scanning unit 600 for two scanning directions is shown. Specifically, the pipeline unit 615 is inserted between the output of the multiplexer 612 and the input of the flip-flop 611. Therefore, the pipeline unit 615 works for both the scanning direction from right to left and the scanning direction from left to right.

[0062] Various examples of the disclosed technology can be implemented by a computing device (e.g., a programmable computer) by executing software instructions. For example, a computing device can be caused to execute a method for creating a scan chain including a bidirectional scan unit in a circuit design for testing a chip manufactured according to the circuit design. Therefore, Figure 7 An illustrative example of a computing device 701 is shown. As seen in the figure, computing device 701 includes a computing unit 703 having a processing unit 705 and a system memory 707. Processing unit 705 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. System memory 707 can include both a read-only memory (ROM) 709 and a random access memory (RAM) 711. As will be appreciated by one of ordinary skill in the art, both the read-only memory (ROM) 709 and the random access memory (RAM) 711 can store software instructions that are executed by processing unit 705.

[0063] The processing unit 705 and the system memory 707 are directly or indirectly connected to one or more peripheral devices via the bus 713 or an alternative communication structure. For example, the processing unit 705 or the system memory 707 can be directly or indirectly connected to one or more additional memory storage devices, such as a "hard" disk drive 715, a removable disk drive 717, an optical drive 719, or a flash memory card 721. The processing unit 705 and the system memory 707 can be directly or indirectly connected to one or more input devices 723 and one or more output devices 725. The input device 723 can include, for example, a keyboard, a pointing device (such as a mouse, a touch pad, a stylus, a trackball, or a joystick), a scanner, a camera, and a microphone. The output device 725 can include, for example, a monitor display, a printer, and a speaker. In various examples of the computer 701, one or more of the peripheral devices 715-725 can be housed internally with the computing unit 703. Alternatively, one or more of peripherals 715 - 725 may be external to the housing of computing unit 703 and connected to bus 713 via, for example, a universal serial bus (USB) connection.

[0064] In some embodiments, the computing unit 703 may be directly or indirectly connected to a network interface 727 for communicating with other devices constituting the network. The network interface 727 converts data and control signals from the computing unit 703 into network messages according to one or more communication protocols (e.g., Transmission Control Protocol (TCP) and Internet Protocol (IP)). In addition, the interface 727 may use any suitable connection agent (or combination of agents) to connect to the network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art and will not be discussed in more detail here.

[0065] It should be understood that computing device 701 is shown only as an example and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices, including Figure 7 The components of the computer 701 shown include only Figure 7 A subset of the components shown, or alternative combinations of these components, including Figure 7 For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, multiple single-processor computers and / or multi-processor computers arranged in a network, or some combination of the two.

[0066] The principles of the disclosed technology have been illustrated and described, and it is explained to those skilled in the art that the disclosed embodiments may be modified in arrangement and detail without departing from these principles. In view of the many possible embodiments to which the principles of the disclosed technology may be applied, it should be recognized that the illustrated embodiments are merely preferred examples of the technology and should not be viewed as limitations on the scope of the disclosed technology. Instead, the scope of the disclosed technology is defined by the following claims and their equivalents. Therefore, we claim all technologies that fall within the scope and spirit of these claims as our disclosed technology.

Claims

1. A circuit comprising: A plurality of scan chains including bidirectional scan units, each of the bidirectional scan units including two serial input-output ports, the serial input-output ports being used as a serial data input port or a serial data output port based on a single control signal, each of the plurality of scan chains being configured to perform a shift operation in a first direction or a second direction based on the single control signal, the first direction being opposite to the second direction.

2. The circuit of claim 1, wherein: Each of the bidirectional scanning units also includes two tri-state buffers, the outputs of the two tri-state buffers are respectively coupled to the two serial input-output ports of each of the bidirectional scanning units, and the two tri-state buffers are respectively controlled by the single control signal and the inversion of the single control signal.

3. The circuit of claim 2, wherein: The two tri-state buffers are in a demultiplexer.

4. The circuit of claim 2, wherein: Each of the bidirectional scanning units further includes a multiplexer, and two inputs of the multiplexer are respectively coupled to the outputs of the two tri-state buffers.

5. The circuit of claim 2, wherein: Each of the scan units further includes a normal scan unit having a serial output coupled to inputs of the two tri-state buffers.

6. The circuit of claim 1, wherein: Each of the scanning units further includes a multiplexer and a demultiplexer, two outputs of the demultiplexer are respectively coupled to the two serial input-output ports, and two inputs of the multiplexer are respectively coupled to the two serial input-output ports.

7. The circuit of claim 1, wherein: Each of the scanning units also includes a first pair of tri-state buffers and a second pair of tri-state buffers respectively controlled by the single control signal and the inversion of the single control signal, wherein the output of one of the tri-state buffers in the first pair of tri-state buffers is coupled to one of the two serial input-output ports, and the output of one of the tri-state buffers in the second pair of tri-state buffers is coupled to the other of the two serial input-output ports.

8. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method comprising: Creating multiple scan chains in a circuit design for testing a chip manufactured according to the circuit design, the multiple scan chains comprising: A bidirectional scanning unit, each of which includes two serial input-output ports, the serial input-output ports are used as serial data input ports or serial data output ports based on a single control signal, and each of the plurality of scan chains is configured to perform a shift operation in a first direction or a second direction based on the single control signal, the first direction being opposite to the second direction.

9. One or more computer-readable media as claimed in claim 8, wherein: Each of the bidirectional scanning units also includes two tri-state buffers, the outputs of the two tri-state buffers are respectively coupled to the two serial input-output ports of each of the bidirectional scanning units, and the two tri-state buffers are respectively controlled by the single control signal and the inversion of the single control signal.

10. One or more computer-readable media as claimed in claim 9, wherein: The two tri-state buffers are in a demultiplexer.

11. One or more computer-readable media as recited in claim 9, wherein: Each of the scanning units further includes a multiplexer, two inputs of the multiplexer are respectively coupled to the outputs of the two tri-state buffers.

12. One or more computer-readable media as recited in claim 9, wherein: Each of the scan units further includes a normal scan unit having a serial output coupled to inputs of the two tri-state buffers.

13. One or more computer-readable media as recited in claim 8, wherein: Each of the scanning units further includes a multiplexer and a demultiplexer, two outputs of the demultiplexer are respectively coupled to the two serial input-output ports, and two inputs of the multiplexer are respectively coupled to the two serial input-output ports.

14. One or more computer-readable media as recited in claim 8, wherein: Each of the scanning units also includes a first pair of tri-state buffers and a second pair of tri-state buffers respectively controlled by the single control signal and the inversion of the single control signal, wherein the output of one of the tri-state buffers in the first pair of tri-state buffers is coupled to one of the two serial input-output ports, and the output of one of the tri-state buffers in the second pair of tri-state buffers is coupled to the other of the two serial input-output ports.

15. A bidirectional scanning unit, comprising: two serial input-output ports that function as either a serial data input port or a serial data output port based on a single control signal; two tri-state buffers, the outputs of the two tri-state buffers being respectively coupled to the two serial input-output ports, the two tri-state buffers being respectively controlled by the single control signal and the inversion of the single control signal; as well as A state element, the output of which is coupled to the inputs of the two tri-state buffers.

16. The bidirectional scanning unit according to claim 15, wherein: The two tri-state buffers are in a demultiplexer.

17. The bidirectional scanning unit according to claim 15, further comprising: A multiplexer, two inputs of the multiplexer are respectively coupled to the outputs of the two tri-state buffers.

18. The bidirectional scanning unit according to claim 15, further comprising: Two additional tri-state buffers are provided, inputs of the two additional tri-state buffers are respectively coupled to the two serial input-output ports, and the two additional tri-state buffers are respectively controlled by the single control signal and the inversion of the single control signal.

19. The bidirectional scanning unit according to claim 15, wherein: The state element is a trigger.

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