Integrated assembly having a transistor body region coupled to a carrier sink structure; and method of forming the integrated assembly

Abstract

Some embodiments include an integrated assembly having a carrier slot structure and having a digit line above the carrier slot structure. A transistor body region is located above the digit line. An extension extends from the carrier slot structure to the transistor body region. The extension is configured to drain excess carriers from the transistor body region. A lower source / drain region is located between the transistor body region and the digit line and is coupled to the digit line. An upper source / drain region is above the transistor body region and is coupled to a storage element. A gate is adjacent to the transistor body region. The transistor body region, the lower source / drain region, and the upper source / drain region together include a plurality of transistors. The transistor and the storage element together consist of a plurality of memory cells of a memory array. Some embodiments include a method of forming an integrated assembly.

Description

[0001] Related patent data

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 62 / 814,689, filed on March 6, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] An integrated assembly having a transistor body region coupled to a carrier sink structure; and a method of forming the integrated assembly. Background Art

[0004] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read using digit lines (which may also be referred to as bit lines, data lines, sense lines, or data / sense lines) and access lines (which may also be referred to as word lines). Digit lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array.

[0005] Field effect transistors (FETs) can be used as access devices for memory cells. The transistor has a channel region (body region) between the source / drain regions. During programming operations, the source / drain regions are gate-coupled to each other through the channel region. Carriers (holes and electrons) migrate into and out of the body region. Rapid cycling (i.e., multiple read / write operations occurring in a short duration) can cause problems in which excess carriers cannot be fully discharged from the body region and therefore accumulate in the body region undesirably. As the level of integration increases, these problems become more difficult to overcome. It is desirable to develop transistors that can be used in applications that require rapid cycling of read / write operations, and which can also be extended to increasing levels of integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 , 1A 1B and 1B are views of a region of an example integrated assembly including an example memory cell. Figure 1 is a diagrammatic top view of the assembly. Figure 1A and 1B are along Figure 1 Diagrammatic cross-sectional side view of lines AA and BB. Figure 1B is along Figure 1A The line BB, and Figure 1A along Figure 1B Line AA.

[0007] Figure 2 is a diagrammatic representation of a region of an example memory array.

[0008] Figure 3 is a diagrammatic schematic diagram of an area of ​​an example assembly that includes an example two-transistor single capacitor (2T-1C) memory cell.

[0009] Figure 4 , 4A 4B are views of a region of an example integrated assembly including an example memory cell. Figure 4 is along Figure 4A and 4B Diagrammatic top cross-sectional view along line CC. Figure 4A and 4B are respectively along Figure 4 Diagrammatic cross-sectional side view of lines AA and BB. Figure 4B is along Figure 4A The line BB, and Figure 4A along Figure 4B Line AA.

[0010] Figure 5 , 5A 5B are views of a region of an example integrated assembly including an example memory cell. Figure 5 is a diagrammatic top view of the assembly. Figure 5A and 5B are respectively along Figure 5 Diagrammatic cross-sectional side view of lines AA and BB. Figure 5B is along Figure 5A The line BB, and Figure 5A along Figure 5B Line AA.

[0011] Figure 6 , 6A 6B are views of a region of an example integrated assembly including an example memory cell. Figure 6 is along Fig. 6A and 6B Diagrammatic top cross-sectional view along line CC. Fig. 6A and 6B are respectively along Figure 6 Diagrammatic cross-sectional side view of lines AA and BB. Figure 6B is along Fig. 6A The line BB, and Fig. 6A along Figure 6B Line AA.

[0012] Figure 7 is a diagrammatic cross-sectional side view of a region of an example assembly including stacked layers.

[0013] Figures 8 to 17 is a diagrammatic top view of an example construction at an example process stage of an example method for fabricating an example assembly including an example memory array. Figures 8A to 17Ais along Figures 8 to 17 Diagrammatic cross-sectional side view of line AA. Figures 8B to 17B is along Figures 8 to 17 Diagrammatic cross-sectional side view of line BB. DETAILED DESCRIPTION

[0014] Conventional transistors may be p-channel devices (i.e., may have p-type source / drain regions, and have a channel that operates to conduct holes between the p-type source / drain regions), or may be n-channel devices (i.e., may have n-type source / drain regions, and have a channel that operates to conduct electrons between the n-type source / drain regions). Some embodiments include the recognition that a problem with conventional transistors used in memory arrangements is that the body regions of such transistors are electrically floating. This may become a problem during read / write operations because the limiting factor in the cycle time of such operations may be the rate at which excess carriers are removed (drained) from the body region of the transistor (e.g., the rate at which excess holes are removed from the body region of an n-channel transistor). If excess carriers accumulate in the body region of the transistor, the threshold voltage (V T ) and shutdown current (I OFF ) may change, which may make the transistor unusable for the intended application. Some embodiments include a carrier sink that is directly coupled to the body region of the transistor to enable rapid discharge of excess charge from the body region. This can improve performance (e.g., reduce cycle time). Figures 1 to 17 Example embodiments are described.

[0015] As a preliminary matter, it should be noted that some of the figures show various different dopant levels; and the levels are distinguished by some or all of the designations p+, p, p-, n-, n, and n+. The differences in dopant concentration between the regions identified as p+, p, and p- are generally as follows. The p+ region has at least about 10 20 Atom / cm 3 The dopant concentration of the p region ranges from about 10 14 to about 10 18 Atom / cm 3 The dopant concentration of the p-region is about or less than 10 16 Atom / cm 3The regions identified as n-, n and n+ will have dopant concentrations similar to those described above for p-, p and p+ regions, respectively, except, of course, that the n region will have therein a conductivity enhancing dopant of the opposite type to the p region. It should be noted that the terms "p" and "n" may be used herein to refer to both dopant type and relative dopant concentration. It should be understood that the terms "p" and "n" refer only to dopant type and not to relative dopant concentration, except when it is explicitly stated that the terms refer to relative dopant concentration. Therefore, for the purpose of interpreting the present disclosure and the claims below, it should be understood that the terms "p-type doping" and "n-type doping" refer to the dopant type of the region rather than the relative dopant level. Therefore, a p-type doped region may be doped to any of the p+, p and p- dopant levels discussed above, and similarly, an n-type doped region may be doped to any of the n+, n and n- dopant levels discussed above.

[0016] refer to Figures 1 to 1B , with a top view ( Figure 1 ) and a pair of cross-sectional side views ( Figure 1A and 1B ) shows an area of ​​an integrated assembly (construction) 10. The construction includes a plurality of word lines (WL1, WL2, and WL3), wherein Figure 1 The word lines are shown in a dotted (i.e., phantom) view in the top view of FIG. 1 to indicate that they are beneath other materials. Each of the word lines includes a pair of conductive structures extending parallel to each other. The conductive structures of each word line are Figures 1 to 1B In other embodiments, the word lines may include only a single conductive structure, may include a wrap-around gate configuration, or may include any other suitable configuration.

[0017] The structure also includes a plurality of digital lines (DL1, DL2, DL3 and DL4), wherein Figure 1 Such digital lines are shown in a dashed (ie, phantom) view in the top view of FIG. 5 to indicate that they are beneath other material.

[0018] The digit lines may be considered to extend in a first direction (y-axis direction), and the word lines may be considered to extend in a second direction (x-axis direction), where the second direction intersects the first direction. In the embodiment shown, the second direction is substantially orthogonal to the first direction (the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances). The terms "first direction" and "second direction" are arbitrary; and in some embodiments, the x-axis direction may be referred to as the first direction, and the y-axis direction may be referred to as the second direction.

[0019] Assembly 10 includes transistors 12 arranged in an array. In some embodiments, word lines (eg, WL1) may be considered to extend along the rows of such an array, and digit lines (eg, DL1) may be considered to extend along the columns of the array.

[0020] Each of transistors 12 includes a lower (i.e., bottom) source / drain region 14 and an upper (i.e., top) source / drain region 16. In some embodiments, one of the lower and upper source / drain regions of a single transistor 12 may be referred to as a first source / drain region, while the other may be referred to as a second source / drain region. In the illustrated embodiment, source / drain regions 14 and 16 are shown as n-type doped; and therefore, transistor 12 is an n-channel device. In other embodiments, source / drain regions 14 and 16 may be p-type doped, such that transistor 12 is a p-channel device.

[0021] Each of the upper source / drain regions 16 is electrically coupled to a capacitor 15. Each of the capacitors 15 has a node coupled to a reference voltage 17. This reference voltage can be any suitable reference voltage, and in some embodiments can be ground or Vcc / 2. Capacitors 15 represent storage elements that can be used in memory cells, where the term "storage element" means any suitable device with at least two detectable states. In some embodiments, suitable storage elements can be, for example, capacitors, resistive memory devices, conductive bridge devices, phase change memory (PCM) devices, programmable metallization cells (PMCs), etc.

[0022] In the illustrated embodiment, in which the storage elements 15 are capacitors, each capacitor may be considered to include a first node 5 (relative to Figure 1A One of the capacitors is marked), a second node 7 and a capacitor dielectric material 9 between the first and second nodes.

[0023] The lower source / drain region 14 is electrically coupled to a digit line (eg, DL1 ); and in the embodiment shown directly abuts a top surface of the digit line.

[0024] Each transistor 12 has a transistor body region 18 between source / drain regions 14 and 16. In some embodiments, the upper source / drain region 16 and the body region 18 may be formed of vertically extending columns 20 of semiconductor material 22 (for simplicity of the drawings, the upper source / drain region 16 and the body region 18 may be formed of vertically extending columns 20 of semiconductor material 22). Figure 1A and 1B Only one of the pillars 20 is labeled in each of the figures. The vertically extending pillars may extend along the z-axis as shown.

[0025] The bottom source / drain region 14 extends within the line of semiconductor material 24. Semiconductor materials 22 and 24 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, and the like; wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Group III and Group V of the periodic table (wherein Group III and Group V are old nomenclature and are now referred to as Group 13 and Group 15). Semiconductor materials 22 and 24 may be the same composition as one another, or may be different compositions from one another. In some embodiments, semiconductor materials 22 and 24 may both include, consist essentially of, or consist of silicon. The junction between the source / drain regions (14, 16) and the body region (18) may be in any suitable location.

[0026] The word line (e.g., WL1) includes a conductive word line material 23. Such conductive materials may include any suitable conductive composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0027] The word line (e.g., WL1) is adjacent to the transistor body region 18; and is separated from the body region 18 by an intermediate region including a gate dielectric material (gate insulating material) 26. The gate dielectric material may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of one or more of silicon dioxide, a high-k dielectric material, and a low-k dielectric material (where the term high-k means a dielectric constant greater than that of silicon dioxide, and the term low-k means a dielectric constant lower than that of silicon dioxide). In some embodiments, the gate insulating material 26 does not include a ferroelectric material.

[0028] In operation, body region 18 includes a channel region of transistor 12, and a region of a word line adjacent to the body region serves as a transistor gate to gate-couple source / drain regions 14 and 16 to one another through the channel region. Coupling of the source / drain regions may be achieved by selectively providing voltages along the word line to induce electric fields in the channel region, wherein such electric fields cause the channel region to conductively couple source / drain regions 14 and 16 to one another.

[0029] Insulating material 30 is located above and between the word lines. Insulating material 30 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon oxide. Insulating material 30 is configured as a line extending in the same direction as the word line (e.g., WL2). Insulating material 30 separates adjacent transistor body regions 18 from each other along the y-axis direction (e.g., Figure 1B shown).

[0030] The insulating panel 32 separates adjacent transistor body regions 18 from each other along the x-axis direction ( Figure 1A ). Such panels may extend linearly in the same direction as the digit lines (e.g., DL1). Panel 32 includes insulating material 34. Insulating material 34 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon oxide.

[0031] The digit lines (eg, DL1) each include a bottom surface 33 and sidewall surfaces 35 (for simplicity of the drawing, only with respect to the sidewall surfaces 35). Figure 1A ). The digit line (eg, DL1) extends into insulating material 36. Regions of insulating material 36 are below the digit line, while other regions of insulating material 36 are along sidewall surfaces 35 of the digit line.

[0032] The carrier slot structures 38 are below the insulating material 36. In some embodiments, the digit lines (e.g., DL1) can be considered as examples of conductive structures above the carrier slot structures 38. In the embodiment shown, such conductive structures are separated from the carrier slot structures 38 by insulating regions including the insulating material 36.

[0033] The carrier slot structure can be a drain for excess carriers (e.g., holes or electrons). The transistor 12 shown is an n-channel device, and the carrier slot structure 38 shown is p-type and configured as a drain for holes. In other embodiments, the transistor can be a p-channel device, and the carrier slot structure 38 can be n-type and configured as a drain for electrons. The carrier slot structure can be doped with any suitable dopant type to any suitable dopant concentration, which enables the desired operating characteristics of the carrier slot structure to be achieved.

[0034] Carrier sink structure 38 includes semiconductor material 40. Semiconductor material 40 may include any suitable composition; including, for example, one or more of silicon, germanium, III / V semiconductor materials, semiconductor oxides (e.g., oxides including one or more of indium, gallium, and zinc), etc. Semiconductor material 40 may include the same semiconductor composition as one or both of semiconductor materials 22 and 24, or may include a different semiconductor composition relative to one or both of semiconductor materials 22 and 24. In some embodiments, semiconductor materials 22, 24, and 40 may all include, consist essentially of, or consist of silicon.

[0035] The semiconductor material 40 of the carrier channel structure 38 is shown as being doped to a p+ dopant level; and in some embodiments, may be doped to at least about 1×10 20 Atom / cm 3 concentration.

[0036] like Figure 1A As shown, an extension region (i.e., extension portion) 44 extends from the carrier slot structure 38 to the transistor body region 18 (or at least to the vertical level of the transistor body region). The extension region 44 is shown as including the same semiconductor material 40 as the carrier slot structure 38. In other embodiments, the extension region 44 may include a different semiconductor material than the carrier slot structure 38.

[0037] Extension region 44 is shown as being doped to a "p+" dopant level. In some embodiments, extension region 44 may be doped to at least about 1×10 20 Atom / cm 3 The extension region 44 has the same dopant type as the carrier slot structure 38. Thus, in some embodiments, the extension region 44 may be p-type (as shown), while in other embodiments, it may be n-type. The extension region may be doped to any suitable dopant type and concentration to achieve the desired operating characteristics.

[0038] Transistors 12 and storage elements 15 may together be considered to consist of memory cells 48; wherein such memory cells are assembled in a memory array 50. Each memory cell is uniquely addressed by a combination of one of the bit lines (e.g., DL1) and one of the word lines (e.g., WL1).

[0039] Individual memory cells 48 may be programmed (i.e., written) to a first memory state (the so-called "1" state) by operating the associated word and digit lines to store charge on capacitor 15. Individual memory cells may be programmed to a second memory state (the so-called "0" state) by operating the associated word and digit lines to discharge capacitor 15. Individual memory cells may be read by operating the associated word and digit lines to discharge any stored charge from the memory cell to a detection system to thereby determine whether the memory cell is in the first memory state or the second memory state.

[0040] In conventional memory cells, in applications where operations (i.e., write operations and / or read operations) are rapidly cycled, excess carriers (e.g., excess holes in some applications of the illustrated n-channel device) may accumulate along the body region of the transistor. In contrast, the extension 44 of the illustrated example memory cell 48 is configured to drain excess carriers from the body region 18 of the memory cell to the carrier sink structure 38, and thereby enable rapid cycling of operations associated with the memory cell.

[0041] The carrier slot structure 38 is shown coupled to a device 51 that provides the carrier slot structure 38 with appropriate electrical characteristics to enable excess carriers to easily flow from the body region 18 to the carrier slot structure. In some embodiments, the device 51 can be considered as a voltage source configured to provide a reference voltage. Depending on whether the carriers are holes or electrons, and depending on the operating parameters of the memory cell 48, the reference voltage can be grounded, greater than zero (i.e., a positive reference voltage), or less than zero (i.e., a negative reference voltage). In some embodiments, during operation of the body region coupled to region 38, the device 51 can be used to maintain a constant bias on the p+ material 40 (region 38).

[0042] The memory array 50 is supported by a base 56. The base 56 may include a semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. The base 56 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including a semiconducting material, including, but not limited to, bulk semiconducting material, such as a semiconducting wafer (alone or in an assembly including other materials) and a layer of semiconducting material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrate described above. In some applications, the base 56 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like.

[0043] A gap is provided between substrate 56 and carrier slot structure 38 to indicate that other materials and / or components may be present between substrate 56 and carrier slot structure 38. However, it should be understood that in some embodiments, semiconductor material 40 of carrier slot structure 38 may be coextensive with semiconductor material of substrate 56.

[0044] exist Figures 1 to 1B In the embodiment of the present invention, it can be considered that the digital line (for example, DL3) extends along the first direction (y-axis direction) and has a width W (for example, Figure 1A ). The lower source / drain region 14 has the same width (W) as the digit line along the cross section. The transistor body region 18 and the upper source / drain region 16 have a width W1 along the cross section, where the width W1 is greater than the width W. In some embodiments, the transistor body region 18 may be considered to include a flange region 52 (in order to simplify the drawings). Figure 1A Only two of them are marked in FIG. 5 ). The flange area 52 is along Figure 1A The cross-section of 44 extends laterally beyond the lower source / drain region 14 . The extension 44 directly contacts the underside of the transistor body region 18 along the flange region 52 .

[0045] Memory cells 48 may be considered as examples of single-transistor single-capacitor (1T-1C) devices, where each memory cell includes a single transistor 12 combined with a single capacitor 15 . Figure 2 A portion of a memory array 50 is schematically shown, and such a memory array is shown including bit lines DL1, DL2, DL3, and DL4 and word lines WL1, WL2, and WL3. Each of the memory cells 48 within the memory array is uniquely addressed by a combination of one of the word lines and one of the bit lines. The memory array may include any suitable number of memory cells 48; and in some embodiments may include hundreds, millions, tens of millions, etc. of memory cells.

[0046] In some embodiments, a method similar to Figures 1 to 1B The carrier slot structures and extensions of those in are incorporated into a two-transistor single-capacitor (2T-1C) memory cell. Figure 3An example 2T-1C memory cell configuration 54 is schematically shown in FIG. The 2T-1C configuration includes two transistors (T1 and T2) and a capacitor (CAP). The source / drain region of T1 is connected to a first node of the capacitor (CAP), while the other source / drain region of T1 is connected to a first comparison digital line (DL-C). The gate of T1 is connected to a word line (WL). The source / drain region of T2 is connected to a second node of the capacitor (CAP), while the other source / drain region of T2 is connected to a second comparison digital line DL-T. The gate of T2 is connected to a word line (WL). The comparison digital lines DL-T and DL-C extend to a sense amplifier circuit (SA), which compares the electrical characteristics (e.g., voltage) of the two to determine the memory state of the memory cell 54. The comparison digital lines DL-T and DL-C can be considered as a pair group (DL-1 / DL-C) including a true digital line (DL-T) and a complementary digital line (DL-C). The terms "true" and "complementary" are arbitrary. The electrical values ​​of the paired groups of true and complementary digit lines are used together during read / write operations of the memory cells associated with that group (eg, memory cell 54).

[0047] Figures 4 to 4B An area of ​​an example integrated assembly (configuration) 10b illustrating example 2T-1C memory cells 54a, 54b, 54c, and 54d of a memory array 55 is shown. Memory cell 54a includes first and second transistors T1a and T2a, and capacitor CAP-a. Similarly, memory cell 54b includes first and second transistors T1b and T2b, and capacitor CAP-b (where first transistor T1b and capacitor CAP-b are not in Figures 4 to 4B ); the memory cell 54c includes first and second transistors T1c and T2c, and a capacitor CAP-c; and the memory cell 54d includes first and second transistors T1d and T2d, and a capacitor CAP-d.

[0048] Capacitor CAP-a has first and second nodes 5a and 7a, respectively, and capacitor dielectric material 9a between the first and second nodes. Similarly, capacitor CAP-c has first and second nodes 5c and 7c, respectively, and capacitor dielectric material 9c between the first and second nodes; and capacitor CAP-d has first and second nodes 5d and 7d, respectively, and capacitor dielectric material 9d between the first and second nodes. Capacitor CAP-b will be similarly configured, but in Figures 4 to 4B Not shown.

[0049] The first and second transistors of each of the memory cells (e.g., the first and second transistors T1c and T2c of the memory cell 54c) can be considered together to include, in ascending order, a first source / drain region 14-1, a second source / drain region 16-1, a third source / drain region 16-2, and a fourth source / drain region 14-2. The first and second transistors also together include a first transistor body region 18-1 and a second transistor body region 18-2. The first transistor body region 18-1 and the second source / drain region 16-1 are located within a vertically extending first column 20-1; and the second transistor body region 18-2 and the third source / drain region 16-2 are located within a vertically extending second column 20-2. The first and second columns 20-1 and 20-2 may include the above reference Figures 1 to 1B The semiconductor material 22 described Figures 4 to 4B The first and fourth source / drain regions 14-1 and 14-2 may include the above-mentioned Figures 1 to 1B The semiconductor material 24 described Figures 4 to 4B (not marked in the figure).

[0050] The capacitor (eg, CAP-c) has a first node (eg, 5c) coupled to the second source / drain region 16-1, and has a second node (eg, 7c) coupled to the third source / drain region 16-2.

[0051] The assembly 10b includes a substrate 56 and a lower carrier tank structure 38L above the substrate. The first comparison digit lines DL-1T and DL-2T are above the lower carrier tank structure 38L and are separated from the lower carrier tank structure by the insulating material 36. The first source / drain region 14-1 is electrically coupled to the first comparison digit line and directly abuts the first comparison digit line in the illustrated embodiment.

[0052] The second comparison digit lines DL- 1C and DL- 2C are above the fourth source / drain region 14 - 2 and are electrically coupled to the fourth source / drain region.

[0053] The upper carrier slot structure 38U is located above the second comparison digit line and is separated from the second comparison digit line by the insulating material 36 .

[0054] The first extension region (extension) 44-1 extends upward from the lower carrier slot structure 38L to the first transistor body region 18-1, and the second extension region 44-2 extends downward from the upper carrier slot structure 38U to the second transistor body region 18-2. The first and second extension regions 44-1 and 44-2 may be configured similarly to the above with respect to Figures 1 to 1B The extension regions 44 of the embodiment described above drain excess carriers from the first and second body regions 18 - 1 and 18 - 2 .

[0055] A first word line WL1 extends along memory cells 54a and 54b; and a second word line WL2 extends along memory cells 54c and 54d. The first word line WL1 has a component adjacent to each of the body regions 18-1 and 18-2 of the memory cells selected by such word line, and similarly, the second word line WL2 has a component adjacent to each of the body regions 18-1 and 18-2 of the memory cells selected by such word line. The word lines are separated from the body regions by intervening insulating regions including gate dielectric material 26. The region of the second word line WL2 is relative to Figure 4A Shown in dashed lines (ghost image) because the area is outside the plane of the view.

[0056] The true and complementary digital lines DL-1T and DL-1C form a first paired group DL-1C / DL-1T, and the true and complementary digital lines DL-2T and DL-2C form a second paired group DL-2C / DL-2T. The digital lines (e.g., DL-1T / DL-1C) of each of the paired digital line groups are electrically coupled to a sense amplifier SA. The sense amplifier can be used to compare the electrical characteristics of the true digital line (e.g., DL-1T) with the electrical characteristics of the comparison digital line (e.g., DL-1C) during a read operation; and / or can be used to give the desired electrical characteristics to the true and complementary comparison digital lines (e.g., DL-1T and DL-1C) during a programming (i.e., writing) operation.

[0057] Figures 5 to 5B Shows an alternative to Figures 1 to 1B 1. The memory array 50a of the memory array 50 includes a 1T-1C memory cell 48a, which includes a transistor 12a combined with a capacitor 15. The transistor 12a has a Figures 1 to 1B The transistor 12 has different configurations.

[0058] Transistor 12a includes a lower (ie, bottom) source / drain region 14, an upper (ie, top) source / drain region 16, and a body region 18 between source / drain regions 14 and 16. Figure 1A In contrast to the embodiment of Figure 5A In the cross section of FIG. 1 , the width W1 of the transistor body region 18 and the upper source / drain region 16 is the same as the width W of the lower source / drain region 14 .

[0059] Word lines WL1-WL3 extend along the rows of array 50a, while digit lines DL1-DL4 extend along the columns of array 50a.

[0060] Word lines WL1 - WL3 have gate regions adjacent to body region 18 and are spaced apart from body region 18 by gate dielectric material 26 .

[0061] A dielectric material 30 is over word lines WL1 - WL3 .

[0062] The carrier sink structure 38 is below the transistor 12 and supported by the substrate 56 .

[0063] Figures 5 to 5B Examples and Figures 1 to 1B The embodiment of the present invention also differs in that insulating material 60 is provided adjacent to the sidewalls of pillar 20, and in particular along the sidewalls of transistor body region 18. Insulating material 60 may include any suitable composition; including, for example, silicon dioxide, high-k materials (aluminum oxide, zirconium oxide, hafnium oxide, etc.), etc.

[0064] The transistor body region 18 is along Figure 5A The cross-section of the embodiment has a vertically extending sidewall 19. The insulating material 60 forms an intermediate insulating region 62 that is laterally adjacent to the sidewall 19, and in the illustrated embodiment is directly adjacent to the sidewall 19. The insulating region 62 can have any suitable lateral thickness T1; for example, a lateral thickness of about to about within the range.

[0065] Extension region (extension) 44 has a portion 64 that is laterally adjacent to transistor body region 18 (i.e., vertically overlaps the transistor body region) and is separated from the transistor body region by an intermediate insulating region 62. In operation, excess carriers may tunnel (or otherwise migrate) from body region 18, through intermediate insulating region 62 and into extension 44 to be exhausted from the body region. The migration of excess carriers is Figure 5A This is illustrated in FIG. 6 by dashed line 65. Portion 64 has sufficient overlap with the bulk region to enable excess carriers to be pumped out of the bulk region.

[0066] In the illustrated embodiment, insulating material 66 is disposed over extension 44. Insulating material 66 may include the same composition as material 60, or a different composition than material 60. Insulating materials 30, 60, and 66 may include the same composition as one another, or at least one of the materials may include a different composition relative to at least one other of the materials.

[0067] In some embodiments, Figures 5 to 5B The extension 44 may be provided between adjacent digit lines (eg, between adjacent digit lines DL1 and DL2, such as Figure 5A ) provides the added benefit of shielding.

[0068] Figures 5 to 5BThe configuration may be modified to incorporate a configuration similar to that of the above reference Figures 4 to 4B The 2T-1C memory cell described. Figures 6 to 6B An area of ​​an example integrated assembly (configuration) 10d illustrating example 2T-1C memory cells 54e, 54f, 54g, and 54h of a memory array 55a is shown. Memory cell 54e includes first and second transistors T1e and T2e, and capacitor CAP-e. Similarly, memory cell 54f includes first and second transistors T1f and T2f, and capacitor CAP-f (where first transistor T1f and capacitor CAP-f are not in Figures 6 to 6B ); the memory cell 54g includes first and second transistors T1g and T2g, and a capacitor CAP-g; and the memory cell 54h includes first and second transistors T1h and T2h, and a capacitor CAP-h.

[0069] Capacitor CAP-e has first and second nodes 5e and 7e, respectively, and capacitor dielectric material 9e between the first and second nodes. Similarly, capacitor CAP-g has first and second nodes 5g and 7g, respectively, and capacitor dielectric material 9g between the first and second nodes; and capacitor CAP-h has first and second nodes 5h and 7h, respectively, and capacitor dielectric material 9h between the first and second nodes. Capacitor CAP-f will be similarly configured, but in Figures 6 to 6B Not shown.

[0070] The first and second transistors of each of the memory cells (e.g., the first and second transistors T1g and T2g of the memory cell 54g) can be considered together to include, in ascending order, a first source / drain region 14-1, a second source / drain region 16-1, a third source / drain region 16-2, and a fourth source / drain region 14-2. The first and second transistors also together include a first transistor body region 18-1 and a second transistor body region 18-2. The first transistor body region 18-1 and the second source / drain region 16-1 are located within a vertically extending first column 20-1; and the second transistor body region 18-2 and the third source / drain region 16-2 are located within a vertically extending second column 20-2. The first and second columns 20-1 and 20-2 may include the above reference Figures 1 to 1B The semiconductor material 22 described Figures 6 to 6B The first and fourth source / drain regions 14-1 and 14-2 may include the above-mentioned Figures 1 to 1B The semiconductor material 24 described Figures 6 to 6B (not marked in the figure).

[0071] The capacitor (eg, CAP-c) has a first node (eg, 5c) coupled to the second source / drain region 16-1, and has a second node (eg, 7c) coupled to the third source / drain region 16-2.

[0072] The assembly 10d includes a substrate 56 and a lower carrier tank structure 38L above the substrate. The first comparison digit lines DL-1T and DL-2T are above the lower carrier tank structure 38L and are separated from the lower carrier tank structure by the insulating material 36. The first source / drain region 14-1 is coupled to the first comparison digit line and directly abuts the first comparison digit line in the illustrated embodiment.

[0073] The second comparison digit lines DL- 1C and DL- 2C are above the fourth source / drain region 14 - 2 and coupled to the fourth source / drain region.

[0074] The upper carrier slot structure 38U is located above the second comparison digit line and is separated from the second comparison digit line by the insulating material 36 .

[0075] The first extension region (extension) 44-1 extends upward from the lower carrier slot structure 38L to vertically overlap the first transistor body region 18-1, and the second extension region 44-2 extends downward from the upper carrier slot structure 38U to vertically overlap the second transistor body region 18-2. The first and second extension regions 44-1 and 44-2 may be configured similarly to the above with respect to Figures 5 to 5B The extension region 44 in the embodiment of the present invention drains excess carriers from the first and second body regions 18-1 and 18-2 in the manner described. The extension region 44-1 can be considered to be separated from the body region 18-1 by the first intermediate insulating region 62-1, and the extension region 44-2 can be considered to be separated from the body region 18-2 by the second intermediate insulating region 62-2.

[0076] A first word line WL1 extends along memory cells 54e and 54f; and a second word line WL2 extends along memory cells 54g and 54h. The first word line WL1 has a component adjacent to each of the body regions 18-1 and 18-2 of the memory cells gated by such word line, and similarly, the second word line WL1 has a component adjacent to each of the body regions 18-1 and 18-2 of the memory cells gated by such word line. The word lines are separated from the body regions by gate dielectric material 26.

[0077] The true and complementary digital lines DL-1T and DL-1C form a first pair group DL-1C / DL-1T, and the true and complementary digital lines DL-2T and DL-2C form a second pair group DL-2C / DL-2T. The digital lines of each group in the paired digital line groups (e.g., DL-1T / DL-1C) are electrically coupled to the sense amplifier SA.

[0078] In some embodiments, Figure 1 and 4 The memory array of 6 can be in a memory layer (ie, memory level) that is in a vertically stacked arrangement of layers (or levels). For example, Figure 7 A portion of an integrated assembly 10e is shown that includes a vertically stacked arrangement of layers 1 to 4. The vertically stacked arrangement can be extended upward to include additional layers. Layers 1 to 4 can be considered as examples of layers stacked one on top of another. The layers can be within different semiconductor dies (wafers), or at least two of the layers can be within the same semiconductor die. The bottom layer (layer 1) can include control circuitry and / or sensing circuitry (and in some embodiments can include CMOS circuitry). The upper layers (layers 2 to 4) can include memory arrays, such as Figure 1 and 4 6. The memory arrays in different layers may be identical to each other (e.g., may all be DRAM arrays), or may be different from each other. Moreover, one or more of the upper layers may include control circuits or other logic circuits. Circuits in one of the layers may be electrically coupled to circuits in another layer vertically offset from the layer. For example, circuits in a memory layer may be coupled to control circuits in a bottom layer. In some example embodiments, word lines in a memory layer may be electrically coupled to word line driver circuits in a bottom layer. In some example embodiments, bit lines in a memory layer may be electrically coupled to sense amplifier circuits in a bottom layer.

[0079] Figure 1 and 4 The integrated assembly of 6 may be formed by any suitable process. Figures 8 to 17 Shown is the method for forming Figures 1 to 1B An instance of an assembly is handled by.

[0080] refer to Figures 8 to 8B , the assembly 10 is shown in an initial processing stage. Figures 8 to 8B The assembly 10 includes semiconductor material 40, insulating material 36, conductive digit line material 70, and semiconductor material 24 of carrier sink structure 38. In some embodiments, materials 40, 36, 70, and 24 may be considered to be within a stack 72. In some embodiments, such a stack may be considered to include, in ascending order, a first semiconductor material 40, insulating material 36, conductive digit line material 70, and a second semiconductor material 24.

[0081] Semiconductor materials 40 and 24 are shown as p-type doped and n-type doped, respectively, to ultimately form the semiconductor materials described above with reference to Figures 1 to 1B However, it should be understood that in other embodiments, the dopant types of materials 40 and 24 can be reversed, so that material 40 is n-type doped and material 24 is p-type doped. Material 24 is appropriately doped for the lower source / drain region 14 ( Figures 1 to 1B ).

[0082] Digit line material 70 may include any suitable conductive composition such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, the digit line material will include a metal (e.g., one or more of titanium, titanium nitride, titanium silicide, tungsten, tungsten nitride, tungsten silicide, etc.) and will be referred to as a metal-containing digit line material.

[0083] exist Figures 8 to 8B The carrier slot structure 38 is not shown as being coupled to the device 51 (see above). Figures 1 to 1B In some embodiments, the Figures 8 to 8B This coupling may exist at a processing stage of the embodiment, and in other embodiments, this coupling may be provided at a later processing stage.

[0084] exist Figures 8 to 8B The processing stages are not shown above with reference to Figures 1 to 1B A substrate 56 is depicted to simplify the drawing, but it is understood that such a substrate may be present.

[0085] refer to Figures 9 to 9B , materials 36, 70 and 24 are patterned into tracks 74 extending in the y-axis direction. The materials may be patterned using any suitable method. For example, a mask (not shown) may be provided on the structure 10 to define the location of the tracks, then one or more suitable etches may be used to pattern the tracks, and finally the mask may be removed to leave Figures 9 to 9B In some embodiments, Figures 9 to 9B At least a portion of the mask may remain during the processing stage to protect the upper surface of semiconductor material 24 during subsequent processing stages.

[0086] Tracks 74 are separated from each other by gaps 76. Gap 76 extends to and exposes upper surface 41 of semiconductor material 40. In some embodiments, the exposed upper surface of material 40 can be considered to be along the bottom periphery of gap 76.

[0087] The formation of tracks 74 patterns digit line material 70 into digit lines DL1 , DL2 , DL3 , and DL4 ; and patterns semiconductor material 24 into lower source / drain regions 14 .

[0088] refer to Figures 10 to 10B , insulating spacers 75 are formed along the sidewalls of the track 70. The insulating spacers include an insulating material 36. In some embodiments, the insulating spacers 75 may be referred to as first insulating spacers to distinguish them from other insulating spacers formed in subsequent process steps.

[0089] Insulating spacers 75 may be formed using any suitable process. For example, a layer of material 36 may be provided to extend over rails 74 , along the sidewalls of the rails, and across gaps 76 ; and then this layer may be anisotropically etched to form spacers 75 .

[0090] refer to Figures 11 to 11B The semiconductor extension 44 (ie, the extension region) is formed along the insulating spacer 75 . The semiconductor extension 44 includes the semiconductor material 40 .

[0091] Semiconductor extensions 44 may be formed using any suitable process. For example, a layer of semiconductor material 40 may be provided to extend over rails 74, along the sidewalls of spacers 75 and across gaps 76; and then this layer may be anisotropically etched to form semiconductor extensions 44 as shown.

[0092] Semiconductor extension 44 may be doped with any suitable dopant type and concentration; Figures 1 to 1B Example dopant types and concentrations are discussed.

[0093] Semiconductor extension 44 and spacer 75 narrow gap 76 .

[0094] refer to Figures 12 to 12B , the insulating spacers 80 are formed in the narrowed gaps 76 (these narrowed gaps are Fig.11A ). The insulating spacer 80 may be referred to as a second spacer to distinguish it from the first insulating spacer 75.

[0095] The insulating spacer 80 includes the insulating material 34 .

[0096] Planarized surface 81 is formed to extend across rail 74, first insulating spacer 75, semiconductor extension 44, and second insulating spacer 80. Planarized surface 81 may be formed using any suitable process; and in some embodiments, may be formed using chemical mechanical polishing (CMP).

[0097] refer to Figures 13 to 13B, semiconductor material 22 is formed above and directly against planarized surface 81. Semiconductor material 22 may include the same Figures 1 to 1B The same composition described above. In some embodiments, semiconductor material 22 may be referred to as a third semiconductor material to distinguish it from first semiconductor material 40 and second semiconductor material 24. In some embodiments, the first, second, and third semiconductor materials may all include the same composition as each other. For example, the first, second, and third semiconductor materials may all include silicon. In other embodiments, at least one of the first, second, and third semiconductor materials may include a different composition relative to another of the first, second, and third semiconductor materials (for example, one may include silicon and the other may include germanium or a semiconductor oxide).

[0098] In the embodiment shown, the upper region of the semiconductor material 22 is doped with the dopant of the upper source / drain region 16; Figures 1 to 1B Such upper source / drain regions are discussed. The dopant within the upper source / drain region 16 is shown as an n-type dopant, but may be a p-type dopant in other embodiments.

[0099] refer to Figures 14 to 14B , a slit 84 is formed to extend through the third semiconductor material 22 to the insulating spacer 80. The slit extends linearly along the y-axis direction.

[0100] Slits 84 may be formed using any suitable process. For example, a patterned mask (not shown) may be provided over structure 10 to define the location of the slits, the slits may then be etched through material 22 using a suitable etch, and the mask may then be removed to leave the slits. Figures 14 to 14B The structure shown.

[0101] refer to Figures 15 to 15B , the insulating panel 32 is formed in the slit 84 ( Figures 14 to 14B ). The insulating panel 32 includes an insulating material 34 .

[0102] The insulating panel 32 may include silicon dioxide. In some embodiments, the insulating material 36, the first insulating spacer 75 ( Fig. 10A )、Second insulating spacer 80( Fig. 12A ) and the insulating panel 32 may both include the same composition as each other (eg, silicon dioxide). In some embodiments, the insulating material 36, the first insulating spacer 75 ( Fig. 10A )、Second insulating spacer 80( Fig. 12A ) and at least one of the insulating panel 32 is relative to the insulating material 36, the first insulating spacer 75 ( Fig. 10A )、Second insulating spacer 80( Fig. 12A) and another different composition in the insulating panel 32.

[0103] refer to Figures 16 to 16B A trench 90 is formed to extend through the third semiconductor material 22 and the insulating panel 32. The trench 90 extends along the x-axis direction.

[0104] Grooves 90 may be formed using any suitable process. For example, a patterned mask (not shown) may be provided over structure 10 to define the locations of grooves 90; one or more etches may be used to form the grooves within the defined locations; and then, the mask may be removed to leave Figures 16 to 16B The structure shown.

[0105] The trenches 90 pattern the semiconductor material 22 to the Figures 1 to 1B The transistor body region 18 is depicted, and the upper source / drain regions 16 are formed (patterned).

[0106] refer to Figures 17 to 17B , a gate dielectric material 26 and a conductive word line material 23 are formed and patterned in the trench 90 (wherein Figures 16 to 16B Such grooves are shown in FIG. Figures 1 to 1B The structure described above. Any suitable process now known or yet to be developed can be used to form and pattern the materials in the trenches. A person of ordinary skill will readily recognize that the gate dielectric material 26 and the conductive word line material 23 can be formed into a similar Figures 17 to 17B A conventional method for the structure described in or a structure substantially the same as that described in .

[0107] The word line material 23 is formed as described above. Figures 1 to 1B Word lines WL1, WL2, and WL3 are described.

[0108] An insulating material 30 is formed over and around the word lines WL1 , WL2 , and WL3 .

[0109] In subsequent processing, capacitor 15 (or other suitable storage element) may be formed over and electrically connected to source / drain region 16 to form the above referenced Figures 1 to 1B A memory array 50 is described.

[0110] The assemblies and structures discussed above may be used within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, for memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0111] Unless otherwise stated, the various materials, substances, compositions, etc. described herein may be formed by any suitable method, whether now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0112] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In this disclosure, these terms are considered synonymous. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language variation within the disclosure to simplify the premise basis within the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0113] Both the terms "electrically connected" and "electrically coupled" may be used in the present disclosure. These terms are considered synonyms. The use of one term in some cases and another term in other cases may provide language variation within the present disclosure to simplify the premise basis within the appended claims.

[0114] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or is rotated relative to this orientation.

[0115] To simplify the drawings, the cross-sectional views of the drawings show only the features within the plane of the cross-section and do not show material behind the plane of the cross-section unless otherwise indicated.

[0116] When a structure is referred to above as being "on another structure," "adjacent to another structure," or "against another structure," it may be directly on the other structure, or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0117] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may extend substantially orthogonally relative to an upper surface of the base, or may extend non-orthogonally.

[0118] Some embodiments include an integrated assembly having a carrier slot structure and having a digit line above the carrier slot structure. A transistor body region is located above the digit line. An extension extends from the carrier slot structure to the transistor body region (or at least to a vertical level of the transistor body region). The extension is configured to drain excess carriers from the transistor body region. A lower source / drain region is located between the transistor body region and the digit line and is coupled to the digit line. An upper source / drain region is above the transistor body region and is coupled to a storage element. A word line is adjacent to the transistor body region. The transistor body region, the lower source / drain region, and the upper source / drain region together include a plurality of transistors. The transistor and the storage element together consist of a plurality of memory cells of a memory array.

[0119] Some embodiments include an integrated assembly having a lower carrier slot structure, a first comparison digital line above the lower carrier slot structure, and a first source / drain region above the first digital line and coupled to the first digital line. A vertically extending first column is located above the first source / drain region. Each of the first columns includes a first transistor body region and a second source / drain region. A capacitor is coupled to the second source / drain region. A vertically extending second column is located above the capacitor. Each of the second columns includes a third source / drain region and a second transistor body region above the third source / drain region. The third source / drain region is coupled to a second capacitor node. A fourth source / drain region is located above the second transistor body region. A second comparison digital line is located above the fourth source / drain region and coupled to the fourth source / drain region. In a plurality of first / second comparison digital line groups, individuals of the first comparison digital lines are paired with individuals of the second comparison digital lines. The comparison first and second digit lines of each of the first / second comparison digit line groups extend to a sense amplifier, which is configured to compare electrical characteristics of the first and second comparison digit lines within the first / second comparison digit line group. An upper carrier slot structure is located above the second digit line. A first extension extends from the lower carrier slot structure to the first transistor body region. The first extension is configured to drain excess carriers from the first transistor body region. A second extension extends from the upper carrier slot structure to the second transistor body region. The second extension is configured to drain excess carriers from the second transistor body region. The word line has components adjacent to the first and second transistor body regions.

[0120] Some embodiments include a method of forming an integrated assembly. A stack is formed to include, in ascending order, a first semiconductor material, an insulating material, a digit line material, and a second semiconductor material. The first semiconductor material is p-type doped or n-type doped, and the second semiconductor material is the other of p-type doped and n-type doped. The insulating material, the digit line material, and the second semiconductor material are patterned into tracks extending along a first direction. The tracks are spaced apart from each other by gaps. An area of ​​the first semiconductor material is exposed along a bottom periphery of the gap. The track has a sidewall along the gap. The patterned digit line material within the track is a digit line. A first insulating spacer is formed along the sidewall of the track. A semiconductor extension is formed along the first insulating spacer. The semiconductor extension and the first insulating spacer narrow the gap. A second insulating spacer is formed within the narrowed gap. A planarized surface is formed to extend across the track, the first insulating spacer, the semiconductor extension, and the second insulating spacer. A third semiconductor material is formed above the planarized surface and directly against the planarized surface. A slit is formed to extend through the third semiconductor material to the second insulating spacer. The slit extends linearly along the first direction. An insulating panel is formed within the slit. A trench is formed to extend through the third semiconductor material and the insulating panel. The trench extends in a second direction intersecting the first direction. The trench patterns the third semiconductor material into a column including a transistor body region. The second semiconductor material includes a first source / drain region below the transistor body region. A gate dielectric material is formed along the sidewalls of the transistor body region. A word line is formed along the gate dielectric material. The word line extends in the second direction. A second source / drain region is formed in an upper region of the column. A storage element is coupled to the second source / drain region. The first source / drain region, the second source / drain region, and the transistor body region are incorporated into an access transistor together. The access transistor and the storage element are incorporated into a memory cell of a memory array. The extension is configured to discharge excess carriers from the transistor body region to the first semiconductor material during operation of the memory cell.

[0121] In accordance with the statute, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims are to be given their full scope literally and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: Carrier slot structure; a digit line above the carrier slot structure; a transistor body region above the digit line; an extension extending from the carrier trough structure to at least a vertical level of the transistor body region; the extension being configured to drain excess carriers from the transistor body region to the carrier trough structure; a lower source / drain region between the transistor body region and the digit line; the lower source / drain region coupled to the digit line; an upper source / drain region above the transistor body region; a storage element coupled to the upper source / drain region; a gate adjacent to a body region of the transistor; as well as The transistor body region, the lower source / drain region and the upper source / drain region together comprise a plurality of transistors; the transistors and the storage elements together comprise a plurality of memory cells of a memory array. 2 . The integrated assembly of claim 1 , wherein the current carrier slot structure is coupled to a voltage source configured to provide a reference voltage to the current carrier slot structure.

3. The integrated assembly of claim 2, wherein the carrier sink structure is maintained at a constant bias voltage during operation of the transistor body region.

4. The integrated assembly of claim 1 wherein the transistor body region is within a vertically extending semiconductor pillar.

5. The integrated assembly of claim 1 , wherein the digit line extends along a first direction; and wherein the lower source / drain region, the transistor body region, and the upper source / drain region all have the same width as one another along a cross-section orthogonal to the first direction.

6. An integrated assembly according to claim 1, wherein the digit line extends along a first direction; and wherein the lower source / drain region has a different width relative to the transistor body region and the upper source / drain region along a cross-section orthogonal to the first direction.

7. The integrated assembly of claim 1, wherein the storage element is a capacitor.

8. The integrated assembly of claim 7, wherein the memory cell is a single transistor single capacitor (1T-1C) memory cell.

9. The integrated assembly of claim 7, wherein the memory cell is a two-transistor single capacitor (2T-1C) memory cell.

10. The integrated assembly of claim 1, wherein the carrier sink structure is of p-type.

11. The integrated assembly of claim 1, wherein the carrier sink structure is n-type.

12. The integrated assembly of claim 1, wherein the carrier sink structure comprises a p-type dopant or an n-type dopant doped to at least 1×10 20 Atom / cm 3 The concentration of silicon.

13. The integrated assembly of claim 12, wherein the extension comprises a doped portion with the p-type dopant or the n-type dopant to at least 1×10 20 Atom / cm 3 The concentration of silicon.

14. The integrated assembly of claim 1, wherein the extension directly contacts the transistor body region.

15. An integrated assembly according to claim 14, wherein: The digital line has a width along a cross section; The transistor body region has a flange region along the cross section, wherein the flange region extends outwardly beyond the width and has a lower side; and The extension directly contacts the underside of the flange area.

16. The integrated assembly of claim 1, wherein the extension is spaced apart from the transistor body region by an intermediate insulating region.

17. An integrated assembly according to claim 16, wherein: The transistor body region has vertically extending sidewalls; The portion of the extension is a laterally adjacent region of the vertically extending sidewall; and The intermediate insulating region is located between the portion of the extension and the vertically extending sidewall.

18. The integrated assembly of claim 16, wherein the intermediate insulating region comprises silicon dioxide.

19. The integrated assembly of claim 16, wherein the intermediate insulating region comprises a high-k material.

20. The integrated assembly of claim 16, wherein the intermediate insulating region has a length from arrive Thickness within the range.

21. The integrated assembly of claim 1 wherein the memory array is within a layer; the layer is within a vertically stacked arrangement of layers and above at least one other of the layers within the vertically stacked arrangement.

22. An integrated assembly comprising: A lower carrier slot structure; a first comparison digit line above the lower carrier slot structure; a first source / drain region over and coupled to the first comparison digit line; vertically extending first pillars above the first source / drain regions; each of the first pillars comprising a first transistor body region and a second source / drain region; a capacitor coupled to the second source / drain region; a second vertically extending column above the capacitor; each of the second columns comprising a third source / drain region and a second transistor body region above the third source / drain region; the third source / drain region being coupled to a second node of the capacitor; a fourth source / drain region over the second transistor body region; a second comparison digital line over and coupled to the fourth source / drain region; an individual of the first comparison digital line is paired with an individual of the second comparison digital line in a plurality of first / second comparison digital line groups; the first and second comparison digital lines of each of the first / second comparison digital line groups extend to a sense amplifier configured to compare electrical characteristics of the first and second comparison digital lines within the first / second comparison digital line group; an upper carrier slot structure above the second comparison digit line; a first extension extending from the lower carrier slot structure to the first transistor body region; Said a first extension configured to drain excess carriers from the first transistor body region to the lower carrier sink structure; a second extension extending from the upper carrier slot structure to the second transistor body region; The second extension is configured to drain excess carriers from the second transistor body region to the upper carrier sink structure; as well as A gate has components adjacent to the first and second transistor body regions.

23. The integrated assembly of claim 22, wherein the upper and lower current carrier slot structures are coupled to a voltage source configured to provide a reference voltage to the upper and lower current carrier slot structures.

24. The integrated assembly of claim 22, wherein the capacitor, first pillar, and second pillar together consist of a two-transistor single-capacitor memory (2T-1C) memory cell of a memory array.

25. The integrated assembly of claim 24, wherein the memory array is within a layer; the layer is within a vertically stacked arrangement of layers and is above at least one other of the layers within the vertically stacked arrangement.

26. The integrated assembly of claim 22, wherein the upper and lower carrier sink structures are p-type.

27. The integrated assembly of claim 22, wherein the upper and lower carrier sink structures are n-type.

28. The integrated assembly of claim 22, wherein the first extension directly contacts the first transistor body region; and wherein the second extension directly contacts the second transistor body region.

29. The integrated assembly of claim 22, wherein the first extension is spaced apart from the first transistor body region by a first intermediate insulating region; and wherein the second extension is spaced apart from the second transistor body region by a second intermediate insulating region.

30. A method of forming an integrated assembly, comprising: forming a stack comprising, in ascending order, a first semiconductor material, an insulating material, a digit line material, and a second semiconductor material; The first semiconductor material is p-type doped or n-type doped, and the second semiconductor material is the other of p-type doped and n-type doped; patterning the insulating material, the digit line material, and the second semiconductor material into tracks extending in a first direction; The rails are spaced apart from each other by gaps; A region of the first semiconductor material is exposed along a bottom periphery of the gap; The track has sidewalls along the gap; the patterned digit line material within the track is a digit line; forming a first insulating spacer along the sidewall of the track; forming a semiconductor extension along the first insulating spacer; the semiconductor extension and the first insulating spacer narrowing the gap; forming a second insulating spacer in the narrowed gap; forming a planarized surface extending across the track, the first insulating spacer, the semiconductor extension, and the second insulating spacer; forming a third semiconductor material over and directly against the planarized surface; forming a slit extending through the third semiconductor material to the second insulating spacer; The slit extends linearly along the first direction; forming an insulating panel within the slit; forming a trench extending through the third semiconductor material and the insulating panel; The groove extends along a second direction intersecting the first direction; The trench patterns the third semiconductor material into a pillar including a transistor body region; the second semiconductor material includes a first source / drain region below the transistor body region; forming a gate dielectric material along sidewalls of the transistor body region; forming a word line along the gate dielectric material; The word line extends along the second direction; forming a second source / drain region in an upper region of the pillar; forming a storage element coupled to the second source / drain region; wherein the first source / drain region, the second source / drain region and the transistor body region are together incorporated into an access transistor; wherein the access transistor and the storage element are incorporated into a memory cell of a memory array; and Wherein the extension is configured to drain excess carriers from the transistor body region to the first semiconductor material during operation of the memory cell.

31. The method of claim 30, wherein the storage element is a capacitor.

32. The method of claim 30, wherein the gate dielectric material consists of silicon dioxide.

33. The method of claim 30, wherein the insulating material, the first insulating spacer, the second insulating spacer, and the insulating panel are the same composition as one another.

34. The method of claim 33, wherein the insulating material, the first insulating spacer, the second insulating spacer, and the insulating panel all comprise silicon dioxide.

35. The method of claim 30, wherein at least one of the insulating material, the first insulating spacer, the second insulating spacer, and the insulating panel is a different composition relative to another one of the insulating material, the first insulating spacer, the second insulating spacer, and the insulating panel.

36. The method of claim 30, wherein the first, second, and third semiconductor materials are the same composition as one another.

37. The method of claim 36, wherein the first, second and third semiconductor materials comprise silicon.

38. The method of claim 30, wherein at least one of the first, second, and third semiconductor materials is a different composition than at least another of the first, second, and third semiconductor materials.

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