Semiconductor devices

Abstract

This invention provides a semiconductor device with a higher degree of freedom in monitoring functionality. The semiconductor device includes: a functional unit that executes a predetermined process based on a start signal sent from an external device and outputs a completion signal upon completion of the predetermined process; a first timing unit that monitors a first anomaly during the predetermined process based on the start signal and the completion signal; and a branch pair, including: a first branch that branches the start signal to the functional unit and the first timing unit, and a second branch that branches the completion signal to the first timing unit and the external device.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] In semiconductor devices, there are cases where monitoring functions are included as needed. Furthermore, as one method of implementing the monitoring function, the use of a timer is known. For example, the semiconductor device disclosed in Patent Document 1 is known as a semiconductor device equipped with a monitoring function implemented by a timer. The semiconductor device disclosed in Patent Document 1 includes an anomaly detection block comprising a detection circuit, a detection signal setting circuit, a determination circuit, and a timer. In the anomaly detection block of Patent Document 1, the detection circuit, which is instructed by the detection signal setting circuit to detect a signal change, outputs a pulse when the signal obtained from the input / output port undergoes the signal change. The timer specifies the period for monitoring the occurrence of a signal state that is detected as abnormal by setting a value in an anomaly detection control register. The determination circuit determines whether a signal state that should be detected as abnormal has occurred based on whether a detection pulse is generated by the detection circuit before the timer expires. In the semiconductor device of Patent Document 1, a dedicated timer is provided for each of the multiple anomaly detection blocks.

[0003] In the prior art, a circuit that operates based on a specified function (hereinafter referred to as a "functional circuit") is connected to another functional circuit, and the connection between the other functional circuits is also set to one, not multiple. Therefore, if it is necessary to monitor, for example, the operating time of this functional circuit during its operation, this is achieved by embedding a dedicated monitoring circuit in the functional circuit. Figure 7 This section describes an example of a semiconductor device 50 having the functions described above. The semiconductor device 50 is a structure that controls a series of operations in multiple functional circuits via timing circuits.

[0004] like Figure 7 As shown, the semiconductor device 50 includes a connection switching circuit 51, a functional circuit 52, and a timing circuit 53. The functional circuit 52 is a circuit that operates based on a predetermined function and includes a dedicated timer 55 for each functional circuit. The timing circuit 53 is a circuit that controls the execution of a series of actions (hereinafter referred to as "timing") of the multiple functional circuits included in the semiconductor device 50, generates a start signal for each functional circuit, and receives completion signals from each functional circuit. The connection switching circuit 51 includes selectors 54-1 and 54-2. Selector 54-1 distributes the start signal sent from the timing circuit 53 to each functional circuit, and selector 54-2 centrally sends the completion signals from each functional circuit to the timing circuit 53. Furthermore, the processes included in the timing are not limited to being executed by different multiple functional circuits 52, but also include cases where a single functional circuit 52 executes the function multiple times.

[0005] [Existing Technical Documents]

[0006] [Patent Literature]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2010-250581 Summary of the Invention

[0008] [The problem the invention aims to solve]

[0009] Here, in the semiconductor device of Patent Document 1 or the semiconductor device 50 of the comparative example, since a monitoring circuit is mounted on each functional circuit, it is only necessary to mount a monitoring circuit equal to the number of functional circuits. However, depending on the application of the semiconductor device, there are cases where not all of the mounted functions are used, but only a portion of the functions. In cases where the required application can be achieved using only a portion of the functions as described above, the monitoring circuit mounted for the unused functional circuits is wasted. This results in unnecessary constraints on the circuit configuration of the semiconductor device 50 and increases costs. On the other hand, if a dedicated monitoring circuit is not mounted in advance to reduce the number of monitoring circuits, it is impossible to monitor specific functions. Therefore, in the event of a fault or abnormal operation related to this function, it is impossible to notify the upper system or restore the function through some form of avoidance or switching.

[0010] Based on the aforementioned circumstances, the present invention aims to provide a semiconductor device with a higher degree of freedom in monitoring functions.

[0011] [Technical means to solve the problem]

[0012] To address the aforementioned issues, the semiconductor device of the present invention includes: a functional unit that performs a predetermined process upon receiving a start signal from an external device and outputs a completion signal upon completion of the predetermined process; a first timing unit that monitors a first anomaly in the predetermined process based on the start signal and the completion signal; and a branch pair, including: a first branch that branches the start signal and sends it to the functional unit and the first timing unit, and a second branch that branches the completion signal and sends it to the first timing unit and the external device.

[0013] [The effects of the invention]

[0014] According to the present invention, the following effect is achieved: a semiconductor device with a higher degree of freedom in monitoring functions can be provided. Attached Figure Description

[0015] Figure 1 This is a block diagram illustrating an example of the structure of the semiconductor device according to the first embodiment.

[0016] Figure 2This is a block diagram illustrating other forms of the semiconductor device in an embodiment.

[0017] Figure 3 This is a flowchart illustrating the operation of the semiconductor device according to the first embodiment.

[0018] Figure 4 This is a block diagram illustrating an example of the structure of the semiconductor device according to the second embodiment.

[0019] Figure 5 This is a block diagram illustrating an example of the structure of the semiconductor device according to the third embodiment.

[0020] Figure 6 This is a block diagram illustrating an example of the structure of the semiconductor device according to the fourth embodiment.

[0021] Figure 7 This is a block diagram showing the structure of the semiconductor device in the comparative example.

[0022] [Explanation of Symbols]

[0023] 1: Microcomputer

[0024] 2: CPU

[0025] 3: Functional Department

[0026] 10, 10A, 10B, 10C: Semiconductor devices

[0027] 11-1~11-3: Connect the switching circuit

[0028] 12, 12-1~12-5: Timers

[0029] 13. 13-1~13-4: Functional Circuits

[0030] 14, 14-1~14-17: Selectors

[0031] 15-1~15-3: Sequential Circuits

[0032] 16: Register

[0033] 17-1, 17-2: Branch offices

[0034] 18-1, 18-2: Branch offices

[0035] 50: Semiconductor devices

[0036] 51: Connection switching circuit

[0037] 52: Functional Circuit

[0038] 53: Sequential Circuits

[0039] 54-1, 54-2: Selectors

[0040] 55: Dedicated timer for functional circuits Detailed Implementation

[0041] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0042] [First Implementation Method]

[0043] Reference Figures 1 to 3 The semiconductor device of this embodiment will be described. Figure 1 This illustrates an example of the structure of the semiconductor device 10 in this embodiment. For example... Figure 1 As shown, the semiconductor device 10 includes a functional circuit 13-1 (hereinafter collectively referred to as "functional circuit 13"), a connection switching circuit 11-1, and a timer 12-1 (hereinafter collectively referred to as "timer 12").

[0044] Functional circuit 13-1 is a circuit in semiconductor device 10 that operates based on a predetermined function. It starts operating this function according to a start signal and outputs a completion signal when the operation is completed. Figure 1 Although only one example is shown, this embodiment may include multiple functional circuits 13-1. Timer 12-1 is a timing circuit that starts counting (timing) using a start trigger and ends counting and resets using an end trigger. Timer 12-1 uses a start signal as the start trigger and a finish signal as the end trigger. In this embodiment, Timer 12-1 is a general-purpose timer that is not part of a specific functional circuit 13-1. There may also be multiple Timer 12-1s. Examples of specific functional circuits 13-1 generally include: analog-to-digital converters, digital-to-analog converters, comparators, pulse modulation circuits, communication circuits, and other circuits expected to end within a predetermined time after starting operation.

[0045] On the other hand, in order to enable timer 12-1 to function as a monitoring circuit, a threshold time can be set as an upper limit for the timing duration in timer 12-1. For example, it can be configured such that, if a predetermined upper limit can be set for the running time from the start of operation of functional circuit 13-1 to its completion, functional circuit 13-1 is associated with timer 12-1, and if the timed running time exceeds this threshold time, a completion interrupt is output from timer 12-1. The threshold time can be set by multiplying, for example, the time required for normal processing by a predetermined tolerance factor (e.g., 1.5). The completion interrupt is a signal indicating that an abnormality has been detected in functional circuit 13-1.

[0046] The connection switching circuit 11-1 distributes the start signal to the functional circuit 13-1 and the timer 12-1, and distributes the completion signal to the timer 12-1 and the external device. Therefore, it includes branch sections 17-1 and 18-1, selector 14-1, selector 14-2, selector 14-3, and selector 14-4 (hereinafter collectively referred to as "selector 14"). The connection switching circuit 11-1 also includes a register 16, and selector 14 controls the switching by register settings set by register 16 according to a setting signal.

[0047] In the semiconductor device 10 of this embodiment, as an example, a start signal for activating the functional circuit 13-1 and the timer 12-1 is input from an external device, and a completion signal output by the functional circuit 13-1 is output to the external device. The external device is not particularly limited. Figure 2 An example of an external device is shown in the figure. Figure 2 An example is shown in which the semiconductor device 10 of this embodiment is configured as part of the microcomputer 1. For example... Figure 2 As shown, the microcomputer 1 includes a central processing unit (CPU) 2 and a functional unit 3, and the semiconductor device 10 is configured as the functional unit 3. Furthermore, Figure 2 Other circuits included in the microcomputer 1 are not shown in the diagram. Figure 2 In the case of the microcomputer 1 shown, for example, the CPU 2 outputs a start signal and a setting signal to the function unit 3, and the function unit 3 outputs a completion signal and a completion interrupt to the CPU 2.

[0048] Secondly, refer to Figure 1 The structure and operation of the semiconductor device 10 will be explained in more detail.

[0049] First, a start signal is input to the connection switching circuit 11-1 from an external device (e.g., a CPU). The start signal is used to activate the functional circuit 13-1; it can be a signal that causes the functional circuit 13-1 to run once, but in this embodiment, it is assumed to be multiple signals that cause the functional circuit 13-1 to perform sequential operations. Therefore, multiple start signals corresponding to the multiple operations included in a timing sequence are input to the connection switching circuit 11-1. Furthermore, this sequential operation considers both the case of continuously operating a single functional circuit 13-1 and the case of sequentially operating multiple functional circuits 13-1, but in this embodiment, the case of continuously operating a single functional circuit 13-1 will be described. A specific example of continuously operating a single functional circuit 13-1 is as follows: the functional circuit 13-1, for example, acting as a sensor, is run multiple times to obtain multiple measurement values, which are then averaged. The case of sequentially operating multiple functional circuits 13-1 can be understood from the following explanation.

[0050] The start signal input to the connection switching circuit 11-1 is split into two parts at branch 17-1, one of which is input to selector 14-1 and the other to selector 14-3. The output of selector 14-1 is connected to timer 12-1, and when the start signal is selected by setting a register, this start signal is output to timer 12-1. The output of selector 14-3 is connected to function circuit 13-1, and when the start signal is selected by setting a register, this start signal is output to function circuit 13-1.

[0051] On the other hand, the completion signal output from the functional circuit 13-1 is split into two parts at branch 18-1, one of which is input to selector 14-2 and the other to selector 14-4. The output of selector 14-2 is connected to timer 12-1, and when this completion signal is selected via register setting, it is output to timer 12-1. The output of selector 14-4 is connected to an external device (e.g., CPU), and when this completion signal is selected via register setting, it is output to the external device. By receiving this completion signal, the external device transitions, for example, the processing included in the timing sequence to the next processing step.

[0052] Figure 1 Although detailed illustrations are omitted, each of selectors 14-1, 14-2, and 14-3 is connected to a start signal, a completion signal, all outputs of multiple function circuits 13-1, and all outputs of timer 12-1 (or all outputs of each timer 12-1 if multiple timers 12-1 are configured). Additionally, all completion signals are connected to selector 14-4. In other words, selector 14 functions as an n:1 switch, the operation of which is controlled by register settings.

[0053] Here, the output of timer 12-1 is not limited to a completion interrupt, and the output of functional circuit 13-1 is not limited to a completion signal; various outputs are also possible. For example, the output of timer 12-1 could be a clock signal from an internal clock source. In this case, all outputs of functional circuit 13-1 except for the completion signal and all outputs of timer 12-1 except for the completion interrupt are input to selectors 14-1 to 14-3. Thus, timer 12-1 and functional circuit 13-1 can be freely connected in semiconductor device 10.

[0054] The semiconductor device 10 configured as described above operates as follows: When the start signals for each process included in the timing sequence are input sequentially, this start signal branches at branch 17-1. Based on one start signal, the functional circuit 13-1 begins its prescribed operation, and based on the other start signal, the timer 12-1 begins timing. If the functional circuit 13-1 completes its prescribed operation, it outputs a completion signal. This completion signal is divided into two parts at branch 18-1. Based on one completion signal, the timer 12-1 stops timing and resets. The other completion signal is output to an external device (e.g., a CPU) via selector 14-4. At this time, if the timed period is within a predetermined threshold time, the timer 12-1 does not output any signal. On the other hand, if the timed period exceeds the threshold time, the timer 12-1 outputs a completion interrupt to the external device. This completion interrupt indicates an abnormal state, and therefore, the external device (host device) receiving this completion interrupt performs, for example, predetermined exception handling.

[0055] By sequentially executing the above actions in each process included in the timing sequence, and with the functional circuit 13-1 successfully completing its operation and being reset, the timer 12-1 is restarted based on the start signal for the next process. Thus, in the semiconductor device 10, the functional circuit 13-1 and timer 12-1 are started based on a start signal input from an external device, and timer 12-1 stops counting based on a completion signal output from the functional circuit 13-1, allowing the external device to transition the process included in the timing sequence to the next process. At this time, if the functional circuit 13-1 can complete the process within a predetermined threshold time, the external device can transition the timing sequence to the next process or complete the timing sequence. On the other hand, if the functional circuit 13-1 cannot complete the process within the predetermined threshold time, a timer interrupt signal (completion interrupt) is generated as the timer 12-1 expires, thereby notifying of an abnormality.

[0056] Reference Figure 3 The operation of the semiconductor device 10 in this embodiment will be explained in more detail. Figure 3 This is a flowchart illustrating the sequence of timing processing performed by the semiconductor device 10. Figure 3 The “sequencer” shown is equivalent to the external device.

[0057] In step S1, it is determined whether the sequencer has completed the entire prescribed timing sequence. If the determination is negative, the process proceeds to step S2. On the other hand, if the determination is positive, the process proceeds to step S7, and the sequencer outputs a completion interrupt. This completion interrupt is a signal indicating that all processing included in the timing sequence has ended.

[0058] In step S2, the sequencer outputs a start signal. The output start signal is branched by branch 17-1 and sent to functional circuit 13-1 and timer 12-1.

[0059] In step S3, functional circuit 13-1 starts running; in step S4, timer 12-1 starts running. Steps S3 and S4 are not time-lapse actions, but rather independent actions.

[0060] In step S5, depending on whether the functional circuit 13-1 has successfully completed the prescribed process, the following processing branches are steps S6 and S8. Furthermore, no judgment is made in this step; this branch is performed independently through circuit operation.

[0061] If the functional circuit 13-1 fails to complete the specified processing normally, in step S6, timer 12-1 continues timing until the timing time reaches the threshold time. If the timing time reaches the threshold time, the process transitions to step S10, and timer 12-1 outputs a completion interrupt.

[0062] In step S8, the functional circuit 13-1 receives the signal and completes the processing normally. The functional circuit 13-1 then sends the completion signal to the sequencer and timer 12-1.

[0063] If the sequencer receives a completion signal, it proceeds to step S1 to begin the next process. On the other hand, timer 12-1, which received the completion signal, stops counting midway through step S9 and is reset. That is, timer 12-1 enters a standby state relative to the next start signal.

[0064] As described above, in the semiconductor device 10 of this embodiment, the general-purpose timer 12-1, which can also be used for other purposes such as functional circuits, is used as the monitoring circuit for the functional circuit 13-1, and a dedicated monitoring circuit for the functional circuit 13-1 is not provided. Furthermore, when multiple functional circuits 13 are provided, by connecting the timer 12-1 to each of the multiple functional circuits 13, the multiple functional circuits 13 can share a single timer 12-1. That is, the monitoring circuit can be reduced, resulting in cost reduction.

[0065] Furthermore, in the semiconductor device 10 of this embodiment, the connection switching circuit 11-1 includes branch 17-1 and branch 18-1, which distribute each input signal (start signal, completion signal) to multiple connection targets. Through these branch 17-1, branch 18-1, and selector 14, even when multiple functional circuits such as the functional circuit 13 and timer 12 are provided, the connections can be freely switched. Therefore, if the connections of the functional circuit 13 and timer 12 included in the semiconductor device 10 change depending on the application, the connections of each selector can be reconfigured according to register settings, thereby constructing a semiconductor device 10 corresponding to different applications.

[0066] As detailed above, the semiconductor device according to this embodiment has the following effect: it can provide a semiconductor device with a higher degree of freedom in monitoring functions.

[0067] [Second Implementation]

[0068] Reference Figure 4 The semiconductor device 10A of this embodiment will be described. The semiconductor device 10A is a configuration in which a timing circuit 15-1 is added to the semiconductor device 10 of the aforementioned embodiment. Therefore, the portions including the connection switching circuit 11-1, the functional circuit 13-1, and the timer 12-1 are the same as those in the semiconductor device 10, and will be referred to as needed. Figure 1 Furthermore, detailed explanations are omitted. Figure 4 in, omit Figure 1 The diagram shows register 16.

[0069] Figure 4 The timing circuit 15-1 shown is a circuit that controls the timing of multiple processes in the functional circuit 13-1, and has the same characteristics as... Figure 2 The CPU 2 shown has the same function. That is, timing circuit 15-1 sends a start signal to the connection switching circuit 11-1 to control each process in functional circuit 13-1, and receives completion signals from the connection switching circuit 11-1 for each process in functional circuit 13-1. Each time timing circuit 15-1 receives the completion signal of a sequentially executed process, it transitions the process to the next process. Furthermore, upon receiving the completion signal of the last process, timing circuit 15-1 outputs a completion interrupt to an external device. Additionally, a completion interrupt issued by timer 12-1 is also output to an external device.

[0070] In this embodiment, there are no particular restrictions on the form of the external device; for example, it can be set to... Figure 2 CPU 2 in the middle. In this case, semiconductor device 10A is set to Figure 2 Functional section 3 is shown. Furthermore... Figure 4Although not shown in the figure, it can also be configured such that the timing circuit 15-1 receives an initial start signal from an external device (e.g., a CPU) to begin the timing operation. The semiconductor device 10A of this embodiment can also achieve the same effect as the semiconductor device 10 of the above embodiment.

[0071] [Third Implementation Method]

[0072] Reference Figure 5 The semiconductor device 10B of this embodiment will now be described. The semiconductor device 10B is configured to have a plurality of timers 12 corresponding to their uses.

[0073] like Figure 5 As shown, semiconductor device 10B includes: timing circuit 15-2, connection switching circuit 11-2, functional circuit 13-2, timer 12-2, timer 12-3, and timer 12-4. It includes the connections and... (The sentence is incomplete and requires further context to translate accurately.) Figure 1 The semiconductor device 10B shown is identical to the semiconductor device 10. Therefore, the operation of this part is the same as that of the semiconductor device 10. In this embodiment, the functional circuit 13-2 also executes multiple processes corresponding to the processes included in the timing sequence. The semiconductor device 10B may include a single unit or be configured as... Figure 2 Functional unit 3 in the microcomputer 1 shown. Furthermore... Figure 5 in, omit Figure 1 The diagram shows register 16.

[0074] The timing circuit 15-2 controls the order of multiple processes performed by the functional circuit 13-2 included in the timing sequence, and adds the next function to the timing circuit 15-1. That is, it sends a start signal to the timer 12-3 via the connection switching circuit 11-2, sends a timing completion signal indicating the completion of the timing sequence to the timer 12-2 via the connection switching circuit 11-2, and receives a completion signal from the timer 12-3 via the connection switching circuit 11-2.

[0075] In addition to selectors 14-8 to 14-11, the connection switching circuit 11-2 also includes selectors 14-5, 14-6, and 14-7. Selector 14-5 receives a timing completion signal from timing circuit 15-2 and sends this timing completion signal to timer 12-2. Selector 14-6 receives a start signal from timing circuit 15-2 and sends this start signal to timer 12-3. Selector 14-7 receives a completion signal from timer 12-3 and sends this completion signal to timing circuit 15-2.

[0076] Here, the functions of each timer included in semiconductor device 10B are explained. Timer 12-4 and... Figure 1 Similarly, timer 12-1 shown is used to monitor each process in the function circuit 13-2. That is, a threshold time is set for the processing time of each process, which starts according to the start signal. If the time exceeds this threshold time, an abnormal completion interrupt will be output.

[0077] Timer 12-3 has the following function: for each process included in the timing sequence, a waiting time is set before the process begins. Specifically, a start signal indicating the start of the waiting time for each process is input from timing circuit 15-2 to timer 12-3, and a completion signal indicating the end of the waiting time is output from timer 12-3. The waiting time is preset for timer 12-3; this waiting time can be the same or different for each process.

[0078] Furthermore, Timer 12-2 is a timer used to monitor the overall timing sequence. Therefore, a threshold time is set for Timer 12-2 corresponding to the processing time of the overall timing sequence. If the timing ends within this threshold time by receiving a timing completion signal indicating the completion of the overall timing sequence, Timer 12-2 will not output any signal. If the timing exceeds this threshold time, Timer 12-2 will output a completion interrupt to an external device.

[0079] Next, the timing processing order T executed by timing circuit 15-2 will be explained. In this embodiment, the timing processes 1, 2, ..., n are executed in this order.

[0080] First, the timing processing of each process in functional circuit 13-2 under normal conditions is as follows.

[0081] <T1>: The timing start signal for starting the sequence is sent to timer 12-2. This timing start signal is sent from timing circuit 15-2 or an external device (illustration omitted).

[0082] <T2>: The timing circuit 15-2 sends the start signal that enables the waiting time of process 1 to start to timer 12-3 simultaneously with the timing start signal or after a predetermined delay time.

[0083] <T3>: Timer 12-3 outputs a completion signal after a predetermined timing period, resetting the timing.

[0084] <T4>: Since the timing circuit 15-2 receives the completion signal from the timer 12-3, it sends the start signal of processing 1 to the functional circuit 13-2 and the timer 12-4.

[0085] <T5>: Functional circuit 13-2, which receives the start signal of processing 1, begins processing 1, and timer 12-4 begins timing.

[0086] <T6>: The function circuit 13-2 normally completes the processing 1 and outputs the completion signal.

[0087] <T7>: Timer 12-4, which receives the completion signal from self-function circuit 13-2, will reset its timing. Additionally, timing circuit 15-2, which also receives the completion signal from self-function circuit 13-2, sends a start signal to timer 12-3.

[0088] Order T7 is equivalent to order T2, and orders T2 through T7 are repeated below. Order TN is added to the process starting from the following process n.

[0089] <TN1>: The timing circuit 15-2 sends a start signal to timer 12-3 to start the process after a waiting time n.

[0090] <TN2>: Timer 12-3 outputs a completion signal after a predetermined timing period.

[0091] <TN3>: Since the timing circuit 15-2 receives the completion signal from the timer 12-3, it sends the start signal for processing n to the functional circuit 13-2 and the timer 12-4.

[0092] <TN4>: Functional circuit 13-2, which receives the start signal for processing n, begins processing n, and timer 12-4 begins timing.

[0093] <TN5>: The function circuit 13-2 normally completes the processing of n and outputs the completion signal.

[0094] <TN6>: The timing circuit 15-2, which receives the completion signal from the self-function circuit 13-2, sends a timing completion signal to the timer 12-2.

[0095] <TN7>: Timer 12-2, upon receiving the timing completion signal, stops timing and is reset.

[0096] On the other hand, the order T' after T5 in the case of an abnormality in the functional circuit 13-2 in process 1 is as follows. Furthermore, the following order applies to processes other than process 1.

[0097] <T'5>: The abnormal functional circuit 13-2 does not operate even if it receives the start signal of process 1.

[0098] <T'6>: Since the functional circuit 13-2 does not output the completion signal of sequence 1, the timing time of timer 12-4 reaches the threshold time, and timer 12-4 outputs a completion interrupt.

[0099] <T'7>: An external device (e.g., CPU) that receives the completion interrupt in sequence T'6 executes pre-determined exception handling, such as stopping each functional circuit 13-2. In addition, this completion interrupt is sent to timing circuit 15-2, which can also execute exception handling.

[0100] In addition, if the timing completion signal is not sent to timer 12-2 due to some reason, such as an abnormality of timing circuit 15-2, the sequence TN' after sequence TN6 is as follows.

[0101] <TN'6>: Even if the timing circuit 15-2 receives a completion signal from the self-function circuit 13-2, it will not send a timing completion signal to the timer 12-2.

[0102] <TN'7>: The timing completion signal was not received, and the timing time in Timer 12-2 reached the threshold time. Therefore, Timer 12-2 outputs a completion interrupt.

[0103] <TN'8>: An external device (e.g., CPU) that receives the completion interrupt in sequence TN'7 executes pre-determined exception handling, such as stopping each functional circuit 13-2. Furthermore, this completion interrupt is sent to timing circuit 15-2, which can also perform exception handling.

[0104] As detailed above, in the semiconductor device 10B of this embodiment, in addition to the effects of the semiconductor device 10 of the aforementioned embodiment, different functions can be assigned to each timer by changing the connections of the general-purpose timers, namely timer 12-2, timer 12-3, and timer 12-4. Furthermore, this connection change can be made by changing the register settings of the selector 14. In addition, this embodiment illustrates a configuration where different functions are assigned to timer 12, but it is also possible to assign different functions to the functional circuit 13. Furthermore, in the semiconductor device 10B of this embodiment, since the monitoring function can be run using hardware, software can be reduced, thus reducing software development time and achieving lower power consumption due to reduced CPU runtime.

[0105] [Fourth Implementation Method]

[0106] Reference Figure 6The semiconductor device 10C of this embodiment will be described below. The semiconductor device 10C differs from the semiconductor devices of the other embodiments in that it includes multiple functional circuits 13. Therefore, structures with the same function are labeled with the same symbols, and detailed descriptions are omitted. Figure 6 As shown, the semiconductor device 10C includes: a timing circuit 15-3, a connection switching circuit 11-3, a functional circuit 13-3, a functional circuit 13-4, and a timer 12-5. Figure 6 The example illustrates a scenario where two functional circuits, 13-3 and 13-4, share a single timer 12-5 as a monitoring circuit. Furthermore, Figure 6 in, omit Figure 1 The diagram shows register 16.

[0107] like Figure 6 As shown, in this embodiment, the timing circuit 15-3, according to the processing included in the timing, sends the start signal used to start the functional circuits 13-3 and 13-4 respectively to the functional circuits 13-3, 13-4 and timer 12-5 via the connection switching circuit 11-3, and receives the completion signals from the functional circuits 13-3 and 13-4 respectively via the connection switching circuit 11-3. Furthermore, the timing circuit 15-3 sends the completion signals received from the functional circuits 13-3 and 13-4 respectively to an external device.

[0108] The connection switching circuit 11-3 in this embodiment includes: branch 17-2, branch 17-3, branch 18-2, branch 18-3, and selectors 14-12, 14-13, 14-14, 14-15, 14-16, and 14-17. Branch 17-2 distributes the start signal of functional circuit 13-3 to timer 12-5 and functional circuit 13-3, and branch 18-2 distributes the completion signal from functional circuit 13-3 to timer 12-5 and selector 14-15. The completion signal input to selector 14-15 is sent to timing circuit 15-3. Additionally, branch 17-3 distributes the start signal of functional circuit 13-4 to timer 12-5 and functional circuit 13-4, and branch 18-3 distributes the completion signal from functional circuit 13-4 to timer 12-5 and selector 14-17. The completion signal input to selector 14-17 is sent to timing circuit 15-3.

[0109] According to the above structure, the start signals of functional circuits 13-3 and 13-4 are sent to functional circuits 13-3 and 13-4 respectively, and are also sent to timer 12-5. The completion signals from functional circuits 13-3 and 13-4 are sent to timing circuit 15-3, and are also sent to timer 12-5. This is the same even if there are three or more functional circuits 13. That is, by including pairs (branch pairs) of branches 17 and 18 corresponding to the number of functional circuits, multiple functional circuits 13 can share a single timer 12, thereby reducing the number of monitoring circuits.

[0110] Furthermore, in the semiconductor device 10C, the only difference between the semiconductor devices of the various embodiments is that the start signals of each process included in the timing are individually sent to the functional circuit 13. Therefore, the operation of the semiconductor device 10C is the same as that of the semiconductor devices of the various embodiments.

[0111] As described above, the semiconductor device according to this embodiment also has the following effect: it can provide a semiconductor device with a higher degree of freedom in monitoring functions.

Claims

1. A semiconductor device, comprising: The functional unit executes a predetermined process based on a start signal sent from an external device, and outputs a completion signal after the predetermined process is completed. The first timing unit monitors the first abnormality in the specified process based on the start signal and the completion signal; The branch pair includes: a first branch that branches the start signal to the function unit and the first timing unit, and a second branch that branches the completion signal to the first timing unit and the external device; A first selector, configured at the rear end of the first branch, distributes the activation signal to the functional unit; and A second selector is configured at the rear end of the first branch and distributes the start signal to the first timing unit.

2. The semiconductor device according to claim 1, further comprising: A third selector is configured at the rear end of the second branch and distributes the completion signal to the timing unit; as well as A fourth selector is configured at the rear of the second branch and distributes the completion signal to the external device.

3. The semiconductor device according to claim 1 or 2, wherein The functional unit performs multiple of the specified processes, and The external device controls the execution order of the multiple specified processes.

4. The semiconductor device according to claim 1 or 2, wherein The functional unit includes multiple functional units. The branch pair includes a plurality of branch pairs corresponding to each of the plurality of functional units, and The start signal is sent to each of the plurality of functional units and the first timing unit, and the completion signal from each of the plurality of functional units is sent to the first timing unit and the external device.

5. The semiconductor device according to claim 4, wherein The external device controls the execution order of the multiple specified processes performed by the multiple functional units.

6. The semiconductor device according to claim 1 or 2, wherein A predetermined threshold time is set for the first timing unit, and After the first timing unit starts timing according to the start signal, it does not receive the completion signal, thereby detecting the first abnormality when the timing time exceeds the threshold time.

7. A semiconductor device, comprising: The functional unit executes a predetermined process based on a start signal sent from an external device, and outputs a completion signal after the predetermined process is completed. The first timing unit monitors the first abnormality in the specified process based on the start signal and the completion signal; Branch pairs, including: The first branch sends the start signal to the functional unit and the first timing unit, and the second branch sends the completion signal to the first timing unit and the external device; At least one second timing unit monitors the prescribed process based on the start signal; and The second timing unit monitors for a second anomaly that differs from the first anomaly in the specified processing. The second timing unit outputs a signal indicating the end of the waiting time based on the start signal of the waiting time for the specified processing, or outputs the completion signal if the timeout exceeds a threshold time after receiving a completion signal indicating the overall completion of the specified processing.

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