Integrated assembly including folded digital line configuration

Abstract

The present application relates to an integrated assembly including a folded digital line configuration. Some embodiments include an integrated assembly having a second level above a first level. A first true digital line has first and second segments along the first level. A first complementary digital line has third and fourth segments along the second level. The first true digital line is relatively compared to the first complementary digital line. A second true digital line has a third region along the first level and a fourth region along the second level. The third region is adjacent to the first segment, and the fourth region is adjacent to the third segment. A second complementary digital line has a fifth region along the first level and a sixth region along the second level. The fifth region is adjacent to the second segment, and the sixth region is adjacent to the fourth segment. The second true digital line is relatively compared to the second complementary digital line.

Description

Technical Field

[0001] Memory arrays (e.g., DRAM arrays). Integrated assemblies comprising vertically stacked layers. Integrated assemblies comprising folded digit line configurations. Background Art

[0002] Modern computing architectures utilize memory to store data. One type of memory is dynamic random access memory (DRAM). Compared to alternative types of memory, DRAM offers advantages of simplicity, low cost, and high speed.

[0003] DRAM can utilize a memory cell (cell) having one capacitor combined with one transistor (so-called 1T-1C memory cell), where the capacitor is coupled to the source / drain region of the transistor. An example 1T-1C memory cell 2 is shown in FIG. 1 , where the transistor is labeled T and the capacitor is labeled C. The capacitor has one node coupled to the source / drain region of the transistor, and another node coupled to the common plate CP. The common plate CP can be coupled to any suitable voltage, for example, a voltage in the range from greater than or equal to ground to less than or equal to VCC (i.e., ground ≤ CP ≤ VCC). In some applications, the common plate is at a voltage of about half VCC (i.e., about VCC / 2). The transistor has a gate coupled to a word line WL (i.e., an access line, a routing line, a first linear structure, etc.), and has a source / drain region coupled to a bit line BL (i.e., a digital line, a sense line, a second linear structure, etc.). In operation, during a read / write operation, the electric field generated by the voltage along the word line can couple the bit line gate to the capacitor.

[0004] Another prior art 1T-1C memory cell configuration is shown in FIG2. The configuration of FIG2 shows two memory cells 2a and 2b; wherein memory cell 2a includes a transistor T1 and a capacitor C1, and wherein memory cell 2b includes a transistor T2 and a capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. The connection to the bit line BL is shared by memory cells 2a and 2b.

[0005] The memory cells described above may be incorporated into a memory array, and in some applications, the memory array may have an open bit line arrangement. An example integrated assembly 9 having an open bit line architecture is shown in FIG. 3. Assembly 9 includes two laterally adjacent memory arrays ("ARRAY-1" and "ARRAY-2"), each of which includes memory cells of the type described in FIG. 2 (not labeled in FIG. 3 to simplify the diagram). Word lines WL0 to WL7 extend across the arrays and are coupled to word line drivers. Digital lines D0 to D8 are associated with the first array (ARRAY-1), and digital lines D0* to D8* are associated with the second array (ARRAY-2). Sense amplifiers SA0 to SA8 are provided between the first array and the second array. Digital lines at the same height are paired with each other and compared by sense amplifiers (e.g., digital lines D0 and D0* are paired with each other and compared with sense amplifier SA0). In a read operation, one of the paired digital lines may serve as a reference for determining the electrical properties (e.g., voltage) of the other of the paired digital lines.

[0006] Highly integrated memories have closely spaced memory cells and digit lines. Problems may be encountered due to undesired capacitive coupling between closely spaced digit lines (as discussed in H. Hidaka et al., "Twisted Bit-Line Architectures for Multi-Megabit DRAM"; IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February 1989; pp. 21-27). Capacitive coupling can cause excessive noise during data read operations, and the problem of capacitive coupling becomes more severe as the level of integration increases. It is desirable to develop new architectures that can reduce or eliminate problematic capacitive coupling. Summary of the invention

[0007] Some embodiments include an integrated assembly having a first plane and a second plane above the first plane. A first true digital line has a first region along the first plane. The first region has a first segment and a second segment. A first complementary digital line has a second region along the second plane. The second region has a third segment and a fourth segment. The first true digital line is relatively compared to the first complementary digital line by a first sense amplifier circuit. A second true digital line has a third region along the first plane and a fourth region along the second plane. The third region is laterally adjacent to the first segment of the first region of the first true digital line, and the fourth region is laterally adjacent to the third segment of the second region of the first complementary digital line. A second complementary digital line has a fifth region along the first plane and has a sixth region along the second plane. The fifth region is laterally adjacent to the second segment of the first region of the first true digital line, and the sixth region is laterally adjacent to the fourth segment of the second region of the first complementary digital line. The second true digital line is relatively compared to the second complementary digital line by a second sense amplifier circuit.

[0008] Some embodiments include an integrated assembly comprising: a substrate including first and second sense amplifier circuits; a first level above the substrate; and a second level above the first level. A first true digital line has a first region along the first level. The first region has a first segment and a second segment. A first complementary digital line has a second region along the second level. The second region has a third segment and a fourth segment. The first true digital line is relatively compared to the first complementary digital line by the first sense amplifier circuit. A second true digital line has a third region along the first level and a fourth region along the second level. The third region is laterally adjacent to the first segment of the first region of the first true digital line, and the fourth region is laterally adjacent to the third segment of the second region of the first complementary digital line. A second complementary digital line has a fifth region along the first level and has a sixth region along the second level. The fifth region is laterally adjacent to the second segment of the first region of the first true digital line, and the sixth region is laterally adjacent to the fourth segment of the second region of the first complementary digital line. The second true digital line is relatively compared to the second complementary digital line by the second sense amplifier circuit. A first word line extends from memory cells in the third region along the second true digit line to memory cells in the first section of the first region along the first true digit line. A second word line extends from memory cells in the fourth region along the second true digit line to memory cells in the third section of the second region along the first complementary digit line. A third word line extends from memory cells in the fifth region along the second complementary digit line to memory cells in the second section of the first region along the first true digit line. A fourth word line extends from memory cells in the sixth region along the second complementary digit line to memory cells in the fourth section of the second region along the first complementary digit line.

[0009] Some embodiments include an integrated assembly having a substrate including a sense amplifier circuit, a first level above the substrate, a second level above the first level, a first set of true and complementary digital lines, and a second set of true and complementary digital lines. The true digital lines of the first set are relatively coupled to the complementary digital lines of the first set through the first set of the sense amplifier circuits. The true digital lines of the first set are associated with a first set of memory cells. The memory cells of the first set are only along the first level. The complementary digital lines of the first set are associated with a second set of memory cells. The memory cells of the second set are only along the second level. The true digital lines of the second set are relatively coupled to the complementary digital lines of the second set through the second set of the sense amplifier circuits. The true digital lines of the second set are associated with a third set of memory cells. Some of the memory cells of the third set are along the first level and others of the memory cells of the third set are along the second level. The complementary digital lines of the first set are associated with a fourth set of memory cells. Some of the memory cells of the fourth set are along the first level and others of the memory cells of the fourth set are along the second level. A first word line extends between the memory cells of the first set and the memory cells of the third set. A second word line extends between the memory cells of the first group and the memory cells of the fourth group. A third word line extends between the memory cells of the second group and the memory cells of the third group. A fourth word line extends between the memory cells of the second group and the memory cells of the fourth group. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a schematic diagram of a prior art memory cell having 1 transistor and 1 capacitor.

[0011] 2 is a schematic diagram of a pair of prior art memory cells, each of which has 1 transistor and 1 capacitor, and their shared bit line connection.

[0012] FIG. 3 is a schematic diagram of a prior art integrated assembly having an open bitline architecture.

[0013] Figure 4 is a schematic diagram of an example integrated assembly having multiple levels that are vertically displaced relative to each other.

[0014] Figure 5 yes Figure 4 A diagrammatic multidimensional side view of an example layout of a folded number line within an example level of .

[0015] Figure 5A yes Figure 5 A diagrammatic side view of one of the memory cells of FIG.

[0016] Figure 6 Yes Figure 5 A multi-dimensional view of areas of an assembly of a layout.

[0017] Figure 7 is a diagrammatic top view of an example region of an example assembly.

[0018] Figure 8 is a diagrammatic top view of an example region of an example assembly. DETAILED DESCRIPTION

[0019] Some embodiments include integrated assemblies having folded digit line configurations. The folded digit line configurations may be provided in an arrangement that may reduce or eliminate problematic capacitive coupling. Some conventional assemblies may utilize shielding between adjacent digit lines to reduce problematic capacitive coupling. The embodiments described herein may eliminate problematic coupling without utilizing such shielding. Omitting shielding may simplify manufacturing of the architectures described herein compared to conventional architectures that include shielding, and may enable forming the architectures described herein into tighter packing of adjacent digit lines compared to architectures with shielding between adjacent digit lines. Reference Figures 4 to 8 Example embodiments are described.

[0020] refer to Figure 4 , integrated assembly 10 includes a substrate 12, a first level 14 above the substrate, and a second level 16 above the first level. Structures 12, 14, and 16 are stacked vertically above each other. The substrate 12, first level 14, and second level 16 can be considered as examples of levels (tiers) stacked above each other. The levels can be within different semiconductor dies, or at least two of the levels can be within the same semiconductor die.

[0021] The first layer 14 and the second layer 16 have memory areas 18 and 22, respectively. The first and second memory arrays (array-1 and array-2) are supported by the first layer 14 and the second layer 16, wherein each of the memory arrays has a first portion along the first (lower) layer 14 and a second portion along the second (upper) layer 16. The first memory array includes first memory cells 20a, and the second memory array includes second memory cells 20b. The memory cells are illustrated diagrammatically as circles. The first and second memory arrays may include any suitable number of memory cells, and in some embodiments may include hundreds, thousands, millions, etc. of memory cells. The memory cells may be DRAM cells, and in some embodiments may be configured into an arrangement of the type described above with respect to prior art Figures 1 to 3 (i.e., array-1 and array-2 may be DRAM arrays). Array-1 and array-2 are shown separated from each other to simplify Figure 4In some embodiments, the regions of array-1 may overlap with the regions of array-2, as described below with respect to Figure 5 As described in the embodiments described.

[0022] In some embodiments, the first level 14 and the second level 16 may be referred to as first and second memory levels, respectively.

[0023] Base 12 may include semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. Base 12 may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any construction including a semiconductive material, including, but not limited to, a bulk semiconductive material such as a semiconductive wafer (alone or in an assembly including other materials) and a layer of semiconductive material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrate described above. In some applications, base 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of a refractory metal material, a barrier material, a diffusion material, an insulator material, etc. Each of layers 14 and 16 may also include a semiconductor material.

[0024] In the embodiment shown, substrate 12 includes sense amplifier circuitry (SA) and word line driver circuitry (WD).

[0025] The sense amplifier circuit includes a region 26 labeled "SA-E" to identify it as being associated with the "even" portion of the circuit, and a region 28 labeled "SA-O" to identify it as being associated with the "odd" portion of the circuit. The terms "even" and "odd" are arbitrary and are used to distinguish different sense amplifier circuits from one another. The illustrated configuration has sense amplifier circuits SA-O and SA-E paired with one another and distributed as structure 24. The sense amplifier circuits SA-O and SA-E may be referred to as first and second sense amplifier circuits, respectively. In some embodiments, the sense amplifier circuit SA-O may be considered to correspond to a first set of sense amplifier circuits, and the sense amplifier circuit SA-E may be considered to correspond to a second set of sense amplifier circuits.

[0026] The word line driver circuit (i.e., row driver circuit) includes a region 31 labeled SWD-L and a region 33 labeled SWD-U. The acronym SWD stands for sub-word line driver, and is used to emphasize that components SWD-L and SWD-U are part of a general word line driver circuit. Word line driver circuit SWD-L is utilized during operation of memory cells associated with lower level 14, and word line driver circuit SWD-U is utilized during operation of memory cells associated with upper level 16.

[0027] In some embodiments, word line driver circuits SWD-L and SWD-U may be considered paired with each other and distributed as structure 30 .

[0028] The structures (blocks) 24 and 30 may be considered to form a patch region. The patch regions may be considered together to form a quilted arrangement of circuit subunits along the substrate 12. Figure 7 and 8 Describe the instance patch area in more detail.

[0029] Still refer to Figure 4 , first digit lines D0, D1, and D2 are associated with a first memory array (array-1). The first digit lines D0, D1, and D2 extend along the first memory array (array-1) and are coupled to first memory cells 20a of the first memory array. The digit lines D0, D1, and D2 are laterally spaced from one another and may represent a large number of substantially identical digit lines extending across the first memory array; wherein the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. The first digit lines alternate between even first digit lines and odd first digit lines, wherein digit lines D0 and D2 represent even first digit lines, and digit line D1 represents odd first digit lines. The even first digit lines (e.g., D0) are coupled to a first sense amplifier circuit 26 (i.e., SA-E), and the odd first digit lines (e.g., D1) are coupled to a second sense amplifier circuit 28 (i.e., SA-O). The first digit lines D0 and D2 have a first portion along the first level 14, and have a second portion along the second level 16. The first digit line D1 has a portion along the first plane 14 , but does not have a portion along the second plane 16 .

[0030] Second digit lines D0*, D1*, and D2* are associated with a second memory array (array-2). The second digit lines D0*, D1*, and D2* extend along the second memory array and are coupled to second memory cells 20b of the second memory array (array-2). The digit lines D0*, D1*, and D2* are laterally spaced from one another and may represent a large number of substantially identical digit lines extending across the second memory array. The second digit lines alternate between even second digit lines and odd second digit lines, wherein digit lines D0* and D2* represent even second digit lines and digit line D1* represents odd second digit lines. The even second digit lines (e.g., D0*) are coupled to a first sense amplifier circuit 26 (SA-E), and the odd second digit lines (e.g., D1*) are coupled to a second sense amplifier circuit 28 (SA-O). The second digit lines D0* and D2* have a first portion along the first plane 14 and have a second portion along the second plane 16. The second digit line D2 * has a portion along the second plane 16 , but does not have a portion along the first plane 14 .

[0031] Even first digit lines D0 and D2 are oppositely coupled to even second digit lines D0* and D2* through first sense amplifier circuit 26 (SA-E); and odd first digit line D1 is oppositely coupled to odd second digit line D1* through second sense amplifier circuit 28 (SA-O). For purposes of understanding the present invention and the appended claims, a first digit line is “oppositely coupled” to a second digit line through a sense amplifier circuit if the sense amplifier circuit is configured to compare electrical properties (e.g., voltages) of the first and second digit lines to each other.

[0032] Two digital lines coupled relative to each other through a sense amplifier circuit may be considered to include a true digital line and a complementary digital line. For example, digital lines D0 and D0* may be considered to be a true digital line and a complementary digital line, respectively; and similarly, digital lines D1 and D1* may be considered to be a true digital line and a complementary digital line, respectively. The terms "true" and "complementary" are arbitrary. During read / write operations of the memory cells (e.g., 20a, 20b) associated with the set of true digital lines and complementary digital lines, the electrical values ​​of this set are utilized together. For purposes of describing the embodiments herein, true digital lines will be those indicated as having no asterisks in the labels (e.g., D0, D1, D2, etc.), and complementary digital lines will be those indicated as having asterisks in the labels (e.g., D0*, D1*, D2*, etc.).

[0033] Still reference Figure 4 , word lines 32 extend along the first and second memory arrays (array-1 and array-2).

[0034] Each of the first memory cells 20a within the first memory array (Array-1) is uniquely addressed by one of the digit lines extending along the first memory array (e.g., one of the digit lines D0, D1, and D2) and one of the word lines 32. Similarly, each of the memory cells 20b within the second memory array (Array-2) is uniquely addressed by one of the digit lines extending along the second memory array (e.g., one of the digit lines D0*, D1*, and D2*) and one of the word lines 32. In some embodiments, the digit lines along the first memory array (Array-1) may be referred to as a first set of digit lines, while the digit lines along the second memory array (Array-2) are referred to as a second set of digit lines.

[0035] Figure 4An advantage of the configuration is that all of the sense amplifier circuits and all of the word line driver circuits can be provided directly beneath the memory arrays (array-1 and array-2), which can enable tight packaging of the memory array across the semiconductor substrate; or in other words, this can save valuable semiconductor real estate compared to conventional configurations in which at least some of the sense amplifier circuits and / or at least some of the word line driver circuits are not directly beneath the memory array. Vertical stacking of regions of the memory arrays (array-1 and array-2) can further save valuable semiconductor real estate. Figure 4 In the illustrated embodiment, digit lines D0, D0*, D1, D1*, D2, and D2* are all vertically displaced relative to first and second sense amplifier circuits SA-E and SA-O, and vertically displaced relative to word line driver circuits SWD-U and SWD-L.

[0036] Figure 5 An example integrated assembly 10 is shown in accordance with an example embodiment. Assembly 10 includes a pair of digit lines DL1 and DL1* coupled relative to each other through sense amplifier circuit 28 (SA-O). Digit line DL1 may be referred to as a true digit line, and digit line DL1* may be referred to as a complementary digit line. In some embodiments, digit lines DL1 and DL1* may be referred to as first digit lines to distinguish them from Figure 5 ; and in such embodiments, digit line DL1 may be referred to as a first true digit line, and digit line DL1* may be referred to as a first complementary digit line. In some embodiments, digit lines DL1 and DL1* may be referred to as a first set of true and complementary digit lines, where this first set corresponds to digit lines that are compared to each other by SA-O circuits (and SA-O circuits may be considered a first set of sense amplifier circuits). Sense amplifier circuits 28 are associated with (along) substrate 12.

[0037] exist Figure 5 1 , a substrate 12, a first plane 14, and a second plane 16 are diagrammatically represented at different height levels. A true digital line DL1 is illustrated as having a region 40a along (associated with) the first plane (lower plane) 14, and having no region along the second plane (upper plane) 16. A complementary digital line DL1* is illustrated as having a region 40b along (associated with) the second plane (upper plane) 16, and having no region along the first plane 14. The regions 40a and 40b may be referred to as first and second regions, respectively.

[0038] Assembly 10 also includes a pair of digit lines DL0 and DL0* coupled relative to each other by sense amplifier circuitry 26 (SA-E). Digit line DL0 may be referred to as a second true digit line, and digit line DL0* may be referred to as a second complementary digit line. In some embodiments, digit lines DL0 and DL0* may be referred to as a second set of true and complementary digit lines, where this second set corresponds to digit lines that are compared to each other by SA-E circuitry (and the SA-E circuitry may be considered a second set of sense amplifier circuitry). Sense amplifier circuitry 26 is associated with (along) substrate 12.

[0039] The second true digit line DL0 is illustrated as having a third region 40c along (associated with) the first plane (lower plane) 14 and a fourth region 40d along (associated with) the second plane (upper plane) 16. The second complementary digit line DL0* is illustrated as having a fifth region 40e along (associated with) the first plane (lower plane) 14 and a sixth region 40f along (associated with) the second plane (upper plane) 16.

[0040] The first region 40a of the first true digit line DL1 can be considered to be subdivided into a first section 42a and a second section 42b, wherein the first section 42a is laterally adjacent to the third region 40c of the second true digit line DL0 and the second section 42b is laterally adjacent to the fifth region 40e of the second complementary digit line DL0*.

[0041] Second region 40b of first complementary digit line DL1* may be considered to be subdivided into third and fourth sections 42c and 42b, wherein third section 42c is laterally adjacent to fourth region 40d of second true digit line DL0 and fourth section 42d is laterally adjacent to sixth region 40f of second complementary digit line DL0*.

[0042] Example memory cells 20a and 20b are shown along height levels corresponding to levels 14 and 16, and word lines 32 are also shown along height levels corresponding to levels 14 and 16. Each of the memory cells 20a of array-1 (where array-1 is described in FIG. 3 ) is uniquely addressed by a true digit line (DL0 or DL1) and a word line 32. Similarly, each of the memory cells 20b of array-2 (where array-1 is described in FIG. 3 ) is uniquely addressed by a complementary digit line (DL1* or DL0*) and a word line 32. The word lines extend along the rows of memory cells 20a / 20b.

[0043] The first set of word lines are labeled word lines 32a, and such word lines extend from memory cells 20a along a first section 42a of a first true digit line DL1 to memory cells 20a along a third region 40c of a second true digit line DL0.

[0044] The second set of word lines are labeled word lines 32b, and such word lines extend from memory cells 20a along the second section 42b of the first true digit line DL1 to memory cells 20b along the fifth region 40e of the second complementary digit line DL0*.

[0045] The third group of word lines is labeled word lines 32c, and such word lines extend from memory cells 20b along a third section 42c of the first complementary digit line DL1* to memory cells 20a along a fourth region 40d of the second true digit line DL0.

[0046] A fourth group of word lines are labeled word lines 32d, and such word lines extend from memory cells 20b along a fourth section 42d of the first complementary digit line DL1* to memory cells 20b along a sixth section 40f of the second complementary digit line DL0*.

[0047] The terms "first," "second," "third," and "fourth" are arbitrary when describing word lines 32a, 32b, 32c, and 32d, and are used only to distinguish the word lines from one another. The terms "first," "second," "third," and "fourth" may be used to refer to and distinguish any of word lines 32a, 32b, 32c, and 32d in any desired order in various embodiments. For example, in some embodiments, word lines 32a, 32c, 32b, and 32d may be referred to as first, second, third, and fourth word lines, respectively.

[0048] Memory cells 20a along the first true digit line DL1 may be considered as a first group 44a of memory cells, memory cells 20b along the first complementary digit line DL1* may be considered as a second group 44b of memory cells, memory cells 20a along the second true digit line DL0 may be considered as a third group 44c of memory cells, and memory cells 20b along the second complementary digit line DL0* may be considered as a fourth group 44d of memory cells. The memory cells of the first group 44a are only along the lower level 14, and the memory cells of the second group 44b are only along the upper level 16. In contrast, the memory cells of the third group 44c are along both levels 14 and 16, and the memory cells of the fourth group 44d are also along both levels 14 and 16.

[0049] Word line driver circuits (SWD-up and SWD-down) may be supported by substrate 12 and may be coupled with word lines 32 . Figure 5 Several example connections to the word line driver circuits are shown in FIG. Figure 5 Most of the connections to the word line driver circuits are not shown in FIG. 1 to simplify the diagram. The illustrated connections show that lower word lines 32a and 32b are coupled to SWD lower circuit 31, and upper word lines 32c and 32d are coupled to SWD upper circuit 33. Circuits 31 and 33 may be different from each other and laterally spaced apart from each other along substrate 12. Figure 4 and5 Instructions and referenced below Figure 7 and 8 Describe in more detail.

[0050] Memory cells 20a and 20b may have any suitable configuration. Figure 5 An example memory cell 20 is shown in an enlarged view of FIG. 2B to simplify labeling of components of the memory cell. Memory cell 20 includes a transistor T coupled to a capacitor C. Transistor T includes a vertically extending pillar 70 of semiconductor material 72. Semiconductor material 72 may include any suitable composition(s); and in some embodiments, may include, consist essentially of, or consist of one or more of silicon, germanium, a Group III / V semiconductor material (e.g., gallium phosphide), a semiconductor oxide, or the like; wherein the term Group III / V semiconductor material refers to a semiconductor material including elements selected from Group III and Group V of the periodic table (where Group III and Group V are old nomenclature and are now referred to as Groups 13 and 15).

[0051] A gate dielectric material (insulating material) 74 is along the sidewalls of the pillar 70, and a conductive gate material 76 is along the gate dielectric material.

[0052] The gate dielectric material 74 may comprise any suitable composition(s) and, in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0053] The conductive gate material 76 may include any (several) suitable conductive compositions; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0054] Conductive gate material 76 forms a transistor gate of transistor T. The transistor includes a first source / drain region 86 within an upper region of pillar 70, a second source / drain region 88 within a lower region of pillar 70, and a channel region 90 between the first source / drain region 86 and the second source / drain region 88. In operation, an electric field generated by a voltage within gate material 76 (i.e., a voltage along word line 32 coupled to gate material 76) may gate-couple source / drain regions 86 and 88 to each other through channel region 90. When the term "gated coupling" is utilized herein, this may refer to controlled coupling / decoupling of source / drain regions of a transistor, which may be induced by electrical activation / deactivation of a gate of the transistor.

[0055] Capacitor C includes a first conductive node 78, a second conductive node 80, and an insulating material (capacitor dielectric material) 82 between the first conductive node and the second conductive node.

[0056] The first conductive node 78 and the second conductive node 80 may include any (several) suitable conductive compositions; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). The first and second conductive nodes may include the same composition as one another, or may include different compositions from one another.

[0057] Insulating material 82 may comprise any suitable composition(s), and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0058] In the illustrated embodiment, the lower conductive node 78 is configured as an upwardly open container. In other embodiments, the lower conductive node may have another suitable shape. In the illustrated embodiment in which the lower conductive node 78 is configured as an upwardly open container, the dielectric material 82 and the upper node 80 extend into the upwardly open container of the lower node 78.

[0059] Capacitor C is an example storage element coupled with transistor T. In other embodiments, other suitable storage elements may be utilized in place of capacitor C. A suitable storage element may be a device having at least two detectable states; and in some embodiments, a suitable storage element may be, for example, a resistive memory device, a conductive bridge device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc.

[0060] Figure 5 The digit lines DL0, DL0*, DL1, and DL1* of 80 include a conductive material 84. This conductive material may include any (several) suitable conductive compositions; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0061] Figure 5 An advantage of the configuration is that each of the odd digit lines (DL1 and DL1*) has a first portion of a region adjacent to one of the even digit lines (e.g., odd digit line DL1 has a first portion 42a adjacent to even digit line DL0), and has a second portion of a region adjacent to the complementary line of the one of the even digit lines (e.g., odd digit line DL1 has a second portion 42b adjacent to even digit line DL0*). This can achieve the elimination of noise along the adjacent digit lines DL1, DL0, DL1*, and DL0* during differential sensing operations (where example noise is noise generated by capacitive coupling). Therefore, Figure 5 The configuration can advantageously reduce problematic noise between adjacent digit lines (eg, noise generated by capacitive coupling).

[0062] Figure 6 exhibit Figure 5 1 is an alternative view of assembly 10 of FIG. 1. Specifically, each of levels 14 and 16 is diagrammatically illustrated as being above substrate 12, and regions of digit lines DL0, DL0*, DL1, and DL1* are diagrammatically illustrated as being associated with levels 14 and 16. Additional digit lines are shown but not labeled.

[0063] The connection between the region along the digit line of the upper stack 16 and the region along the digit line of the lower stack 14 is illustrated diagrammatically by dashed line 55 .

[0064] Sense amplifier circuits 26 and 28 and word line driver circuits 31 and 33 are diagrammatically illustrated along substrate 12 ; and beneath the memory arrays ( Array- 1 and Array- 2 ) associated with levels 14 and 16 .

[0065] The above article about Figure 5 and 6 The described configuration may have the sense amplifier circuits and word line driver circuits distributed in any suitable arrangement along substrate 12. Figure 7 An example arrangement is described. This example arrangement includes repeated patches (where the example patch is identified as patch 64). Each of the patches includes sense amplifier circuits (SA-E and SA-O), and includes word line driver circuits (SWD-L and SWD-U). Example wiring 54 (only some of which are labeled) is shown arranged for coupling the various sense amplifier circuits and word line driver circuits to elements outside the indicated patches.

[0066] Figure 8 Another example arrangement of sense amplifier circuits and word line driver circuits along substrate 12 is illustrated in FIG. The word line driver circuits (SWD-U and SWD-L) are laterally offset relative to the sense amplifier circuits (SA-E and SA-O). In some embodiments, the word line driver circuits may be considered to be within a second area 46 of substrate 12, and the sense amplifier circuits may be considered to be within a first area 44 of this substrate. The second area is laterally offset from the first area. In some embodiments, as described above in Figure 4 and 6 As indicated in , at least some of the first and second regions may be directly below first and second memory cells of the first and second memory arrays.

[0067] Example word line 32 and digit lines DL0, DL1, DL2, DL3, DL3*, and DL4* are shown superimposed on Figure 8The word lines and digit lines will be along the layer above the substrate 12, rather than along the substrate 12, such as Figure 4 , 5 and as indicated in 6.

[0068] SA-E circuit 28 may be considered as a first sense amplifier circuit, and SA-O circuit 26 may be considered as a second sense amplifier circuit. In the embodiment shown, the second sense amplifier circuit is laterally displaced from the first sense amplifier circuit. SWD-U circuit 33 may be considered as a first word line driver circuit, and SWD-L circuit 31 may be considered as a second word line driver circuit. In the embodiment shown, the second word line driver circuit is laterally displaced from the first word line driver circuit. The first sense amplifier circuit 26 and the second sense amplifier circuit 28 within patch 64 are associated with the circuit represented by digital lines DL0, DL1, DL2, DL3, DL3* and DL4*. Two groups of word line driver circuits are also associated with this circuit. One of such groups includes SWD-L labeled 31a and SWD-U labeled 33a. This group is along a region of substrate 12 adjacent to one side of SA-E circuit 28 within patch 64. The other of the groups of word line driver circuits includes SWD-L labeled 31b and SWD-U labeled 33b. This set is along areas of substrate 12 that are adjacent edges of both the SA-E and SA-O circuits within patch 64 .

[0069] Figure 8 The illustrated embodiment of shows a socket region 66 along the edge of the patch, where such a socket region enables an interconnect to pass along the edge of a circuit associated with the patch.

[0070] Although the embodiments described herein indicate that there are two memory levels (14, 16) above the substrate 12, it should be understood that in other embodiments, there may be more than two memory levels above the substrate.

[0071] The assemblies and structures discussed above may be used within integrated circuits (where the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0072] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method (now known or yet to be developed), including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0073] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In the present invention, the terms are considered synonymous. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language changes within the present invention to simplify the preamble basis within the appended claims, and is not intended to indicate any significant chemical or electrical differences.

[0074] Both the terms "electrically connected" and "electrically coupled" may be used in the present invention. The terms are considered synonymous. Utilizing one term in some cases and another term in other cases may provide language variation within the present invention to simplify preamble basis within the appended claims. The terms "couple", "coupling", "coupled", etc. may refer to an electrical connection.

[0075] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the figures or rotated relative to such orientation.

[0076] The cross-sectional views of the drawings show only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings, unless otherwise indicated.

[0077] When a structure is referred to above as being "on another structure," "adjacent to," or "against" another structure, it may be directly above the other structure and there may also be intervening structures. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly against" another structure, there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0078] A structure (eg, layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure extends generally upward from an underlying base (eg, substrate). A vertically extending structure may extend substantially orthogonally relative to an upper surface of a base, or non-orthogonally.

[0079] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims should be given full scope as literally worded and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: First level; a second level, which is above the first level; A first true digital line having a first region along the first layer, the first region having a first section and a second section; A first complementary digital line having a second region along the second plane; the second region having a third section and a fourth section; the first true digital line and the first complementary digital line are relatively compared by a first sense amplifier circuit; a second true digit line having a third region along the first plane and a fourth region along the second plane; the third region being laterally adjacent to the first section of the first region of the first true digit line, and the fourth region being laterally adjacent to the third section of the second region of the first complementary digit line; and A second complementary digital line having a fifth region along the first plane and a sixth region along the second plane; the fifth region being laterally adjacent to the second segment of the first region of the first true digital line, and the sixth region being laterally adjacent to the fourth segment of the second region of the first complementary digital line; the second true digital line being relatively compared with the second complementary digital line by a second sense amplifier circuit.

2. The integrated assembly of claim 1, wherein a word line extends from memory cells of the third region along the second true digital line to memory cells of the first section of the first region along the first true digital line.

3. The integrated assembly of claim 1 wherein word lines extend from memory cells of the fourth region along the second true digit line to memory cells of the third section of the second region along the first complementary digit line.

4. The integrated assembly of claim 1 wherein word lines extend from memory cells of the fifth region along the second complementary digit line to memory cells of the second section of the first region along the first true digit line.

5. The integrated assembly of claim 1 wherein word lines extend from memory cells along the sixth region of the second complementary digit line to memory cells along the fourth section of the second region of the first complementary digit line.

6. An integrated assembly comprising: a substrate including first and second sense amplifier circuits; A first layer, which is above the substrate; a second level, which is above the first level; A first true digital line having a first region along the first layer, the first region having a first section and a second section; A first complementary digital line having a second region along the second plane; the second region having a third section and a fourth section; and being relatively compared with the first complementary digital line by the first sense amplifier circuit; a second true digit line having a third region along the first plane and having a fourth region along the second plane, the third region being laterally adjacent to the first section of the first region of the first true digit line and the fourth region being laterally adjacent to the third section of the second region of the first complementary digit line; a second complementary digit line having a fifth region along the first plane and having a sixth region along the second plane; the fifth region being laterally adjacent to the second section of the first region of the first true digit line and the sixth region being laterally adjacent to the fourth section of the second region of the first complementary digit line; the second true digit line being relatively compared with the second complementary digit line by the second sense amplifier circuit; a first word line extending from memory cells of the third region along the second true digit line to memory cells of the first section of the first region along the first true digit line; a second word line extending from memory cells of the fourth region along the second true digit line to memory cells of the third section of the second region along the first complementary digit line; a third word line extending from memory cells of the fifth region along the second complementary digit line to memory cells of the second segment of the first region along the first true digit line; and A fourth word line extends from memory cells along the sixth region of the second complementary digit line to memory cells along the fourth section of the second region of the first complementary digit line.

7. The integrated assembly of claim 6, wherein the memory cell comprises a capacitor.

8. The integrated assembly of claim 7, wherein the bottom electrode of the capacitor is configured as an upwardly open container.

9. The integrated assembly of claim 6, wherein the first word line is coupled with a first word line driver circuit and the second word line is coupled with a second word line driver circuit different from the first word line driver circuit.

10. The integrated assembly of claim 6, wherein the third word line is coupled with the first word line driver circuit and the fourth word line is coupled with the second word line driver circuit.

11. The integrated assembly according to claim 6, wherein: the first sense amplifier circuit being laterally offset from the second sense amplifier circuit along the substrate; The first word line is coupled to a first word line driver circuit, and the second word line is coupled to a second word line driver circuit different from the first word line driver circuit; and The first and second word line driver circuits are within a region along the substrate that is along one side of the first and second sense amplifier circuits.

12. The integrated assembly of claim 11 wherein the memory cells along the first and second true digit lines are within a first memory array and the memory cells along the first and second complementary digit lines are within a second memory array; and wherein at least a portion of one or more of the first and second word line driver circuits and the first and second sense amplifier circuits are directly beneath the first and second memory arrays.

13. The integrated assembly of claim 11 wherein the memory cells along the first and second true digit lines are within a first memory array and the memory cells along the first and second complementary digit lines are within a second memory array; and wherein the first and second word line driver circuits and the first and second sense amplifier circuits are completely directly beneath the first and second memory arrays.

14. The integrated assembly according to claim 6, wherein: the first sense amplifier circuit being laterally offset from the second sense amplifier circuit along the substrate; The first word line is coupled to a first word line driver circuit, and the second word line is coupled to a second word line driver circuit different from the first word line driver circuit; and The first and second word line driver circuits are within a region along the substrate that is along edges of both the first and second sense amplifier circuits.

15. The integrated assembly of claim 14 wherein the memory cells along the first and second true digit lines are within a first memory array and the memory cells along the first and second complementary digit lines are within a second memory array; and wherein at least a portion of one or more of the first and second word line driver circuits and the first and second sense amplifier circuits are directly beneath the first and second arrays.

16. An integrated assembly comprising: a substrate including a sense amplifier circuit; A first layer, which is above the substrate; a second level, which is above the first level; a first set of true and complementary digital lines; the true digital lines of the first set are relatively coupled to the complementary digital lines of the first set through a first set of the sense amplifier circuits; the true digital lines of the first set are associated with a first set of memory cells, the memory cells of the first set are only along the first level; the complementary digital lines of the first set are associated with a second set of memory cells, the memory cells of the second set are only along the second level; a second set of true and complementary digital lines; the true digital lines of the second set are relatively coupled to the complementary digital lines of the second set through a second set of the sense amplifier circuits; the true digital lines of the second set are associated with a third set of memory cells, some of the memory cells of the third set are along the first level and others of the memory cells of the third set are along the second level; the complementary digital lines of the first set are associated with a fourth set of memory cells, some of the memory cells of the fourth set are along the first level and others of the memory cells of the fourth set are along the second level; a first word line extending between the memory cells of the first group and the memory cells of the third group; a second word line extending between the memory cells of the first group and the memory cells of the fourth group; a third word line extending between the memory cells of the second group and the memory cells of the third group; and A fourth word line extends between the memory cells of the second group and the memory cells of the fourth group.

17. The integrated assembly of claim 16, wherein the first word line is coupled with a first word line driver circuit, and wherein the third word line is coupled with a second word line driver circuit different from the first word line driver circuit.

18. The integrated assembly of claim 16, wherein the first word line is coupled with a first word line driver circuit, and wherein the fourth word line is coupled with a second word line driver circuit different from the first word line driver circuit.

19. The integrated assembly of claim 16, wherein the second word line is coupled to a first word line driver circuit, and wherein the third word line is coupled to a second word line driver circuit different from the first word line driver circuit.

20. The integrated assembly of claim 16, wherein the second word line is coupled with a first word line driver circuit, and wherein the fourth word line is coupled with a second word line driver circuit different from the first word line driver circuit.

21. The integrated assembly of claim 16, wherein the first and second word lines are coupled with a first word line driver circuit, and wherein the third and fourth word lines are coupled with a second word line driver circuit different from the first word line driver circuit.

22. The integrated assembly of claim 16, wherein the memory cell comprises a storage element.

23. The integrated assembly of claim 16, wherein the memory cell comprises a capacitor.

24. The integrated assembly of claim 23 wherein the capacitor has a bottom electrode shaped as an upwardly open container and has a dielectric material and a top electrode extending into the upwardly open container.

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