Electronic device, electronic module and manufacturing method thereof

Abstract

An electronic device, an electronic module including the electronic device and a manufacturing method thereof are shown. The electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack includes a first layer, wherein the first layer includes NiSi.

Description

[0001] This application is a divisional application of Chinese patent application 201710854614.X, whose application date is September 20, 2017 and whose invention name is “Electronic device, electronic module and manufacturing method thereof”. Technical Field

[0002] The invention relates to an electronic device, an electronic module and a manufacturing method thereof. Background Art

[0003] Manufacturers of electronic devices are constantly striving to improve the performance of their products while striving to reduce their manufacturing costs. A cost-intensive area in the manufacture of electronic devices or electronic modules is the preparation of a metal stack arranged on the surface of a semiconductor substrate. Backside metallization (BSM) may be an example of such a metal stack. Such a metal stack may include a first layer that reacts with a solder layer when the semiconductor substrate is soldered to a carrier. Improvements in such a metal stack, such as improvements in the first layer, and improved soldering methods may help to reduce manufacturing costs, improve the reliability of solder joints, and reduce wafer warpage and chip warpage. For these and other reasons, the present invention is needed. Summary of the invention

[0004] According to one aspect of the present invention, an electronic device is provided, comprising a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises: a first layer, wherein the first layer comprises NiSi.

[0005] According to an optional embodiment of the present invention, the semiconductor substrate includes one or more of a power semiconductor chip, an IGBT and a diode, and the metal stack is arranged on a chip pad of the power semiconductor chip, the IGBT or the diode.

[0006] According to an optional embodiment of the present invention, the metal stack contains N impurities in the first layer, in particular in the form of one or more of NiN and SiN.

[0007] According to an optional embodiment of the present invention, the metal stack further includes a second layer arranged between the first layer and the semiconductor substrate, in particular, the second layer includes one or more of the following materials: Ti, WTi, Ta or an alloy including at least one of these materials.

[0008] According to an optional embodiment of the present invention, the metal stack further includes a third layer disposed on the first layer, in particular, the third layer includes one or more of Ag, Pt, Pd and Au.

[0009] According to an optional embodiment of the present invention, the metal stack further includes a fourth layer disposed between the semiconductor substrate and the first layer, in particular, the fourth layer includes one or more of Al and Ti.

[0010] According to an optional embodiment of the present invention, the first layer has a thickness in the range of 50 nm to 2000 nm, in particular 100 nm to 1000 nm, more particularly 200 nm to 600 nm, even more particularly 400 nm to 500 nm.

[0011] According to an optional embodiment of the present invention, the first layer contains Si in an amount ranging from 2wt% to 50wt%, particularly 2wt% to 20wt%, more particularly 3wt% to 10wt%, more particularly 4wt% to 5wt%, even more particularly 4.5wt% Si.

[0012] According to another aspect of the present invention, an electronic module is provided, comprising: a carrier; a semiconductor chip arranged on the carrier; a metal stack arranged between the carrier and the semiconductor substrate, the metal stack comprising a first layer; and a solder layer arranged on the first layer, wherein the first layer contains NiSi.

[0013] According to an optional embodiment of the present invention, the carrier includes a power electronic substrate, a lead frame, a DCB, a DAB, an AMB, an IMS or a PCB.

[0014] According to an optional embodiment of the present invention, the electronic module further comprises a packaging body encapsulating the semiconductor chip.

[0015] According to an optional embodiment of the present invention, the solder layer comprises a Pb-based or Pb-free solder.

[0016] According to an optional embodiment of the present invention, the solder layer includes Sn or SnAg.

[0017] According to an optional embodiment of the present invention, the electronic module further includes an intermetallic phase formed between the first layer and the solder layer.

[0018] According to an optional embodiment of the present invention, the metal stack includes N impurities.

[0019] According to an optional embodiment of the present invention, N impurities are located along an interface between the first layer and the solder layer.

[0020] According to another aspect of the present invention, a method for manufacturing an electronic module is provided, comprising: providing a carrier and a semiconductor substrate, arranging a first layer on the semiconductor substrate, arranging a solder layer between the first layer and the carrier, and soldering the semiconductor substrate to the carrier, wherein the first layer contains NiSi, and wherein arranging the first layer on the semiconductor substrate includes sputtering in the presence of a process gas containing N.

[0021] According to an optional embodiment of the present invention, the sputtering comprises a magnetron sputtering process.

[0022] According to an optional embodiment of the present invention, the amount of N in the process gas is about 80%, or 70%, or 60%, or 50%, or 40%, or 30%, or 20%, or 10% or 5%.

[0023] According to an optional embodiment of the present invention, the process gas further contains Ar, Xe, Kr or Ne. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of the embodiments, are incorporated in conjunction with the drawings and constitute a part of this description. The accompanying drawings illustrate the embodiments and together with the description are used to explain the principles of the embodiments. Other embodiments and many of the expected advantages of the embodiments may be better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. The same reference numerals refer to corresponding similar parts.

[0025] Figure 1 A cross-sectional view schematically shows an example of an electronic device according to the present invention.

[0026] Figure 2 A cross-sectional view schematically shows an example of an electronic module according to the present invention.

[0027] Figure 3 A flow chart of a method for manufacturing an electronic device according to the present invention is shown.

[0028] Figure 4 A flow chart of a method for manufacturing an electronic module according to the present invention is shown. DETAILED DESCRIPTION

[0029] In the following detailed description, reference is made to the accompanying drawings forming part of the specification, which illustrate specific embodiments of the present invention. However, it will be apparent to those skilled in the art that one or more aspects of the embodiments may be implemented with less specific details. In other cases, known structures and elements are shown in schematic form to facilitate description of one or more aspects of the embodiments. In this regard, directional terms such as "top", "bottom", "left", "right", "up", "down", etc. are used with reference to the orientation of the described figures. Because the components of the embodiments may be positioned in a plurality of different orientations, the directional terms are used for illustrative purposes, rather than restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention.

[0030] In addition, although specific features or aspects of an embodiment may be disclosed for only one of several embodiments, it may be desirable and advantageous for any given or specific application that such features or aspects may be combined with one or more other features or aspects of other embodiments, unless explicitly stated not to be so or unless technically limited. The terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact with each other, or not in direct contact with each other; intermediate elements or layers may be provided between "combined", "attached" or "connected" elements.

[0031] The semiconductor substrate or semiconductor chip described further below may be of different types and may be manufactured by different technologies. Embodiments of electronic devices and electronic modules and methods for manufacturing electronic devices and electronic modules may use various types of semiconductor chips or circuits incorporated into semiconductor chips, which may be, for example, AC / DC or DC / DC converter circuits, power MOS transistors, power Schottky diodes, JFETs (junction gate field effect transistors: Junction Gate Field Effect Transistor), power bipolar transistors, logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, sensor circuits, MEMS (micro-electro-mechanical systems: Micro-Electro-Mechanical-System), power integrated circuits, chips with integrated passive devices, etc. Embodiments may also use, for example, semiconductor chips including MOS transistor structures or vertical transistor structures, such as IGBT (insulated gate bipolar transistor: Insulated Gate Bipolar Transistor) structures, diodes, or generally speaking, transistor structures in which at least one electrical contact pad is arranged on a first main surface of the semiconductor chip and at least one other electrical contact pad is arranged on a second main surface of the semiconductor chip opposite to the first main surface of the semiconductor chip. Furthermore, embodiments of the insulating material may be used, for example, to provide insulating layers in various types of enclosures or insulations of circuits and components and / or to provide insulating layers in various types of semiconductor chips or circuits incorporated into semiconductor chips (including the semiconductor chips and circuits mentioned above).

[0032] The semiconductor substrate or semiconductor chip considered herein may be thin. The semiconductor substrate or semiconductor chip may be made of a specific semiconductor material, such as Si, SiC, SiGe, GaAs, GaN or any other semiconductor material, and may, for example, contain one or more inorganic and organic materials that are not semiconductor materials, such as insulators, plastics or metals.

[0033] The semiconductor substrate or chip may have contact pads (or electrodes) that allow electrical contact with the integrated circuit included in the semiconductor substrate or chip. The electrodes may all be arranged at only one main surface of the semiconductor substrate or chip or at two main surfaces. They may include one or more electrode metal layers applied to the semiconductor material. The electrode metal layers may be manufactured in any desired geometry and any desired material composition. For example, they may include or be made of a material selected from the following group: Cu, Ni, NiSn, Au, Ag, Pt, Pd, an alloy of one or more of these metals, a conductive organic material, or a conductive semiconductor material.

[0034] The semiconductor substrate or chip can be bonded to a carrier. The carrier can be a (permanent) device carrier for packaging. The carrier can, for example, include or consist of any kind of material, such as a ceramic or metal material, copper or a copper alloy or an iron / nickel alloy. The carrier can include a power electronic substrate, a lead frame, a DCB (Direct Copper Bond), a DAB (Direct Aluminum Bond), an AMB (Active Metal Braze) substrate, an IMS (Insulated Metal Substrate) or a PCB (Printed Circuit Board). The carrier can be mechanically and electrically connected to a contact element of the semiconductor substrate or chip. The semiconductor substrate or chip can be connected to the carrier by welding, for example, by one or more of reflow soldering, vacuum soldering and diffusion soldering. If diffusion soldering is used as a connection technology between a semiconductor substrate or a semiconductor chip and a carrier, a solder material that causes an intermetallic phase at the interface between the semiconductor and the carrier due to an interface diffusion process after the soldering process can be used. A soft solder material or a solder material that can form a diffusion solder bond, for example a solder material comprising one or more metal materials selected from the group consisting of Sn, SnAg, SnAu, SnCu, In, InAg, InCu and InAu, can be used. The solder material may include Pb, or a Pb-free solder material may be used.

[0035] The electronic module may include an encapsulation material covering the semiconductor chip. The encapsulation material may be electrically insulating. The encapsulation material may, for example, include or be made of any suitable plastic or polymer material, such as silicone gel, duroplast, thermoplastic or thermosetting material or laminate (prepreg), and may, for example, contain filler. The semiconductor chip may be encapsulated with the encapsulation material using various techniques, such as compression molding, injection molding, powder molding, liquid molding or lamination. The encapsulation material may be applied using heat and / or pressure.

[0036] In several embodiments, multiple layers or layer stacks are applied to each other or materials are applied or deposited onto layers. It should be understood that any term such as "apply" or "deposit" is intended to literally cover all types and techniques of applying layers to each other. In particular, they are intended to cover techniques in which layers are applied as a whole at once, such as lamination techniques, as well as techniques for depositing layers in a sequential manner, such as sputtering, plating, molding, CVD, etc.

[0037] The following discloses an example of an electronic device including a metal stack disposed on a semiconductor substrate or a semiconductor chip. The metal stack may be disposed on the back side of a semiconductor substrate. The metal stack may be disposed on a chip pad of a semiconductor substrate and may be configured to provide an electrical connection between the chip pad and a carrier to which the semiconductor substrate is attached. The metal stack may include a single metal layer, or it may include multiple metal layers, such as two, three, four or more layers. The metal stack may have any suitable size or form. The metal stack may completely cover the surface of a semiconductor substrate, or it may only partially cover the surface.

[0038] The metal stack may include a first layer configured to be used as a reaction partner for solder deposits during welding. The first layer may include a nickel silicon (NiSi) composite, and may be particularly composed of NiSi. Compared with other materials, such as pure nickel or nickel vanadium (Ni) composites, NiSi as a first layer can exhibit more excellent performance. For example, compared with Ni or NiV, NiSi reacts slower with Sn during welding. In particular, if the same welding process is performed, the consumption of NiV is about twice that of NiSi. Therefore, compared with NiV, a thinner NiSi layer can be used in the metal stack. This can reduce the manufacturing time and cost of the metal stack, and can also minimize the wafer warpage or chip warpage caused by the difference in the coefficient of thermal expansion (CTE: Coefficient of Thermal Expansion) of the semiconductor substrate and the metal stack.

[0039] The first layer can be made using a variety of deposition techniques known in the art. For example, the first layer can be made using magnetron sputtering. Unlike pure Ni, NiSi is not ferromagnetic and therefore does not interfere with the magnetron of the deposition chamber.

[0040] Magnetron sputtering can be performed in the presence of a process gas. The process gas may include an inert gas, such as Ar, Xe, Kr, or Ne. According to one aspect of the present invention, the process gas may include N (nitrogen). The process gas may, for example, include about 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or even greater than 80% N. The remainder of the process gas may consist of Ar. The presence of N in the process gas during magnetron sputtering may result in the incorporation of N impurities into the metal stack. For example, N impurities may be incorporated into the first layer. N may be incorporated into the first layer comprising NiSi, so that one or more of NiN and SiN are formed in the first layer. N may have a positive impact on the performance of the metal stack, such as a positive impact on the quality of the solder joint between the metal stack and the carrier.

[0041] Figure 1An example of an electronic device 100 according to a first aspect of the present invention is shown. The electronic device 100 includes a semiconductor substrate 110 and a metal stack 120 disposed on a first surface 110A of the semiconductor substrate. The semiconductor substrate 110 may include a semiconductor wafer or a single semiconductor chip. The first surface 110A may be the back side of the semiconductor substrate 110. The semiconductor substrate may include a chip pad (not shown) arranged on the first surface 110A, and the metal stack 120 may be disposed on the chip pad and electrically connected to the chip pad.

[0042] The metal stack 120 may completely cover the first surface 110A or may Figure 1 As shown, it may only partially cover the first surface 110A. The metal stack 120 may have any suitable shape and any suitable size in a lateral or vertical direction relative to the first surface 110A. The metal stack 120 may be structured or unstructured. As described above, the metal stack 120 may include N impurities.

[0043] The metal stack 120 may include a first layer 126, wherein the first layer 126 includes or consists of NiSi. The first layer 126 may have any suitable thickness according to the respective requirements for the first layer 126, wherein the thickness is measured along a direction perpendicular to the first surface 110A. The first layer 126 may have a thickness in the range of 50 nm to 2000 nm, in particular 100 nm to 1000 nm, more particularly 200 nm to 600 nm, even more particularly 400 nm to 500 nm. The thickness of the first layer 126 may also be about 300 nm or exactly 300 nm.

[0044] The amount of Si included in the first layer 126 may be in the range of 2wt% (2 weight percent) to 50wt%, particularly 2wt% to 20wt%, more particularly 3wt% to 10wt%, more particularly 4wt% to 5wt%, and even more particularly about 4.5wt% or exactly 4.5wt%, of the total material amount of the first layer 126.

[0045] The metal stack 120 may include additional layers in addition to the first layer 126. For example, the metal stack may include a third layer 128 disposed on the first layer 126. The third layer 128 may be configured to protect the first layer 126 from corrosion. The third layer may include or consist of any suitable material or material composite. For example, the third layer may include or consist of one or more of Ag, Pt, Pd, and Au. The third layer 128 may have any suitable thickness and may, for example, have a thickness in the range of 50 nm to 2000 nm, particularly 100 nm to 1000 nm, more particularly 150 nm to 500 nm, and even more particularly 200 nm to 300 nm. The thickness of the third layer 128 may also be about 200 nm or exactly 200 nm.

[0046] The metal stack 120 may include a second layer 124, wherein the second layer 124 is arranged between the first layer 126 and the semiconductor substrate 110. The second layer 124 may act as a barrier layer and may prevent impurities from diffusing into the semiconductor substrate 110. The second layer may have any suitable thickness, such as a thickness of about 200 nm or exactly 200 nm. The second layer 124 may include any suitable material, such as may include or consist of the following materials: one or more of Ti, WTi, Ta, or an alloy including at least one of these materials.

[0047] The metal stack 120 may include a fourth layer 122 disposed between the first layer 126 and the semiconductor substrate 110. In the case where the metal stack 120 includes a second layer 124, the fourth layer 122 is disposed between the second layer 124 and the semiconductor substrate 110. The fourth layer 122 may have any suitable thickness, for example, a thickness in the range of 50 nm to 2000 nm, particularly 100 nm to 1000 nm, more particularly 200 nm to 600 nm, and even more particularly 300 nm to 500 nm. The thickness of the fourth layer 122 may also be about or exactly 400 nm. The fourth layer 122 may include any suitable material, for example, may include or consist of one or more of Al and Ti.

[0048] Figure 2 An example of an electronic module 200 according to the present invention is shown. The electronic module 200 includes an electronic device 100 (including a semiconductor substrate 110 and a metal stack 120 ′) and a carrier 240 to which the electronic device 100 is attached. The electronic module 200 may also include an encapsulation 250 encapsulating the semiconductor substrate 110 .

[0049] The electronic module 200 further comprises a solder layer 230 arranged on the carrier 240 and soldered to the metal stack 120'. The solder layer 230 may comprise, for example, SnAg or Sn.

[0050] In addition to the changes introduced by soldering the electronic device 100 to the solder layer 230, the metal stack 120' of the electronic module 200 may be Figure 1 The metal stack 120 of the electronic device 100 is the same. According to one example of the electronic module 200, the first layer 126 can be thinner after welding than before welding. The first layer 126 can be, for example, one-quarter thinner, one-half thinner, three-quarter thinner, or there can be no first layer in the metal stack 120' after welding. Except for some patches 232 containing NiSi that can remain in the metal stack 120' after welding, the first layer may also be almost completely consumed by the welding process. The patches 232 can be positioned along the interface between the first layer and the solder layer. The patches 232 can contain a higher Si concentration than the precursor first layer 126 because Ni may be "extracted" during welding. For example, in the case where the first layer 126 contains 4.5% Si, the patches 232 can contain about four times the Si, or in other words, can contain about 20% Si.

[0051] According to one example of the electronic module 200 , the metal stack 120 ′ may include an intermetallic phase formed between the first layer 126 and the solder layer 230 .

[0052] According to one example of the electronic device 200, the metal stack 120' may include N impurities. N may improve the quality of the solder joint formed between the metal stack 120' and the solder layer 230. For example, in the case where the first layer 126 is completely consumed by the soldering process, the electronic module 200 does not show a delamination problem of the metal stack 120' being delaminated from the solder layer 230 because the N in the metal stack 120' may offset the delamination. In the case where the metal stack 120' includes the patch 232, the patch 232 may include N, for example, in the form of one or more of NiN and SiN.

[0053] Semiconductor substrate 110 of electronic module 200 may include a first electrode on first surface 110A and a second electrode on second surface 110B opposite to first surface 110A. Electronic module 200 may be configured for current to flow vertically from the second electrode to the first electrode and further through metal stack 120 ′ to carrier 240 .

[0054] Figure 2 The electronic module 200 shown only shows one semiconductor substrate 110, one metal stack 120' and one carrier 240. However, different examples of the electronic module 200 may of course include additional components such as additional semiconductor substrates, additional metal stacks or additional carriers or other suitable additional components. The additional components may be relative to Figure 2The components are shown in a side-by-side arrangement and / or in a vertically stacked arrangement.

[0055] Figure 3 A method for manufacturing a Figure 1 The method 300 of the electronic device 100 includes a first process step 301, wherein the first process step 301 includes providing a semiconductor substrate such as the semiconductor substrate 110. The method 300 also includes a second process step 302, wherein the second process step 302 includes arranging a metal stack such as the metal stack 120 on the semiconductor substrate.

[0056] The arrangement of the metal stack in the second process step 302 may include sputtering the first layer onto the semiconductor substrate. The sputtering may be performed in the presence of a process gas containing N as described above.

[0057] The arrangement of the metal stack in the second process step 302 may also include doping N impurities into the metal stack as described above.

[0058] Figure 4 A method for manufacturing a Figure 2 The method 400 of the electronic module of the electronic module 200 is provided. The method 400 comprises a first process step 401, wherein the first process step 401 comprises providing a semiconductor substrate and a carrier. The method 400 comprises a second process step 402, wherein the second process step 402 comprises arranging a metal stack on the semiconductor substrate. The method 400 comprises a third process step 403, wherein the third process step 403 comprises arranging a solder layer on the carrier. The method 400 comprises a fourth process step 404, wherein the fourth process step 404 comprises soldering the semiconductor substrate to the carrier.

[0059] Although the present invention has been shown and described with respect to one or more embodiments, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), unless otherwise indicated, the terms used to describe these components (including references to "methods") are intended to correspond to any component or structure (e.g., functionally identical) that performs the specified functions of the components, even if not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the invention shown herein.

Claims

1. An electronic device comprising: Carrier; Semiconductor substrate; as well as A metal stack is provided on the semiconductor substrate, the metal stack comprising: First floor, wherein the first layer comprises NiSi; and a diffusion solder bond between the carrier and the semiconductor substrate, The metal stack completely covers the back side of the semiconductor substrate.

2. The electronic device according to claim 1, wherein: The diffusion solder bond includes an intermetallic phase.

3. The electronic device according to claim 1, wherein: The semiconductor substrate includes one or more of a power semiconductor chip and a diode, and the metal stack is arranged on a chip pad of the power semiconductor chip or the diode.

4. The electronic device according to claim 1, wherein: The metal stack includes N impurities in the first layer in the form of one or both of NiN and SiN.

5. The electronic device according to claim 1, wherein: The metal stack further includes a second layer disposed between the first layer and the semiconductor substrate, the second layer including one or more of the following: Ti, WTi, Ta, or an alloy including at least one of these materials.

6. The electronic device according to claim 1, wherein: The metal stack further includes another layer disposed between the semiconductor substrate and the first layer, the other layer including one or both of Al and Ti.

7. The electronic device according to claim 1, wherein: The first layer has a thickness in the range of 50 nm to 2000 nm, and the first layer contains an amount of Si in the range of 2 wt % to 50 wt %.

8. The electronic device according to claim 3, wherein: The power semiconductor chip is an IGBT.

9. An electronic module comprising: Carrier; A semiconductor chip disposed on a carrier; as well as A metal stack is disposed between the carrier and the semiconductor chip, the metal stack comprising: a first layer comprising NiSi; and A diffusion solder bond is arranged between the first layer and the carrier and comprises an intermetallic phase, wherein the metal stack completely covers the back side of the semiconductor chip.

10. The electronic module according to claim 9, wherein: The carrier comprises a power electronic substrate, a lead frame, a DCB, a DAB, an AMB, an IMS or a PCB.

11. The electronic module according to claim 9, wherein: The electronic module further comprises a packaging body encapsulating the semiconductor chip.

12. The electronic module according to claim 9, wherein: The diffusion solder bond includes Pb-based or Pb-free solders.

13. The electronic module according to claim 12, wherein: The diffusion solder bond includes Sn or SnAg.

14. The electronic module according to claim 9, wherein: The metal stack includes N impurities.

15. The electronic module according to claim 14, wherein: N impurities are located along an interface between the first layer and the diffusion solder bond.

16. A method for manufacturing an electronic module, comprising: providing a carrier and a semiconductor substrate; Disposing a first layer comprising NiSi on the semiconductor substrate; providing a solder layer between the first layer and the carrier; as well as diffusion bonding the semiconductor substrate to the carrier to form an intermetallic phase between the first layer and the carrier, wherein providing the first layer on the semiconductor substrate comprises sputtering in the presence of a process gas, The first layer completely covers the back side of the semiconductor substrate.

17. The method according to claim 16, wherein: Sputtering includes a magnetron sputtering process.

18. The method according to claim 16, wherein: The process gas contains N, and an amount of N in the process gas is 80%. The process gas further contains Ar, Xe, Kr or Ne.

Images