Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a substrate including an active region and a dummy active region separated by an isolation layer; a buried word line extending from the active region to the dummy active region; and a contact plug coupled to an edge portion of the buried word line, wherein an upper surface of the active region is located at a higher level than an upper surface of the buried word line, and an upper surface of the dummy active region is located at a lower level than an upper surface of the buried word line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0039204, filed on Mar. 31, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a buried word line and a method for manufacturing the semiconductor device. Background Art

[0004] Generally, the use of buried word lines to improve the characteristics of transistors in semiconductor devices is well known. However, a great deal of research and product development effort has been focused on developing new and improved structures that exhibit improved performance characteristics. Summary of the invention

[0005] Embodiments of the present invention are directed to a semiconductor device including a buried word line and a method for manufacturing the same, the semiconductor device exhibiting significantly improved reliability.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a substrate including an active region and a dummy active region separated by an isolation layer; a buried word line extending from the active region to the dummy active region; and a contact plug coupled to an edge portion of the buried word line, wherein an upper surface of the active region is located at a higher level than an upper surface of the buried word line, and an upper surface of the dummy active region is located at a lower level than an upper surface of the buried word line.

[0007] According to another embodiment of the present invention, a semiconductor device includes: a substrate including a plurality of active regions and a plurality of dummy active regions separated by an isolation layer; a plurality of buried word lines buried in the substrate and extending from the active regions to the dummy active regions; a covering layer covering an edge portion of each of the buried word lines; and a contact plug coupled to the edge portion of each of the buried word lines, wherein the edge portion of each of the buried word lines includes: a buried portion buried in the dummy active region; and a protruding portion formed above the buried portion and having a level higher than an upper surface of the dummy active region.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming an active area and a dummy active area in a substrate; forming a buried word line, which is buried in the substrate and extends from the active area to the dummy active area; making the dummy active area recessed to be lower than the upper surface of the edge portion of the buried word line; forming a covering layer above the recessed dummy active area; and forming a contact plug, which penetrates the covering layer and is coupled to the edge portion of the buried word line.

[0009] According to another embodiment of the present invention, a semiconductor device includes: an active area and a dummy active area separated by an isolation layer, the upper surface of the dummy active area being located at a lower position than the upper surface of the active area; and a buried word line extending from the active area to the dummy active area, wherein the buried word line is completely buried within the active area and only partially buried in the dummy active area.

[0010] These and other features and advantages of the present invention will be better understood from the following detailed description of specific embodiments of the present invention taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

[0012] Figure 2A It is shown Figure 1 A magnified view of a portion of .

[0013] Figure 2B Indicates along Figure 2A The cross-sectional views are taken along the lines AA′ and BB′ shown.

[0014] Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0015] Figure 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0016] Figure 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0017] 6A to 6H is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0018] 7A to 7E is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0019] Figure 8 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0020] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout the present disclosure, the same reference numerals throughout the various drawings and embodiments of the present invention refer to the same components. Various embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic diagrams of various embodiments (and intermediate structures). In this way, the configuration and shape changes of the diagrams caused by, for example, manufacturing technology and / or tolerances can be expected. Therefore, the described embodiments should not be interpreted as being limited to the specific configurations and shapes shown herein, but may be included in the configurations and shapes that do not depart from the spirit and scope of the present invention defined by the appended claims.

[0021] The drawings are not necessarily drawn to scale, and in some cases, the proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0022] It will also be understood that when an element is referred to as being "connected" or "coupled to" another element, it can be directly on the other element, directly connected to or directly coupled to the other element, or one or more intervening elements may be present. Furthermore, the connection / coupling may not be limited to physical connections, but may also include non-physical connections, such as wireless connections.

[0023] In addition, it will also be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0024] When a first element is referred to as being 'on' a second element, it not only refers to a case where the first element is directly formed on the second element but also refers to a case where a third element exists between the first element and the second element.

[0025] It should be understood that the drawings are simplified schematic diagrams of the devices being described and may not include well-known details in order to avoid obscuring aspects of the present invention.

[0026] It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the present invention.

[0027] Figure 1 is a plan view showing a semiconductor device 100 according to an embodiment of the present invention. Figure 2A It is shown Figure 1An enlarged view of a portion 100A. Figure 2B Indicates along Figure 2A The cross-sectional views are taken along the lines AA′ and BB′ shown.

[0028] refer to Figure 1 , Figure 2A and Figure 2B , the semiconductor device 100 may include a substrate 101 provided with a plurality of active regions 103 and a plurality of dummy active regions 103D spaced apart from each other by an isolation layer 102. The semiconductor device 100 may further include: a buried word line 104 buried in the substrate 101 and extending from the active region 103 to the dummy active region 103D; and a contact plug 110 coupled to an edge portion 104D of the buried word line 104. The buried word line 104 is completely buried in the active region 103 and only partially buried in the dummy active region 103D.

[0029] The active areas 103 may all have the same shape. From the perspective of the top view, each active area 103 may have an island shape. Each active area 103 may extend along the AA' direction. Each active area 103 may have a major axis and a minor axis, and the length of the major axis may be greater than the length of the minor axis. The dummy active areas 103D may have the same length or different lengths. Each dummy active area 103D may extend along the BB' direction. The BB' direction may be the same as the AA' direction. Each dummy active area 103D may have a major axis and a minor axis, and the length of the major axis may be greater than the length of the minor axis. Each dummy active area 103D may be larger than each active area 103. For example, each dummy active area 103D and each active area 103 may extend with the same directivity, but each dummy active area 103D may extend longer than each active area 103. As described above, the dummy active area 103D may have a linear shape extending along the BB' direction. The active area 103 may also have a linear shape elongated along the AA′ direction. The linear shape of the dummy active area 103D may be significantly longer than the linear shape of the active area 103. The linear shape of the active area may also be referred to as a short island shape hereinafter. Each active area 103 may have a size large enough so that two buried word lines 104 are placed therein, and each dummy active area 103D may have a size large enough so that at least three or more buried word lines 104 are placed therein. In some embodiments of the present invention, two word lines may be arranged in each dummy active area 103D, but in this case, each dummy active area 103D may also be larger than each active area 103. Each active area 103 may have a first length D1, and each dummy active area 103D may have a second length D2. The second length D2 may be greater than the first length D1.

[0030] The upper surface T1 of the active region 103 may be located at a higher level than the upper surface T2 of the dummy active region 103D. The upper surface T1 of the active region 103 may be located at a higher level than the upper surface L1 of the buried word line 104. The upper surface T2 of the dummy active region 103D may be located at a lower level than the upper surface L2 of the edge portion 104D of the buried word line 104. The upper surface L2 of the edge portion 104D of the buried word line 104 may be located at a lower level than the upper surface T1 of the active region 103.

[0031] The edge portion 104D of the buried word line 104 may include a buried portion BP buried in the dummy active region 103D and a protruding portion PP formed on the buried portion BP. The upper surface L2 of the edge portion 104D of the buried word line 104 may be provided by the upper surface of the protruding portion PP. The upper surface L2 of the protruding portion PP may be located at a level higher than the upper surface T2 of the dummy active region 103D. The upper surface L2 of the protruding portion PP may be located at a level lower than the upper surface T1 of the active region 103. The upper surface of the buried portion BP and the upper surface T2 of the dummy active region 103D may be located at the same level. The height of the protruding portion PP may be greater than the height of the buried portion BP. The protruding portion PP may include a sidewall and an upper surface L2.

[0032] The sidewalls and upper surface L2 of the protruding portion PP may be covered by a capping layer 107. The bottom surface and sidewalls of the buried portion BP may be covered by a gate dielectric layer 106. The gate dielectric layer 106 may extend to cover the sidewalls of the protruding portion PP. The capping layer 107 may cover the sidewalls of the protruding portion PP over the gate dielectric layer 106. The capping layer 107 may extend to cover the upper surface of the isolation layer 102. The capping layer 107 may cover the upper portion of the buried word line 104, but may be buried in the substrate 101 and extend from the active region 103 to the dummy active region 103D.

[0033] The interlayer dielectric layer 109 may be formed over the capping layer 107. The contact plug 110 may penetrate the interlayer dielectric layer 109 and the capping layer 107 to be coupled to the edge portion 104D of the buried word line 104. The contact plug 110 may be coupled to the protruding portion PP of the edge portion 104D of the buried word line 104. The metal wire 111 may be formed over the contact plug 110. The metal wire 111 may be formed to directly contact the contact plug 110.

[0034] Adjacent contact plugs 110 may be disposed on the same axis or on different axes. Figure 1 , the contact plugs 110 may be disposed in a zigzag arrangement.

[0035] According to the above-described embodiment of the present invention, the bending of the word line 104 can be suppressed by forming the dummy active region 103D longer than the active region 103 .

[0036] Since the upper surface T2 of the dummy active region 103D is lower than the upper surface L2 of the edge portion 104D of the buried word line 104, the physical distance between the contact plug 110 and the dummy active region 103D is increased. This can prevent a short circuit between the contact plug 110 and the dummy active region 103D. Since the capping layer 107 is gap-filled between the edge portions 104D of the buried word lines 104, a short circuit between the contact plug 110 and the dummy active region 103D can be further prevented. Since the capping layer 107 is gap-filled between the edge portions 104D of the adjacent buried word lines 104, the expansion of the bottom of the contact plug 110 can also be suppressed.

[0037] Return to reference Figure 2B , the buried word line 104 may include a metal-based material such as a metal nitride, a metal, a doped semiconductor material such as doped polysilicon, or a combination thereof. Examples of suitable metals may include tungsten, copper, aluminum, titanium, tantalum, etc. Examples of suitable metal nitrides may include titanium nitride, tungsten nitride, tantalum nitride, etc. For example, the buried word line 104 and the edge portion 104D of the buried word line 104 may all include a metal-based material. Here, the edge portion 104D of the buried word line may have a lower surface than the buried word line 104.

[0038] Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Figure 3 The semiconductor device may include some Figure 2B Hereinafter, any repeated detailed description of constituent elements may be omitted.

[0039] refer to Figure 3 , the buried word line 104′ crossing the active region 103 may include a stack of a metal-based material 104A and a semiconductor material 104B. The edge portion 104D′ of the buried word line 104′ may also include the metal-based material 104A. The buried portion BP and the protruding portion PP may all be formed of the metal-based material 104A, and the buried portion BP and the protruding portion PP form the edge portion 104D′ of the buried word line 104′ crossing the dummy active region 103D.

[0040] The upper surface T1 of the active region 103 may be located at a level higher than the upper surface T2 of the dummy active region 103D. The upper surface T1 of the active region 103 may be located at a level higher than the upper surface L1′ of the buried word line 104′. The upper surface T2 of the dummy active region 103D may be located at a level lower than the upper surface L2 of the edge portion 104D′ of the buried word line 104′. The upper surface L2 of the edge portion 104D′ of the buried word line 104′ may be located at a level lower than the upper surface T1 of the active region 103.

[0041] The edge portion 104D′ of the buried word line 104′ may include a buried portion BP buried in the dummy active region 103D and a protruding portion PP located above the buried portion BP. The upper surface L2 of the edge portion 104D′ of the buried word line 104′ may be provided by the upper surface of the protruding portion PP. The upper surface L2 of the protruding portion PP may be located at a level higher than the upper surface T2 of the dummy active region 103D. The upper surface L2 of the protruding portion PP may be located at a level lower than the upper surface T1 of the active region 103. The upper surface of the buried portion BP and the upper surface T2 of the dummy active region 103D may be located at the same level. The height of the protruding portion PP may be greater than the height of the buried portion BP. The protruding portion PP may include a sidewall and an upper surface L2. The upper surface L2 of the protruding portion PP may be lower than the upper surface L1′ of the semiconductor material 104B.

[0042] The upper surface L2 of the protruding portion PP may be covered by the capping layer 107. The bottom surface and sidewalls of the buried portion BP may be covered by the gate dielectric layer 106. The gate dielectric layer 106 may extend to cover the sidewalls of the protruding portion PP (eg, Figure 3 ). The capping layer 107 may cover the gate dielectric layer 106 on the sidewall of the protruding portion PP. The buried word line 104' is completely buried within the active region 103, and only partially buried in the dummy active region 103D.

[0043] Figure 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Figure 4 The semiconductor device may include some Figure 3 Hereinafter, detailed description of any repeated constituent elements may be omitted.

[0044] refer to Figure 4, the buried word line 104′ crossing the active area 103 may include a stack of a metal-based material 104A and a semiconductor material 104B. The edge portion 104D′ of the buried word line 104′ may also include the metal-based material 104A. The buried portion BP and the protruding portion PP may be formed of the metal-based material 104A, and the buried portion BP and the protruding portion PP form the edge portion 104D′ of the buried word line 104′ crossing the dummy active area 103D. The contact plug 110′ may be coupled to the edge portion 104D′ of the buried word line 104′, more specifically, to the protruding portion PP of the edge portion 104D′. The width W1 of the contact plug 110′ may be greater than the width W2 of the edge portion 104D′ of the buried word line 104′.

[0045] The bottom of the contact plug 110′ may include a first portion CB1 overlapping the edge portion 104D′ of the buried word line 104′ and a second portion CB2 overlapping the capping layer 107. For example, the first portion CB1 of the contact plug 110′ may overlap and directly contact the upper surface of the protruding portion PP of the edge portion 104D′ of the buried word line 104′, and the second portion CB2 of the contact plug 110′ may overlap and directly contact the capping layer 107. The buried word line 104′ is completely buried within the active region 103, and is only partially buried in the dummy active region 103D.

[0046] Figure 5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention. Figure 5 The semiconductor device may include some Figure 3 and Figure 4 Hereinafter, detailed description of any repeated constituent elements may be omitted.

[0047] refer to Figure 5 , the buried word line 104′ crossing the active region 103 may include a stack of a metal-based material 104A and a semiconductor material 104B. The edge portion 104D′ of the buried word line 104′ may also include the metal-based material 104A. The buried portion BP and the protruding portion PP may all be formed of the metal-based material 104A, and the buried portion BP and the protruding portion PP form the edge portion 104D′ of the buried word line 104′ crossing the dummy active region 103D.

[0048] The contact plug 110 ″ may be coupled to the edge portion 104D′ of the buried word line 104 ′. A width W1 of the contact plug 110 ″ may be greater than a width W2 of the edge portion 104D′ of the buried word line 104 ′.

[0049] The bottom of the contact plug 110″ may include a first portion CB1 overlapping the edge portion 104D′ of the buried word line 104′ and a second portion CB2′ overlapping the covering layer 107. The second portion CB2′ of the contact plug 110″ may overlap one side wall of the protruding portion PP. The contact plug 110″ may be in direct contact with the upper surface of the protruding portion PP of the edge portion 104D′, and may also be in direct contact with the upper portion of the gate dielectric layer 106, the upper portion of which covers the upper portion of one of the side walls of the protruding portion PP of the edge portion 104D′. The buried word line 104′ is completely buried within the active area 103, and is only partially buried in the dummy active area 103D.

[0050] 6A to 6H is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 6A to 6H Shown for manufacturing Figure 3 An example of a method of a semiconductor device is shown.

[0051] refer to Fig. 6A , an isolation layer 12 may be formed in the substrate 11. A plurality of active areas 13 may be defined by the isolation layer 12. The isolation layer 12 may be formed by a shallow trench isolation (STI) process. For example, the substrate 11 may be etched to form an isolation trench (not shown). The isolation trench may be filled with a dielectric material to form the isolation layer 12. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. A chemical vapor deposition (CVD) process or other deposition process may be used to fill the isolation trench with a dielectric material. A planarization process such as chemical mechanical polishing (CMP) may be used in addition. Each active area 13 may have the same shape. From a top view perspective, each active area 13 may have an island shape surrounded by the isolation layer 12. Each active area 13 may extend in a diagonal direction. Each active area 13 may have a major axis and a minor axis. The length of the major axis may be greater than the length of the minor axis.

[0052] The substrate 11 may include a first region R1 and a second region R2. The active region 13 may be formed in the first region R1. A plurality of dummy active regions 13D may be formed in the second region R2. The dummy active regions 13D and the active regions 13 may have different sizes. The dummy active regions 13D may have the same length or different lengths. Each dummy active region 13D may have a linear shape extending along a diagonal direction. Each dummy active region 13D may be larger than each active region 13. For example, each dummy active region 13D and each active region 13 may extend in the same direction, but each dummy active region 13D may extend longer than each active region 13. As described above, the dummy active region 13D may have a linear shape with a longer elongated shape (relative to the active region 13), while the active region 13 may have a shorter elongated shape (relative to the dummy active region 13D), which is referred to as an island shape. As will be described later, each active region 13 may have a size large enough to place two word lines therein, and each dummy active region 13D may have a size large enough to place at least three word lines therein. In some embodiments, two word lines may be provided in each dummy active region 13D, but in this case, each dummy active region 13D may also be larger than each active region 13.

[0053] refer to Figure 6B , a plurality of trenches 15 may be formed in the substrate 11. The trenches 15 may be formed in a linear shape that crosses the active region 13 and the isolation layer 12. The trenches 15 may be formed by performing an etching process on the substrate 11 using the hard mask layer 14 as an etching mask. The hard mask layer 14 may be formed over the substrate 11 and may have a plurality of linear openings. The hard mask layer 14 may be formed of a material having an etching selectivity relative to the substrate 11. For example, the hard mask layer 14 may be made of silicon oxide such as an ultra low temperature oxide (ULTO) or tetraethylorthosilicate (TEOS). The trenches 15 may be formed to have a depth shallower than the bottom surface of the isolation layer 12. The trenches 15 may have a depth sufficient to increase the average cross-sectional area of ​​the word lines to be subsequently formed. As a result, the resistance of the word lines may be reduced. As Figure 6B The bottom edge of the groove 15 shown is flat. However, the bottom edge of the groove 15 according to another embodiment of the present invention (not shown) may have a curvature. Adjacent grooves 15 may be parallel to each other by being spaced apart from each other.

[0054] Although not shown, a fin region (not shown) may be formed after forming the trench 15. To form the fin region, the isolation layer 12 under the trench 15 may be selectively recessed. As a result, the active area 13 under the trench 15 may include a fin region located at a higher level than the recessed isolation layer 12.

[0055] The trenches 15 may be formed in the first region R1. The trenches 15 may each include a trench edge portion 15D located in the second region R2, and the trench edge portion 15D may refer to the trench 15 located in the second region R2. The trench edge portion 15D may be formed by etching the dummy active region 13D and the isolation layer 12.

[0056] The trench 15 located in the isolation layer 12 may be deeper than the trench 15 located in the active region 13 and the dummy active region 13D. The trench edge portion 15D may have an elongated shape extending in a direction crossing the dummy active region 13D.

[0057] refer to Figure 6C , a gate dielectric layer 16 may be formed on the surface of the trench 15. Before forming the gate dielectric layer 16, etching damage on the surface of the trench 15 may be cured. For example, after forming a sacrificial oxide by thermal oxidation, the sacrificial oxide may be removed. For example, the gate dielectric layer 16 may include silicon oxide.

[0058] For example, the gate dielectric layer 16 may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The gate dielectric layer 16 formed by the deposition method may include, for example, a high-k material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The high-k material may include, for example, a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. According to another embodiment of the present invention, the high-k material may include lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. As for the high-k material, other known high-k materials may be selectively used. The gate dielectric layer 16 may include a stack of silicon oxide and a high-k material, wherein the high-k material may include a material having a higher surface density of oxygen atoms than silicon oxide.

[0059] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by a thermal oxidation process.

[0060] According to another embodiment of the present invention, the gate dielectric layer 16 may be formed by sequentially performing an ULTO deposition process and a high temperature oxidation process. The ULTO deposition process may refer to the deposition of ultra low temperature silicon oxide. The ultra low temperature silicon oxide (ULTO) may be deposited at a temperature of about 400°C. The high temperature oxidation process may be an oxidation process performed at a temperature of about 1050°C after the ultra low temperature silicon oxide (ULTO) is deposited. As described above, the reduction of the critical dimension of the active region 13 may be suppressed by combining the ULTO deposition process and the high temperature oxidation process.

[0061] The gate dielectric layer edge portion 16D may be formed over the trench edge portion 15D. The gate dielectric layer edge portion 16D may be a portion of the gate dielectric layer 16, and may refer to the gate dielectric layer 16 located in the second region R2. The gate dielectric layer edge portion 16D may be formed simultaneously with the formation of the gate dielectric layer 16. The gate dielectric layer edge portion 16D and the gate dielectric layer 16 may be formed of the same material. The gate dielectric layer edge portion 16D and the gate dielectric layer 16 may have the same thickness.

[0062] refer to Fig.6D , a word line 17 may be formed. The word line 17 may partially fill the trench 15 above the gate dielectric layer 16. The word line 17 may be referred to as a buried word line. The word line 17 may include a lower gate layer 18 and an upper gate layer 19. The upper gate layer 19 may be formed above the lower gate layer 18. An upper surface of the upper gate layer 19 may be located at a lower level than an upper surface of the hard mask layer 14.

[0063] The lower gate layer 18 may fill the bottom of the trench 15 above the gate dielectric layer 16. The lower gate layer 18 may include a low resistance metal material. The lower gate layer 18 may include, for example, tungsten. The lower gate layer 18 may be formed, for example, by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. According to another embodiment of the present invention, the lower gate layer 18 may include a high work function material. For example, the lower gate layer 18 may include a high work function metal or a high work function polysilicon. The high work function polysilicon may include, for example, P-type polysilicon. The high work function metal may include, for example, nitrogen-rich titanium nitride (TiN). In order to form the lower gate layer 18, a recess process of the lower gate material may be performed after gap filling the trench 15 with the lower gate material (not shown). The recess process may be performed by a dry etching process (e.g., an etch-back process). The etch-back process may be performed using plasma. The lower gate layer 18 may be formed by an etch-back process of the lower gate material. According to another embodiment of the present invention, the recessing process may be performed by first performing a planarization process to expose the upper surface of the hard mask layer 14 and then subsequently performing an etch-back process. The upper surface of the lower gate layer 18 may be recessed to be lower than the upper surface of the active region 13 .

[0064] In order to form the upper gate layer 19, after depositing the upper gate material (not shown) to fill the trench 15 above the lower gate layer 18, a recess process of the upper gate material can be performed. The upper gate material can be formed, for example, by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The recess process of the upper gate material can be performed by a dry etching process (e.g., an etch-back process). The upper gate layer 19 can be formed by an etch-back process of the upper gate material. According to another embodiment of the present invention, the recess process of the upper gate material can be performed by performing a planarization process to expose the upper surface of the hard mask layer 14 and then subsequently performing an etch-back process. The upper surface of the upper gate layer 19 can be located at a level lower than the upper surface of the active area 13.

[0065] The upper gate layer 19 may have a lower work function than the lower gate layer 18. The upper gate layer 19 may have a work function smaller than the mid-gap work function of silicon. The upper gate layer 19 may be referred to as a low work function gate layer. The upper gate layer 19 may include a low work function metal or a low work function polysilicon. The low work function polysilicon may include, for example, N-type polysilicon. The low work function metal may include, for example, titanium-rich titanium nitride (TiN). In this embodiment of the present invention, the upper gate layer 19 may be polysilicon doped with N-type impurities.

[0066] The word line 17 formed in the first region R1 may extend to be located in the second region R2. The word line 17 may include a word line edge portion 17D located in the second region R2. The word line edge portion 17D may partially fill the trench edge portion 15D above the gate dielectric layer edge portion 16D. The word line edge portion 17D and the word line 17 may be formed at the same time. The word line edge portion 17D and the word line 17 may be made of the same material. The word line edge portion 17D and the word line 17 may have the same height. The word line edge portion 17D may include a lower gate layer edge portion 18D and an upper gate layer edge portion 19D located above the lower gate layer edge portion 18D. The lower gate layer edge portion 18D may be a portion of the lower gate layer 18 and may refer to the lower gate layer 18 located in the second region R2. The upper gate layer edge portion 19D may be a portion of the upper gate layer 19 and may refer to the upper gate layer 19 located in the second region R2. The word line edge portion 17D may correspond to Figures 1 to 5 The buried word line 104 is shown with edge portions 104D and 104D'.

[0067] The word line 17 located in the isolation layer 12 may be deeper than the word line 17 located in the active region 13 and the dummy active region 13D. The word line edge portion 17D may have an elongated shape extending in a direction crossing the dummy active region 13D.

[0068] refer to Fig. 6E , a mask layer 20 may be formed. The mask layer 20 may be formed in the first region R1. The mask layer 20 may include a photoresist pattern or a hard mask material. The second region R2 may be exposed through the mask layer 20. The mask layer 20 may expose an etch target portion 22 of the second region R2. The etch target portion 22 may refer to a structure having a level higher than the bottom surface of the lower gate layer edge portion 18D.

[0069] An etching process using the mask layer 20 may be performed, and the etching target portion 22 may be removed by the etching process. For example, the hard mask layer 14, the upper gate layer edge portion 19D, a portion of the gate dielectric layer edge portion 16D, and a portion of the isolation layer 12 may be etched. Through the etching process of the etching target portion 22, an isolation layer 12′ with a reduced height and a gate dielectric layer edge portion 16D′ with a reduced height may be formed in the second region R2. As the upper gate layer edge portion 19D is removed, the lower gate layer edge portion 18D may remain in the second region R2. The lower gate layer edge portion 18D may fill the trench edge portion 15D′ with a reduced height.

[0070] In addition, the etching process using the mask layer 20 may etch a portion of the dummy active region 13D. As a result, a dummy active region 13D' with a reduced height may be formed. The dummy active region 13D' with a reduced height may be simply referred to as a recessed dummy active region 13D'.

[0071] The upper surface 21 of the recessed dummy active region 13D′ may be located at a level lower than the upper surface L1 of the lower gate layer edge portion 18D, and the upper surface 21 of the recessed dummy active region 13D′ may be located at a level higher than the bottom surface L2 of the lower gate layer edge portion 18D. The gate dielectric layer edge portion 16D′ may cover the bottom surface and sidewalls of the lower gate layer edge portion 18D. The upper surface of the gate dielectric layer edge portion 16D′ and the upper surface of the lower gate layer edge portion 18D may be located at the same level.

[0072] As described above, in order to recess the dummy active region 13D′, the dummy active region 13D′ may be selectively etched with respect to the lower gate layer edge portion 18D.

[0073] refer to Fig. 6F After removing the mask layer 20, a capping layer 23 may be formed. The capping layer 23 may include a dielectric material. For example, the capping layer 23 may include silicon nitride. In one embodiment, the capping layer 23 may have an oxide-nitride-oxide (ONO) structure.

[0074] The covering layer 23 may be formed in both the first region R1 and the second region R2. The covering layer 23 formed in the second region R2 may be referred to as a covering layer edge portion 23D. The covering layer edge portion 23D may cover the upper surface of the recessed dummy active region 13D′. The covering layer edge portion 23D may cover the upper surface of the lower gate layer edge portion 18D. The covering layer edge portion 23D may cover a portion of the sidewall of the gate dielectric layer edge portion 16D′. The covering layer edge portion 23D may cover the upper surface and a portion of the sidewall of the isolation layer 12′.

[0075] The capping layer 23 formed in the first region R1 may directly contact the upper gate layer 19. The capping layer edge portion 23D formed in the second region R2 may directly contact the lower gate layer edge portion 18D.

[0076] As described above, the capping layer edge portion 23D may be filled between adjacent lower gate layer edge portions 18D in the second region R2 .

[0077] refer to Figure 6G , an interlayer dielectric layer 24 may be formed over the capping layer 23. For example, the interlayer dielectric layer 24 may include silicon oxide.

[0078] Subsequently, one or more contact holes 25A and 25B may be formed by etching the interlayer dielectric layer 24 and the capping layer edge portion 23D. The contact holes 25A and 25B may be formed in the second region R2. The contact holes 25A and 25B may fall on the upper surface of the lower gate layer edge portion 18D. The contact hole 25A may fall on the upper surface of the lower gate layer edge portion 18D that crosses the recessed dummy active region 13D'. The contact hole 25B may fall on the upper surface of the lower gate layer edge portion 18D buried in the isolation layer 12'.

[0079] refer to Figure 6H , a metal wire 27 may be formed, which is coupled to the lower gate layer edge portion 18D through the contact holes 25A and 25B. The metal wire 27 may be electrically connected to the lower gate layer edge portion 18D through the contact plug 26. The contact plug 26 may fill the contact holes 25A and 25B.

[0080] According to the above-described embodiment of the present invention, by forming the dummy active region 13D′ to be longer, the bending of the word line 17 can be suppressed.

[0081] Since the height of the dummy active region 13D' is reduced by using the mask layer 20, the physical distance between the contact holes 25A and 25B and the dummy active region 13D' can be increased. Therefore, the short circuit between the contact holes 25A and 25B and the dummy active region 13D' can be prevented. Since the cover layer edge portion 23D between the lower gate layer edge portions 18D is a gap-filled space, the short circuit between the contact holes 25A and 25B and the dummy active region 13D' can be further prevented. Since the cover layer edge portion 23D between the adjacent lower gate layer edge portions 18D is gap-filled, the expansion of the contact holes 25A and 25B can also be suppressed.

[0082] As a comparative example, when the dummy active regions 13D and 13D′ are omitted, only the isolation layer 12 may be formed in the second region R2. Therefore, the stress caused by the isolation layer 12 may cause bending of the edge portion of the word line 17 coupled to the contact plug 26. The bending of the word line may cause a short circuit between adjacent word lines. In contrast, in this embodiment of the present invention, although the word line edge portion 17D′ ​​is subjected to the stress caused by the isolation layer 12, the dummy active region 13D′ is able to support the word line edge portion 17D′, thereby suppressing the bending of the word line edge portion 17D′.

[0083] As a comparative example, when the capping layer edge portion 23D is not gap-filled between the adjacent lower gate layer edge portions 18D, a short circuit may occur between the contact holes 25A and 25B and the adjacent word line edge portion 17D'. In contrast, in this embodiment of the present invention, the capping layer edge portion 23D between the adjacent lower gate layer edge portions 18D is gap-filled. Therefore, even if the critical dimension of the bottom of the contact holes 25A and 25B is increased, a short circuit with the adjacent word line edge portion 17D' can be suppressed.

[0084] 7A to 7E is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0085] First, you can FIG. 6A to FIG. 6C The gate dielectric layer 16 is formed by a series of processes as shown.

[0086] Then, if Fig. 7A As shown, a word line 27 may be formed. The word line 27 may partially fill the trench 15 above the gate dielectric layer 16. The word line 27 may be referred to as a buried word line. The word line 27 may include a single gate layer. The upper surface of the word line 27 may be located at a level lower than the upper surface of the hard mask layer 14.

[0087] The word line 27 may include a low resistance metal material. The word line 27 may include, for example, tungsten. The word line 27 may include a high work function material. The word line 27 may include a high work function metal or a high work function polysilicon. The high work function polysilicon may include, for example, P-type polysilicon. The high work function metal may include, for example, nitrogen-rich titanium nitride (TiN). In order to form the word line 27, the trench 15 may be gap-filled with a gate material (not shown), and then the gate material may be recessed. The recessing process may be performed by a dry etching process (e.g., an etch-back process). The etch-back process may be performed using plasma. The word line 27 may be formed by an etch-back process of the gate material. According to another embodiment of the present invention, the recess may be performed by performing a planarization process to expose the upper surface of the hard mask layer 14 and then performing an etch-back process. The upper surface of the word line 27 may be recessed to a level lower than the upper surface of the active area 13. In this embodiment of the present invention, the word line 27 may include a TiN / W stack.

[0088] The word line 27 formed in the first region R1 may extend to be located in the second region R2. The word line 27 may include a word line edge portion 27D located in the second region R2. The word line edge portion 27D may partially fill the trench edge portion 15D above the gate dielectric layer edge portion 16D. The word line edge portion 27D and the word line 27 may be formed simultaneously. The word line edge portion 27D and the word line 27 may be made of the same material. The word line edge portion 27D and the word line 27 may have the same height.

[0089] The word line 27 located in the isolation layer 12 may be deeper than the word line 27 located in the active region 13 and the dummy active region 13D. The word line edge portion 27D may have an elongated shape extending in a direction crossing the dummy active region 13D.

[0090] refer to Figure 7B , a mask layer 20 may be formed. The mask layer 20 may be formed in the first region R1. The mask layer 20 may include a photoresist pattern or a hard mask material. The second region R2 may be exposed through the mask layer 20. The mask layer 20 may expose an etching target portion 22 of the second region R2. The etching target portion 22 may refer to a structure located at a level higher than the upper surface of the word line edge portion 27D.

[0091] An etching process using the mask layer 20 may be performed, and the etching target portion 22 may be removed by the etching process. For example, the hard mask layer 14, a portion of the word line edge portion 27D, a portion of the gate dielectric layer edge portion 16D, and a portion of the isolation layer 12 may be etched. Through the etching process of the etching target portion 22, an isolation layer 12′ with a reduced height and a gate dielectric layer edge portion 16D′ with a reduced height may be formed in the second region R2. As a portion of the word line edge portion 27D is removed, a word line edge portion 27D′ with a reduced height may remain in the second region R2. The word line edge portion 27D′ may fill the trench edge portion 15D′ with a reduced height.

[0092] In addition, the etching process using the mask layer 20 may etch a portion of the dummy active region 13D. As a result, a dummy active region 13D' with a reduced height may be formed. The dummy active region 13D' with a reduced height may be simply referred to as a recessed dummy active region 13D'.

[0093] The upper surface 21 of the recessed dummy active region 13D′ may be located at a level lower than the upper surface L1 of the word line edge portion 27D′, and the upper surface 21 of the recessed dummy active region 13D′ may be located at a level higher than the bottom surface L2 of the word line edge portion 27D′. The gate dielectric layer edge portion 16D′ may cover the bottom surface and sidewall of the word line edge portion 27D′. The upper surface of the gate dielectric layer edge portion 16D′ and the upper surface of the word line edge portion 27D′ may be located at the same level.

[0094] The word line edge portion 27D′ may have a lower upper surface than the word line 27 .

[0095] refer to Figure 7C After removing the mask layer 20, a capping layer 23 may be formed. The capping layer 23 may include a dielectric material. The capping layer 23 may include silicon nitride. The capping layer 23 may have an oxide-nitride-oxide (ONO) structure.

[0096] The covering layer 23 may be formed in both the first region R1 and the second region R2. The covering layer 23 formed in the second region R2 may be referred to as a covering layer edge portion 23D. The covering layer edge portion 23D may cover the upper surface of the recessed dummy active region 13D′. The covering layer edge portion 23D may cover the upper surface of the word line edge portion 27D′. The covering layer edge portion 23D may cover a portion of the sidewall of the gate dielectric layer edge portion 16D′. The covering layer edge portion 23D may cover the upper surface and a portion of the sidewall of the isolation layer 12′.

[0097] The capping layer 23 formed in the first region R1 may directly contact the word line 27. The capping layer edge portion 23D formed in the second region R2 may directly contact the word line edge portion 27D'.

[0098] As described above, in the second region R2, the capping layer edge portion 23D between adjacent word line edge portions 27D′ may be filled.

[0099] refer to Fig.7D , an interlayer dielectric layer 24 may be formed on the capping layer 23. The interlayer dielectric layer 24 may include silicon oxide.

[0100] Subsequently, one or more contact holes 25A and 25B may be formed by etching the interlayer dielectric layer 24 and the capping layer edge portion 23D. The contact holes 25A and 25B may be formed in the second region R2. The contact holes 25A and 25B may fall on the upper surface of the word line edge portion 27D'. The contact hole 25A may fall on the upper surface of the word line edge portion 27D' that crosses the recessed dummy active region 13D'. The contact hole 25B may fall on the upper surface of the word line edge portion 27D' buried in the isolation layer 12'.

[0101] refer to Fig. 7E A metal wire 27 may be formed, which is coupled to the word line edge portion 27D′ through the contact holes 25A and 25B. The metal wire 27 may be electrically connected to the word line edge portion 27D′ through the contact plug 26. The contact plug 26 may fill the contact holes 25A and 25B.

[0102] Figure 8 is a cross-sectional view of a semiconductor device 200 according to another embodiment of the present invention.

[0103] refer to Figure 8 , the semiconductor device 200 may be part of a memory cell, and the memory cell may include a DRAM memory cell.

[0104] The semiconductor device 200 may include a bit line structure BL located at a higher level than the buried word line 104. The bit line structure BL may be oriented in a direction (not shown) that intersects the orientation of the buried word line 104, and a capacitor CAP is located at a higher level than the bit line structure BL while being coupled to a portion of the active region 103. The capacitor CAP may be coupled to a portion of the active region 103 through a storage node contact plug (SNC). The bit line structure BL may be coupled to another portion of the active region 103 through a bit line contact plug BLC.

[0105] The buried word line 104 may correspond to the word lines 104, 17, and 27 according to the above-described embodiments of the present invention. Therefore, the buried word line 104 may include a word line edge portion 104D.

[0106] According to the embodiment of the present invention, the bending of the word line can be suppressed by forming the dummy active region to be longer.

[0107] According to the embodiment of the present invention, since the height of the dummy active region is lowered, a short circuit between the contact hole and the dummy active region can be prevented.

[0108] According to the embodiment of the present invention, since the edge portion of the capping layer between the edge portions of the word lines is gap-filled, a short circuit between the contact hole and the dummy active region can be further prevented.

[0109] According to the embodiment of the present invention, since the edge portion of the capping layer is between the edge portions of the adjacent word lines, the enlargement of the contact hole can be suppressed.

[0110] According to the embodiments of the present invention, the connection between the contact plug and the word line can be improved, and thus the electrical characteristics and reliability of the semiconductor device can be improved.

[0111] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. A semiconductor device, include: a substrate including an active region and a dummy active region separated by an isolation layer; a buried word line extending from the active area to the dummy active area, the dummy active area supporting an edge portion of the buried word line; as well as a contact plug coupled to the edge portion of the buried word line, The upper surface of the active region is located at a higher level than the upper surface of the buried word line, and the upper surface of the dummy active region is located at a lower level than the upper surface of the buried word line and the upper surface of the active region.

2. The semiconductor device according to claim 1, in, The edge portion of the buried word line includes a buried portion buried in the dummy active region and a protruding portion formed on the buried portion, and The upper surface of the protruding portion is located at a higher level than the upper surface of the dummy active region.

3. The semiconductor device according to claim 2, further comprising: include: a covering layer covering the side walls and the upper surface of the protruding portion; as well as The contact plug is coupled to an upper surface of the protruding portion through the cover layer.

4. The semiconductor device according to claim 3, in, The bottom of the contact plug includes: a first portion that overlaps an edge portion of the buried word line; and A second portion overlaps the cover layer.

5. The semiconductor device according to claim 4, in, The second portion of the contact plug extends to overlap one sidewall of the protruding portion of the buried word line.

6. The semiconductor device according to claim 3, in, The cover layer extends to cover an upper surface of the isolation layer.

7. The semiconductor device according to claim 3, in, The capping layer includes silicon nitride.

8. The semiconductor device according to claim 1, in, The buried word line includes a metal-based material, a doped semiconductor material, a metal, or a combination thereof.

9. The semiconductor device according to claim 1, in, The edge portion of the buried word line includes a metal-based material, and the buried word line includes the metal-based material and a semiconductor material over the metal-based material.

10. The semiconductor device according to claim 1, in, The contact plug has a width greater than a width of the edge portion of the buried word line.

11. The semiconductor device according to claim 1, in, The dummy active region has a shape extending longer than the active region.

12. A semiconductor device, include: a substrate including a plurality of active regions and a plurality of dummy active regions separated by isolation layers; a plurality of buried word lines buried in the substrate and extending from the active region to the dummy active region, the dummy active region supporting an edge portion of each of the buried word lines; a capping layer covering the edge portion of each of the buried word lines; as well as a contact plug coupled to the edge portion of each of the buried word lines, Wherein, the edge portion of each of the buried word lines comprises: a buried portion buried in the dummy active region; and a protruding portion formed above the buried portion and having a level higher than an upper surface of the dummy active region, The upper surface of the dummy active region is located at a level lower than the upper surface of the buried word line and the upper surface of the active region.

13. The semiconductor device according to claim 12, in, The cover layer covers the side walls and the upper surface of the protruding portion.

14. The semiconductor device according to claim 12, in, The bottom of the contact plug includes: a first portion overlapping an edge portion of each of the buried word lines; and A second portion overlaps the cover layer.

15. The semiconductor device according to claim 14, in, The second portion of the contact plug extends to overlap one sidewall of the protruding portion of each of the buried word lines.

16. The semiconductor device according to claim 12, in, The cover layer extends to cover an upper surface of the isolation layer.

17. The semiconductor device according to claim 12, in, The capping layer includes silicon nitride.

18. The semiconductor device according to claim 12, in, The edge portion of each of the buried word lines includes a metal-based material, and the buried word line includes the metal-based material and a semiconductor material over the metal-based material.

19. The semiconductor device according to claim 12, in, The capping layer covers an upper portion of the buried word line, and the capping layer is buried in the substrate and extends from the active region to the dummy active region.

20. The semiconductor device according to claim 12, in, The contact plug has a width greater than a width of the edge portion of each of the buried word lines.

21. The semiconductor device according to claim 12, further comprising: include: a bit line structure located at a higher level than the buried word line and intersecting the buried word line; A capacitor is located at a higher level than the bit line structure and is coupled to a portion of the active region.

22. A semiconductor device, include: an active region and a dummy active region separated by an isolation layer, wherein an upper surface of the dummy active region is located at a lower position than an upper surface of the active region; as well as a buried word line extending from the active area to the dummy active area, the dummy active area supporting an edge portion of the buried word line, The buried word line is completely buried in the active region and only partially buried in the dummy active region.

23. A method for manufacturing a semiconductor device, include: forming an active region and a dummy active region in a substrate; forming a buried word line buried in the substrate and extending from the active region to the dummy active region; causing the dummy active region to be recessed to be lower than an upper surface of an edge portion of the buried word line; forming a capping layer on the recessed dummy active region; as well as A contact plug is formed that penetrates the capping layer and is coupled to the edge portion of the buried word line.

24. The method according to claim 23, in, The step of recessing the dummy active region to be lower than the upper surface of the edge portion of the buried word line comprises: forming a mask layer covering an upper portion of the substrate in which the active region and the buried word line are formed; and The substrate in which the dummy active region and the edge portion of the buried word line are formed is etched by using the mask layer.

25. The method according to claim 24, in, The dummy active region is selectively etched with respect to the edge portion of the buried word line so as to recess the dummy active region.

26. The method according to claim 23, in, The dummy active region includes silicon, and the edge portion of the buried word line includes a metal-based material.

27. The method according to claim 23, in, The dummy active region includes silicon, and the edge portion of the buried word line includes a metal-based material and a semiconductor material over the metal-based material, and The semiconductor material is etched while recessing the dummy active region.

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